1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 /*- 22 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 23 * http://www.ralinktech.com/ 24 */ 25 26 #include <sys/param.h> 27 #include <sys/sysctl.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/firmware.h> 40 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_radiotap.h> 56 #include <net80211/ieee80211_regdomain.h> 57 #include <net80211/ieee80211_ratectl.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_ether.h> 64 65 #include <dev/ral/rt2860reg.h> 66 #include <dev/ral/rt2860var.h> 67 68 #define RAL_DEBUG 69 #ifdef RAL_DEBUG 70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n, x) 75 #endif 76 77 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 78 const char [IFNAMSIZ], int, enum ieee80211_opmode, 79 int, const uint8_t [IEEE80211_ADDR_LEN], 80 const uint8_t [IEEE80211_ADDR_LEN]); 81 static void rt2860_vap_delete(struct ieee80211vap *); 82 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 83 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 84 struct rt2860_tx_ring *); 85 static void rt2860_reset_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_free_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 90 static void rt2860_free_tx_pool(struct rt2860_softc *); 91 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 92 struct rt2860_rx_ring *); 93 static void rt2860_reset_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_free_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_updatestats(struct rt2860_softc *); 98 static void rt2860_newassoc(struct ieee80211_node *, int); 99 static void rt2860_node_free(struct ieee80211_node *); 100 #ifdef IEEE80211_HT 101 static int rt2860_ampdu_rx_start(struct ieee80211com *, 102 struct ieee80211_node *, uint8_t); 103 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 #endif 106 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 107 int); 108 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 109 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 110 static void rt2860_intr_coherent(struct rt2860_softc *); 111 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 112 static void rt2860_tx_intr(struct rt2860_softc *, int); 113 static void rt2860_rx_intr(struct rt2860_softc *); 114 static void rt2860_tbtt_intr(struct rt2860_softc *); 115 static void rt2860_gp_intr(struct rt2860_softc *); 116 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 117 struct ieee80211_node *); 118 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 119 const struct ieee80211_bpf_params *); 120 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 121 struct ieee80211_node *, 122 const struct ieee80211_bpf_params *params); 123 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 124 static void rt2860_start(struct rt2860_softc *); 125 static void rt2860_watchdog(void *); 126 static void rt2860_parent(struct ieee80211com *); 127 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 128 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 129 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 130 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 131 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 132 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 133 static void rt2860_enable_mrr(struct rt2860_softc *); 134 static void rt2860_set_txpreamble(struct rt2860_softc *); 135 static void rt2860_set_basicrates(struct rt2860_softc *, 136 const struct ieee80211_rateset *); 137 static void rt2860_scan_start(struct ieee80211com *); 138 static void rt2860_scan_end(struct ieee80211com *); 139 static void rt2860_getradiocaps(struct ieee80211com *, int, int *, 140 struct ieee80211_channel[]); 141 static void rt2860_set_channel(struct ieee80211com *); 142 static void rt2860_select_chan_group(struct rt2860_softc *, int); 143 static void rt2860_set_chan(struct rt2860_softc *, u_int); 144 static void rt3090_set_chan(struct rt2860_softc *, u_int); 145 static void rt5390_set_chan(struct rt2860_softc *, u_int); 146 static int rt3090_rf_init(struct rt2860_softc *); 147 static void rt5390_rf_init(struct rt2860_softc *); 148 static void rt3090_rf_wakeup(struct rt2860_softc *); 149 static void rt5390_rf_wakeup(struct rt2860_softc *); 150 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 151 uint8_t *); 152 static void rt3090_rf_setup(struct rt2860_softc *); 153 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 154 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 155 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 156 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 157 static void rt2860_update_promisc(struct ieee80211com *); 158 static void rt2860_updateslot(struct ieee80211com *); 159 static void rt2860_updateprot(struct rt2860_softc *); 160 static int rt2860_updateedca(struct ieee80211com *); 161 #ifdef HW_CRYPTO 162 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 163 struct ieee80211_key *); 164 static void rt2860_delete_key(struct ieee80211com *, 165 struct ieee80211_node *, struct ieee80211_key *); 166 #endif 167 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 168 static const char *rt2860_get_rf(uint16_t); 169 static int rt2860_read_eeprom(struct rt2860_softc *, 170 uint8_t macaddr[IEEE80211_ADDR_LEN]); 171 static int rt2860_bbp_init(struct rt2860_softc *); 172 static void rt5390_bbp_init(struct rt2860_softc *); 173 static int rt2860_txrx_enable(struct rt2860_softc *); 174 static void rt2860_init(void *); 175 static void rt2860_init_locked(struct rt2860_softc *); 176 static void rt2860_stop(void *); 177 static void rt2860_stop_locked(struct rt2860_softc *); 178 static int rt2860_load_microcode(struct rt2860_softc *); 179 #ifdef NOT_YET 180 static void rt2860_calib(struct rt2860_softc *); 181 #endif 182 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 183 static void rt2860_switch_chan(struct rt2860_softc *, 184 struct ieee80211_channel *); 185 static int rt2860_setup_beacon(struct rt2860_softc *, 186 struct ieee80211vap *); 187 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 188 189 static const struct { 190 uint32_t reg; 191 uint32_t val; 192 } rt2860_def_mac[] = { 193 RT2860_DEF_MAC 194 }; 195 196 static const struct { 197 uint8_t reg; 198 uint8_t val; 199 } rt2860_def_bbp[] = { 200 RT2860_DEF_BBP 201 }, rt5390_def_bbp[] = { 202 RT5390_DEF_BBP 203 }; 204 205 static const struct rfprog { 206 uint8_t chan; 207 uint32_t r1, r2, r3, r4; 208 } rt2860_rf2850[] = { 209 RT2860_RF2850 210 }; 211 212 struct { 213 uint8_t n, r, k; 214 } rt3090_freqs[] = { 215 RT3070_RF3052 216 }; 217 218 static const struct { 219 uint8_t reg; 220 uint8_t val; 221 } rt3090_def_rf[] = { 222 RT3070_DEF_RF 223 }, rt5390_def_rf[] = { 224 RT5390_DEF_RF 225 }, rt5392_def_rf[] = { 226 RT5392_DEF_RF 227 }; 228 229 static const uint8_t rt2860_chan_5ghz[] = 230 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 231 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 232 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 }; 233 234 int 235 rt2860_attach(device_t dev, int id) 236 { 237 struct rt2860_softc *sc = device_get_softc(dev); 238 struct ieee80211com *ic = &sc->sc_ic; 239 uint32_t tmp; 240 int error, ntries, qid; 241 242 sc->sc_dev = dev; 243 sc->sc_debug = 0; 244 245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 246 MTX_DEF | MTX_RECURSE); 247 248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 249 mbufq_init(&sc->sc_snd, ifqmaxlen); 250 251 /* wait for NIC to initialize */ 252 for (ntries = 0; ntries < 100; ntries++) { 253 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 254 if (tmp != 0 && tmp != 0xffffffff) 255 break; 256 DELAY(10); 257 } 258 if (ntries == 100) { 259 device_printf(sc->sc_dev, 260 "timeout waiting for NIC to initialize\n"); 261 error = EIO; 262 goto fail1; 263 } 264 sc->mac_ver = tmp >> 16; 265 sc->mac_rev = tmp & 0xffff; 266 267 if (sc->mac_ver != 0x2860 && 268 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 269 sc->sc_flags |= RT2860_ADVANCED_PS; 270 271 /* retrieve RF rev. no and various other things from EEPROM */ 272 rt2860_read_eeprom(sc, ic->ic_macaddr); 273 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 274 "RF %s (MIMO %dT%dR), address %6D\n", 275 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 276 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 277 278 /* 279 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 280 */ 281 for (qid = 0; qid < 6; qid++) { 282 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 283 device_printf(sc->sc_dev, 284 "could not allocate Tx ring %d\n", qid); 285 goto fail2; 286 } 287 } 288 289 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 290 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 291 goto fail2; 292 } 293 294 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 295 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 296 goto fail3; 297 } 298 299 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 300 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 301 WME_AC_VO : 5; 302 303 ic->ic_softc = sc; 304 ic->ic_name = device_get_nameunit(dev); 305 ic->ic_opmode = IEEE80211_M_STA; 306 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 307 308 /* set device capabilities */ 309 ic->ic_caps = 310 IEEE80211_C_STA /* station mode */ 311 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 312 | IEEE80211_C_HOSTAP /* hostap mode */ 313 | IEEE80211_C_MONITOR /* monitor mode */ 314 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 315 | IEEE80211_C_WDS /* 4-address traffic works */ 316 | IEEE80211_C_MBSS /* mesh point link mode */ 317 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 318 | IEEE80211_C_SHSLOT /* short slot time supported */ 319 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 320 #if 0 321 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 322 #endif 323 | IEEE80211_C_WME /* 802.11e */ 324 ; 325 326 ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD; 327 328 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 329 ic->ic_channels); 330 331 ieee80211_ifattach(ic); 332 333 ic->ic_wme.wme_update = rt2860_updateedca; 334 ic->ic_scan_start = rt2860_scan_start; 335 ic->ic_scan_end = rt2860_scan_end; 336 ic->ic_getradiocaps = rt2860_getradiocaps; 337 ic->ic_set_channel = rt2860_set_channel; 338 ic->ic_updateslot = rt2860_updateslot; 339 ic->ic_update_promisc = rt2860_update_promisc; 340 ic->ic_raw_xmit = rt2860_raw_xmit; 341 sc->sc_node_free = ic->ic_node_free; 342 ic->ic_node_free = rt2860_node_free; 343 ic->ic_newassoc = rt2860_newassoc; 344 ic->ic_transmit = rt2860_transmit; 345 ic->ic_parent = rt2860_parent; 346 ic->ic_vap_create = rt2860_vap_create; 347 ic->ic_vap_delete = rt2860_vap_delete; 348 349 ieee80211_radiotap_attach(ic, 350 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 351 RT2860_TX_RADIOTAP_PRESENT, 352 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 353 RT2860_RX_RADIOTAP_PRESENT); 354 355 #ifdef RAL_DEBUG 356 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 357 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 358 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 359 #endif 360 if (bootverbose) 361 ieee80211_announce(ic); 362 363 return 0; 364 365 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 366 fail2: while (--qid >= 0) 367 rt2860_free_tx_ring(sc, &sc->txq[qid]); 368 fail1: mtx_destroy(&sc->sc_mtx); 369 return error; 370 } 371 372 int 373 rt2860_detach(void *xsc) 374 { 375 struct rt2860_softc *sc = xsc; 376 struct ieee80211com *ic = &sc->sc_ic; 377 int qid; 378 379 RAL_LOCK(sc); 380 rt2860_stop_locked(sc); 381 RAL_UNLOCK(sc); 382 383 ieee80211_ifdetach(ic); 384 mbufq_drain(&sc->sc_snd); 385 for (qid = 0; qid < 6; qid++) 386 rt2860_free_tx_ring(sc, &sc->txq[qid]); 387 rt2860_free_rx_ring(sc, &sc->rxq); 388 rt2860_free_tx_pool(sc); 389 390 mtx_destroy(&sc->sc_mtx); 391 392 return 0; 393 } 394 395 void 396 rt2860_shutdown(void *xsc) 397 { 398 struct rt2860_softc *sc = xsc; 399 400 rt2860_stop(sc); 401 } 402 403 void 404 rt2860_suspend(void *xsc) 405 { 406 struct rt2860_softc *sc = xsc; 407 408 rt2860_stop(sc); 409 } 410 411 void 412 rt2860_resume(void *xsc) 413 { 414 struct rt2860_softc *sc = xsc; 415 416 if (sc->sc_ic.ic_nrunning > 0) 417 rt2860_init(sc); 418 } 419 420 static struct ieee80211vap * 421 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 422 enum ieee80211_opmode opmode, int flags, 423 const uint8_t bssid[IEEE80211_ADDR_LEN], 424 const uint8_t mac[IEEE80211_ADDR_LEN]) 425 { 426 struct rt2860_softc *sc = ic->ic_softc; 427 struct rt2860_vap *rvp; 428 struct ieee80211vap *vap; 429 430 switch (opmode) { 431 case IEEE80211_M_STA: 432 case IEEE80211_M_IBSS: 433 case IEEE80211_M_AHDEMO: 434 case IEEE80211_M_MONITOR: 435 case IEEE80211_M_HOSTAP: 436 case IEEE80211_M_MBSS: 437 /* XXXRP: TBD */ 438 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 439 device_printf(sc->sc_dev, "only 1 vap supported\n"); 440 return NULL; 441 } 442 if (opmode == IEEE80211_M_STA) 443 flags |= IEEE80211_CLONE_NOBEACONS; 444 break; 445 case IEEE80211_M_WDS: 446 if (TAILQ_EMPTY(&ic->ic_vaps) || 447 ic->ic_opmode != IEEE80211_M_HOSTAP) { 448 device_printf(sc->sc_dev, 449 "wds only supported in ap mode\n"); 450 return NULL; 451 } 452 /* 453 * Silently remove any request for a unique 454 * bssid; WDS vap's always share the local 455 * mac address. 456 */ 457 flags &= ~IEEE80211_CLONE_BSSID; 458 break; 459 default: 460 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 461 return NULL; 462 } 463 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 464 vap = &rvp->ral_vap; 465 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 466 467 /* override state transition machine */ 468 rvp->ral_newstate = vap->iv_newstate; 469 vap->iv_newstate = rt2860_newstate; 470 #if 0 471 vap->iv_update_beacon = rt2860_beacon_update; 472 #endif 473 474 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 475 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 476 477 ieee80211_ratectl_init(vap); 478 /* complete setup */ 479 ieee80211_vap_attach(vap, ieee80211_media_change, 480 ieee80211_media_status, mac); 481 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 482 ic->ic_opmode = opmode; 483 return vap; 484 } 485 486 static void 487 rt2860_vap_delete(struct ieee80211vap *vap) 488 { 489 struct rt2860_vap *rvp = RT2860_VAP(vap); 490 491 ieee80211_ratectl_deinit(vap); 492 ieee80211_vap_detach(vap); 493 free(rvp, M_80211_VAP); 494 } 495 496 static void 497 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 498 { 499 if (error != 0) 500 return; 501 502 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 503 504 *(bus_addr_t *)arg = segs[0].ds_addr; 505 } 506 507 static int 508 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 509 { 510 int size, error; 511 512 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 513 514 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 515 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 516 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 517 if (error != 0) { 518 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 519 goto fail; 520 } 521 522 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 523 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 524 if (error != 0) { 525 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 526 goto fail; 527 } 528 529 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 530 size, rt2860_dma_map_addr, &ring->paddr, 0); 531 if (error != 0) { 532 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 533 goto fail; 534 } 535 536 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 537 538 return 0; 539 540 fail: rt2860_free_tx_ring(sc, ring); 541 return error; 542 } 543 544 void 545 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 546 { 547 struct rt2860_tx_data *data; 548 int i; 549 550 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 551 if ((data = ring->data[i]) == NULL) 552 continue; /* nothing mapped in this slot */ 553 554 if (data->m != NULL) { 555 bus_dmamap_sync(sc->txwi_dmat, data->map, 556 BUS_DMASYNC_POSTWRITE); 557 bus_dmamap_unload(sc->txwi_dmat, data->map); 558 m_freem(data->m); 559 data->m = NULL; 560 } 561 if (data->ni != NULL) { 562 ieee80211_free_node(data->ni); 563 data->ni = NULL; 564 } 565 566 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 567 ring->data[i] = NULL; 568 } 569 570 ring->queued = 0; 571 ring->cur = ring->next = 0; 572 } 573 574 void 575 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 576 { 577 struct rt2860_tx_data *data; 578 int i; 579 580 if (ring->txd != NULL) { 581 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 582 BUS_DMASYNC_POSTWRITE); 583 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 584 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 585 } 586 if (ring->desc_dmat != NULL) 587 bus_dma_tag_destroy(ring->desc_dmat); 588 589 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 590 if ((data = ring->data[i]) == NULL) 591 continue; /* nothing mapped in this slot */ 592 593 if (data->m != NULL) { 594 bus_dmamap_sync(sc->txwi_dmat, data->map, 595 BUS_DMASYNC_POSTWRITE); 596 bus_dmamap_unload(sc->txwi_dmat, data->map); 597 m_freem(data->m); 598 } 599 if (data->ni != NULL) 600 ieee80211_free_node(data->ni); 601 602 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 603 } 604 } 605 606 /* 607 * Allocate a pool of TX Wireless Information blocks. 608 */ 609 int 610 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 611 { 612 caddr_t vaddr; 613 bus_addr_t paddr; 614 int i, size, error; 615 616 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 617 618 /* init data_pool early in case of failure.. */ 619 SLIST_INIT(&sc->data_pool); 620 621 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 622 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 623 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 624 if (error != 0) { 625 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 626 goto fail; 627 } 628 629 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 630 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 631 if (error != 0) { 632 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 633 goto fail; 634 } 635 636 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 637 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 638 if (error != 0) { 639 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 640 goto fail; 641 } 642 643 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 644 645 vaddr = sc->txwi_vaddr; 646 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 647 struct rt2860_tx_data *data = &sc->data[i]; 648 649 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 650 if (error != 0) { 651 device_printf(sc->sc_dev, "could not create DMA map\n"); 652 goto fail; 653 } 654 data->txwi = (struct rt2860_txwi *)vaddr; 655 data->paddr = paddr; 656 vaddr += RT2860_TXWI_DMASZ; 657 paddr += RT2860_TXWI_DMASZ; 658 659 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 660 } 661 662 return 0; 663 664 fail: rt2860_free_tx_pool(sc); 665 return error; 666 } 667 668 void 669 rt2860_free_tx_pool(struct rt2860_softc *sc) 670 { 671 if (sc->txwi_vaddr != NULL) { 672 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 673 BUS_DMASYNC_POSTWRITE); 674 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 675 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 676 } 677 if (sc->txwi_dmat != NULL) 678 bus_dma_tag_destroy(sc->txwi_dmat); 679 680 while (!SLIST_EMPTY(&sc->data_pool)) { 681 struct rt2860_tx_data *data; 682 data = SLIST_FIRST(&sc->data_pool); 683 bus_dmamap_destroy(sc->txwi_dmat, data->map); 684 SLIST_REMOVE_HEAD(&sc->data_pool, next); 685 } 686 } 687 688 int 689 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 690 { 691 bus_addr_t physaddr; 692 int i, size, error; 693 694 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 695 696 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 697 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 698 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 699 if (error != 0) { 700 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 701 goto fail; 702 } 703 704 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 705 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 706 if (error != 0) { 707 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 708 goto fail; 709 } 710 711 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 712 size, rt2860_dma_map_addr, &ring->paddr, 0); 713 if (error != 0) { 714 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 715 goto fail; 716 } 717 718 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 719 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 720 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 721 if (error != 0) { 722 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 723 goto fail; 724 } 725 726 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 727 struct rt2860_rx_data *data = &ring->data[i]; 728 struct rt2860_rxd *rxd = &ring->rxd[i]; 729 730 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 731 if (error != 0) { 732 device_printf(sc->sc_dev, "could not create DMA map\n"); 733 goto fail; 734 } 735 736 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 737 if (data->m == NULL) { 738 device_printf(sc->sc_dev, 739 "could not allocate rx mbuf\n"); 740 error = ENOMEM; 741 goto fail; 742 } 743 744 error = bus_dmamap_load(ring->data_dmat, data->map, 745 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 746 &physaddr, 0); 747 if (error != 0) { 748 device_printf(sc->sc_dev, 749 "could not load rx buf DMA map"); 750 goto fail; 751 } 752 753 rxd->sdp0 = htole32(physaddr); 754 rxd->sdl0 = htole16(MCLBYTES); 755 } 756 757 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 758 759 return 0; 760 761 fail: rt2860_free_rx_ring(sc, ring); 762 return error; 763 } 764 765 void 766 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 767 { 768 int i; 769 770 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 771 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 772 773 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 774 775 ring->cur = 0; 776 } 777 778 void 779 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 780 { 781 int i; 782 783 if (ring->rxd != NULL) { 784 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 785 BUS_DMASYNC_POSTWRITE); 786 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 787 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 788 } 789 if (ring->desc_dmat != NULL) 790 bus_dma_tag_destroy(ring->desc_dmat); 791 792 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 793 struct rt2860_rx_data *data = &ring->data[i]; 794 795 if (data->m != NULL) { 796 bus_dmamap_sync(ring->data_dmat, data->map, 797 BUS_DMASYNC_POSTREAD); 798 bus_dmamap_unload(ring->data_dmat, data->map); 799 m_freem(data->m); 800 } 801 if (data->map != NULL) 802 bus_dmamap_destroy(ring->data_dmat, data->map); 803 } 804 if (ring->data_dmat != NULL) 805 bus_dma_tag_destroy(ring->data_dmat); 806 } 807 808 static void 809 rt2860_updatestats(struct rt2860_softc *sc) 810 { 811 struct ieee80211com *ic = &sc->sc_ic; 812 813 /* 814 * In IBSS or HostAP modes (when the hardware sends beacons), the 815 * MAC can run into a livelock and start sending CTS-to-self frames 816 * like crazy if protection is enabled. Fortunately, we can detect 817 * when such a situation occurs and reset the MAC. 818 */ 819 if (ic->ic_curmode != IEEE80211_M_STA) { 820 /* check if we're in a livelock situation.. */ 821 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 822 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 823 /* ..and reset MAC/BBP for a while.. */ 824 DPRINTF(("CTS-to-self livelock detected\n")); 825 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 826 RAL_BARRIER_WRITE(sc); 827 DELAY(1); 828 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 829 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 830 } 831 } 832 } 833 834 static void 835 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 836 { 837 struct ieee80211com *ic = ni->ni_ic; 838 struct rt2860_softc *sc = ic->ic_softc; 839 uint8_t wcid; 840 841 wcid = IEEE80211_AID(ni->ni_associd); 842 if (isnew && ni->ni_associd != 0) { 843 sc->wcid2ni[wcid] = ni; 844 845 /* init WCID table entry */ 846 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 847 ni->ni_macaddr, IEEE80211_ADDR_LEN); 848 } 849 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 850 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 851 } 852 853 static void 854 rt2860_node_free(struct ieee80211_node *ni) 855 { 856 struct ieee80211com *ic = ni->ni_ic; 857 struct rt2860_softc *sc = ic->ic_softc; 858 uint8_t wcid; 859 860 if (ni->ni_associd != 0) { 861 wcid = IEEE80211_AID(ni->ni_associd); 862 863 /* clear Rx WCID search table entry */ 864 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 865 } 866 sc->sc_node_free(ni); 867 } 868 869 #ifdef IEEE80211_HT 870 static int 871 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 872 uint8_t tid) 873 { 874 struct rt2860_softc *sc = ic->ic_softc; 875 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 876 uint32_t tmp; 877 878 /* update BA session mask */ 879 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 880 tmp |= (1 << tid) << 16; 881 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 882 return 0; 883 } 884 885 static void 886 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 887 uint8_t tid) 888 { 889 struct rt2860_softc *sc = ic->ic_softc; 890 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 891 uint32_t tmp; 892 893 /* update BA session mask */ 894 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 895 tmp &= ~((1 << tid) << 16); 896 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 897 } 898 #endif 899 900 static int 901 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 902 { 903 struct rt2860_vap *rvp = RT2860_VAP(vap); 904 struct ieee80211com *ic = vap->iv_ic; 905 struct rt2860_softc *sc = ic->ic_softc; 906 uint32_t tmp; 907 int error; 908 909 if (vap->iv_state == IEEE80211_S_RUN) { 910 /* turn link LED off */ 911 rt2860_set_leds(sc, RT2860_LED_RADIO); 912 } 913 914 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 915 /* abort TSF synchronization */ 916 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 917 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 918 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 919 RT2860_TBTT_TIMER_EN)); 920 } 921 922 rt2860_set_gp_timer(sc, 0); 923 924 error = rvp->ral_newstate(vap, nstate, arg); 925 if (error != 0) 926 return (error); 927 928 if (nstate == IEEE80211_S_RUN) { 929 struct ieee80211_node *ni = vap->iv_bss; 930 931 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 932 rt2860_enable_mrr(sc); 933 rt2860_set_txpreamble(sc); 934 rt2860_set_basicrates(sc, &ni->ni_rates); 935 rt2860_set_bssid(sc, ni->ni_bssid); 936 } 937 938 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 939 vap->iv_opmode == IEEE80211_M_IBSS || 940 vap->iv_opmode == IEEE80211_M_MBSS) { 941 error = rt2860_setup_beacon(sc, vap); 942 if (error != 0) 943 return error; 944 } 945 946 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 947 rt2860_enable_tsf_sync(sc); 948 rt2860_set_gp_timer(sc, 500); 949 } 950 951 /* turn link LED on */ 952 rt2860_set_leds(sc, RT2860_LED_RADIO | 953 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 954 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 955 } 956 return error; 957 } 958 959 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 960 static uint16_t 961 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 962 { 963 uint32_t tmp; 964 uint16_t reg; 965 int ntries; 966 967 addr *= 2; 968 /*- 969 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 970 * DATA0: F E D C 971 * DATA1: B A 9 8 972 * DATA2: 7 6 5 4 973 * DATA3: 3 2 1 0 974 */ 975 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 976 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 977 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 978 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 979 for (ntries = 0; ntries < 500; ntries++) { 980 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 981 if (!(tmp & RT3070_EFSROM_KICK)) 982 break; 983 DELAY(2); 984 } 985 if (ntries == 500) 986 return 0xffff; 987 988 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 989 return 0xffff; /* address not found */ 990 991 /* determine to which 32-bit register our 16-bit word belongs */ 992 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 993 tmp = RAL_READ(sc, reg); 994 995 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 996 } 997 998 /* 999 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1000 * 93C66 or 93C86). 1001 */ 1002 static uint16_t 1003 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1004 { 1005 uint32_t tmp; 1006 uint16_t val; 1007 int n; 1008 1009 /* clock C once before the first command */ 1010 RT2860_EEPROM_CTL(sc, 0); 1011 1012 RT2860_EEPROM_CTL(sc, RT2860_S); 1013 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1014 RT2860_EEPROM_CTL(sc, RT2860_S); 1015 1016 /* write start bit (1) */ 1017 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1018 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1019 1020 /* write READ opcode (10) */ 1021 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1023 RT2860_EEPROM_CTL(sc, RT2860_S); 1024 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1025 1026 /* write address (A5-A0 or A7-A0) */ 1027 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1028 for (; n >= 0; n--) { 1029 RT2860_EEPROM_CTL(sc, RT2860_S | 1030 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1031 RT2860_EEPROM_CTL(sc, RT2860_S | 1032 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1033 } 1034 1035 RT2860_EEPROM_CTL(sc, RT2860_S); 1036 1037 /* read data Q15-Q0 */ 1038 val = 0; 1039 for (n = 15; n >= 0; n--) { 1040 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1041 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1042 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1043 RT2860_EEPROM_CTL(sc, RT2860_S); 1044 } 1045 1046 RT2860_EEPROM_CTL(sc, 0); 1047 1048 /* clear Chip Select and clock C */ 1049 RT2860_EEPROM_CTL(sc, RT2860_S); 1050 RT2860_EEPROM_CTL(sc, 0); 1051 RT2860_EEPROM_CTL(sc, RT2860_C); 1052 1053 return val; 1054 } 1055 1056 static __inline uint16_t 1057 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1058 { 1059 /* either eFUSE ROM or EEPROM */ 1060 return sc->sc_srom_read(sc, addr); 1061 } 1062 1063 static void 1064 rt2860_intr_coherent(struct rt2860_softc *sc) 1065 { 1066 uint32_t tmp; 1067 1068 /* DMA finds data coherent event when checking the DDONE bit */ 1069 1070 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1071 1072 /* restart DMA engine */ 1073 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1074 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1075 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1076 1077 (void)rt2860_txrx_enable(sc); 1078 } 1079 1080 static void 1081 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1082 { 1083 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 1084 struct ieee80211_node *ni; 1085 uint32_t stat; 1086 uint8_t wcid, mcs, pid; 1087 1088 /* drain Tx status FIFO (maxsize = 16) */ 1089 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 1090 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1091 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1092 1093 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1094 if (wcid > RT2860_WCID_MAX) 1095 continue; 1096 ni = sc->wcid2ni[wcid]; 1097 1098 /* if no ACK was requested, no feedback is available */ 1099 if (!(stat & RT2860_TXQ_ACKREQ) || ni == NULL) 1100 continue; 1101 1102 /* update per-STA AMRR stats */ 1103 if (stat & RT2860_TXQ_OK) { 1104 /* 1105 * Check if there were retries, ie if the Tx success 1106 * rate is different from the requested rate. Note 1107 * that it works only because we do not allow rate 1108 * fallback from OFDM to CCK. 1109 */ 1110 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1111 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1112 if (mcs + 1 != pid) 1113 txs->long_retries = 1; 1114 else 1115 txs->long_retries = 0; 1116 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 1117 ieee80211_ratectl_tx_complete(ni, txs); 1118 } else { 1119 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 1120 txs->long_retries = 1; /* XXX */ 1121 ieee80211_ratectl_tx_complete(ni, txs); 1122 if_inc_counter(ni->ni_vap->iv_ifp, 1123 IFCOUNTER_OERRORS, 1); 1124 } 1125 } 1126 } 1127 1128 static void 1129 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1130 { 1131 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1132 uint32_t hw; 1133 1134 rt2860_drain_stats_fifo(sc); 1135 1136 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1137 while (ring->next != hw) { 1138 struct rt2860_tx_data *data = ring->data[ring->next]; 1139 1140 if (data != NULL) { 1141 bus_dmamap_sync(sc->txwi_dmat, data->map, 1142 BUS_DMASYNC_POSTWRITE); 1143 bus_dmamap_unload(sc->txwi_dmat, data->map); 1144 ieee80211_tx_complete(data->ni, data->m, 0); 1145 data->ni = NULL; 1146 data->m = NULL; 1147 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1148 ring->data[ring->next] = NULL; 1149 } 1150 ring->queued--; 1151 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1152 } 1153 1154 sc->sc_tx_timer = 0; 1155 if (ring->queued < RT2860_TX_RING_COUNT) 1156 sc->qfullmsk &= ~(1 << qid); 1157 rt2860_start(sc); 1158 } 1159 1160 /* 1161 * Return the Rx chain with the highest RSSI for a given frame. 1162 */ 1163 static __inline uint8_t 1164 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1165 { 1166 uint8_t rxchain = 0; 1167 1168 if (sc->nrxchains > 1) { 1169 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1170 rxchain = 1; 1171 if (sc->nrxchains > 2) 1172 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1173 rxchain = 2; 1174 } 1175 return rxchain; 1176 } 1177 1178 static void 1179 rt2860_rx_intr(struct rt2860_softc *sc) 1180 { 1181 struct rt2860_rx_radiotap_header *tap; 1182 struct ieee80211com *ic = &sc->sc_ic; 1183 struct ieee80211_frame *wh; 1184 struct ieee80211_node *ni; 1185 struct mbuf *m, *m1; 1186 bus_addr_t physaddr; 1187 uint32_t hw; 1188 uint16_t phy; 1189 uint8_t ant; 1190 int8_t rssi, nf; 1191 int error; 1192 1193 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1194 while (sc->rxq.cur != hw) { 1195 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1196 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1197 struct rt2860_rxwi *rxwi; 1198 1199 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1200 BUS_DMASYNC_POSTREAD); 1201 1202 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1203 DPRINTF(("RXD DDONE bit not set!\n")); 1204 break; /* should not happen */ 1205 } 1206 1207 if (__predict_false(rxd->flags & 1208 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1209 counter_u64_add(ic->ic_ierrors, 1); 1210 goto skip; 1211 } 1212 1213 #ifdef HW_CRYPTO 1214 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1215 /* report MIC failures to net80211 for TKIP */ 1216 ic->ic_stats.is_rx_locmicfail++; 1217 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1218 counter_u64_add(ic->ic_ierrors, 1); 1219 goto skip; 1220 } 1221 #endif 1222 1223 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1224 if (__predict_false(m1 == NULL)) { 1225 counter_u64_add(ic->ic_ierrors, 1); 1226 goto skip; 1227 } 1228 1229 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1230 BUS_DMASYNC_POSTREAD); 1231 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1232 1233 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1234 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1235 &physaddr, 0); 1236 if (__predict_false(error != 0)) { 1237 m_freem(m1); 1238 1239 /* try to reload the old mbuf */ 1240 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1241 mtod(data->m, void *), MCLBYTES, 1242 rt2860_dma_map_addr, &physaddr, 0); 1243 if (__predict_false(error != 0)) { 1244 panic("%s: could not load old rx mbuf", 1245 device_get_name(sc->sc_dev)); 1246 } 1247 /* physical address may have changed */ 1248 rxd->sdp0 = htole32(physaddr); 1249 counter_u64_add(ic->ic_ierrors, 1); 1250 goto skip; 1251 } 1252 1253 /* 1254 * New mbuf successfully loaded, update Rx ring and continue 1255 * processing. 1256 */ 1257 m = data->m; 1258 data->m = m1; 1259 rxd->sdp0 = htole32(physaddr); 1260 1261 rxwi = mtod(m, struct rt2860_rxwi *); 1262 1263 /* finalize mbuf */ 1264 m->m_data = (caddr_t)(rxwi + 1); 1265 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1266 1267 wh = mtod(m, struct ieee80211_frame *); 1268 #ifdef HW_CRYPTO 1269 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1270 /* frame is decrypted by hardware */ 1271 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1272 } 1273 #endif 1274 1275 /* HW may insert 2 padding bytes after 802.11 header */ 1276 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1277 u_int hdrlen = ieee80211_hdrsize(wh); 1278 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1279 m->m_data += 2; 1280 wh = mtod(m, struct ieee80211_frame *); 1281 } 1282 1283 ant = rt2860_maxrssi_chain(sc, rxwi); 1284 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1285 nf = RT2860_NOISE_FLOOR; 1286 1287 if (ieee80211_radiotap_active(ic)) { 1288 tap = &sc->sc_rxtap; 1289 tap->wr_flags = 0; 1290 tap->wr_antenna = ant; 1291 tap->wr_antsignal = nf + rssi; 1292 tap->wr_antnoise = nf; 1293 /* in case it can't be found below */ 1294 tap->wr_rate = 2; 1295 phy = le16toh(rxwi->phy); 1296 switch (phy & RT2860_PHY_MODE) { 1297 case RT2860_PHY_CCK: 1298 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1299 case 0: tap->wr_rate = 2; break; 1300 case 1: tap->wr_rate = 4; break; 1301 case 2: tap->wr_rate = 11; break; 1302 case 3: tap->wr_rate = 22; break; 1303 } 1304 if (phy & RT2860_PHY_SHPRE) 1305 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1306 break; 1307 case RT2860_PHY_OFDM: 1308 switch (phy & RT2860_PHY_MCS) { 1309 case 0: tap->wr_rate = 12; break; 1310 case 1: tap->wr_rate = 18; break; 1311 case 2: tap->wr_rate = 24; break; 1312 case 3: tap->wr_rate = 36; break; 1313 case 4: tap->wr_rate = 48; break; 1314 case 5: tap->wr_rate = 72; break; 1315 case 6: tap->wr_rate = 96; break; 1316 case 7: tap->wr_rate = 108; break; 1317 } 1318 break; 1319 } 1320 } 1321 1322 RAL_UNLOCK(sc); 1323 wh = mtod(m, struct ieee80211_frame *); 1324 1325 /* send the frame to the 802.11 layer */ 1326 ni = ieee80211_find_rxnode(ic, 1327 (struct ieee80211_frame_min *)wh); 1328 if (ni != NULL) { 1329 (void)ieee80211_input(ni, m, rssi - nf, nf); 1330 ieee80211_free_node(ni); 1331 } else 1332 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1333 1334 RAL_LOCK(sc); 1335 1336 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1337 1338 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1339 BUS_DMASYNC_PREWRITE); 1340 1341 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1342 } 1343 1344 /* tell HW what we have processed */ 1345 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1346 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1347 } 1348 1349 static void 1350 rt2860_tbtt_intr(struct rt2860_softc *sc) 1351 { 1352 #if 0 1353 struct ieee80211com *ic = &sc->sc_ic; 1354 1355 #ifndef IEEE80211_STA_ONLY 1356 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1357 /* one less beacon until next DTIM */ 1358 if (ic->ic_dtim_count == 0) 1359 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1360 else 1361 ic->ic_dtim_count--; 1362 1363 /* update dynamic parts of beacon */ 1364 rt2860_setup_beacon(sc); 1365 1366 /* flush buffered multicast frames */ 1367 if (ic->ic_dtim_count == 0) 1368 ieee80211_notify_dtim(ic); 1369 } 1370 #endif 1371 /* check if protection mode has changed */ 1372 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1373 rt2860_updateprot(sc); 1374 sc->sc_ic_flags = ic->ic_flags; 1375 } 1376 #endif 1377 } 1378 1379 static void 1380 rt2860_gp_intr(struct rt2860_softc *sc) 1381 { 1382 struct ieee80211com *ic = &sc->sc_ic; 1383 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1384 1385 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1386 1387 if (vap->iv_state == IEEE80211_S_RUN) 1388 rt2860_updatestats(sc); 1389 } 1390 1391 void 1392 rt2860_intr(void *arg) 1393 { 1394 struct rt2860_softc *sc = arg; 1395 uint32_t r; 1396 1397 RAL_LOCK(sc); 1398 1399 r = RAL_READ(sc, RT2860_INT_STATUS); 1400 if (__predict_false(r == 0xffffffff)) { 1401 RAL_UNLOCK(sc); 1402 return; /* device likely went away */ 1403 } 1404 if (r == 0) { 1405 RAL_UNLOCK(sc); 1406 return; /* not for us */ 1407 } 1408 1409 /* acknowledge interrupts */ 1410 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1411 1412 if (r & RT2860_TX_RX_COHERENT) 1413 rt2860_intr_coherent(sc); 1414 1415 if (r & RT2860_MAC_INT_2) /* TX status */ 1416 rt2860_drain_stats_fifo(sc); 1417 1418 if (r & RT2860_TX_DONE_INT5) 1419 rt2860_tx_intr(sc, 5); 1420 1421 if (r & RT2860_RX_DONE_INT) 1422 rt2860_rx_intr(sc); 1423 1424 if (r & RT2860_TX_DONE_INT4) 1425 rt2860_tx_intr(sc, 4); 1426 1427 if (r & RT2860_TX_DONE_INT3) 1428 rt2860_tx_intr(sc, 3); 1429 1430 if (r & RT2860_TX_DONE_INT2) 1431 rt2860_tx_intr(sc, 2); 1432 1433 if (r & RT2860_TX_DONE_INT1) 1434 rt2860_tx_intr(sc, 1); 1435 1436 if (r & RT2860_TX_DONE_INT0) 1437 rt2860_tx_intr(sc, 0); 1438 1439 if (r & RT2860_MAC_INT_0) /* TBTT */ 1440 rt2860_tbtt_intr(sc); 1441 1442 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1443 /* TBD wakeup */; 1444 1445 if (r & RT2860_MAC_INT_4) /* GP timer */ 1446 rt2860_gp_intr(sc); 1447 1448 RAL_UNLOCK(sc); 1449 } 1450 1451 static int 1452 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1453 { 1454 struct ieee80211com *ic = &sc->sc_ic; 1455 struct ieee80211vap *vap = ni->ni_vap; 1456 struct rt2860_tx_ring *ring; 1457 struct rt2860_tx_data *data; 1458 struct rt2860_txd *txd; 1459 struct rt2860_txwi *txwi; 1460 struct ieee80211_frame *wh; 1461 const struct ieee80211_txparam *tp = ni->ni_txparms; 1462 struct ieee80211_key *k; 1463 struct mbuf *m1; 1464 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1465 bus_dma_segment_t *seg; 1466 u_int hdrlen; 1467 uint16_t qos, dur; 1468 uint8_t type, qsel, mcs, pid, qid; 1469 int i, nsegs, ntxds, pad, rate, ridx, error; 1470 1471 /* the data pool contains at least one element, pick the first */ 1472 data = SLIST_FIRST(&sc->data_pool); 1473 1474 wh = mtod(m, struct ieee80211_frame *); 1475 1476 ieee80211_output_seqno_assign(ni, -1, m); 1477 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1478 k = ieee80211_crypto_encap(ni, m); 1479 if (k == NULL) { 1480 m_freem(m); 1481 return ENOBUFS; 1482 } 1483 1484 /* packet header may have moved, reset our local pointer */ 1485 wh = mtod(m, struct ieee80211_frame *); 1486 } 1487 1488 hdrlen = ieee80211_anyhdrsize(wh); 1489 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1490 1491 if (m->m_flags & M_EAPOL) { 1492 rate = tp->mgmtrate; 1493 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1494 rate = tp->mcastrate; 1495 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1496 rate = tp->ucastrate; 1497 } else { 1498 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1499 rate = ieee80211_node_get_txrate_dot11rate(ni); 1500 } 1501 rate &= IEEE80211_RATE_VAL; 1502 1503 qid = M_WME_GETAC(m); 1504 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1505 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1506 } else { 1507 qos = 0; 1508 } 1509 ring = &sc->txq[qid]; 1510 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1511 1512 /* get MCS code from rate index */ 1513 mcs = rt2860_rates[ridx].mcs; 1514 1515 /* setup TX Wireless Information */ 1516 txwi = data->txwi; 1517 txwi->flags = 0; 1518 /* let HW generate seq numbers for non-QoS frames */ 1519 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1520 if (type == IEEE80211_FC0_TYPE_DATA) 1521 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1522 else 1523 txwi->wcid = 0xff; 1524 txwi->len = htole16(m->m_pkthdr.len); 1525 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1526 txwi->phy = htole16(RT2860_PHY_CCK); 1527 if (ridx != RT2860_RIDX_CCK1 && 1528 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1529 mcs |= RT2860_PHY_SHPRE; 1530 } else 1531 txwi->phy = htole16(RT2860_PHY_OFDM); 1532 txwi->phy |= htole16(mcs); 1533 1534 /* 1535 * We store the MCS code into the driver-private PacketID field. 1536 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1537 * that we know at which initial rate the frame was transmitted. 1538 * We add 1 to the MCS code because setting the PacketID field to 1539 * 0 means that we don't want feedback in TX_STAT_FIFO. 1540 */ 1541 pid = (mcs + 1) & 0xf; 1542 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1543 1544 /* check if RTS/CTS or CTS-to-self protection is required */ 1545 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1546 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1547 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1548 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1549 txwi->txop = RT2860_TX_TXOP_HT; 1550 else 1551 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1552 1553 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1554 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1555 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1556 txwi->xflags |= RT2860_TX_ACK; 1557 1558 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1559 dur = rt2860_rates[ridx].sp_ack_dur; 1560 else 1561 dur = rt2860_rates[ridx].lp_ack_dur; 1562 *(uint16_t *)wh->i_dur = htole16(dur); 1563 } 1564 /* ask MAC to insert timestamp into probe responses */ 1565 if (IEEE80211_IS_MGMT_PROBE_RESP(wh)) 1566 /* NOTE: beacons do not pass through tx_data() */ 1567 txwi->flags |= RT2860_TX_TS; 1568 1569 if (ieee80211_radiotap_active_vap(vap)) { 1570 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1571 1572 tap->wt_flags = 0; 1573 tap->wt_rate = rate; 1574 if (mcs & RT2860_PHY_SHPRE) 1575 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1576 1577 ieee80211_radiotap_tx(vap, m); 1578 } 1579 1580 pad = (hdrlen + 3) & ~3; 1581 1582 /* copy and trim 802.11 header */ 1583 memcpy(txwi + 1, wh, hdrlen); 1584 m_adj(m, hdrlen); 1585 1586 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1587 &nsegs, 0); 1588 if (__predict_false(error != 0 && error != EFBIG)) { 1589 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1590 error); 1591 m_freem(m); 1592 return error; 1593 } 1594 if (__predict_true(error == 0)) { 1595 /* determine how many TXDs are required */ 1596 ntxds = 1 + (nsegs / 2); 1597 1598 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1599 /* not enough free TXDs, force mbuf defrag */ 1600 bus_dmamap_unload(sc->txwi_dmat, data->map); 1601 error = EFBIG; 1602 } 1603 } 1604 if (__predict_false(error != 0)) { 1605 m1 = m_defrag(m, M_NOWAIT); 1606 if (m1 == NULL) { 1607 device_printf(sc->sc_dev, 1608 "could not defragment mbuf\n"); 1609 m_freem(m); 1610 return ENOBUFS; 1611 } 1612 m = m1; 1613 1614 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1615 segs, &nsegs, 0); 1616 if (__predict_false(error != 0)) { 1617 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1618 error); 1619 m_freem(m); 1620 return error; 1621 } 1622 1623 /* determine how many TXDs are now required */ 1624 ntxds = 1 + (nsegs / 2); 1625 1626 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1627 /* this is a hopeless case, drop the mbuf! */ 1628 bus_dmamap_unload(sc->txwi_dmat, data->map); 1629 m_freem(m); 1630 return ENOBUFS; 1631 } 1632 } 1633 1634 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1635 1636 /* first segment is TXWI + 802.11 header */ 1637 txd = &ring->txd[ring->cur]; 1638 txd->sdp0 = htole32(data->paddr); 1639 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1640 txd->flags = qsel; 1641 1642 /* setup payload segments */ 1643 seg = &segs[0]; 1644 for (i = nsegs; i >= 2; i -= 2) { 1645 txd->sdp1 = htole32(seg->ds_addr); 1646 txd->sdl1 = htole16(seg->ds_len); 1647 seg++; 1648 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1649 /* grab a new Tx descriptor */ 1650 txd = &ring->txd[ring->cur]; 1651 txd->sdp0 = htole32(seg->ds_addr); 1652 txd->sdl0 = htole16(seg->ds_len); 1653 txd->flags = qsel; 1654 seg++; 1655 } 1656 /* finalize last segment */ 1657 if (i > 0) { 1658 txd->sdp1 = htole32(seg->ds_addr); 1659 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1660 } else { 1661 txd->sdl0 |= htole16(RT2860_TX_LS0); 1662 txd->sdl1 = 0; 1663 } 1664 1665 /* remove from the free pool and link it into the SW Tx slot */ 1666 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1667 data->m = m; 1668 data->ni = ni; 1669 ring->data[ring->cur] = data; 1670 1671 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1672 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1673 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1674 1675 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1676 qid, txwi->wcid, nsegs, ridx)); 1677 1678 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1679 ring->queued += ntxds; 1680 if (ring->queued >= RT2860_TX_RING_COUNT) 1681 sc->qfullmsk |= 1 << qid; 1682 1683 /* kick Tx */ 1684 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1685 1686 return 0; 1687 } 1688 1689 static int 1690 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1691 const struct ieee80211_bpf_params *params) 1692 { 1693 struct ieee80211com *ic = ni->ni_ic; 1694 struct rt2860_softc *sc = ic->ic_softc; 1695 int error; 1696 1697 RAL_LOCK(sc); 1698 1699 /* prevent management frames from being sent if we're not ready */ 1700 if (!(sc->sc_flags & RT2860_RUNNING)) { 1701 RAL_UNLOCK(sc); 1702 m_freem(m); 1703 return ENETDOWN; 1704 } 1705 if (params == NULL) { 1706 /* 1707 * Legacy path; interpret frame contents to decide 1708 * precisely how to send the frame. 1709 */ 1710 error = rt2860_tx(sc, m, ni); 1711 } else { 1712 /* 1713 * Caller supplied explicit parameters to use in 1714 * sending the frame. 1715 */ 1716 error = rt2860_tx_raw(sc, m, ni, params); 1717 } 1718 sc->sc_tx_timer = 5; 1719 RAL_UNLOCK(sc); 1720 return error; 1721 } 1722 1723 static int 1724 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1725 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1726 { 1727 struct ieee80211com *ic = &sc->sc_ic; 1728 struct ieee80211vap *vap = ni->ni_vap; 1729 struct rt2860_tx_ring *ring; 1730 struct rt2860_tx_data *data; 1731 struct rt2860_txd *txd; 1732 struct rt2860_txwi *txwi; 1733 struct ieee80211_frame *wh; 1734 struct mbuf *m1; 1735 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1736 bus_dma_segment_t *seg; 1737 u_int hdrlen; 1738 uint16_t dur; 1739 uint8_t qsel, mcs, pid, qid; 1740 int i, nsegs, ntxds, pad, rate, ridx, error; 1741 1742 /* the data pool contains at least one element, pick the first */ 1743 data = SLIST_FIRST(&sc->data_pool); 1744 1745 wh = mtod(m, struct ieee80211_frame *); 1746 hdrlen = ieee80211_hdrsize(wh); 1747 1748 /* Choose a TX rate index. */ 1749 rate = params->ibp_rate0; 1750 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1751 rate & IEEE80211_RATE_VAL); 1752 if (ridx == (uint8_t)-1) { 1753 /* XXX fall back to mcast/mgmt rate? */ 1754 m_freem(m); 1755 return EINVAL; 1756 } 1757 1758 ieee80211_output_seqno_assign(ni, -1, m); 1759 1760 qid = params->ibp_pri & 3; 1761 ring = &sc->txq[qid]; 1762 1763 /* get MCS code from rate index */ 1764 mcs = rt2860_rates[ridx].mcs; 1765 1766 /* setup TX Wireless Information */ 1767 txwi = data->txwi; 1768 txwi->flags = 0; 1769 /* let HW generate seq numbers for non-QoS frames */ 1770 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1771 txwi->wcid = 0xff; 1772 txwi->len = htole16(m->m_pkthdr.len); 1773 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1774 txwi->phy = htole16(RT2860_PHY_CCK); 1775 if (ridx != RT2860_RIDX_CCK1 && 1776 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1777 mcs |= RT2860_PHY_SHPRE; 1778 } else 1779 txwi->phy = htole16(RT2860_PHY_OFDM); 1780 txwi->phy |= htole16(mcs); 1781 1782 /* 1783 * We store the MCS code into the driver-private PacketID field. 1784 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1785 * that we know at which initial rate the frame was transmitted. 1786 * We add 1 to the MCS code because setting the PacketID field to 1787 * 0 means that we don't want feedback in TX_STAT_FIFO. 1788 */ 1789 pid = (mcs + 1) & 0xf; 1790 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1791 1792 /* check if RTS/CTS or CTS-to-self protection is required */ 1793 if (params->ibp_flags & IEEE80211_BPF_RTS || 1794 params->ibp_flags & IEEE80211_BPF_CTS) 1795 txwi->txop = RT2860_TX_TXOP_HT; 1796 else 1797 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1798 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1799 txwi->xflags |= RT2860_TX_ACK; 1800 1801 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1802 dur = rt2860_rates[ridx].sp_ack_dur; 1803 else 1804 dur = rt2860_rates[ridx].lp_ack_dur; 1805 *(uint16_t *)wh->i_dur = htole16(dur); 1806 } 1807 /* ask MAC to insert timestamp into probe responses */ 1808 if (IEEE80211_IS_MGMT_PROBE_RESP(wh)) 1809 /* NOTE: beacons do not pass through tx_data() */ 1810 txwi->flags |= RT2860_TX_TS; 1811 1812 if (ieee80211_radiotap_active_vap(vap)) { 1813 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1814 1815 tap->wt_flags = 0; 1816 tap->wt_rate = rate; 1817 if (mcs & RT2860_PHY_SHPRE) 1818 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1819 1820 ieee80211_radiotap_tx(vap, m); 1821 } 1822 1823 pad = (hdrlen + 3) & ~3; 1824 1825 /* copy and trim 802.11 header */ 1826 memcpy(txwi + 1, wh, hdrlen); 1827 m_adj(m, hdrlen); 1828 1829 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1830 &nsegs, 0); 1831 if (__predict_false(error != 0 && error != EFBIG)) { 1832 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1833 error); 1834 m_freem(m); 1835 return error; 1836 } 1837 if (__predict_true(error == 0)) { 1838 /* determine how many TXDs are required */ 1839 ntxds = 1 + (nsegs / 2); 1840 1841 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1842 /* not enough free TXDs, force mbuf defrag */ 1843 bus_dmamap_unload(sc->txwi_dmat, data->map); 1844 error = EFBIG; 1845 } 1846 } 1847 if (__predict_false(error != 0)) { 1848 m1 = m_defrag(m, M_NOWAIT); 1849 if (m1 == NULL) { 1850 device_printf(sc->sc_dev, 1851 "could not defragment mbuf\n"); 1852 m_freem(m); 1853 return ENOBUFS; 1854 } 1855 m = m1; 1856 1857 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1858 segs, &nsegs, 0); 1859 if (__predict_false(error != 0)) { 1860 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1861 error); 1862 m_freem(m); 1863 return error; 1864 } 1865 1866 /* determine how many TXDs are now required */ 1867 ntxds = 1 + (nsegs / 2); 1868 1869 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1870 /* this is a hopeless case, drop the mbuf! */ 1871 bus_dmamap_unload(sc->txwi_dmat, data->map); 1872 m_freem(m); 1873 return ENOBUFS; 1874 } 1875 } 1876 1877 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1878 1879 /* first segment is TXWI + 802.11 header */ 1880 txd = &ring->txd[ring->cur]; 1881 txd->sdp0 = htole32(data->paddr); 1882 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1883 txd->flags = qsel; 1884 1885 /* setup payload segments */ 1886 seg = &segs[0]; 1887 for (i = nsegs; i >= 2; i -= 2) { 1888 txd->sdp1 = htole32(seg->ds_addr); 1889 txd->sdl1 = htole16(seg->ds_len); 1890 seg++; 1891 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1892 /* grab a new Tx descriptor */ 1893 txd = &ring->txd[ring->cur]; 1894 txd->sdp0 = htole32(seg->ds_addr); 1895 txd->sdl0 = htole16(seg->ds_len); 1896 txd->flags = qsel; 1897 seg++; 1898 } 1899 /* finalize last segment */ 1900 if (i > 0) { 1901 txd->sdp1 = htole32(seg->ds_addr); 1902 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1903 } else { 1904 txd->sdl0 |= htole16(RT2860_TX_LS0); 1905 txd->sdl1 = 0; 1906 } 1907 1908 /* remove from the free pool and link it into the SW Tx slot */ 1909 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1910 data->m = m; 1911 data->ni = ni; 1912 ring->data[ring->cur] = data; 1913 1914 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1915 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1916 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1917 1918 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1919 qid, txwi->wcid, nsegs, ridx)); 1920 1921 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1922 ring->queued += ntxds; 1923 if (ring->queued >= RT2860_TX_RING_COUNT) 1924 sc->qfullmsk |= 1 << qid; 1925 1926 /* kick Tx */ 1927 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1928 1929 return 0; 1930 } 1931 1932 static int 1933 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1934 { 1935 struct rt2860_softc *sc = ic->ic_softc; 1936 int error; 1937 1938 RAL_LOCK(sc); 1939 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 1940 RAL_UNLOCK(sc); 1941 return (ENXIO); 1942 } 1943 error = mbufq_enqueue(&sc->sc_snd, m); 1944 if (error) { 1945 RAL_UNLOCK(sc); 1946 return (error); 1947 } 1948 rt2860_start(sc); 1949 RAL_UNLOCK(sc); 1950 1951 return (0); 1952 } 1953 1954 static void 1955 rt2860_start(struct rt2860_softc *sc) 1956 { 1957 struct ieee80211_node *ni; 1958 struct mbuf *m; 1959 1960 RAL_LOCK_ASSERT(sc); 1961 1962 if ((sc->sc_flags & RT2860_RUNNING) == 0) 1963 return; 1964 1965 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1966 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1967 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1968 if (rt2860_tx(sc, m, ni) != 0) { 1969 if_inc_counter(ni->ni_vap->iv_ifp, 1970 IFCOUNTER_OERRORS, 1); 1971 ieee80211_free_node(ni); 1972 continue; 1973 } 1974 sc->sc_tx_timer = 5; 1975 } 1976 } 1977 1978 static void 1979 rt2860_watchdog(void *arg) 1980 { 1981 struct rt2860_softc *sc = arg; 1982 1983 RAL_LOCK_ASSERT(sc); 1984 1985 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 1986 1987 if (sc->sc_invalid) /* card ejected */ 1988 return; 1989 1990 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1991 device_printf(sc->sc_dev, "device timeout\n"); 1992 rt2860_stop_locked(sc); 1993 rt2860_init_locked(sc); 1994 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1995 return; 1996 } 1997 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 1998 } 1999 2000 static void 2001 rt2860_parent(struct ieee80211com *ic) 2002 { 2003 struct rt2860_softc *sc = ic->ic_softc; 2004 int startall = 0; 2005 2006 RAL_LOCK(sc); 2007 if (ic->ic_nrunning> 0) { 2008 if (!(sc->sc_flags & RT2860_RUNNING)) { 2009 rt2860_init_locked(sc); 2010 startall = 1; 2011 } else 2012 rt2860_update_promisc(ic); 2013 } else if (sc->sc_flags & RT2860_RUNNING) 2014 rt2860_stop_locked(sc); 2015 RAL_UNLOCK(sc); 2016 if (startall) 2017 ieee80211_start_all(ic); 2018 } 2019 2020 /* 2021 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2022 * We access the BBP through the 8051 microcontroller unit which means that 2023 * the microcode must be loaded first. 2024 */ 2025 void 2026 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2027 { 2028 int ntries; 2029 2030 for (ntries = 0; ntries < 100; ntries++) { 2031 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2032 break; 2033 DELAY(1); 2034 } 2035 if (ntries == 100) { 2036 device_printf(sc->sc_dev, 2037 "could not write to BBP through MCU\n"); 2038 return; 2039 } 2040 2041 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2042 RT2860_BBP_CSR_KICK | reg << 8 | val); 2043 RAL_BARRIER_WRITE(sc); 2044 2045 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2046 DELAY(1000); 2047 } 2048 2049 uint8_t 2050 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2051 { 2052 uint32_t val; 2053 int ntries; 2054 2055 for (ntries = 0; ntries < 100; ntries++) { 2056 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2057 break; 2058 DELAY(1); 2059 } 2060 if (ntries == 100) { 2061 device_printf(sc->sc_dev, 2062 "could not read from BBP through MCU\n"); 2063 return 0; 2064 } 2065 2066 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2067 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2068 RAL_BARRIER_WRITE(sc); 2069 2070 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2071 DELAY(1000); 2072 2073 for (ntries = 0; ntries < 100; ntries++) { 2074 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2075 if (!(val & RT2860_BBP_CSR_KICK)) 2076 return val & 0xff; 2077 DELAY(1); 2078 } 2079 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2080 2081 return 0; 2082 } 2083 2084 /* 2085 * Write to one of the 4 programmable 24-bit RF registers. 2086 */ 2087 static void 2088 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2089 { 2090 uint32_t tmp; 2091 int ntries; 2092 2093 for (ntries = 0; ntries < 100; ntries++) { 2094 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2095 break; 2096 DELAY(1); 2097 } 2098 if (ntries == 100) { 2099 device_printf(sc->sc_dev, "could not write to RF\n"); 2100 return; 2101 } 2102 2103 /* RF registers are 24-bit on the RT2860 */ 2104 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2105 (val & 0x3fffff) << 2 | (reg & 3); 2106 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2107 } 2108 2109 static uint8_t 2110 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2111 { 2112 uint32_t tmp; 2113 int ntries; 2114 2115 for (ntries = 0; ntries < 100; ntries++) { 2116 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2117 break; 2118 DELAY(1); 2119 } 2120 if (ntries == 100) { 2121 device_printf(sc->sc_dev, "could not read RF register\n"); 2122 return 0xff; 2123 } 2124 tmp = RT3070_RF_KICK | reg << 8; 2125 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2126 2127 for (ntries = 0; ntries < 100; ntries++) { 2128 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2129 if (!(tmp & RT3070_RF_KICK)) 2130 break; 2131 DELAY(1); 2132 } 2133 if (ntries == 100) { 2134 device_printf(sc->sc_dev, "could not read RF register\n"); 2135 return 0xff; 2136 } 2137 return tmp & 0xff; 2138 } 2139 2140 void 2141 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2142 { 2143 uint32_t tmp; 2144 int ntries; 2145 2146 for (ntries = 0; ntries < 10; ntries++) { 2147 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2148 break; 2149 DELAY(10); 2150 } 2151 if (ntries == 10) { 2152 device_printf(sc->sc_dev, "could not write to RF\n"); 2153 return; 2154 } 2155 2156 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2157 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2158 } 2159 2160 /* 2161 * Send a command to the 8051 microcontroller unit. 2162 */ 2163 int 2164 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2165 { 2166 int slot, ntries; 2167 uint32_t tmp; 2168 uint8_t cid; 2169 2170 for (ntries = 0; ntries < 100; ntries++) { 2171 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2172 break; 2173 DELAY(2); 2174 } 2175 if (ntries == 100) 2176 return EIO; 2177 2178 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2179 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2180 RAL_BARRIER_WRITE(sc); 2181 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2182 2183 if (!wait) 2184 return 0; 2185 /* wait for the command to complete */ 2186 for (ntries = 0; ntries < 200; ntries++) { 2187 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2188 /* find the command slot */ 2189 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2190 if ((tmp & 0xff) == cid) 2191 break; 2192 if (slot < 4) 2193 break; 2194 DELAY(100); 2195 } 2196 if (ntries == 200) { 2197 /* clear command and status */ 2198 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2199 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2200 return ETIMEDOUT; 2201 } 2202 /* get command status (1 means success) */ 2203 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2204 tmp = (tmp >> (slot * 8)) & 0xff; 2205 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2206 cmd, slot, tmp)); 2207 /* clear command and status */ 2208 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2209 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2210 return (tmp == 1) ? 0 : EIO; 2211 } 2212 2213 static void 2214 rt2860_enable_mrr(struct rt2860_softc *sc) 2215 { 2216 #define CCK(mcs) (mcs) 2217 #define OFDM(mcs) (1U << 3 | (mcs)) 2218 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2219 OFDM(6) << 28 | /* 54->48 */ 2220 OFDM(5) << 24 | /* 48->36 */ 2221 OFDM(4) << 20 | /* 36->24 */ 2222 OFDM(3) << 16 | /* 24->18 */ 2223 OFDM(2) << 12 | /* 18->12 */ 2224 OFDM(1) << 8 | /* 12-> 9 */ 2225 OFDM(0) << 4 | /* 9-> 6 */ 2226 OFDM(0)); /* 6-> 6 */ 2227 2228 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2229 CCK(2) << 12 | /* 11->5.5 */ 2230 CCK(1) << 8 | /* 5.5-> 2 */ 2231 CCK(0) << 4 | /* 2-> 1 */ 2232 CCK(0)); /* 1-> 1 */ 2233 #undef OFDM 2234 #undef CCK 2235 } 2236 2237 static void 2238 rt2860_set_txpreamble(struct rt2860_softc *sc) 2239 { 2240 struct ieee80211com *ic = &sc->sc_ic; 2241 uint32_t tmp; 2242 2243 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2244 tmp &= ~RT2860_CCK_SHORT_EN; 2245 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2246 tmp |= RT2860_CCK_SHORT_EN; 2247 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2248 } 2249 2250 void 2251 rt2860_set_basicrates(struct rt2860_softc *sc, 2252 const struct ieee80211_rateset *rs) 2253 { 2254 struct ieee80211com *ic = &sc->sc_ic; 2255 uint32_t mask = 0; 2256 uint8_t rate; 2257 int i; 2258 2259 for (i = 0; i < rs->rs_nrates; i++) { 2260 rate = rs->rs_rates[i]; 2261 2262 if (!(rate & IEEE80211_RATE_BASIC)) 2263 continue; 2264 2265 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2266 IEEE80211_RV(rate)); 2267 } 2268 2269 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2270 } 2271 2272 static void 2273 rt2860_scan_start(struct ieee80211com *ic) 2274 { 2275 struct rt2860_softc *sc = ic->ic_softc; 2276 uint32_t tmp; 2277 2278 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2279 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2280 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2281 RT2860_TBTT_TIMER_EN)); 2282 rt2860_set_gp_timer(sc, 0); 2283 } 2284 2285 static void 2286 rt2860_scan_end(struct ieee80211com *ic) 2287 { 2288 struct rt2860_softc *sc = ic->ic_softc; 2289 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2290 2291 if (vap->iv_state == IEEE80211_S_RUN) { 2292 rt2860_enable_tsf_sync(sc); 2293 rt2860_set_gp_timer(sc, 500); 2294 } 2295 } 2296 2297 static void 2298 rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, 2299 struct ieee80211_channel chans[]) 2300 { 2301 struct rt2860_softc *sc = ic->ic_softc; 2302 uint8_t bands[IEEE80211_MODE_BYTES]; 2303 2304 memset(bands, 0, sizeof(bands)); 2305 setbit(bands, IEEE80211_MODE_11B); 2306 setbit(bands, IEEE80211_MODE_11G); 2307 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2308 2309 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 2310 setbit(bands, IEEE80211_MODE_11A); 2311 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2312 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0); 2313 } 2314 } 2315 2316 static void 2317 rt2860_set_channel(struct ieee80211com *ic) 2318 { 2319 struct rt2860_softc *sc = ic->ic_softc; 2320 2321 RAL_LOCK(sc); 2322 rt2860_switch_chan(sc, ic->ic_curchan); 2323 RAL_UNLOCK(sc); 2324 } 2325 2326 static void 2327 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2328 { 2329 uint32_t tmp; 2330 uint8_t agc; 2331 2332 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2333 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2334 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2335 rt2860_mcu_bbp_write(sc, 86, 0x00); 2336 2337 if (group == 0) { 2338 if (sc->ext_2ghz_lna) { 2339 rt2860_mcu_bbp_write(sc, 82, 0x62); 2340 rt2860_mcu_bbp_write(sc, 75, 0x46); 2341 } else { 2342 rt2860_mcu_bbp_write(sc, 82, 0x84); 2343 rt2860_mcu_bbp_write(sc, 75, 0x50); 2344 } 2345 } else { 2346 if (sc->ext_5ghz_lna) { 2347 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2348 rt2860_mcu_bbp_write(sc, 75, 0x46); 2349 } else { 2350 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2351 rt2860_mcu_bbp_write(sc, 75, 0x50); 2352 } 2353 } 2354 2355 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2356 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2357 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2358 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2359 2360 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2361 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2362 if (sc->nrxchains > 1) 2363 tmp |= RT2860_LNA_PE1_EN; 2364 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2365 tmp |= RT3593_LNA_PE2_EN; 2366 if (group == 0) { /* 2GHz */ 2367 tmp |= RT2860_PA_PE_G0_EN; 2368 if (sc->ntxchains > 1) 2369 tmp |= RT2860_PA_PE_G1_EN; 2370 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2371 tmp |= RT3593_PA_PE_G2_EN; 2372 } else { /* 5GHz */ 2373 tmp |= RT2860_PA_PE_A0_EN; 2374 if (sc->ntxchains > 1) 2375 tmp |= RT2860_PA_PE_A1_EN; 2376 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2377 tmp |= RT3593_PA_PE_A2_EN; 2378 } 2379 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2380 2381 if (sc->mac_ver == 0x3593) { 2382 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2383 if (sc->sc_flags & RT2860_PCIE) { 2384 tmp &= ~0x01010000; 2385 if (group == 0) 2386 tmp |= 0x00010000; 2387 } else { 2388 tmp &= ~0x00008080; 2389 if (group == 0) 2390 tmp |= 0x00000080; 2391 } 2392 tmp = (tmp & ~0x00001000) | 0x00000010; 2393 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2394 } 2395 2396 /* set initial AGC value */ 2397 if (group == 0) { /* 2GHz band */ 2398 if (sc->mac_ver >= 0x3071) 2399 agc = 0x1c + sc->lna[0] * 2; 2400 else 2401 agc = 0x2e + sc->lna[0]; 2402 } else { /* 5GHz band */ 2403 agc = 0x32 + (sc->lna[group] * 5) / 3; 2404 } 2405 rt2860_mcu_bbp_write(sc, 66, agc); 2406 2407 DELAY(1000); 2408 } 2409 2410 static void 2411 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2412 { 2413 const struct rfprog *rfprog = rt2860_rf2850; 2414 uint32_t r2, r3, r4; 2415 int8_t txpow1, txpow2; 2416 u_int i; 2417 2418 /* find the settings for this channel (we know it exists) */ 2419 for (i = 0; rfprog[i].chan != chan; i++); 2420 2421 r2 = rfprog[i].r2; 2422 if (sc->ntxchains == 1) 2423 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2424 if (sc->nrxchains == 1) 2425 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2426 else if (sc->nrxchains == 2) 2427 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2428 2429 /* use Tx power values from EEPROM */ 2430 txpow1 = sc->txpow1[i]; 2431 txpow2 = sc->txpow2[i]; 2432 if (chan > 14) { 2433 if (txpow1 >= 0) 2434 txpow1 = txpow1 << 1 | 1; 2435 else 2436 txpow1 = (7 + txpow1) << 1; 2437 if (txpow2 >= 0) 2438 txpow2 = txpow2 << 1 | 1; 2439 else 2440 txpow2 = (7 + txpow2) << 1; 2441 } 2442 r3 = rfprog[i].r3 | txpow1 << 7; 2443 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2444 2445 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2446 rt2860_rf_write(sc, RT2860_RF2, r2); 2447 rt2860_rf_write(sc, RT2860_RF3, r3); 2448 rt2860_rf_write(sc, RT2860_RF4, r4); 2449 2450 DELAY(200); 2451 2452 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2453 rt2860_rf_write(sc, RT2860_RF2, r2); 2454 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2455 rt2860_rf_write(sc, RT2860_RF4, r4); 2456 2457 DELAY(200); 2458 2459 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2460 rt2860_rf_write(sc, RT2860_RF2, r2); 2461 rt2860_rf_write(sc, RT2860_RF3, r3); 2462 rt2860_rf_write(sc, RT2860_RF4, r4); 2463 } 2464 2465 static void 2466 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2467 { 2468 int8_t txpow1, txpow2; 2469 uint8_t rf; 2470 int i; 2471 2472 /* RT3090 is 2GHz only */ 2473 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2474 2475 /* find the settings for this channel (we know it exists) */ 2476 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2477 2478 /* use Tx power values from EEPROM */ 2479 txpow1 = sc->txpow1[i]; 2480 txpow2 = sc->txpow2[i]; 2481 2482 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2483 rf = rt3090_rf_read(sc, 3); 2484 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2485 rt3090_rf_write(sc, 3, rf); 2486 rf = rt3090_rf_read(sc, 6); 2487 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2488 rt3090_rf_write(sc, 6, rf); 2489 2490 /* set Tx0 power */ 2491 rf = rt3090_rf_read(sc, 12); 2492 rf = (rf & ~0x1f) | txpow1; 2493 rt3090_rf_write(sc, 12, rf); 2494 2495 /* set Tx1 power */ 2496 rf = rt3090_rf_read(sc, 13); 2497 rf = (rf & ~0x1f) | txpow2; 2498 rt3090_rf_write(sc, 13, rf); 2499 2500 rf = rt3090_rf_read(sc, 1); 2501 rf &= ~0xfc; 2502 if (sc->ntxchains == 1) 2503 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2504 else if (sc->ntxchains == 2) 2505 rf |= RT3070_TX2_PD; 2506 if (sc->nrxchains == 1) 2507 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2508 else if (sc->nrxchains == 2) 2509 rf |= RT3070_RX2_PD; 2510 rt3090_rf_write(sc, 1, rf); 2511 2512 /* set RF offset */ 2513 rf = rt3090_rf_read(sc, 23); 2514 rf = (rf & ~0x7f) | sc->freq; 2515 rt3090_rf_write(sc, 23, rf); 2516 2517 /* program RF filter */ 2518 rf = rt3090_rf_read(sc, 24); /* Tx */ 2519 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2520 rt3090_rf_write(sc, 24, rf); 2521 rf = rt3090_rf_read(sc, 31); /* Rx */ 2522 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2523 rt3090_rf_write(sc, 31, rf); 2524 2525 /* enable RF tuning */ 2526 rf = rt3090_rf_read(sc, 7); 2527 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2528 } 2529 2530 static void 2531 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2532 { 2533 uint8_t h20mhz, rf, tmp; 2534 int8_t txpow1, txpow2; 2535 int i; 2536 2537 /* RT5390 is 2GHz only */ 2538 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2539 2540 /* find the settings for this channel (we know it exists) */ 2541 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2542 2543 /* use Tx power values from EEPROM */ 2544 txpow1 = sc->txpow1[i]; 2545 txpow2 = sc->txpow2[i]; 2546 2547 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2548 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2549 rf = rt3090_rf_read(sc, 11); 2550 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2551 rt3090_rf_write(sc, 11, rf); 2552 2553 rf = rt3090_rf_read(sc, 49); 2554 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2555 /* the valid range of the RF R49 is 0x00~0x27 */ 2556 if ((rf & 0x3f) > 0x27) 2557 rf = (rf & ~0x3f) | 0x27; 2558 rt3090_rf_write(sc, 49, rf); 2559 if (sc->mac_ver == 0x5392) { 2560 rf = rt3090_rf_read(sc, 50); 2561 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2562 /* the valid range of the RF R50 is 0x00~0x27 */ 2563 if ((rf & 0x3f) > 0x27) 2564 rf = (rf & ~0x3f) | 0x27; 2565 rt3090_rf_write(sc, 50, rf); 2566 } 2567 2568 rf = rt3090_rf_read(sc, 1); 2569 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2570 if (sc->mac_ver == 0x5392) 2571 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2572 rt3090_rf_write(sc, 1, rf); 2573 2574 rf = rt3090_rf_read(sc, 2); 2575 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2576 DELAY(1000); 2577 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2578 2579 rf = rt3090_rf_read(sc, 17); 2580 tmp = rf; 2581 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2582 rf = MIN(rf, 0x5f); 2583 if (tmp != rf) 2584 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2585 2586 if (sc->mac_ver == 0x5390) { 2587 if (chan <= 4) 2588 rf = 0x73; 2589 else if (chan >= 5 && chan <= 6) 2590 rf = 0x63; 2591 else if (chan >= 7 && chan <= 10) 2592 rf = 0x53; 2593 else 2594 rf = 43; 2595 rt3090_rf_write(sc, 55, rf); 2596 2597 if (chan == 1) 2598 rf = 0x0c; 2599 else if (chan == 2) 2600 rf = 0x0b; 2601 else if (chan == 3) 2602 rf = 0x0a; 2603 else if (chan >= 4 && chan <= 6) 2604 rf = 0x09; 2605 else if (chan >= 7 && chan <= 12) 2606 rf = 0x08; 2607 else if (chan == 13) 2608 rf = 0x07; 2609 else 2610 rf = 0x06; 2611 rt3090_rf_write(sc, 59, rf); 2612 } 2613 2614 /* Tx/Rx h20M */ 2615 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2616 rf = rt3090_rf_read(sc, 30); 2617 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2618 rt3090_rf_write(sc, 30, rf); 2619 2620 /* Rx BB filter VCM */ 2621 rf = rt3090_rf_read(sc, 30); 2622 rf = (rf & ~0x18) | 0x10; 2623 rt3090_rf_write(sc, 30, rf); 2624 2625 /* Initiate VCO calibration. */ 2626 rf = rt3090_rf_read(sc, 3); 2627 rf |= RT3593_VCOCAL; 2628 rt3090_rf_write(sc, 3, rf); 2629 } 2630 2631 static int 2632 rt3090_rf_init(struct rt2860_softc *sc) 2633 { 2634 uint32_t tmp; 2635 uint8_t rf, bbp; 2636 int i; 2637 2638 rf = rt3090_rf_read(sc, 30); 2639 /* toggle RF R30 bit 7 */ 2640 rt3090_rf_write(sc, 30, rf | 0x80); 2641 DELAY(1000); 2642 rt3090_rf_write(sc, 30, rf & ~0x80); 2643 2644 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2645 tmp &= ~0x1f000000; 2646 if (sc->patch_dac && sc->mac_rev < 0x0211) 2647 tmp |= 0x0d000000; /* 1.35V */ 2648 else 2649 tmp |= 0x01000000; /* 1.2V */ 2650 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2651 2652 /* patch LNA_PE_G1 */ 2653 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2654 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2655 2656 /* initialize RF registers to default value */ 2657 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2658 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2659 rt3090_def_rf[i].val); 2660 } 2661 2662 /* select 20MHz bandwidth */ 2663 rt3090_rf_write(sc, 31, 0x14); 2664 2665 rf = rt3090_rf_read(sc, 6); 2666 rt3090_rf_write(sc, 6, rf | 0x40); 2667 2668 if (sc->mac_ver != 0x3593) { 2669 /* calibrate filter for 20MHz bandwidth */ 2670 sc->rf24_20mhz = 0x1f; /* default value */ 2671 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2672 2673 /* select 40MHz bandwidth */ 2674 bbp = rt2860_mcu_bbp_read(sc, 4); 2675 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2676 rf = rt3090_rf_read(sc, 31); 2677 rt3090_rf_write(sc, 31, rf | 0x20); 2678 2679 /* calibrate filter for 40MHz bandwidth */ 2680 sc->rf24_40mhz = 0x2f; /* default value */ 2681 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2682 2683 /* go back to 20MHz bandwidth */ 2684 bbp = rt2860_mcu_bbp_read(sc, 4); 2685 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2686 } 2687 if (sc->mac_rev < 0x0211) 2688 rt3090_rf_write(sc, 27, 0x03); 2689 2690 tmp = RAL_READ(sc, RT3070_OPT_14); 2691 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2692 2693 if (sc->rf_rev == RT3070_RF_3020) 2694 rt3090_set_rx_antenna(sc, 0); 2695 2696 bbp = rt2860_mcu_bbp_read(sc, 138); 2697 if (sc->mac_ver == 0x3593) { 2698 if (sc->ntxchains == 1) 2699 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2700 else if (sc->ntxchains == 2) 2701 bbp |= 0x40; /* turn off DAC2 */ 2702 if (sc->nrxchains == 1) 2703 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2704 else if (sc->nrxchains == 2) 2705 bbp &= ~0x04; /* turn off ADC2 */ 2706 } else { 2707 if (sc->ntxchains == 1) 2708 bbp |= 0x20; /* turn off DAC1 */ 2709 if (sc->nrxchains == 1) 2710 bbp &= ~0x02; /* turn off ADC1 */ 2711 } 2712 rt2860_mcu_bbp_write(sc, 138, bbp); 2713 2714 rf = rt3090_rf_read(sc, 1); 2715 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2716 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2717 rt3090_rf_write(sc, 1, rf); 2718 2719 rf = rt3090_rf_read(sc, 15); 2720 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2721 2722 rf = rt3090_rf_read(sc, 17); 2723 rf &= ~RT3070_TX_LO1; 2724 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2725 rf |= 0x20; /* fix for long range Rx issue */ 2726 if (sc->txmixgain_2ghz >= 2) 2727 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2728 rt3090_rf_write(sc, 17, rf); 2729 2730 rf = rt3090_rf_read(sc, 20); 2731 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2732 2733 rf = rt3090_rf_read(sc, 21); 2734 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2735 2736 return (0); 2737 } 2738 2739 static void 2740 rt5390_rf_init(struct rt2860_softc *sc) 2741 { 2742 uint8_t rf, bbp; 2743 int i; 2744 2745 rf = rt3090_rf_read(sc, 2); 2746 /* Toggle RF R2 bit 7. */ 2747 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2748 DELAY(1000); 2749 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2750 2751 /* Initialize RF registers to default value. */ 2752 if (sc->mac_ver == 0x5392) { 2753 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2754 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2755 rt5392_def_rf[i].val); 2756 } 2757 } else { 2758 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2759 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2760 rt5390_def_rf[i].val); 2761 } 2762 } 2763 2764 sc->rf24_20mhz = 0x1f; 2765 sc->rf24_40mhz = 0x2f; 2766 2767 if (sc->mac_rev < 0x0211) 2768 rt3090_rf_write(sc, 27, 0x03); 2769 2770 /* Set led open drain enable. */ 2771 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2772 2773 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2774 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2775 2776 if (sc->mac_ver == 0x5390) 2777 rt3090_set_rx_antenna(sc, 0); 2778 2779 /* Patch RSSI inaccurate issue. */ 2780 rt2860_mcu_bbp_write(sc, 79, 0x13); 2781 rt2860_mcu_bbp_write(sc, 80, 0x05); 2782 rt2860_mcu_bbp_write(sc, 81, 0x33); 2783 2784 /* Enable DC filter. */ 2785 if (sc->mac_rev >= 0x0211) 2786 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2787 2788 bbp = rt2860_mcu_bbp_read(sc, 138); 2789 if (sc->ntxchains == 1) 2790 bbp |= 0x20; /* Turn off DAC1. */ 2791 if (sc->nrxchains == 1) 2792 bbp &= ~0x02; /* Turn off ADC1. */ 2793 rt2860_mcu_bbp_write(sc, 138, bbp); 2794 2795 /* Enable RX LO1 and LO2. */ 2796 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2797 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2798 2799 /* Avoid data lost and CRC error. */ 2800 rt2860_mcu_bbp_write(sc, 4, 2801 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2802 2803 rf = rt3090_rf_read(sc, 30); 2804 rf = (rf & ~0x18) | 0x10; 2805 rt3090_rf_write(sc, 30, rf); 2806 } 2807 2808 static void 2809 rt3090_rf_wakeup(struct rt2860_softc *sc) 2810 { 2811 uint32_t tmp; 2812 uint8_t rf; 2813 2814 if (sc->mac_ver == 0x3593) { 2815 /* enable VCO */ 2816 rf = rt3090_rf_read(sc, 1); 2817 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2818 2819 /* initiate VCO calibration */ 2820 rf = rt3090_rf_read(sc, 3); 2821 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2822 2823 /* enable VCO bias current control */ 2824 rf = rt3090_rf_read(sc, 6); 2825 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2826 2827 /* initiate res calibration */ 2828 rf = rt3090_rf_read(sc, 2); 2829 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2830 2831 /* set reference current control to 0.33 mA */ 2832 rf = rt3090_rf_read(sc, 22); 2833 rf &= ~RT3593_CP_IC_MASK; 2834 rf |= 1 << RT3593_CP_IC_SHIFT; 2835 rt3090_rf_write(sc, 22, rf); 2836 2837 /* enable RX CTB */ 2838 rf = rt3090_rf_read(sc, 46); 2839 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2840 2841 rf = rt3090_rf_read(sc, 20); 2842 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2843 rt3090_rf_write(sc, 20, rf); 2844 } else { 2845 /* enable RF block */ 2846 rf = rt3090_rf_read(sc, 1); 2847 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2848 2849 /* enable VCO bias current control */ 2850 rf = rt3090_rf_read(sc, 7); 2851 rt3090_rf_write(sc, 7, rf | 0x30); 2852 2853 rf = rt3090_rf_read(sc, 9); 2854 rt3090_rf_write(sc, 9, rf | 0x0e); 2855 2856 /* enable RX CTB */ 2857 rf = rt3090_rf_read(sc, 21); 2858 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2859 2860 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2861 rf = rt3090_rf_read(sc, 27); 2862 rf &= ~0x77; 2863 if (sc->mac_rev < 0x0211) 2864 rf |= 0x03; 2865 rt3090_rf_write(sc, 27, rf); 2866 } 2867 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2868 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2869 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2870 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2871 } 2872 } 2873 2874 static void 2875 rt5390_rf_wakeup(struct rt2860_softc *sc) 2876 { 2877 uint32_t tmp; 2878 uint8_t rf; 2879 2880 rf = rt3090_rf_read(sc, 1); 2881 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2882 RT3070_TX0_PD; 2883 if (sc->mac_ver == 0x5392) 2884 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2885 rt3090_rf_write(sc, 1, rf); 2886 2887 rf = rt3090_rf_read(sc, 6); 2888 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2889 if (sc->mac_ver == 0x5390) 2890 rf &= ~RT3593_VCO_IC; 2891 rt3090_rf_write(sc, 6, rf); 2892 2893 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2894 2895 rf = rt3090_rf_read(sc, 22); 2896 rf = (rf & ~0xe0) | 0x20; 2897 rt3090_rf_write(sc, 22, rf); 2898 2899 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2900 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2901 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2902 2903 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2904 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2905 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2906 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2907 } 2908 } 2909 2910 static int 2911 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2912 uint8_t *val) 2913 { 2914 uint8_t rf22, rf24; 2915 uint8_t bbp55_pb, bbp55_sb, delta; 2916 int ntries; 2917 2918 /* program filter */ 2919 rf24 = rt3090_rf_read(sc, 24); 2920 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2921 rt3090_rf_write(sc, 24, rf24); 2922 2923 /* enable baseband loopback mode */ 2924 rf22 = rt3090_rf_read(sc, 22); 2925 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2926 2927 /* set power and frequency of passband test tone */ 2928 rt2860_mcu_bbp_write(sc, 24, 0x00); 2929 for (ntries = 0; ntries < 100; ntries++) { 2930 /* transmit test tone */ 2931 rt2860_mcu_bbp_write(sc, 25, 0x90); 2932 DELAY(1000); 2933 /* read received power */ 2934 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2935 if (bbp55_pb != 0) 2936 break; 2937 } 2938 if (ntries == 100) 2939 return (ETIMEDOUT); 2940 2941 /* set power and frequency of stopband test tone */ 2942 rt2860_mcu_bbp_write(sc, 24, 0x06); 2943 for (ntries = 0; ntries < 100; ntries++) { 2944 /* transmit test tone */ 2945 rt2860_mcu_bbp_write(sc, 25, 0x90); 2946 DELAY(1000); 2947 /* read received power */ 2948 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2949 2950 delta = bbp55_pb - bbp55_sb; 2951 if (delta > target) 2952 break; 2953 2954 /* reprogram filter */ 2955 rf24++; 2956 rt3090_rf_write(sc, 24, rf24); 2957 } 2958 if (ntries < 100) { 2959 if (rf24 != init) 2960 rf24--; /* backtrack */ 2961 *val = rf24; 2962 rt3090_rf_write(sc, 24, rf24); 2963 } 2964 2965 /* restore initial state */ 2966 rt2860_mcu_bbp_write(sc, 24, 0x00); 2967 2968 /* disable baseband loopback mode */ 2969 rf22 = rt3090_rf_read(sc, 22); 2970 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2971 2972 return (0); 2973 } 2974 2975 static void 2976 rt3090_rf_setup(struct rt2860_softc *sc) 2977 { 2978 uint8_t bbp; 2979 int i; 2980 2981 if (sc->mac_rev >= 0x0211) { 2982 /* enable DC filter */ 2983 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2984 2985 /* improve power consumption */ 2986 bbp = rt2860_mcu_bbp_read(sc, 31); 2987 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2988 } 2989 2990 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2991 if (sc->mac_rev < 0x0211) { 2992 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2993 sc->patch_dac ? 0x2c : 0x0f); 2994 } else 2995 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2996 2997 /* initialize RF registers from ROM */ 2998 if (sc->mac_ver < 0x5390) { 2999 for (i = 0; i < 10; i++) { 3000 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 3001 continue; 3002 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3003 } 3004 } 3005 } 3006 3007 static void 3008 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3009 { 3010 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3011 which | (sc->leds & 0x7f), 0); 3012 } 3013 3014 /* 3015 * Hardware has a general-purpose programmable timer interrupt that can 3016 * periodically raise MAC_INT_4. 3017 */ 3018 static void 3019 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3020 { 3021 uint32_t tmp; 3022 3023 /* disable GP timer before reprogramming it */ 3024 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3025 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3026 3027 if (ms == 0) 3028 return; 3029 3030 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3031 ms *= 16; /* Unit: 64us */ 3032 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3033 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3034 3035 /* enable GP timer */ 3036 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3037 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3038 } 3039 3040 static void 3041 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3042 { 3043 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3044 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3045 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3046 bssid[4] | bssid[5] << 8); 3047 } 3048 3049 static void 3050 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3051 { 3052 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3053 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3054 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3055 addr[4] | addr[5] << 8 | 0xff << 16); 3056 } 3057 3058 static void 3059 rt2860_updateslot(struct ieee80211com *ic) 3060 { 3061 struct rt2860_softc *sc = ic->ic_softc; 3062 uint32_t tmp; 3063 3064 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3065 tmp &= ~0xff; 3066 tmp |= IEEE80211_GET_SLOTTIME(ic); 3067 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3068 } 3069 3070 static void 3071 rt2860_updateprot(struct rt2860_softc *sc) 3072 { 3073 struct ieee80211com *ic = &sc->sc_ic; 3074 uint32_t tmp; 3075 3076 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3077 /* setup protection frame rate (MCS code) */ 3078 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3079 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3080 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3081 3082 /* CCK frames don't require protection */ 3083 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3084 3085 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3086 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3087 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3088 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3089 tmp |= RT2860_PROT_CTRL_CTS; 3090 } 3091 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3092 } 3093 3094 static void 3095 rt2860_update_promisc(struct ieee80211com *ic) 3096 { 3097 struct rt2860_softc *sc = ic->ic_softc; 3098 uint32_t tmp; 3099 3100 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3101 tmp &= ~RT2860_DROP_NOT_MYBSS; 3102 if (ic->ic_promisc == 0) 3103 tmp |= RT2860_DROP_NOT_MYBSS; 3104 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3105 } 3106 3107 static int 3108 rt2860_updateedca(struct ieee80211com *ic) 3109 { 3110 struct rt2860_softc *sc = ic->ic_softc; 3111 struct chanAccParams chp; 3112 const struct wmeParams *wmep; 3113 int aci; 3114 3115 ieee80211_wme_ic_getparams(ic, &chp); 3116 3117 wmep = chp.cap_wmeParams; 3118 3119 /* update MAC TX configuration registers */ 3120 for (aci = 0; aci < WME_NUM_AC; aci++) { 3121 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3122 wmep[aci].wmep_logcwmax << 16 | 3123 wmep[aci].wmep_logcwmin << 12 | 3124 wmep[aci].wmep_aifsn << 8 | 3125 wmep[aci].wmep_txopLimit); 3126 } 3127 3128 /* update SCH/DMA registers too */ 3129 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3130 wmep[WME_AC_VO].wmep_aifsn << 12 | 3131 wmep[WME_AC_VI].wmep_aifsn << 8 | 3132 wmep[WME_AC_BK].wmep_aifsn << 4 | 3133 wmep[WME_AC_BE].wmep_aifsn); 3134 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3135 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3136 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3137 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3138 wmep[WME_AC_BE].wmep_logcwmin); 3139 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3140 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3141 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3142 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3143 wmep[WME_AC_BE].wmep_logcwmax); 3144 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3145 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3146 wmep[WME_AC_BE].wmep_txopLimit); 3147 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3148 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3149 wmep[WME_AC_VI].wmep_txopLimit); 3150 3151 return 0; 3152 } 3153 3154 #ifdef HW_CRYPTO 3155 static int 3156 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3157 struct ieee80211_key *k) 3158 { 3159 struct rt2860_softc *sc = ic->ic_softc; 3160 bus_size_t base; 3161 uint32_t attr; 3162 uint8_t mode, wcid, iv[8]; 3163 3164 /* defer setting of WEP keys until interface is brought up */ 3165 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3166 (IFF_UP | IFF_RUNNING)) 3167 return 0; 3168 3169 /* map net80211 cipher to RT2860 security mode */ 3170 switch (k->k_cipher) { 3171 case IEEE80211_CIPHER_WEP40: 3172 mode = RT2860_MODE_WEP40; 3173 break; 3174 case IEEE80211_CIPHER_WEP104: 3175 mode = RT2860_MODE_WEP104; 3176 break; 3177 case IEEE80211_CIPHER_TKIP: 3178 mode = RT2860_MODE_TKIP; 3179 break; 3180 case IEEE80211_CIPHER_CCMP: 3181 mode = RT2860_MODE_AES_CCMP; 3182 break; 3183 default: 3184 return EINVAL; 3185 } 3186 3187 if (k->k_flags & IEEE80211_KEY_GROUP) { 3188 wcid = 0; /* NB: update WCID0 for group keys */ 3189 base = RT2860_SKEY(0, k->k_id); 3190 } else { 3191 wcid = ((struct rt2860_node *)ni)->wcid; 3192 base = RT2860_PKEY(wcid); 3193 } 3194 3195 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3196 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3197 #ifndef IEEE80211_STA_ONLY 3198 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3199 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3200 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3201 } else 3202 #endif 3203 { 3204 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3205 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3206 } 3207 } else 3208 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3209 3210 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3211 (k->k_flags & IEEE80211_KEY_TX)) { 3212 /* set initial packet number in IV+EIV */ 3213 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3214 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3215 uint32_t val = arc4random(); 3216 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3217 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3218 val += 0x000100; 3219 iv[0] = val; 3220 iv[1] = val >> 8; 3221 iv[2] = val >> 16; 3222 iv[3] = k->k_id << 6; 3223 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3224 } else { 3225 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3226 iv[0] = k->k_tsc >> 8; 3227 iv[1] = (iv[0] | 0x20) & 0x7f; 3228 iv[2] = k->k_tsc; 3229 } else /* CCMP */ { 3230 iv[0] = k->k_tsc; 3231 iv[1] = k->k_tsc >> 8; 3232 iv[2] = 0; 3233 } 3234 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3235 iv[4] = k->k_tsc >> 16; 3236 iv[5] = k->k_tsc >> 24; 3237 iv[6] = k->k_tsc >> 32; 3238 iv[7] = k->k_tsc >> 40; 3239 } 3240 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3241 } 3242 3243 if (k->k_flags & IEEE80211_KEY_GROUP) { 3244 /* install group key */ 3245 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3246 attr &= ~(0xf << (k->k_id * 4)); 3247 attr |= mode << (k->k_id * 4); 3248 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3249 } else { 3250 /* install pairwise key */ 3251 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3252 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3253 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3254 } 3255 return 0; 3256 } 3257 3258 static void 3259 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3260 struct ieee80211_key *k) 3261 { 3262 struct rt2860_softc *sc = ic->ic_softc; 3263 uint32_t attr; 3264 uint8_t wcid; 3265 3266 if (k->k_flags & IEEE80211_KEY_GROUP) { 3267 /* remove group key */ 3268 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3269 attr &= ~(0xf << (k->k_id * 4)); 3270 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3271 3272 } else { 3273 /* remove pairwise key */ 3274 wcid = ((struct rt2860_node *)ni)->wcid; 3275 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3276 attr &= ~0xf; 3277 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3278 } 3279 } 3280 #endif 3281 3282 static int8_t 3283 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3284 { 3285 struct ieee80211com *ic = &sc->sc_ic; 3286 struct ieee80211_channel *c = ic->ic_curchan; 3287 int delta; 3288 3289 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3290 u_int chan = ieee80211_chan2ieee(ic, c); 3291 delta = sc->rssi_5ghz[rxchain]; 3292 3293 /* determine channel group */ 3294 if (chan <= 64) 3295 delta -= sc->lna[1]; 3296 else if (chan <= 128) 3297 delta -= sc->lna[2]; 3298 else 3299 delta -= sc->lna[3]; 3300 } else 3301 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3302 3303 return -12 - delta - rssi; 3304 } 3305 3306 /* 3307 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3308 * Used to adjust per-rate Tx power registers. 3309 */ 3310 static __inline uint32_t 3311 b4inc(uint32_t b32, int8_t delta) 3312 { 3313 int8_t i, b4; 3314 3315 for (i = 0; i < 8; i++) { 3316 b4 = b32 & 0xf; 3317 b4 += delta; 3318 if (b4 < 0) 3319 b4 = 0; 3320 else if (b4 > 0xf) 3321 b4 = 0xf; 3322 b32 = b32 >> 4 | (uint32_t)b4 << 28; 3323 } 3324 return b32; 3325 } 3326 3327 static const char * 3328 rt2860_get_rf(uint16_t rev) 3329 { 3330 switch (rev) { 3331 case RT2860_RF_2820: return "RT2820"; 3332 case RT2860_RF_2850: return "RT2850"; 3333 case RT2860_RF_2720: return "RT2720"; 3334 case RT2860_RF_2750: return "RT2750"; 3335 case RT3070_RF_3020: return "RT3020"; 3336 case RT3070_RF_2020: return "RT2020"; 3337 case RT3070_RF_3021: return "RT3021"; 3338 case RT3070_RF_3022: return "RT3022"; 3339 case RT3070_RF_3052: return "RT3052"; 3340 case RT3070_RF_3320: return "RT3320"; 3341 case RT3070_RF_3053: return "RT3053"; 3342 case RT5390_RF_5360: return "RT5360"; 3343 case RT5390_RF_5390: return "RT5390"; 3344 default: return "unknown"; 3345 } 3346 } 3347 3348 static int 3349 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3350 { 3351 int8_t delta_2ghz, delta_5ghz; 3352 uint32_t tmp; 3353 uint16_t val; 3354 int ridx, ant, i; 3355 3356 /* check whether the ROM is eFUSE ROM or EEPROM */ 3357 sc->sc_srom_read = rt2860_eeprom_read_2; 3358 if (sc->mac_ver >= 0x3071) { 3359 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3360 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3361 if (tmp & RT3070_SEL_EFUSE) 3362 sc->sc_srom_read = rt3090_efuse_read_2; 3363 } 3364 3365 #ifdef RAL_DEBUG 3366 /* read EEPROM version */ 3367 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3368 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3369 #endif 3370 3371 /* read MAC address */ 3372 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3373 macaddr[0] = val & 0xff; 3374 macaddr[1] = val >> 8; 3375 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3376 macaddr[2] = val & 0xff; 3377 macaddr[3] = val >> 8; 3378 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3379 macaddr[4] = val & 0xff; 3380 macaddr[5] = val >> 8; 3381 3382 #ifdef RAL_DEBUG 3383 /* read country code */ 3384 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3385 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3386 #endif 3387 3388 /* read vendor BBP settings */ 3389 for (i = 0; i < 8; i++) { 3390 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3391 sc->bbp[i].val = val & 0xff; 3392 sc->bbp[i].reg = val >> 8; 3393 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3394 } 3395 if (sc->mac_ver >= 0x3071) { 3396 /* read vendor RF settings */ 3397 for (i = 0; i < 10; i++) { 3398 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3399 sc->rf[i].val = val & 0xff; 3400 sc->rf[i].reg = val >> 8; 3401 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3402 sc->rf[i].val)); 3403 } 3404 } 3405 3406 /* read RF frequency offset from EEPROM */ 3407 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3408 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3409 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3410 if ((val >> 8) != 0xff) { 3411 /* read LEDs operating mode */ 3412 sc->leds = val >> 8; 3413 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3414 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3415 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3416 } else { 3417 /* broken EEPROM, use default settings */ 3418 sc->leds = 0x01; 3419 sc->led[0] = 0x5555; 3420 sc->led[1] = 0x2221; 3421 sc->led[2] = 0xa9f8; 3422 } 3423 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3424 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3425 3426 /* read RF information */ 3427 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3428 if (sc->mac_ver >= 0x5390) 3429 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3430 else 3431 sc->rf_rev = (val >> 8) & 0xf; 3432 sc->ntxchains = (val >> 4) & 0xf; 3433 sc->nrxchains = val & 0xf; 3434 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3435 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3436 3437 /* check if RF supports automatic Tx access gain control */ 3438 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3439 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3440 /* check if driver should patch the DAC issue */ 3441 if ((val >> 8) != 0xff) 3442 sc->patch_dac = (val >> 15) & 1; 3443 if ((val & 0xff) != 0xff) { 3444 sc->ext_5ghz_lna = (val >> 3) & 1; 3445 sc->ext_2ghz_lna = (val >> 2) & 1; 3446 /* check if RF supports automatic Tx access gain control */ 3447 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3448 /* check if we have a hardware radio switch */ 3449 sc->rfswitch = val & 1; 3450 } 3451 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3452 /* read PCIe power save level */ 3453 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3454 if ((val & 0xff) != 0xff) { 3455 sc->pslevel = val & 0x3; 3456 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3457 if ((val & 0xff80) != 0x9280) 3458 sc->pslevel = MIN(sc->pslevel, 1); 3459 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3460 } 3461 } 3462 3463 /* read power settings for 2GHz channels */ 3464 for (i = 0; i < 14; i += 2) { 3465 val = rt2860_srom_read(sc, 3466 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3467 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3468 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3469 3470 if (sc->mac_ver != 0x5390) { 3471 val = rt2860_srom_read(sc, 3472 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3473 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3474 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3475 } 3476 } 3477 /* fix broken Tx power entries */ 3478 for (i = 0; i < 14; i++) { 3479 if (sc->txpow1[i] < 0 || 3480 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3481 sc->txpow1[i] = 5; 3482 if (sc->mac_ver != 0x5390) { 3483 if (sc->txpow2[i] < 0 || 3484 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3485 sc->txpow2[i] = 5; 3486 } 3487 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3488 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3489 } 3490 /* read power settings for 5GHz channels */ 3491 for (i = 0; i < 40; i += 2) { 3492 val = rt2860_srom_read(sc, 3493 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3494 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3495 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3496 3497 val = rt2860_srom_read(sc, 3498 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3499 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3500 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3501 } 3502 /* fix broken Tx power entries */ 3503 for (i = 0; i < 40; i++) { 3504 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3505 sc->txpow1[14 + i] = 5; 3506 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3507 sc->txpow2[14 + i] = 5; 3508 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3509 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3510 sc->txpow2[14 + i])); 3511 } 3512 3513 /* read Tx power compensation for each Tx rate */ 3514 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3515 delta_2ghz = delta_5ghz = 0; 3516 if ((val & 0xff) != 0xff && (val & 0x80)) { 3517 delta_2ghz = val & 0xf; 3518 if (!(val & 0x40)) /* negative number */ 3519 delta_2ghz = -delta_2ghz; 3520 } 3521 val >>= 8; 3522 if ((val & 0xff) != 0xff && (val & 0x80)) { 3523 delta_5ghz = val & 0xf; 3524 if (!(val & 0x40)) /* negative number */ 3525 delta_5ghz = -delta_5ghz; 3526 } 3527 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3528 delta_2ghz, delta_5ghz)); 3529 3530 for (ridx = 0; ridx < 5; ridx++) { 3531 uint32_t reg; 3532 3533 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3534 reg = val; 3535 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3536 reg |= (uint32_t)val << 16; 3537 3538 sc->txpow20mhz[ridx] = reg; 3539 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3540 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3541 3542 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3543 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3544 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3545 } 3546 3547 /* read factory-calibrated samples for temperature compensation */ 3548 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3549 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3550 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3551 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3552 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3553 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3554 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3555 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3556 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3557 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3558 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3559 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3560 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3561 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3562 sc->step_2ghz = val >> 8; 3563 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3564 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3565 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3566 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3567 sc->tssi_2ghz[8], sc->step_2ghz)); 3568 /* check that ref value is correct, otherwise disable calibration */ 3569 if (sc->tssi_2ghz[4] == 0xff) 3570 sc->calib_2ghz = 0; 3571 3572 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3573 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3574 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3575 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3576 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3577 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3578 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3579 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3580 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3581 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3582 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3583 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3584 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3585 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3586 sc->step_5ghz = val >> 8; 3587 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3588 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3589 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3590 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3591 sc->tssi_5ghz[8], sc->step_5ghz)); 3592 /* check that ref value is correct, otherwise disable calibration */ 3593 if (sc->tssi_5ghz[4] == 0xff) 3594 sc->calib_5ghz = 0; 3595 3596 /* read RSSI offsets and LNA gains from EEPROM */ 3597 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3598 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3599 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3600 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3601 if (sc->mac_ver >= 0x3071) { 3602 /* 3603 * On RT3090 chips (limited to 2 Rx chains), this ROM 3604 * field contains the Tx mixer gain for the 2GHz band. 3605 */ 3606 if ((val & 0xff) != 0xff) 3607 sc->txmixgain_2ghz = val & 0x7; 3608 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3609 } else 3610 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3611 sc->lna[2] = val >> 8; /* channel group 2 */ 3612 3613 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3614 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3615 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3616 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3617 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3618 sc->lna[3] = val >> 8; /* channel group 3 */ 3619 3620 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3621 if (sc->mac_ver >= 0x3071) 3622 sc->lna[0] = RT3090_DEF_LNA; 3623 else /* channel group 0 */ 3624 sc->lna[0] = val & 0xff; 3625 sc->lna[1] = val >> 8; /* channel group 1 */ 3626 3627 /* fix broken 5GHz LNA entries */ 3628 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3629 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3630 sc->lna[2] = sc->lna[1]; 3631 } 3632 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3633 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3634 sc->lna[3] = sc->lna[1]; 3635 } 3636 3637 /* fix broken RSSI offset entries */ 3638 for (ant = 0; ant < 3; ant++) { 3639 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3640 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3641 ant + 1, sc->rssi_2ghz[ant])); 3642 sc->rssi_2ghz[ant] = 0; 3643 } 3644 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3645 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3646 ant + 1, sc->rssi_5ghz[ant])); 3647 sc->rssi_5ghz[ant] = 0; 3648 } 3649 } 3650 3651 return 0; 3652 } 3653 3654 static int 3655 rt2860_bbp_init(struct rt2860_softc *sc) 3656 { 3657 int i, ntries; 3658 3659 /* wait for BBP to wake up */ 3660 for (ntries = 0; ntries < 20; ntries++) { 3661 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3662 if (bbp0 != 0 && bbp0 != 0xff) 3663 break; 3664 } 3665 if (ntries == 20) { 3666 device_printf(sc->sc_dev, 3667 "timeout waiting for BBP to wake up\n"); 3668 return (ETIMEDOUT); 3669 } 3670 3671 /* initialize BBP registers to default values */ 3672 if (sc->mac_ver >= 0x5390) 3673 rt5390_bbp_init(sc); 3674 else { 3675 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3676 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3677 rt2860_def_bbp[i].val); 3678 } 3679 } 3680 3681 /* fix BBP84 for RT2860E */ 3682 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3683 rt2860_mcu_bbp_write(sc, 84, 0x19); 3684 3685 if (sc->mac_ver >= 0x3071) { 3686 rt2860_mcu_bbp_write(sc, 79, 0x13); 3687 rt2860_mcu_bbp_write(sc, 80, 0x05); 3688 rt2860_mcu_bbp_write(sc, 81, 0x33); 3689 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3690 rt2860_mcu_bbp_write(sc, 69, 0x16); 3691 rt2860_mcu_bbp_write(sc, 73, 0x12); 3692 } 3693 3694 return 0; 3695 } 3696 3697 static void 3698 rt5390_bbp_init(struct rt2860_softc *sc) 3699 { 3700 uint8_t bbp; 3701 int i; 3702 3703 /* Apply maximum likelihood detection for 2 stream case. */ 3704 if (sc->nrxchains > 1) { 3705 bbp = rt2860_mcu_bbp_read(sc, 105); 3706 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3707 } 3708 3709 /* Avoid data lost and CRC error. */ 3710 bbp = rt2860_mcu_bbp_read(sc, 4); 3711 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3712 3713 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3714 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3715 rt5390_def_bbp[i].val); 3716 } 3717 3718 if (sc->mac_ver == 0x5392) { 3719 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3720 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3721 rt2860_mcu_bbp_write(sc, 98, 0x12); 3722 rt2860_mcu_bbp_write(sc, 106, 0x05); 3723 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3724 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3725 } 3726 3727 bbp = rt2860_mcu_bbp_read(sc, 152); 3728 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3729 3730 /* Disable hardware antenna diversity. */ 3731 if (sc->mac_ver == 0x5390) 3732 rt2860_mcu_bbp_write(sc, 154, 0); 3733 } 3734 3735 static int 3736 rt2860_txrx_enable(struct rt2860_softc *sc) 3737 { 3738 struct ieee80211com *ic = &sc->sc_ic; 3739 uint32_t tmp; 3740 int ntries; 3741 3742 /* enable Tx/Rx DMA engine */ 3743 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3744 RAL_BARRIER_READ_WRITE(sc); 3745 for (ntries = 0; ntries < 200; ntries++) { 3746 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3747 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3748 break; 3749 DELAY(1000); 3750 } 3751 if (ntries == 200) { 3752 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3753 return ETIMEDOUT; 3754 } 3755 3756 DELAY(50); 3757 3758 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3759 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3760 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3761 3762 /* set Rx filter */ 3763 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3764 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3765 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3766 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3767 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3768 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3769 if (ic->ic_opmode == IEEE80211_M_STA) 3770 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3771 } 3772 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3773 3774 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3775 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3776 3777 return 0; 3778 } 3779 3780 static void 3781 rt2860_init(void *arg) 3782 { 3783 struct rt2860_softc *sc = arg; 3784 struct ieee80211com *ic = &sc->sc_ic; 3785 3786 RAL_LOCK(sc); 3787 rt2860_init_locked(sc); 3788 RAL_UNLOCK(sc); 3789 3790 if (sc->sc_flags & RT2860_RUNNING) 3791 ieee80211_start_all(ic); 3792 } 3793 3794 static void 3795 rt2860_init_locked(struct rt2860_softc *sc) 3796 { 3797 struct ieee80211com *ic = &sc->sc_ic; 3798 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3799 uint32_t tmp; 3800 uint8_t bbp1, bbp3; 3801 int i, qid, ridx, ntries, error; 3802 3803 RAL_LOCK_ASSERT(sc); 3804 3805 if (sc->rfswitch) { 3806 /* hardware has a radio switch on GPIO pin 2 */ 3807 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3808 device_printf(sc->sc_dev, 3809 "radio is disabled by hardware switch\n"); 3810 #ifdef notyet 3811 rt2860_stop_locked(sc); 3812 return; 3813 #endif 3814 } 3815 } 3816 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3817 3818 /* disable DMA */ 3819 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3820 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3821 RT2860_TX_DMA_EN); 3822 tmp |= RT2860_TX_WB_DDONE; 3823 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3824 3825 /* reset DMA indexes */ 3826 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3827 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3828 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3829 3830 /* PBF hardware reset */ 3831 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3832 RAL_BARRIER_WRITE(sc); 3833 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3834 3835 if ((error = rt2860_load_microcode(sc)) != 0) { 3836 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3837 rt2860_stop_locked(sc); 3838 return; 3839 } 3840 3841 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3842 3843 /* init Tx power for all Tx rates (from EEPROM) */ 3844 for (ridx = 0; ridx < 5; ridx++) { 3845 if (sc->txpow20mhz[ridx] == 0xffffffff) 3846 continue; 3847 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3848 } 3849 3850 for (ntries = 0; ntries < 100; ntries++) { 3851 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3852 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3853 break; 3854 DELAY(1000); 3855 } 3856 if (ntries == 100) { 3857 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3858 rt2860_stop_locked(sc); 3859 return; 3860 } 3861 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3862 RT2860_TX_DMA_EN); 3863 tmp |= RT2860_TX_WB_DDONE; 3864 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3865 3866 /* reset Rx ring and all 6 Tx rings */ 3867 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3868 3869 /* PBF hardware reset */ 3870 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3871 RAL_BARRIER_WRITE(sc); 3872 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3873 3874 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3875 3876 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3877 RAL_BARRIER_WRITE(sc); 3878 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3879 3880 for (i = 0; i < nitems(rt2860_def_mac); i++) 3881 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3882 if (sc->mac_ver >= 0x5390) 3883 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3884 else if (sc->mac_ver >= 0x3071) { 3885 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3886 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3887 4 << RT2860_DLY_PAPE_EN_SHIFT); 3888 } 3889 3890 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3891 sc->sc_flags |= RT2860_PCIE; 3892 /* PCIe has different clock cycle count than PCI */ 3893 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3894 tmp = (tmp & ~0xff) | 0x7d; 3895 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3896 } 3897 3898 /* wait while MAC is busy */ 3899 for (ntries = 0; ntries < 100; ntries++) { 3900 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3901 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3902 break; 3903 DELAY(1000); 3904 } 3905 if (ntries == 100) { 3906 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3907 rt2860_stop_locked(sc); 3908 return; 3909 } 3910 3911 /* clear Host to MCU mailbox */ 3912 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3913 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3914 3915 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3916 DELAY(1000); 3917 3918 if ((error = rt2860_bbp_init(sc)) != 0) { 3919 rt2860_stop_locked(sc); 3920 return; 3921 } 3922 3923 /* clear RX WCID search table */ 3924 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3925 /* clear pairwise key table */ 3926 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3927 /* clear IV/EIV table */ 3928 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3929 /* clear WCID attribute table */ 3930 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3931 /* clear shared key table */ 3932 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3933 /* clear shared key mode */ 3934 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3935 3936 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3937 for (qid = 0; qid < 6; qid++) { 3938 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3939 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3940 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3941 } 3942 3943 /* init Rx ring */ 3944 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3945 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3946 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3947 3948 /* setup maximum buffer sizes */ 3949 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3950 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3951 3952 for (ntries = 0; ntries < 100; ntries++) { 3953 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3954 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3955 break; 3956 DELAY(1000); 3957 } 3958 if (ntries == 100) { 3959 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3960 rt2860_stop_locked(sc); 3961 return; 3962 } 3963 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3964 RT2860_TX_DMA_EN); 3965 tmp |= RT2860_TX_WB_DDONE; 3966 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3967 3968 /* disable interrupts mitigation */ 3969 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3970 3971 /* write vendor-specific BBP values (from EEPROM) */ 3972 for (i = 0; i < 8; i++) { 3973 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3974 continue; 3975 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3976 } 3977 3978 /* select Main antenna for 1T1R devices */ 3979 if (sc->rf_rev == RT3070_RF_2020 || 3980 sc->rf_rev == RT3070_RF_3020 || 3981 sc->rf_rev == RT3070_RF_3320 || 3982 sc->mac_ver == 0x5390) 3983 rt3090_set_rx_antenna(sc, 0); 3984 3985 /* send LEDs operating mode to microcontroller */ 3986 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3987 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3988 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3989 3990 if (sc->mac_ver >= 0x5390) 3991 rt5390_rf_init(sc); 3992 else if (sc->mac_ver >= 0x3071) { 3993 if ((error = rt3090_rf_init(sc)) != 0) { 3994 rt2860_stop_locked(sc); 3995 return; 3996 } 3997 } 3998 3999 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 4000 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 4001 4002 if (sc->mac_ver >= 0x5390) 4003 rt5390_rf_wakeup(sc); 4004 else if (sc->mac_ver >= 0x3071) 4005 rt3090_rf_wakeup(sc); 4006 4007 /* disable non-existing Rx chains */ 4008 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4009 bbp3 &= ~(1 << 3 | 1 << 4); 4010 if (sc->nrxchains == 2) 4011 bbp3 |= 1 << 3; 4012 else if (sc->nrxchains == 3) 4013 bbp3 |= 1 << 4; 4014 rt2860_mcu_bbp_write(sc, 3, bbp3); 4015 4016 /* disable non-existing Tx chains */ 4017 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4018 if (sc->ntxchains == 1) 4019 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4020 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4021 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4022 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4023 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4024 rt2860_mcu_bbp_write(sc, 1, bbp1); 4025 4026 if (sc->mac_ver >= 0x3071) 4027 rt3090_rf_setup(sc); 4028 4029 /* select default channel */ 4030 rt2860_switch_chan(sc, ic->ic_curchan); 4031 4032 /* reset RF from MCU */ 4033 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4034 4035 /* set RTS threshold */ 4036 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4037 tmp &= ~0xffff00; 4038 tmp |= IEEE80211_RTS_DEFAULT << 8; 4039 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4040 4041 /* setup initial protection mode */ 4042 rt2860_updateprot(sc); 4043 4044 /* turn radio LED on */ 4045 rt2860_set_leds(sc, RT2860_LED_RADIO); 4046 4047 /* enable Tx/Rx DMA engine */ 4048 if ((error = rt2860_txrx_enable(sc)) != 0) { 4049 rt2860_stop_locked(sc); 4050 return; 4051 } 4052 4053 /* clear pending interrupts */ 4054 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4055 /* enable interrupts */ 4056 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4057 4058 if (sc->sc_flags & RT2860_ADVANCED_PS) 4059 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4060 4061 sc->sc_flags |= RT2860_RUNNING; 4062 4063 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4064 } 4065 4066 static void 4067 rt2860_stop(void *arg) 4068 { 4069 struct rt2860_softc *sc = arg; 4070 4071 RAL_LOCK(sc); 4072 rt2860_stop_locked(sc); 4073 RAL_UNLOCK(sc); 4074 } 4075 4076 static void 4077 rt2860_stop_locked(struct rt2860_softc *sc) 4078 { 4079 uint32_t tmp; 4080 int qid; 4081 4082 if (sc->sc_flags & RT2860_RUNNING) 4083 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4084 4085 callout_stop(&sc->watchdog_ch); 4086 sc->sc_tx_timer = 0; 4087 sc->sc_flags &= ~RT2860_RUNNING; 4088 4089 /* disable interrupts */ 4090 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4091 4092 /* disable GP timer */ 4093 rt2860_set_gp_timer(sc, 0); 4094 4095 /* disable Rx */ 4096 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4097 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4098 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4099 4100 /* reset adapter */ 4101 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4102 RAL_BARRIER_WRITE(sc); 4103 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4104 4105 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4106 sc->qfullmsk = 0; 4107 for (qid = 0; qid < 6; qid++) 4108 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4109 rt2860_reset_rx_ring(sc, &sc->rxq); 4110 } 4111 4112 int 4113 rt2860_load_microcode(struct rt2860_softc *sc) 4114 { 4115 const struct firmware *fp; 4116 int ntries, error; 4117 4118 RAL_LOCK_ASSERT(sc); 4119 4120 RAL_UNLOCK(sc); 4121 fp = firmware_get("rt2860fw"); 4122 RAL_LOCK(sc); 4123 if (fp == NULL) { 4124 device_printf(sc->sc_dev, 4125 "unable to receive rt2860fw firmware image\n"); 4126 return EINVAL; 4127 } 4128 4129 /* set "host program ram write selection" bit */ 4130 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4131 /* write microcode image */ 4132 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4133 /* kick microcontroller unit */ 4134 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4135 RAL_BARRIER_WRITE(sc); 4136 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4137 4138 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4139 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4140 4141 /* wait until microcontroller is ready */ 4142 RAL_BARRIER_READ_WRITE(sc); 4143 for (ntries = 0; ntries < 1000; ntries++) { 4144 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4145 break; 4146 DELAY(1000); 4147 } 4148 if (ntries == 1000) { 4149 device_printf(sc->sc_dev, 4150 "timeout waiting for MCU to initialize\n"); 4151 error = ETIMEDOUT; 4152 } else 4153 error = 0; 4154 4155 firmware_put(fp, FIRMWARE_UNLOAD); 4156 return error; 4157 } 4158 4159 /* 4160 * This function is called periodically to adjust Tx power based on 4161 * temperature variation. 4162 */ 4163 #ifdef NOT_YET 4164 static void 4165 rt2860_calib(struct rt2860_softc *sc) 4166 { 4167 struct ieee80211com *ic = &sc->sc_ic; 4168 const uint8_t *tssi; 4169 uint8_t step, bbp49; 4170 int8_t ridx, d; 4171 4172 /* read current temperature */ 4173 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4174 4175 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4176 tssi = &sc->tssi_2ghz[4]; 4177 step = sc->step_2ghz; 4178 } else { 4179 tssi = &sc->tssi_5ghz[4]; 4180 step = sc->step_5ghz; 4181 } 4182 4183 if (bbp49 < tssi[0]) { /* lower than reference */ 4184 /* use higher Tx power than default */ 4185 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4186 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4187 /* use lower Tx power than default */ 4188 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4189 } else { 4190 /* use default Tx power */ 4191 d = 0; 4192 } 4193 d *= step; 4194 4195 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4196 4197 /* write adjusted Tx power values for each Tx rate */ 4198 for (ridx = 0; ridx < 5; ridx++) { 4199 if (sc->txpow20mhz[ridx] == 0xffffffff) 4200 continue; 4201 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4202 b4inc(sc->txpow20mhz[ridx], d)); 4203 } 4204 } 4205 #endif 4206 4207 static void 4208 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4209 { 4210 uint32_t tmp; 4211 4212 if (aux) { 4213 if (sc->mac_ver == 0x5390) { 4214 rt2860_mcu_bbp_write(sc, 152, 4215 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4216 } else { 4217 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4218 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4219 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4220 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4221 } 4222 } else { 4223 if (sc->mac_ver == 0x5390) { 4224 rt2860_mcu_bbp_write(sc, 152, 4225 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4226 } else { 4227 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4228 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4229 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4230 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4231 } 4232 } 4233 } 4234 4235 static void 4236 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4237 { 4238 struct ieee80211com *ic = &sc->sc_ic; 4239 u_int chan, group; 4240 4241 chan = ieee80211_chan2ieee(ic, c); 4242 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4243 return; 4244 4245 if (sc->mac_ver >= 0x5390) 4246 rt5390_set_chan(sc, chan); 4247 else if (sc->mac_ver >= 0x3071) 4248 rt3090_set_chan(sc, chan); 4249 else 4250 rt2860_set_chan(sc, chan); 4251 4252 /* determine channel group */ 4253 if (chan <= 14) 4254 group = 0; 4255 else if (chan <= 64) 4256 group = 1; 4257 else if (chan <= 128) 4258 group = 2; 4259 else 4260 group = 3; 4261 4262 /* XXX necessary only when group has changed! */ 4263 if (sc->mac_ver < 0x5390) 4264 rt2860_select_chan_group(sc, group); 4265 4266 DELAY(1000); 4267 } 4268 4269 static int 4270 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4271 { 4272 struct ieee80211com *ic = vap->iv_ic; 4273 struct rt2860_txwi txwi; 4274 struct mbuf *m; 4275 int ridx; 4276 4277 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4278 return ENOBUFS; 4279 4280 memset(&txwi, 0, sizeof txwi); 4281 txwi.wcid = 0xff; 4282 txwi.len = htole16(m->m_pkthdr.len); 4283 /* send beacons at the lowest available rate */ 4284 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4285 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4286 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4287 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4288 txwi.phy |= htole16(RT2860_PHY_OFDM); 4289 txwi.txop = RT2860_TX_TXOP_HT; 4290 txwi.flags = RT2860_TX_TS; 4291 txwi.xflags = RT2860_TX_NSEQ; 4292 4293 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4294 (uint8_t *)&txwi, sizeof txwi); 4295 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4296 mtod(m, uint8_t *), m->m_pkthdr.len); 4297 4298 m_freem(m); 4299 4300 return 0; 4301 } 4302 4303 static void 4304 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4305 { 4306 struct ieee80211com *ic = &sc->sc_ic; 4307 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4308 uint32_t tmp; 4309 4310 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4311 4312 tmp &= ~0x1fffff; 4313 tmp |= vap->iv_bss->ni_intval * 16; 4314 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4315 if (vap->iv_opmode == IEEE80211_M_STA) { 4316 /* 4317 * Local TSF is always updated with remote TSF on beacon 4318 * reception. 4319 */ 4320 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4321 } 4322 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4323 vap->iv_opmode == IEEE80211_M_MBSS) { 4324 tmp |= RT2860_BCN_TX_EN; 4325 /* 4326 * Local TSF is updated with remote TSF on beacon reception 4327 * only if the remote TSF is greater than local TSF. 4328 */ 4329 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4330 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4331 tmp |= RT2860_BCN_TX_EN; 4332 /* SYNC with nobody */ 4333 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4334 } 4335 4336 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4337 } 4338