1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_radiotap.h> 58 #include <net80211/ieee80211_regdomain.h> 59 #include <net80211/ieee80211_ratectl.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_ether.h> 66 67 #include <dev/ral/rt2860reg.h> 68 #include <dev/ral/rt2860var.h> 69 70 #define RAL_DEBUG 71 #ifdef RAL_DEBUG 72 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 73 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n, x) 77 #endif 78 79 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 80 const char [IFNAMSIZ], int, enum ieee80211_opmode, 81 int, const uint8_t [IEEE80211_ADDR_LEN], 82 const uint8_t [IEEE80211_ADDR_LEN]); 83 static void rt2860_vap_delete(struct ieee80211vap *); 84 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 85 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_reset_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static void rt2860_free_tx_ring(struct rt2860_softc *, 90 struct rt2860_tx_ring *); 91 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 92 static void rt2860_free_tx_pool(struct rt2860_softc *); 93 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_reset_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_free_rx_ring(struct rt2860_softc *, 98 struct rt2860_rx_ring *); 99 static void rt2860_updatestats(struct rt2860_softc *); 100 static void rt2860_newassoc(struct ieee80211_node *, int); 101 static void rt2860_node_free(struct ieee80211_node *); 102 #ifdef IEEE80211_HT 103 static int rt2860_ampdu_rx_start(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 106 struct ieee80211_node *, uint8_t); 107 #endif 108 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 109 int); 110 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 111 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 112 static void rt2860_intr_coherent(struct rt2860_softc *); 113 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 114 static void rt2860_tx_intr(struct rt2860_softc *, int); 115 static void rt2860_rx_intr(struct rt2860_softc *); 116 static void rt2860_tbtt_intr(struct rt2860_softc *); 117 static void rt2860_gp_intr(struct rt2860_softc *); 118 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 119 struct ieee80211_node *); 120 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 121 const struct ieee80211_bpf_params *); 122 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 123 struct ieee80211_node *, 124 const struct ieee80211_bpf_params *params); 125 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 126 static void rt2860_start(struct rt2860_softc *); 127 static void rt2860_watchdog(void *); 128 static void rt2860_parent(struct ieee80211com *); 129 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 130 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 131 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 132 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 133 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 134 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 135 static void rt2860_enable_mrr(struct rt2860_softc *); 136 static void rt2860_set_txpreamble(struct rt2860_softc *); 137 static void rt2860_set_basicrates(struct rt2860_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2860_scan_start(struct ieee80211com *); 140 static void rt2860_scan_end(struct ieee80211com *); 141 static void rt2860_getradiocaps(struct ieee80211com *, int, int *, 142 struct ieee80211_channel[]); 143 static void rt2860_set_channel(struct ieee80211com *); 144 static void rt2860_select_chan_group(struct rt2860_softc *, int); 145 static void rt2860_set_chan(struct rt2860_softc *, u_int); 146 static void rt3090_set_chan(struct rt2860_softc *, u_int); 147 static void rt5390_set_chan(struct rt2860_softc *, u_int); 148 static int rt3090_rf_init(struct rt2860_softc *); 149 static void rt5390_rf_init(struct rt2860_softc *); 150 static void rt3090_rf_wakeup(struct rt2860_softc *); 151 static void rt5390_rf_wakeup(struct rt2860_softc *); 152 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 153 uint8_t *); 154 static void rt3090_rf_setup(struct rt2860_softc *); 155 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 156 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 157 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 158 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 159 static void rt2860_update_promisc(struct ieee80211com *); 160 static void rt2860_updateslot(struct ieee80211com *); 161 static void rt2860_updateprot(struct rt2860_softc *); 162 static int rt2860_updateedca(struct ieee80211com *); 163 #ifdef HW_CRYPTO 164 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 165 struct ieee80211_key *); 166 static void rt2860_delete_key(struct ieee80211com *, 167 struct ieee80211_node *, struct ieee80211_key *); 168 #endif 169 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 170 static const char *rt2860_get_rf(uint16_t); 171 static int rt2860_read_eeprom(struct rt2860_softc *, 172 uint8_t macaddr[IEEE80211_ADDR_LEN]); 173 static int rt2860_bbp_init(struct rt2860_softc *); 174 static void rt5390_bbp_init(struct rt2860_softc *); 175 static int rt2860_txrx_enable(struct rt2860_softc *); 176 static void rt2860_init(void *); 177 static void rt2860_init_locked(struct rt2860_softc *); 178 static void rt2860_stop(void *); 179 static void rt2860_stop_locked(struct rt2860_softc *); 180 static int rt2860_load_microcode(struct rt2860_softc *); 181 #ifdef NOT_YET 182 static void rt2860_calib(struct rt2860_softc *); 183 #endif 184 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 185 static void rt2860_switch_chan(struct rt2860_softc *, 186 struct ieee80211_channel *); 187 static int rt2860_setup_beacon(struct rt2860_softc *, 188 struct ieee80211vap *); 189 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 190 191 static const struct { 192 uint32_t reg; 193 uint32_t val; 194 } rt2860_def_mac[] = { 195 RT2860_DEF_MAC 196 }; 197 198 static const struct { 199 uint8_t reg; 200 uint8_t val; 201 } rt2860_def_bbp[] = { 202 RT2860_DEF_BBP 203 }, rt5390_def_bbp[] = { 204 RT5390_DEF_BBP 205 }; 206 207 static const struct rfprog { 208 uint8_t chan; 209 uint32_t r1, r2, r3, r4; 210 } rt2860_rf2850[] = { 211 RT2860_RF2850 212 }; 213 214 struct { 215 uint8_t n, r, k; 216 } rt3090_freqs[] = { 217 RT3070_RF3052 218 }; 219 220 static const struct { 221 uint8_t reg; 222 uint8_t val; 223 } rt3090_def_rf[] = { 224 RT3070_DEF_RF 225 }, rt5390_def_rf[] = { 226 RT5390_DEF_RF 227 }, rt5392_def_rf[] = { 228 RT5392_DEF_RF 229 }; 230 231 static const uint8_t rt2860_chan_2ghz[] = 232 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 233 static const uint8_t rt2860_chan_5ghz[] = 234 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 235 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 236 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 }; 237 238 int 239 rt2860_attach(device_t dev, int id) 240 { 241 struct rt2860_softc *sc = device_get_softc(dev); 242 struct ieee80211com *ic = &sc->sc_ic; 243 uint32_t tmp; 244 int error, ntries, qid; 245 246 sc->sc_dev = dev; 247 sc->sc_debug = 0; 248 249 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 250 MTX_DEF | MTX_RECURSE); 251 252 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 253 mbufq_init(&sc->sc_snd, ifqmaxlen); 254 255 /* wait for NIC to initialize */ 256 for (ntries = 0; ntries < 100; ntries++) { 257 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 258 if (tmp != 0 && tmp != 0xffffffff) 259 break; 260 DELAY(10); 261 } 262 if (ntries == 100) { 263 device_printf(sc->sc_dev, 264 "timeout waiting for NIC to initialize\n"); 265 error = EIO; 266 goto fail1; 267 } 268 sc->mac_ver = tmp >> 16; 269 sc->mac_rev = tmp & 0xffff; 270 271 if (sc->mac_ver != 0x2860 && 272 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 273 sc->sc_flags |= RT2860_ADVANCED_PS; 274 275 /* retrieve RF rev. no and various other things from EEPROM */ 276 rt2860_read_eeprom(sc, ic->ic_macaddr); 277 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 278 "RF %s (MIMO %dT%dR), address %6D\n", 279 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 280 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 281 282 /* 283 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 284 */ 285 for (qid = 0; qid < 6; qid++) { 286 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 287 device_printf(sc->sc_dev, 288 "could not allocate Tx ring %d\n", qid); 289 goto fail2; 290 } 291 } 292 293 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 294 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 295 goto fail2; 296 } 297 298 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 299 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 300 goto fail3; 301 } 302 303 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 304 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 305 WME_AC_VO : 5; 306 307 ic->ic_softc = sc; 308 ic->ic_name = device_get_nameunit(dev); 309 ic->ic_opmode = IEEE80211_M_STA; 310 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 311 312 /* set device capabilities */ 313 ic->ic_caps = 314 IEEE80211_C_STA /* station mode */ 315 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 316 | IEEE80211_C_HOSTAP /* hostap mode */ 317 | IEEE80211_C_MONITOR /* monitor mode */ 318 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 319 | IEEE80211_C_WDS /* 4-address traffic works */ 320 | IEEE80211_C_MBSS /* mesh point link mode */ 321 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 322 | IEEE80211_C_SHSLOT /* short slot time supported */ 323 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 324 #if 0 325 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 326 #endif 327 | IEEE80211_C_WME /* 802.11e */ 328 ; 329 330 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 331 ic->ic_channels); 332 333 ieee80211_ifattach(ic); 334 335 ic->ic_wme.wme_update = rt2860_updateedca; 336 ic->ic_scan_start = rt2860_scan_start; 337 ic->ic_scan_end = rt2860_scan_end; 338 ic->ic_getradiocaps = rt2860_getradiocaps; 339 ic->ic_set_channel = rt2860_set_channel; 340 ic->ic_updateslot = rt2860_updateslot; 341 ic->ic_update_promisc = rt2860_update_promisc; 342 ic->ic_raw_xmit = rt2860_raw_xmit; 343 sc->sc_node_free = ic->ic_node_free; 344 ic->ic_node_free = rt2860_node_free; 345 ic->ic_newassoc = rt2860_newassoc; 346 ic->ic_transmit = rt2860_transmit; 347 ic->ic_parent = rt2860_parent; 348 ic->ic_vap_create = rt2860_vap_create; 349 ic->ic_vap_delete = rt2860_vap_delete; 350 351 ieee80211_radiotap_attach(ic, 352 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 353 RT2860_TX_RADIOTAP_PRESENT, 354 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 355 RT2860_RX_RADIOTAP_PRESENT); 356 357 #ifdef RAL_DEBUG 358 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 359 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 360 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 361 #endif 362 if (bootverbose) 363 ieee80211_announce(ic); 364 365 return 0; 366 367 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 368 fail2: while (--qid >= 0) 369 rt2860_free_tx_ring(sc, &sc->txq[qid]); 370 fail1: mtx_destroy(&sc->sc_mtx); 371 return error; 372 } 373 374 int 375 rt2860_detach(void *xsc) 376 { 377 struct rt2860_softc *sc = xsc; 378 struct ieee80211com *ic = &sc->sc_ic; 379 int qid; 380 381 RAL_LOCK(sc); 382 rt2860_stop_locked(sc); 383 RAL_UNLOCK(sc); 384 385 ieee80211_ifdetach(ic); 386 mbufq_drain(&sc->sc_snd); 387 for (qid = 0; qid < 6; qid++) 388 rt2860_free_tx_ring(sc, &sc->txq[qid]); 389 rt2860_free_rx_ring(sc, &sc->rxq); 390 rt2860_free_tx_pool(sc); 391 392 mtx_destroy(&sc->sc_mtx); 393 394 return 0; 395 } 396 397 void 398 rt2860_shutdown(void *xsc) 399 { 400 struct rt2860_softc *sc = xsc; 401 402 rt2860_stop(sc); 403 } 404 405 void 406 rt2860_suspend(void *xsc) 407 { 408 struct rt2860_softc *sc = xsc; 409 410 rt2860_stop(sc); 411 } 412 413 void 414 rt2860_resume(void *xsc) 415 { 416 struct rt2860_softc *sc = xsc; 417 418 if (sc->sc_ic.ic_nrunning > 0) 419 rt2860_init(sc); 420 } 421 422 static struct ieee80211vap * 423 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 424 enum ieee80211_opmode opmode, int flags, 425 const uint8_t bssid[IEEE80211_ADDR_LEN], 426 const uint8_t mac[IEEE80211_ADDR_LEN]) 427 { 428 struct rt2860_softc *sc = ic->ic_softc; 429 struct rt2860_vap *rvp; 430 struct ieee80211vap *vap; 431 432 switch (opmode) { 433 case IEEE80211_M_STA: 434 case IEEE80211_M_IBSS: 435 case IEEE80211_M_AHDEMO: 436 case IEEE80211_M_MONITOR: 437 case IEEE80211_M_HOSTAP: 438 case IEEE80211_M_MBSS: 439 /* XXXRP: TBD */ 440 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 441 device_printf(sc->sc_dev, "only 1 vap supported\n"); 442 return NULL; 443 } 444 if (opmode == IEEE80211_M_STA) 445 flags |= IEEE80211_CLONE_NOBEACONS; 446 break; 447 case IEEE80211_M_WDS: 448 if (TAILQ_EMPTY(&ic->ic_vaps) || 449 ic->ic_opmode != IEEE80211_M_HOSTAP) { 450 device_printf(sc->sc_dev, 451 "wds only supported in ap mode\n"); 452 return NULL; 453 } 454 /* 455 * Silently remove any request for a unique 456 * bssid; WDS vap's always share the local 457 * mac address. 458 */ 459 flags &= ~IEEE80211_CLONE_BSSID; 460 break; 461 default: 462 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 463 return NULL; 464 } 465 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 466 vap = &rvp->ral_vap; 467 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 468 469 /* override state transition machine */ 470 rvp->ral_newstate = vap->iv_newstate; 471 vap->iv_newstate = rt2860_newstate; 472 #if 0 473 vap->iv_update_beacon = rt2860_beacon_update; 474 #endif 475 476 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 477 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 478 479 ieee80211_ratectl_init(vap); 480 /* complete setup */ 481 ieee80211_vap_attach(vap, ieee80211_media_change, 482 ieee80211_media_status, mac); 483 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 484 ic->ic_opmode = opmode; 485 return vap; 486 } 487 488 static void 489 rt2860_vap_delete(struct ieee80211vap *vap) 490 { 491 struct rt2860_vap *rvp = RT2860_VAP(vap); 492 493 ieee80211_ratectl_deinit(vap); 494 ieee80211_vap_detach(vap); 495 free(rvp, M_80211_VAP); 496 } 497 498 static void 499 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 500 { 501 if (error != 0) 502 return; 503 504 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 505 506 *(bus_addr_t *)arg = segs[0].ds_addr; 507 } 508 509 510 static int 511 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 512 { 513 int size, error; 514 515 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 516 517 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 518 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 519 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 520 if (error != 0) { 521 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 522 goto fail; 523 } 524 525 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 526 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 527 if (error != 0) { 528 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 529 goto fail; 530 } 531 532 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 533 size, rt2860_dma_map_addr, &ring->paddr, 0); 534 if (error != 0) { 535 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 536 goto fail; 537 } 538 539 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 540 541 return 0; 542 543 fail: rt2860_free_tx_ring(sc, ring); 544 return error; 545 } 546 547 void 548 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 549 { 550 struct rt2860_tx_data *data; 551 int i; 552 553 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 554 if ((data = ring->data[i]) == NULL) 555 continue; /* nothing mapped in this slot */ 556 557 if (data->m != NULL) { 558 bus_dmamap_sync(sc->txwi_dmat, data->map, 559 BUS_DMASYNC_POSTWRITE); 560 bus_dmamap_unload(sc->txwi_dmat, data->map); 561 m_freem(data->m); 562 data->m = NULL; 563 } 564 if (data->ni != NULL) { 565 ieee80211_free_node(data->ni); 566 data->ni = NULL; 567 } 568 569 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 570 ring->data[i] = NULL; 571 } 572 573 ring->queued = 0; 574 ring->cur = ring->next = 0; 575 } 576 577 void 578 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 579 { 580 struct rt2860_tx_data *data; 581 int i; 582 583 if (ring->txd != NULL) { 584 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 585 BUS_DMASYNC_POSTWRITE); 586 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 587 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 588 } 589 if (ring->desc_dmat != NULL) 590 bus_dma_tag_destroy(ring->desc_dmat); 591 592 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 593 if ((data = ring->data[i]) == NULL) 594 continue; /* nothing mapped in this slot */ 595 596 if (data->m != NULL) { 597 bus_dmamap_sync(sc->txwi_dmat, data->map, 598 BUS_DMASYNC_POSTWRITE); 599 bus_dmamap_unload(sc->txwi_dmat, data->map); 600 m_freem(data->m); 601 } 602 if (data->ni != NULL) 603 ieee80211_free_node(data->ni); 604 605 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 606 } 607 } 608 609 /* 610 * Allocate a pool of TX Wireless Information blocks. 611 */ 612 int 613 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 614 { 615 caddr_t vaddr; 616 bus_addr_t paddr; 617 int i, size, error; 618 619 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 620 621 /* init data_pool early in case of failure.. */ 622 SLIST_INIT(&sc->data_pool); 623 624 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 625 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 626 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 627 if (error != 0) { 628 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 629 goto fail; 630 } 631 632 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 633 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 634 if (error != 0) { 635 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 636 goto fail; 637 } 638 639 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 640 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 641 if (error != 0) { 642 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 643 goto fail; 644 } 645 646 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 647 648 vaddr = sc->txwi_vaddr; 649 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 650 struct rt2860_tx_data *data = &sc->data[i]; 651 652 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 653 if (error != 0) { 654 device_printf(sc->sc_dev, "could not create DMA map\n"); 655 goto fail; 656 } 657 data->txwi = (struct rt2860_txwi *)vaddr; 658 data->paddr = paddr; 659 vaddr += RT2860_TXWI_DMASZ; 660 paddr += RT2860_TXWI_DMASZ; 661 662 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 663 } 664 665 return 0; 666 667 fail: rt2860_free_tx_pool(sc); 668 return error; 669 } 670 671 void 672 rt2860_free_tx_pool(struct rt2860_softc *sc) 673 { 674 if (sc->txwi_vaddr != NULL) { 675 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 676 BUS_DMASYNC_POSTWRITE); 677 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 678 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 679 } 680 if (sc->txwi_dmat != NULL) 681 bus_dma_tag_destroy(sc->txwi_dmat); 682 683 while (!SLIST_EMPTY(&sc->data_pool)) { 684 struct rt2860_tx_data *data; 685 data = SLIST_FIRST(&sc->data_pool); 686 bus_dmamap_destroy(sc->txwi_dmat, data->map); 687 SLIST_REMOVE_HEAD(&sc->data_pool, next); 688 } 689 } 690 691 int 692 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 693 { 694 bus_addr_t physaddr; 695 int i, size, error; 696 697 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 698 699 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 700 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 701 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 702 if (error != 0) { 703 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 704 goto fail; 705 } 706 707 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 708 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 709 if (error != 0) { 710 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 711 goto fail; 712 } 713 714 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 715 size, rt2860_dma_map_addr, &ring->paddr, 0); 716 if (error != 0) { 717 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 718 goto fail; 719 } 720 721 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 722 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 723 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 724 if (error != 0) { 725 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 726 goto fail; 727 } 728 729 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 730 struct rt2860_rx_data *data = &ring->data[i]; 731 struct rt2860_rxd *rxd = &ring->rxd[i]; 732 733 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 734 if (error != 0) { 735 device_printf(sc->sc_dev, "could not create DMA map\n"); 736 goto fail; 737 } 738 739 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 740 if (data->m == NULL) { 741 device_printf(sc->sc_dev, 742 "could not allocate rx mbuf\n"); 743 error = ENOMEM; 744 goto fail; 745 } 746 747 error = bus_dmamap_load(ring->data_dmat, data->map, 748 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 749 &physaddr, 0); 750 if (error != 0) { 751 device_printf(sc->sc_dev, 752 "could not load rx buf DMA map"); 753 goto fail; 754 } 755 756 rxd->sdp0 = htole32(physaddr); 757 rxd->sdl0 = htole16(MCLBYTES); 758 } 759 760 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 761 762 return 0; 763 764 fail: rt2860_free_rx_ring(sc, ring); 765 return error; 766 } 767 768 void 769 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 770 { 771 int i; 772 773 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 774 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 775 776 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 777 778 ring->cur = 0; 779 } 780 781 void 782 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 783 { 784 int i; 785 786 if (ring->rxd != NULL) { 787 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 788 BUS_DMASYNC_POSTWRITE); 789 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 790 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 791 } 792 if (ring->desc_dmat != NULL) 793 bus_dma_tag_destroy(ring->desc_dmat); 794 795 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 796 struct rt2860_rx_data *data = &ring->data[i]; 797 798 if (data->m != NULL) { 799 bus_dmamap_sync(ring->data_dmat, data->map, 800 BUS_DMASYNC_POSTREAD); 801 bus_dmamap_unload(ring->data_dmat, data->map); 802 m_freem(data->m); 803 } 804 if (data->map != NULL) 805 bus_dmamap_destroy(ring->data_dmat, data->map); 806 } 807 if (ring->data_dmat != NULL) 808 bus_dma_tag_destroy(ring->data_dmat); 809 } 810 811 static void 812 rt2860_updatestats(struct rt2860_softc *sc) 813 { 814 struct ieee80211com *ic = &sc->sc_ic; 815 816 /* 817 * In IBSS or HostAP modes (when the hardware sends beacons), the 818 * MAC can run into a livelock and start sending CTS-to-self frames 819 * like crazy if protection is enabled. Fortunately, we can detect 820 * when such a situation occurs and reset the MAC. 821 */ 822 if (ic->ic_curmode != IEEE80211_M_STA) { 823 /* check if we're in a livelock situation.. */ 824 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 825 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 826 /* ..and reset MAC/BBP for a while.. */ 827 DPRINTF(("CTS-to-self livelock detected\n")); 828 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 829 RAL_BARRIER_WRITE(sc); 830 DELAY(1); 831 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 832 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 833 } 834 } 835 } 836 837 static void 838 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 839 { 840 struct ieee80211com *ic = ni->ni_ic; 841 struct rt2860_softc *sc = ic->ic_softc; 842 uint8_t wcid; 843 844 wcid = IEEE80211_AID(ni->ni_associd); 845 if (isnew && ni->ni_associd != 0) { 846 sc->wcid2ni[wcid] = ni; 847 848 /* init WCID table entry */ 849 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 850 ni->ni_macaddr, IEEE80211_ADDR_LEN); 851 } 852 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 853 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 854 } 855 856 static void 857 rt2860_node_free(struct ieee80211_node *ni) 858 { 859 struct ieee80211com *ic = ni->ni_ic; 860 struct rt2860_softc *sc = ic->ic_softc; 861 uint8_t wcid; 862 863 if (ni->ni_associd != 0) { 864 wcid = IEEE80211_AID(ni->ni_associd); 865 866 /* clear Rx WCID search table entry */ 867 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 868 } 869 sc->sc_node_free(ni); 870 } 871 872 #ifdef IEEE80211_HT 873 static int 874 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 875 uint8_t tid) 876 { 877 struct rt2860_softc *sc = ic->ic_softc; 878 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 879 uint32_t tmp; 880 881 /* update BA session mask */ 882 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 883 tmp |= (1 << tid) << 16; 884 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 885 return 0; 886 } 887 888 static void 889 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 890 uint8_t tid) 891 { 892 struct rt2860_softc *sc = ic->ic_softc; 893 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 894 uint32_t tmp; 895 896 /* update BA session mask */ 897 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 898 tmp &= ~((1 << tid) << 16); 899 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 900 } 901 #endif 902 903 static int 904 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 905 { 906 struct rt2860_vap *rvp = RT2860_VAP(vap); 907 struct ieee80211com *ic = vap->iv_ic; 908 struct rt2860_softc *sc = ic->ic_softc; 909 uint32_t tmp; 910 int error; 911 912 if (vap->iv_state == IEEE80211_S_RUN) { 913 /* turn link LED off */ 914 rt2860_set_leds(sc, RT2860_LED_RADIO); 915 } 916 917 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 918 /* abort TSF synchronization */ 919 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 920 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 921 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 922 RT2860_TBTT_TIMER_EN)); 923 } 924 925 rt2860_set_gp_timer(sc, 0); 926 927 error = rvp->ral_newstate(vap, nstate, arg); 928 if (error != 0) 929 return (error); 930 931 if (nstate == IEEE80211_S_RUN) { 932 struct ieee80211_node *ni = vap->iv_bss; 933 934 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 935 rt2860_enable_mrr(sc); 936 rt2860_set_txpreamble(sc); 937 rt2860_set_basicrates(sc, &ni->ni_rates); 938 rt2860_set_bssid(sc, ni->ni_bssid); 939 } 940 941 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 942 vap->iv_opmode == IEEE80211_M_IBSS || 943 vap->iv_opmode == IEEE80211_M_MBSS) { 944 error = rt2860_setup_beacon(sc, vap); 945 if (error != 0) 946 return error; 947 } 948 949 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 950 rt2860_enable_tsf_sync(sc); 951 rt2860_set_gp_timer(sc, 500); 952 } 953 954 /* turn link LED on */ 955 rt2860_set_leds(sc, RT2860_LED_RADIO | 956 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 957 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 958 } 959 return error; 960 } 961 962 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 963 static uint16_t 964 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 965 { 966 uint32_t tmp; 967 uint16_t reg; 968 int ntries; 969 970 addr *= 2; 971 /*- 972 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 973 * DATA0: F E D C 974 * DATA1: B A 9 8 975 * DATA2: 7 6 5 4 976 * DATA3: 3 2 1 0 977 */ 978 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 979 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 980 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 981 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 982 for (ntries = 0; ntries < 500; ntries++) { 983 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 984 if (!(tmp & RT3070_EFSROM_KICK)) 985 break; 986 DELAY(2); 987 } 988 if (ntries == 500) 989 return 0xffff; 990 991 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 992 return 0xffff; /* address not found */ 993 994 /* determine to which 32-bit register our 16-bit word belongs */ 995 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 996 tmp = RAL_READ(sc, reg); 997 998 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 999 } 1000 1001 /* 1002 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1003 * 93C66 or 93C86). 1004 */ 1005 static uint16_t 1006 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1007 { 1008 uint32_t tmp; 1009 uint16_t val; 1010 int n; 1011 1012 /* clock C once before the first command */ 1013 RT2860_EEPROM_CTL(sc, 0); 1014 1015 RT2860_EEPROM_CTL(sc, RT2860_S); 1016 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1017 RT2860_EEPROM_CTL(sc, RT2860_S); 1018 1019 /* write start bit (1) */ 1020 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1021 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1022 1023 /* write READ opcode (10) */ 1024 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1025 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1026 RT2860_EEPROM_CTL(sc, RT2860_S); 1027 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1028 1029 /* write address (A5-A0 or A7-A0) */ 1030 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1031 for (; n >= 0; n--) { 1032 RT2860_EEPROM_CTL(sc, RT2860_S | 1033 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1034 RT2860_EEPROM_CTL(sc, RT2860_S | 1035 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1036 } 1037 1038 RT2860_EEPROM_CTL(sc, RT2860_S); 1039 1040 /* read data Q15-Q0 */ 1041 val = 0; 1042 for (n = 15; n >= 0; n--) { 1043 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1044 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1045 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1046 RT2860_EEPROM_CTL(sc, RT2860_S); 1047 } 1048 1049 RT2860_EEPROM_CTL(sc, 0); 1050 1051 /* clear Chip Select and clock C */ 1052 RT2860_EEPROM_CTL(sc, RT2860_S); 1053 RT2860_EEPROM_CTL(sc, 0); 1054 RT2860_EEPROM_CTL(sc, RT2860_C); 1055 1056 return val; 1057 } 1058 1059 static __inline uint16_t 1060 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1061 { 1062 /* either eFUSE ROM or EEPROM */ 1063 return sc->sc_srom_read(sc, addr); 1064 } 1065 1066 static void 1067 rt2860_intr_coherent(struct rt2860_softc *sc) 1068 { 1069 uint32_t tmp; 1070 1071 /* DMA finds data coherent event when checking the DDONE bit */ 1072 1073 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1074 1075 /* restart DMA engine */ 1076 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1077 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1078 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1079 1080 (void)rt2860_txrx_enable(sc); 1081 } 1082 1083 static void 1084 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1085 { 1086 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 1087 struct ieee80211_node *ni; 1088 uint32_t stat; 1089 uint8_t wcid, mcs, pid; 1090 1091 /* drain Tx status FIFO (maxsize = 16) */ 1092 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 1093 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1094 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1095 1096 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1097 ni = sc->wcid2ni[wcid]; 1098 1099 /* if no ACK was requested, no feedback is available */ 1100 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL) 1101 continue; 1102 1103 /* update per-STA AMRR stats */ 1104 if (stat & RT2860_TXQ_OK) { 1105 /* 1106 * Check if there were retries, ie if the Tx success 1107 * rate is different from the requested rate. Note 1108 * that it works only because we do not allow rate 1109 * fallback from OFDM to CCK. 1110 */ 1111 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1112 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1113 if (mcs + 1 != pid) 1114 txs->long_retries = 1; 1115 else 1116 txs->long_retries = 0; 1117 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 1118 ieee80211_ratectl_tx_complete(ni, txs); 1119 } else { 1120 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 1121 txs->long_retries = 1; /* XXX */ 1122 ieee80211_ratectl_tx_complete(ni, txs); 1123 if_inc_counter(ni->ni_vap->iv_ifp, 1124 IFCOUNTER_OERRORS, 1); 1125 } 1126 } 1127 } 1128 1129 static void 1130 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1131 { 1132 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1133 uint32_t hw; 1134 1135 rt2860_drain_stats_fifo(sc); 1136 1137 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1138 while (ring->next != hw) { 1139 struct rt2860_tx_data *data = ring->data[ring->next]; 1140 1141 if (data != NULL) { 1142 bus_dmamap_sync(sc->txwi_dmat, data->map, 1143 BUS_DMASYNC_POSTWRITE); 1144 bus_dmamap_unload(sc->txwi_dmat, data->map); 1145 ieee80211_tx_complete(data->ni, data->m, 0); 1146 data->ni = NULL; 1147 data->m = NULL; 1148 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1149 ring->data[ring->next] = NULL; 1150 } 1151 ring->queued--; 1152 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1153 } 1154 1155 sc->sc_tx_timer = 0; 1156 if (ring->queued < RT2860_TX_RING_COUNT) 1157 sc->qfullmsk &= ~(1 << qid); 1158 rt2860_start(sc); 1159 } 1160 1161 /* 1162 * Return the Rx chain with the highest RSSI for a given frame. 1163 */ 1164 static __inline uint8_t 1165 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1166 { 1167 uint8_t rxchain = 0; 1168 1169 if (sc->nrxchains > 1) { 1170 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1171 rxchain = 1; 1172 if (sc->nrxchains > 2) 1173 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1174 rxchain = 2; 1175 } 1176 return rxchain; 1177 } 1178 1179 static void 1180 rt2860_rx_intr(struct rt2860_softc *sc) 1181 { 1182 struct rt2860_rx_radiotap_header *tap; 1183 struct ieee80211com *ic = &sc->sc_ic; 1184 struct ieee80211_frame *wh; 1185 struct ieee80211_node *ni; 1186 struct mbuf *m, *m1; 1187 bus_addr_t physaddr; 1188 uint32_t hw; 1189 uint16_t phy; 1190 uint8_t ant; 1191 int8_t rssi, nf; 1192 int error; 1193 1194 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1195 while (sc->rxq.cur != hw) { 1196 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1197 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1198 struct rt2860_rxwi *rxwi; 1199 1200 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1201 BUS_DMASYNC_POSTREAD); 1202 1203 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1204 DPRINTF(("RXD DDONE bit not set!\n")); 1205 break; /* should not happen */ 1206 } 1207 1208 if (__predict_false(rxd->flags & 1209 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1210 counter_u64_add(ic->ic_ierrors, 1); 1211 goto skip; 1212 } 1213 1214 #ifdef HW_CRYPTO 1215 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1216 /* report MIC failures to net80211 for TKIP */ 1217 ic->ic_stats.is_rx_locmicfail++; 1218 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1219 counter_u64_add(ic->ic_ierrors, 1); 1220 goto skip; 1221 } 1222 #endif 1223 1224 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1225 if (__predict_false(m1 == NULL)) { 1226 counter_u64_add(ic->ic_ierrors, 1); 1227 goto skip; 1228 } 1229 1230 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1231 BUS_DMASYNC_POSTREAD); 1232 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1233 1234 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1235 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1236 &physaddr, 0); 1237 if (__predict_false(error != 0)) { 1238 m_freem(m1); 1239 1240 /* try to reload the old mbuf */ 1241 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1242 mtod(data->m, void *), MCLBYTES, 1243 rt2860_dma_map_addr, &physaddr, 0); 1244 if (__predict_false(error != 0)) { 1245 panic("%s: could not load old rx mbuf", 1246 device_get_name(sc->sc_dev)); 1247 } 1248 /* physical address may have changed */ 1249 rxd->sdp0 = htole32(physaddr); 1250 counter_u64_add(ic->ic_ierrors, 1); 1251 goto skip; 1252 } 1253 1254 /* 1255 * New mbuf successfully loaded, update Rx ring and continue 1256 * processing. 1257 */ 1258 m = data->m; 1259 data->m = m1; 1260 rxd->sdp0 = htole32(physaddr); 1261 1262 rxwi = mtod(m, struct rt2860_rxwi *); 1263 1264 /* finalize mbuf */ 1265 m->m_data = (caddr_t)(rxwi + 1); 1266 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1267 1268 wh = mtod(m, struct ieee80211_frame *); 1269 #ifdef HW_CRYPTO 1270 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1271 /* frame is decrypted by hardware */ 1272 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1273 } 1274 #endif 1275 1276 /* HW may insert 2 padding bytes after 802.11 header */ 1277 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1278 u_int hdrlen = ieee80211_hdrsize(wh); 1279 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1280 m->m_data += 2; 1281 wh = mtod(m, struct ieee80211_frame *); 1282 } 1283 1284 ant = rt2860_maxrssi_chain(sc, rxwi); 1285 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1286 nf = RT2860_NOISE_FLOOR; 1287 1288 if (ieee80211_radiotap_active(ic)) { 1289 tap = &sc->sc_rxtap; 1290 tap->wr_flags = 0; 1291 tap->wr_antenna = ant; 1292 tap->wr_antsignal = nf + rssi; 1293 tap->wr_antnoise = nf; 1294 /* in case it can't be found below */ 1295 tap->wr_rate = 2; 1296 phy = le16toh(rxwi->phy); 1297 switch (phy & RT2860_PHY_MODE) { 1298 case RT2860_PHY_CCK: 1299 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1300 case 0: tap->wr_rate = 2; break; 1301 case 1: tap->wr_rate = 4; break; 1302 case 2: tap->wr_rate = 11; break; 1303 case 3: tap->wr_rate = 22; break; 1304 } 1305 if (phy & RT2860_PHY_SHPRE) 1306 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1307 break; 1308 case RT2860_PHY_OFDM: 1309 switch (phy & RT2860_PHY_MCS) { 1310 case 0: tap->wr_rate = 12; break; 1311 case 1: tap->wr_rate = 18; break; 1312 case 2: tap->wr_rate = 24; break; 1313 case 3: tap->wr_rate = 36; break; 1314 case 4: tap->wr_rate = 48; break; 1315 case 5: tap->wr_rate = 72; break; 1316 case 6: tap->wr_rate = 96; break; 1317 case 7: tap->wr_rate = 108; break; 1318 } 1319 break; 1320 } 1321 } 1322 1323 RAL_UNLOCK(sc); 1324 wh = mtod(m, struct ieee80211_frame *); 1325 1326 /* send the frame to the 802.11 layer */ 1327 ni = ieee80211_find_rxnode(ic, 1328 (struct ieee80211_frame_min *)wh); 1329 if (ni != NULL) { 1330 (void)ieee80211_input(ni, m, rssi - nf, nf); 1331 ieee80211_free_node(ni); 1332 } else 1333 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1334 1335 RAL_LOCK(sc); 1336 1337 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1338 1339 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1340 BUS_DMASYNC_PREWRITE); 1341 1342 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1343 } 1344 1345 /* tell HW what we have processed */ 1346 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1347 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1348 } 1349 1350 static void 1351 rt2860_tbtt_intr(struct rt2860_softc *sc) 1352 { 1353 #if 0 1354 struct ieee80211com *ic = &sc->sc_ic; 1355 1356 #ifndef IEEE80211_STA_ONLY 1357 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1358 /* one less beacon until next DTIM */ 1359 if (ic->ic_dtim_count == 0) 1360 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1361 else 1362 ic->ic_dtim_count--; 1363 1364 /* update dynamic parts of beacon */ 1365 rt2860_setup_beacon(sc); 1366 1367 /* flush buffered multicast frames */ 1368 if (ic->ic_dtim_count == 0) 1369 ieee80211_notify_dtim(ic); 1370 } 1371 #endif 1372 /* check if protection mode has changed */ 1373 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1374 rt2860_updateprot(sc); 1375 sc->sc_ic_flags = ic->ic_flags; 1376 } 1377 #endif 1378 } 1379 1380 static void 1381 rt2860_gp_intr(struct rt2860_softc *sc) 1382 { 1383 struct ieee80211com *ic = &sc->sc_ic; 1384 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1385 1386 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1387 1388 if (vap->iv_state == IEEE80211_S_RUN) 1389 rt2860_updatestats(sc); 1390 } 1391 1392 void 1393 rt2860_intr(void *arg) 1394 { 1395 struct rt2860_softc *sc = arg; 1396 uint32_t r; 1397 1398 RAL_LOCK(sc); 1399 1400 r = RAL_READ(sc, RT2860_INT_STATUS); 1401 if (__predict_false(r == 0xffffffff)) { 1402 RAL_UNLOCK(sc); 1403 return; /* device likely went away */ 1404 } 1405 if (r == 0) { 1406 RAL_UNLOCK(sc); 1407 return; /* not for us */ 1408 } 1409 1410 /* acknowledge interrupts */ 1411 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1412 1413 if (r & RT2860_TX_RX_COHERENT) 1414 rt2860_intr_coherent(sc); 1415 1416 if (r & RT2860_MAC_INT_2) /* TX status */ 1417 rt2860_drain_stats_fifo(sc); 1418 1419 if (r & RT2860_TX_DONE_INT5) 1420 rt2860_tx_intr(sc, 5); 1421 1422 if (r & RT2860_RX_DONE_INT) 1423 rt2860_rx_intr(sc); 1424 1425 if (r & RT2860_TX_DONE_INT4) 1426 rt2860_tx_intr(sc, 4); 1427 1428 if (r & RT2860_TX_DONE_INT3) 1429 rt2860_tx_intr(sc, 3); 1430 1431 if (r & RT2860_TX_DONE_INT2) 1432 rt2860_tx_intr(sc, 2); 1433 1434 if (r & RT2860_TX_DONE_INT1) 1435 rt2860_tx_intr(sc, 1); 1436 1437 if (r & RT2860_TX_DONE_INT0) 1438 rt2860_tx_intr(sc, 0); 1439 1440 if (r & RT2860_MAC_INT_0) /* TBTT */ 1441 rt2860_tbtt_intr(sc); 1442 1443 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1444 /* TBD wakeup */; 1445 1446 if (r & RT2860_MAC_INT_4) /* GP timer */ 1447 rt2860_gp_intr(sc); 1448 1449 RAL_UNLOCK(sc); 1450 } 1451 1452 static int 1453 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1454 { 1455 struct ieee80211com *ic = &sc->sc_ic; 1456 struct ieee80211vap *vap = ni->ni_vap; 1457 struct rt2860_tx_ring *ring; 1458 struct rt2860_tx_data *data; 1459 struct rt2860_txd *txd; 1460 struct rt2860_txwi *txwi; 1461 struct ieee80211_frame *wh; 1462 const struct ieee80211_txparam *tp; 1463 struct ieee80211_key *k; 1464 struct mbuf *m1; 1465 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1466 bus_dma_segment_t *seg; 1467 u_int hdrlen; 1468 uint16_t qos, dur; 1469 uint8_t type, qsel, mcs, pid, tid, qid; 1470 int i, nsegs, ntxds, pad, rate, ridx, error; 1471 1472 /* the data pool contains at least one element, pick the first */ 1473 data = SLIST_FIRST(&sc->data_pool); 1474 1475 wh = mtod(m, struct ieee80211_frame *); 1476 1477 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1478 k = ieee80211_crypto_encap(ni, m); 1479 if (k == NULL) { 1480 m_freem(m); 1481 return ENOBUFS; 1482 } 1483 1484 /* packet header may have moved, reset our local pointer */ 1485 wh = mtod(m, struct ieee80211_frame *); 1486 } 1487 1488 hdrlen = ieee80211_anyhdrsize(wh); 1489 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1490 1491 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1492 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1493 rate = tp->mcastrate; 1494 } else if (m->m_flags & M_EAPOL) { 1495 rate = tp->mgmtrate; 1496 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1497 rate = tp->ucastrate; 1498 } else { 1499 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1500 rate = ni->ni_txrate; 1501 } 1502 rate &= IEEE80211_RATE_VAL; 1503 1504 qid = M_WME_GETAC(m); 1505 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1506 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1507 tid = qos & IEEE80211_QOS_TID; 1508 } else { 1509 qos = 0; 1510 tid = 0; 1511 } 1512 ring = &sc->txq[qid]; 1513 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1514 1515 /* get MCS code from rate index */ 1516 mcs = rt2860_rates[ridx].mcs; 1517 1518 /* setup TX Wireless Information */ 1519 txwi = data->txwi; 1520 txwi->flags = 0; 1521 /* let HW generate seq numbers for non-QoS frames */ 1522 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1523 if (type == IEEE80211_FC0_TYPE_DATA) 1524 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1525 else 1526 txwi->wcid = 0xff; 1527 txwi->len = htole16(m->m_pkthdr.len); 1528 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1529 txwi->phy = htole16(RT2860_PHY_CCK); 1530 if (ridx != RT2860_RIDX_CCK1 && 1531 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1532 mcs |= RT2860_PHY_SHPRE; 1533 } else 1534 txwi->phy = htole16(RT2860_PHY_OFDM); 1535 txwi->phy |= htole16(mcs); 1536 1537 /* 1538 * We store the MCS code into the driver-private PacketID field. 1539 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1540 * that we know at which initial rate the frame was transmitted. 1541 * We add 1 to the MCS code because setting the PacketID field to 1542 * 0 means that we don't want feedback in TX_STAT_FIFO. 1543 */ 1544 pid = (mcs + 1) & 0xf; 1545 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1546 1547 /* check if RTS/CTS or CTS-to-self protection is required */ 1548 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1549 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1550 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1551 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1552 txwi->txop = RT2860_TX_TXOP_HT; 1553 else 1554 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1555 1556 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1557 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1558 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1559 txwi->xflags |= RT2860_TX_ACK; 1560 1561 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1562 dur = rt2860_rates[ridx].sp_ack_dur; 1563 else 1564 dur = rt2860_rates[ridx].lp_ack_dur; 1565 *(uint16_t *)wh->i_dur = htole16(dur); 1566 } 1567 /* ask MAC to insert timestamp into probe responses */ 1568 if ((wh->i_fc[0] & 1569 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1570 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1571 /* NOTE: beacons do not pass through tx_data() */ 1572 txwi->flags |= RT2860_TX_TS; 1573 1574 if (ieee80211_radiotap_active_vap(vap)) { 1575 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1576 1577 tap->wt_flags = 0; 1578 tap->wt_rate = rate; 1579 if (mcs & RT2860_PHY_SHPRE) 1580 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1581 1582 ieee80211_radiotap_tx(vap, m); 1583 } 1584 1585 pad = (hdrlen + 3) & ~3; 1586 1587 /* copy and trim 802.11 header */ 1588 memcpy(txwi + 1, wh, hdrlen); 1589 m_adj(m, hdrlen); 1590 1591 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1592 &nsegs, 0); 1593 if (__predict_false(error != 0 && error != EFBIG)) { 1594 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1595 error); 1596 m_freem(m); 1597 return error; 1598 } 1599 if (__predict_true(error == 0)) { 1600 /* determine how many TXDs are required */ 1601 ntxds = 1 + (nsegs / 2); 1602 1603 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1604 /* not enough free TXDs, force mbuf defrag */ 1605 bus_dmamap_unload(sc->txwi_dmat, data->map); 1606 error = EFBIG; 1607 } 1608 } 1609 if (__predict_false(error != 0)) { 1610 m1 = m_defrag(m, M_NOWAIT); 1611 if (m1 == NULL) { 1612 device_printf(sc->sc_dev, 1613 "could not defragment mbuf\n"); 1614 m_freem(m); 1615 return ENOBUFS; 1616 } 1617 m = m1; 1618 1619 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1620 segs, &nsegs, 0); 1621 if (__predict_false(error != 0)) { 1622 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1623 error); 1624 m_freem(m); 1625 return error; 1626 } 1627 1628 /* determine how many TXDs are now required */ 1629 ntxds = 1 + (nsegs / 2); 1630 1631 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1632 /* this is a hopeless case, drop the mbuf! */ 1633 bus_dmamap_unload(sc->txwi_dmat, data->map); 1634 m_freem(m); 1635 return ENOBUFS; 1636 } 1637 } 1638 1639 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1640 1641 /* first segment is TXWI + 802.11 header */ 1642 txd = &ring->txd[ring->cur]; 1643 txd->sdp0 = htole32(data->paddr); 1644 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1645 txd->flags = qsel; 1646 1647 /* setup payload segments */ 1648 seg = &segs[0]; 1649 for (i = nsegs; i >= 2; i -= 2) { 1650 txd->sdp1 = htole32(seg->ds_addr); 1651 txd->sdl1 = htole16(seg->ds_len); 1652 seg++; 1653 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1654 /* grab a new Tx descriptor */ 1655 txd = &ring->txd[ring->cur]; 1656 txd->sdp0 = htole32(seg->ds_addr); 1657 txd->sdl0 = htole16(seg->ds_len); 1658 txd->flags = qsel; 1659 seg++; 1660 } 1661 /* finalize last segment */ 1662 if (i > 0) { 1663 txd->sdp1 = htole32(seg->ds_addr); 1664 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1665 } else { 1666 txd->sdl0 |= htole16(RT2860_TX_LS0); 1667 txd->sdl1 = 0; 1668 } 1669 1670 /* remove from the free pool and link it into the SW Tx slot */ 1671 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1672 data->m = m; 1673 data->ni = ni; 1674 ring->data[ring->cur] = data; 1675 1676 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1677 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1678 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1679 1680 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1681 qid, txwi->wcid, nsegs, ridx)); 1682 1683 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1684 ring->queued += ntxds; 1685 if (ring->queued >= RT2860_TX_RING_COUNT) 1686 sc->qfullmsk |= 1 << qid; 1687 1688 /* kick Tx */ 1689 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1690 1691 return 0; 1692 } 1693 1694 static int 1695 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1696 const struct ieee80211_bpf_params *params) 1697 { 1698 struct ieee80211com *ic = ni->ni_ic; 1699 struct rt2860_softc *sc = ic->ic_softc; 1700 int error; 1701 1702 RAL_LOCK(sc); 1703 1704 /* prevent management frames from being sent if we're not ready */ 1705 if (!(sc->sc_flags & RT2860_RUNNING)) { 1706 RAL_UNLOCK(sc); 1707 m_freem(m); 1708 return ENETDOWN; 1709 } 1710 if (params == NULL) { 1711 /* 1712 * Legacy path; interpret frame contents to decide 1713 * precisely how to send the frame. 1714 */ 1715 error = rt2860_tx(sc, m, ni); 1716 } else { 1717 /* 1718 * Caller supplied explicit parameters to use in 1719 * sending the frame. 1720 */ 1721 error = rt2860_tx_raw(sc, m, ni, params); 1722 } 1723 sc->sc_tx_timer = 5; 1724 RAL_UNLOCK(sc); 1725 return error; 1726 } 1727 1728 static int 1729 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1730 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1731 { 1732 struct ieee80211com *ic = &sc->sc_ic; 1733 struct ieee80211vap *vap = ni->ni_vap; 1734 struct rt2860_tx_ring *ring; 1735 struct rt2860_tx_data *data; 1736 struct rt2860_txd *txd; 1737 struct rt2860_txwi *txwi; 1738 struct ieee80211_frame *wh; 1739 struct mbuf *m1; 1740 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1741 bus_dma_segment_t *seg; 1742 u_int hdrlen; 1743 uint16_t dur; 1744 uint8_t type, qsel, mcs, pid, tid, qid; 1745 int i, nsegs, ntxds, pad, rate, ridx, error; 1746 1747 /* the data pool contains at least one element, pick the first */ 1748 data = SLIST_FIRST(&sc->data_pool); 1749 1750 wh = mtod(m, struct ieee80211_frame *); 1751 hdrlen = ieee80211_hdrsize(wh); 1752 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1753 1754 /* Choose a TX rate index. */ 1755 rate = params->ibp_rate0; 1756 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1757 rate & IEEE80211_RATE_VAL); 1758 if (ridx == (uint8_t)-1) { 1759 /* XXX fall back to mcast/mgmt rate? */ 1760 m_freem(m); 1761 return EINVAL; 1762 } 1763 1764 qid = params->ibp_pri & 3; 1765 tid = 0; 1766 ring = &sc->txq[qid]; 1767 1768 /* get MCS code from rate index */ 1769 mcs = rt2860_rates[ridx].mcs; 1770 1771 /* setup TX Wireless Information */ 1772 txwi = data->txwi; 1773 txwi->flags = 0; 1774 /* let HW generate seq numbers for non-QoS frames */ 1775 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1776 txwi->wcid = 0xff; 1777 txwi->len = htole16(m->m_pkthdr.len); 1778 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1779 txwi->phy = htole16(RT2860_PHY_CCK); 1780 if (ridx != RT2860_RIDX_CCK1 && 1781 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1782 mcs |= RT2860_PHY_SHPRE; 1783 } else 1784 txwi->phy = htole16(RT2860_PHY_OFDM); 1785 txwi->phy |= htole16(mcs); 1786 1787 /* 1788 * We store the MCS code into the driver-private PacketID field. 1789 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1790 * that we know at which initial rate the frame was transmitted. 1791 * We add 1 to the MCS code because setting the PacketID field to 1792 * 0 means that we don't want feedback in TX_STAT_FIFO. 1793 */ 1794 pid = (mcs + 1) & 0xf; 1795 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1796 1797 /* check if RTS/CTS or CTS-to-self protection is required */ 1798 if (params->ibp_flags & IEEE80211_BPF_RTS || 1799 params->ibp_flags & IEEE80211_BPF_CTS) 1800 txwi->txop = RT2860_TX_TXOP_HT; 1801 else 1802 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1803 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1804 txwi->xflags |= RT2860_TX_ACK; 1805 1806 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1807 dur = rt2860_rates[ridx].sp_ack_dur; 1808 else 1809 dur = rt2860_rates[ridx].lp_ack_dur; 1810 *(uint16_t *)wh->i_dur = htole16(dur); 1811 } 1812 /* ask MAC to insert timestamp into probe responses */ 1813 if ((wh->i_fc[0] & 1814 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1815 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1816 /* NOTE: beacons do not pass through tx_data() */ 1817 txwi->flags |= RT2860_TX_TS; 1818 1819 if (ieee80211_radiotap_active_vap(vap)) { 1820 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1821 1822 tap->wt_flags = 0; 1823 tap->wt_rate = rate; 1824 if (mcs & RT2860_PHY_SHPRE) 1825 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1826 1827 ieee80211_radiotap_tx(vap, m); 1828 } 1829 1830 pad = (hdrlen + 3) & ~3; 1831 1832 /* copy and trim 802.11 header */ 1833 memcpy(txwi + 1, wh, hdrlen); 1834 m_adj(m, hdrlen); 1835 1836 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1837 &nsegs, 0); 1838 if (__predict_false(error != 0 && error != EFBIG)) { 1839 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1840 error); 1841 m_freem(m); 1842 return error; 1843 } 1844 if (__predict_true(error == 0)) { 1845 /* determine how many TXDs are required */ 1846 ntxds = 1 + (nsegs / 2); 1847 1848 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1849 /* not enough free TXDs, force mbuf defrag */ 1850 bus_dmamap_unload(sc->txwi_dmat, data->map); 1851 error = EFBIG; 1852 } 1853 } 1854 if (__predict_false(error != 0)) { 1855 m1 = m_defrag(m, M_NOWAIT); 1856 if (m1 == NULL) { 1857 device_printf(sc->sc_dev, 1858 "could not defragment mbuf\n"); 1859 m_freem(m); 1860 return ENOBUFS; 1861 } 1862 m = m1; 1863 1864 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1865 segs, &nsegs, 0); 1866 if (__predict_false(error != 0)) { 1867 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1868 error); 1869 m_freem(m); 1870 return error; 1871 } 1872 1873 /* determine how many TXDs are now required */ 1874 ntxds = 1 + (nsegs / 2); 1875 1876 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1877 /* this is a hopeless case, drop the mbuf! */ 1878 bus_dmamap_unload(sc->txwi_dmat, data->map); 1879 m_freem(m); 1880 return ENOBUFS; 1881 } 1882 } 1883 1884 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1885 1886 /* first segment is TXWI + 802.11 header */ 1887 txd = &ring->txd[ring->cur]; 1888 txd->sdp0 = htole32(data->paddr); 1889 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1890 txd->flags = qsel; 1891 1892 /* setup payload segments */ 1893 seg = &segs[0]; 1894 for (i = nsegs; i >= 2; i -= 2) { 1895 txd->sdp1 = htole32(seg->ds_addr); 1896 txd->sdl1 = htole16(seg->ds_len); 1897 seg++; 1898 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1899 /* grab a new Tx descriptor */ 1900 txd = &ring->txd[ring->cur]; 1901 txd->sdp0 = htole32(seg->ds_addr); 1902 txd->sdl0 = htole16(seg->ds_len); 1903 txd->flags = qsel; 1904 seg++; 1905 } 1906 /* finalize last segment */ 1907 if (i > 0) { 1908 txd->sdp1 = htole32(seg->ds_addr); 1909 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1910 } else { 1911 txd->sdl0 |= htole16(RT2860_TX_LS0); 1912 txd->sdl1 = 0; 1913 } 1914 1915 /* remove from the free pool and link it into the SW Tx slot */ 1916 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1917 data->m = m; 1918 data->ni = ni; 1919 ring->data[ring->cur] = data; 1920 1921 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1922 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1923 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1924 1925 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1926 qid, txwi->wcid, nsegs, ridx)); 1927 1928 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1929 ring->queued += ntxds; 1930 if (ring->queued >= RT2860_TX_RING_COUNT) 1931 sc->qfullmsk |= 1 << qid; 1932 1933 /* kick Tx */ 1934 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1935 1936 return 0; 1937 } 1938 1939 static int 1940 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1941 { 1942 struct rt2860_softc *sc = ic->ic_softc; 1943 int error; 1944 1945 RAL_LOCK(sc); 1946 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 1947 RAL_UNLOCK(sc); 1948 return (ENXIO); 1949 } 1950 error = mbufq_enqueue(&sc->sc_snd, m); 1951 if (error) { 1952 RAL_UNLOCK(sc); 1953 return (error); 1954 } 1955 rt2860_start(sc); 1956 RAL_UNLOCK(sc); 1957 1958 return (0); 1959 } 1960 1961 static void 1962 rt2860_start(struct rt2860_softc *sc) 1963 { 1964 struct ieee80211_node *ni; 1965 struct mbuf *m; 1966 1967 RAL_LOCK_ASSERT(sc); 1968 1969 if ((sc->sc_flags & RT2860_RUNNING) == 0) 1970 return; 1971 1972 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1973 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1974 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1975 if (rt2860_tx(sc, m, ni) != 0) { 1976 if_inc_counter(ni->ni_vap->iv_ifp, 1977 IFCOUNTER_OERRORS, 1); 1978 ieee80211_free_node(ni); 1979 continue; 1980 } 1981 sc->sc_tx_timer = 5; 1982 } 1983 } 1984 1985 static void 1986 rt2860_watchdog(void *arg) 1987 { 1988 struct rt2860_softc *sc = arg; 1989 1990 RAL_LOCK_ASSERT(sc); 1991 1992 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 1993 1994 if (sc->sc_invalid) /* card ejected */ 1995 return; 1996 1997 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1998 device_printf(sc->sc_dev, "device timeout\n"); 1999 rt2860_stop_locked(sc); 2000 rt2860_init_locked(sc); 2001 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 2002 return; 2003 } 2004 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2005 } 2006 2007 static void 2008 rt2860_parent(struct ieee80211com *ic) 2009 { 2010 struct rt2860_softc *sc = ic->ic_softc; 2011 int startall = 0; 2012 2013 RAL_LOCK(sc); 2014 if (ic->ic_nrunning> 0) { 2015 if (!(sc->sc_flags & RT2860_RUNNING)) { 2016 rt2860_init_locked(sc); 2017 startall = 1; 2018 } else 2019 rt2860_update_promisc(ic); 2020 } else if (sc->sc_flags & RT2860_RUNNING) 2021 rt2860_stop_locked(sc); 2022 RAL_UNLOCK(sc); 2023 if (startall) 2024 ieee80211_start_all(ic); 2025 } 2026 2027 /* 2028 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2029 * We access the BBP through the 8051 microcontroller unit which means that 2030 * the microcode must be loaded first. 2031 */ 2032 void 2033 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2034 { 2035 int ntries; 2036 2037 for (ntries = 0; ntries < 100; ntries++) { 2038 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2039 break; 2040 DELAY(1); 2041 } 2042 if (ntries == 100) { 2043 device_printf(sc->sc_dev, 2044 "could not write to BBP through MCU\n"); 2045 return; 2046 } 2047 2048 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2049 RT2860_BBP_CSR_KICK | reg << 8 | val); 2050 RAL_BARRIER_WRITE(sc); 2051 2052 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2053 DELAY(1000); 2054 } 2055 2056 uint8_t 2057 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2058 { 2059 uint32_t val; 2060 int ntries; 2061 2062 for (ntries = 0; ntries < 100; ntries++) { 2063 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2064 break; 2065 DELAY(1); 2066 } 2067 if (ntries == 100) { 2068 device_printf(sc->sc_dev, 2069 "could not read from BBP through MCU\n"); 2070 return 0; 2071 } 2072 2073 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2074 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2075 RAL_BARRIER_WRITE(sc); 2076 2077 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2078 DELAY(1000); 2079 2080 for (ntries = 0; ntries < 100; ntries++) { 2081 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2082 if (!(val & RT2860_BBP_CSR_KICK)) 2083 return val & 0xff; 2084 DELAY(1); 2085 } 2086 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2087 2088 return 0; 2089 } 2090 2091 /* 2092 * Write to one of the 4 programmable 24-bit RF registers. 2093 */ 2094 static void 2095 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2096 { 2097 uint32_t tmp; 2098 int ntries; 2099 2100 for (ntries = 0; ntries < 100; ntries++) { 2101 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2102 break; 2103 DELAY(1); 2104 } 2105 if (ntries == 100) { 2106 device_printf(sc->sc_dev, "could not write to RF\n"); 2107 return; 2108 } 2109 2110 /* RF registers are 24-bit on the RT2860 */ 2111 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2112 (val & 0x3fffff) << 2 | (reg & 3); 2113 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2114 } 2115 2116 static uint8_t 2117 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2118 { 2119 uint32_t tmp; 2120 int ntries; 2121 2122 for (ntries = 0; ntries < 100; ntries++) { 2123 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2124 break; 2125 DELAY(1); 2126 } 2127 if (ntries == 100) { 2128 device_printf(sc->sc_dev, "could not read RF register\n"); 2129 return 0xff; 2130 } 2131 tmp = RT3070_RF_KICK | reg << 8; 2132 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2133 2134 for (ntries = 0; ntries < 100; ntries++) { 2135 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2136 if (!(tmp & RT3070_RF_KICK)) 2137 break; 2138 DELAY(1); 2139 } 2140 if (ntries == 100) { 2141 device_printf(sc->sc_dev, "could not read RF register\n"); 2142 return 0xff; 2143 } 2144 return tmp & 0xff; 2145 } 2146 2147 void 2148 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2149 { 2150 uint32_t tmp; 2151 int ntries; 2152 2153 for (ntries = 0; ntries < 10; ntries++) { 2154 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2155 break; 2156 DELAY(10); 2157 } 2158 if (ntries == 10) { 2159 device_printf(sc->sc_dev, "could not write to RF\n"); 2160 return; 2161 } 2162 2163 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2164 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2165 } 2166 2167 /* 2168 * Send a command to the 8051 microcontroller unit. 2169 */ 2170 int 2171 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2172 { 2173 int slot, ntries; 2174 uint32_t tmp; 2175 uint8_t cid; 2176 2177 for (ntries = 0; ntries < 100; ntries++) { 2178 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2179 break; 2180 DELAY(2); 2181 } 2182 if (ntries == 100) 2183 return EIO; 2184 2185 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2186 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2187 RAL_BARRIER_WRITE(sc); 2188 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2189 2190 if (!wait) 2191 return 0; 2192 /* wait for the command to complete */ 2193 for (ntries = 0; ntries < 200; ntries++) { 2194 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2195 /* find the command slot */ 2196 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2197 if ((tmp & 0xff) == cid) 2198 break; 2199 if (slot < 4) 2200 break; 2201 DELAY(100); 2202 } 2203 if (ntries == 200) { 2204 /* clear command and status */ 2205 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2206 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2207 return ETIMEDOUT; 2208 } 2209 /* get command status (1 means success) */ 2210 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2211 tmp = (tmp >> (slot * 8)) & 0xff; 2212 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2213 cmd, slot, tmp)); 2214 /* clear command and status */ 2215 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2216 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2217 return (tmp == 1) ? 0 : EIO; 2218 } 2219 2220 static void 2221 rt2860_enable_mrr(struct rt2860_softc *sc) 2222 { 2223 #define CCK(mcs) (mcs) 2224 #define OFDM(mcs) (1 << 3 | (mcs)) 2225 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2226 OFDM(6) << 28 | /* 54->48 */ 2227 OFDM(5) << 24 | /* 48->36 */ 2228 OFDM(4) << 20 | /* 36->24 */ 2229 OFDM(3) << 16 | /* 24->18 */ 2230 OFDM(2) << 12 | /* 18->12 */ 2231 OFDM(1) << 8 | /* 12-> 9 */ 2232 OFDM(0) << 4 | /* 9-> 6 */ 2233 OFDM(0)); /* 6-> 6 */ 2234 2235 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2236 CCK(2) << 12 | /* 11->5.5 */ 2237 CCK(1) << 8 | /* 5.5-> 2 */ 2238 CCK(0) << 4 | /* 2-> 1 */ 2239 CCK(0)); /* 1-> 1 */ 2240 #undef OFDM 2241 #undef CCK 2242 } 2243 2244 static void 2245 rt2860_set_txpreamble(struct rt2860_softc *sc) 2246 { 2247 struct ieee80211com *ic = &sc->sc_ic; 2248 uint32_t tmp; 2249 2250 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2251 tmp &= ~RT2860_CCK_SHORT_EN; 2252 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2253 tmp |= RT2860_CCK_SHORT_EN; 2254 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2255 } 2256 2257 void 2258 rt2860_set_basicrates(struct rt2860_softc *sc, 2259 const struct ieee80211_rateset *rs) 2260 { 2261 struct ieee80211com *ic = &sc->sc_ic; 2262 uint32_t mask = 0; 2263 uint8_t rate; 2264 int i; 2265 2266 for (i = 0; i < rs->rs_nrates; i++) { 2267 rate = rs->rs_rates[i]; 2268 2269 if (!(rate & IEEE80211_RATE_BASIC)) 2270 continue; 2271 2272 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2273 IEEE80211_RV(rate)); 2274 } 2275 2276 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2277 } 2278 2279 static void 2280 rt2860_scan_start(struct ieee80211com *ic) 2281 { 2282 struct rt2860_softc *sc = ic->ic_softc; 2283 uint32_t tmp; 2284 2285 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2286 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2287 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2288 RT2860_TBTT_TIMER_EN)); 2289 rt2860_set_gp_timer(sc, 0); 2290 } 2291 2292 static void 2293 rt2860_scan_end(struct ieee80211com *ic) 2294 { 2295 struct rt2860_softc *sc = ic->ic_softc; 2296 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2297 2298 if (vap->iv_state == IEEE80211_S_RUN) { 2299 rt2860_enable_tsf_sync(sc); 2300 rt2860_set_gp_timer(sc, 500); 2301 } 2302 } 2303 2304 static void 2305 rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, 2306 struct ieee80211_channel chans[]) 2307 { 2308 struct rt2860_softc *sc = ic->ic_softc; 2309 uint8_t bands[IEEE80211_MODE_BYTES]; 2310 2311 memset(bands, 0, sizeof(bands)); 2312 setbit(bands, IEEE80211_MODE_11B); 2313 setbit(bands, IEEE80211_MODE_11G); 2314 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 2315 rt2860_chan_2ghz, nitems(rt2860_chan_2ghz), bands, 0); 2316 2317 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 2318 setbit(bands, IEEE80211_MODE_11A); 2319 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2320 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0); 2321 } 2322 } 2323 2324 static void 2325 rt2860_set_channel(struct ieee80211com *ic) 2326 { 2327 struct rt2860_softc *sc = ic->ic_softc; 2328 2329 RAL_LOCK(sc); 2330 rt2860_switch_chan(sc, ic->ic_curchan); 2331 RAL_UNLOCK(sc); 2332 } 2333 2334 static void 2335 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2336 { 2337 uint32_t tmp; 2338 uint8_t agc; 2339 2340 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2341 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2342 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2343 rt2860_mcu_bbp_write(sc, 86, 0x00); 2344 2345 if (group == 0) { 2346 if (sc->ext_2ghz_lna) { 2347 rt2860_mcu_bbp_write(sc, 82, 0x62); 2348 rt2860_mcu_bbp_write(sc, 75, 0x46); 2349 } else { 2350 rt2860_mcu_bbp_write(sc, 82, 0x84); 2351 rt2860_mcu_bbp_write(sc, 75, 0x50); 2352 } 2353 } else { 2354 if (sc->ext_5ghz_lna) { 2355 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2356 rt2860_mcu_bbp_write(sc, 75, 0x46); 2357 } else { 2358 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2359 rt2860_mcu_bbp_write(sc, 75, 0x50); 2360 } 2361 } 2362 2363 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2364 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2365 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2366 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2367 2368 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2369 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2370 if (sc->nrxchains > 1) 2371 tmp |= RT2860_LNA_PE1_EN; 2372 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2373 tmp |= RT3593_LNA_PE2_EN; 2374 if (group == 0) { /* 2GHz */ 2375 tmp |= RT2860_PA_PE_G0_EN; 2376 if (sc->ntxchains > 1) 2377 tmp |= RT2860_PA_PE_G1_EN; 2378 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2379 tmp |= RT3593_PA_PE_G2_EN; 2380 } else { /* 5GHz */ 2381 tmp |= RT2860_PA_PE_A0_EN; 2382 if (sc->ntxchains > 1) 2383 tmp |= RT2860_PA_PE_A1_EN; 2384 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2385 tmp |= RT3593_PA_PE_A2_EN; 2386 } 2387 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2388 2389 if (sc->mac_ver == 0x3593) { 2390 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2391 if (sc->sc_flags & RT2860_PCIE) { 2392 tmp &= ~0x01010000; 2393 if (group == 0) 2394 tmp |= 0x00010000; 2395 } else { 2396 tmp &= ~0x00008080; 2397 if (group == 0) 2398 tmp |= 0x00000080; 2399 } 2400 tmp = (tmp & ~0x00001000) | 0x00000010; 2401 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2402 } 2403 2404 /* set initial AGC value */ 2405 if (group == 0) { /* 2GHz band */ 2406 if (sc->mac_ver >= 0x3071) 2407 agc = 0x1c + sc->lna[0] * 2; 2408 else 2409 agc = 0x2e + sc->lna[0]; 2410 } else { /* 5GHz band */ 2411 agc = 0x32 + (sc->lna[group] * 5) / 3; 2412 } 2413 rt2860_mcu_bbp_write(sc, 66, agc); 2414 2415 DELAY(1000); 2416 } 2417 2418 static void 2419 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2420 { 2421 const struct rfprog *rfprog = rt2860_rf2850; 2422 uint32_t r2, r3, r4; 2423 int8_t txpow1, txpow2; 2424 u_int i; 2425 2426 /* find the settings for this channel (we know it exists) */ 2427 for (i = 0; rfprog[i].chan != chan; i++); 2428 2429 r2 = rfprog[i].r2; 2430 if (sc->ntxchains == 1) 2431 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2432 if (sc->nrxchains == 1) 2433 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2434 else if (sc->nrxchains == 2) 2435 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2436 2437 /* use Tx power values from EEPROM */ 2438 txpow1 = sc->txpow1[i]; 2439 txpow2 = sc->txpow2[i]; 2440 if (chan > 14) { 2441 if (txpow1 >= 0) 2442 txpow1 = txpow1 << 1 | 1; 2443 else 2444 txpow1 = (7 + txpow1) << 1; 2445 if (txpow2 >= 0) 2446 txpow2 = txpow2 << 1 | 1; 2447 else 2448 txpow2 = (7 + txpow2) << 1; 2449 } 2450 r3 = rfprog[i].r3 | txpow1 << 7; 2451 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2452 2453 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2454 rt2860_rf_write(sc, RT2860_RF2, r2); 2455 rt2860_rf_write(sc, RT2860_RF3, r3); 2456 rt2860_rf_write(sc, RT2860_RF4, r4); 2457 2458 DELAY(200); 2459 2460 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2461 rt2860_rf_write(sc, RT2860_RF2, r2); 2462 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2463 rt2860_rf_write(sc, RT2860_RF4, r4); 2464 2465 DELAY(200); 2466 2467 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2468 rt2860_rf_write(sc, RT2860_RF2, r2); 2469 rt2860_rf_write(sc, RT2860_RF3, r3); 2470 rt2860_rf_write(sc, RT2860_RF4, r4); 2471 } 2472 2473 static void 2474 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2475 { 2476 int8_t txpow1, txpow2; 2477 uint8_t rf; 2478 int i; 2479 2480 /* RT3090 is 2GHz only */ 2481 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2482 2483 /* find the settings for this channel (we know it exists) */ 2484 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2485 2486 /* use Tx power values from EEPROM */ 2487 txpow1 = sc->txpow1[i]; 2488 txpow2 = sc->txpow2[i]; 2489 2490 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2491 rf = rt3090_rf_read(sc, 3); 2492 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2493 rt3090_rf_write(sc, 3, rf); 2494 rf = rt3090_rf_read(sc, 6); 2495 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2496 rt3090_rf_write(sc, 6, rf); 2497 2498 /* set Tx0 power */ 2499 rf = rt3090_rf_read(sc, 12); 2500 rf = (rf & ~0x1f) | txpow1; 2501 rt3090_rf_write(sc, 12, rf); 2502 2503 /* set Tx1 power */ 2504 rf = rt3090_rf_read(sc, 13); 2505 rf = (rf & ~0x1f) | txpow2; 2506 rt3090_rf_write(sc, 13, rf); 2507 2508 rf = rt3090_rf_read(sc, 1); 2509 rf &= ~0xfc; 2510 if (sc->ntxchains == 1) 2511 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2512 else if (sc->ntxchains == 2) 2513 rf |= RT3070_TX2_PD; 2514 if (sc->nrxchains == 1) 2515 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2516 else if (sc->nrxchains == 2) 2517 rf |= RT3070_RX2_PD; 2518 rt3090_rf_write(sc, 1, rf); 2519 2520 /* set RF offset */ 2521 rf = rt3090_rf_read(sc, 23); 2522 rf = (rf & ~0x7f) | sc->freq; 2523 rt3090_rf_write(sc, 23, rf); 2524 2525 /* program RF filter */ 2526 rf = rt3090_rf_read(sc, 24); /* Tx */ 2527 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2528 rt3090_rf_write(sc, 24, rf); 2529 rf = rt3090_rf_read(sc, 31); /* Rx */ 2530 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2531 rt3090_rf_write(sc, 31, rf); 2532 2533 /* enable RF tuning */ 2534 rf = rt3090_rf_read(sc, 7); 2535 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2536 } 2537 2538 static void 2539 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2540 { 2541 uint8_t h20mhz, rf, tmp; 2542 int8_t txpow1, txpow2; 2543 int i; 2544 2545 /* RT5390 is 2GHz only */ 2546 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2547 2548 /* find the settings for this channel (we know it exists) */ 2549 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2550 2551 /* use Tx power values from EEPROM */ 2552 txpow1 = sc->txpow1[i]; 2553 txpow2 = sc->txpow2[i]; 2554 2555 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2556 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2557 rf = rt3090_rf_read(sc, 11); 2558 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2559 rt3090_rf_write(sc, 11, rf); 2560 2561 rf = rt3090_rf_read(sc, 49); 2562 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2563 /* the valid range of the RF R49 is 0x00~0x27 */ 2564 if ((rf & 0x3f) > 0x27) 2565 rf = (rf & ~0x3f) | 0x27; 2566 rt3090_rf_write(sc, 49, rf); 2567 if (sc->mac_ver == 0x5392) { 2568 rf = rt3090_rf_read(sc, 50); 2569 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2570 /* the valid range of the RF R50 is 0x00~0x27 */ 2571 if ((rf & 0x3f) > 0x27) 2572 rf = (rf & ~0x3f) | 0x27; 2573 rt3090_rf_write(sc, 50, rf); 2574 } 2575 2576 rf = rt3090_rf_read(sc, 1); 2577 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2578 if (sc->mac_ver == 0x5392) 2579 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2580 rt3090_rf_write(sc, 1, rf); 2581 2582 rf = rt3090_rf_read(sc, 2); 2583 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2584 DELAY(1000); 2585 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2586 2587 rf = rt3090_rf_read(sc, 17); 2588 tmp = rf; 2589 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2590 rf = MIN(rf, 0x5f); 2591 if (tmp != rf) 2592 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2593 2594 if (sc->mac_ver == 0x5390) { 2595 if (chan <= 4) 2596 rf = 0x73; 2597 else if (chan >= 5 && chan <= 6) 2598 rf = 0x63; 2599 else if (chan >= 7 && chan <= 10) 2600 rf = 0x53; 2601 else 2602 rf = 43; 2603 rt3090_rf_write(sc, 55, rf); 2604 2605 if (chan == 1) 2606 rf = 0x0c; 2607 else if (chan == 2) 2608 rf = 0x0b; 2609 else if (chan == 3) 2610 rf = 0x0a; 2611 else if (chan >= 4 && chan <= 6) 2612 rf = 0x09; 2613 else if (chan >= 7 && chan <= 12) 2614 rf = 0x08; 2615 else if (chan == 13) 2616 rf = 0x07; 2617 else 2618 rf = 0x06; 2619 rt3090_rf_write(sc, 59, rf); 2620 } 2621 2622 /* Tx/Rx h20M */ 2623 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2624 rf = rt3090_rf_read(sc, 30); 2625 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2626 rt3090_rf_write(sc, 30, rf); 2627 2628 /* Rx BB filter VCM */ 2629 rf = rt3090_rf_read(sc, 30); 2630 rf = (rf & ~0x18) | 0x10; 2631 rt3090_rf_write(sc, 30, rf); 2632 2633 /* Initiate VCO calibration. */ 2634 rf = rt3090_rf_read(sc, 3); 2635 rf |= RT3593_VCOCAL; 2636 rt3090_rf_write(sc, 3, rf); 2637 } 2638 2639 static int 2640 rt3090_rf_init(struct rt2860_softc *sc) 2641 { 2642 uint32_t tmp; 2643 uint8_t rf, bbp; 2644 int i; 2645 2646 rf = rt3090_rf_read(sc, 30); 2647 /* toggle RF R30 bit 7 */ 2648 rt3090_rf_write(sc, 30, rf | 0x80); 2649 DELAY(1000); 2650 rt3090_rf_write(sc, 30, rf & ~0x80); 2651 2652 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2653 tmp &= ~0x1f000000; 2654 if (sc->patch_dac && sc->mac_rev < 0x0211) 2655 tmp |= 0x0d000000; /* 1.35V */ 2656 else 2657 tmp |= 0x01000000; /* 1.2V */ 2658 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2659 2660 /* patch LNA_PE_G1 */ 2661 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2662 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2663 2664 /* initialize RF registers to default value */ 2665 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2666 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2667 rt3090_def_rf[i].val); 2668 } 2669 2670 /* select 20MHz bandwidth */ 2671 rt3090_rf_write(sc, 31, 0x14); 2672 2673 rf = rt3090_rf_read(sc, 6); 2674 rt3090_rf_write(sc, 6, rf | 0x40); 2675 2676 if (sc->mac_ver != 0x3593) { 2677 /* calibrate filter for 20MHz bandwidth */ 2678 sc->rf24_20mhz = 0x1f; /* default value */ 2679 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2680 2681 /* select 40MHz bandwidth */ 2682 bbp = rt2860_mcu_bbp_read(sc, 4); 2683 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2684 rf = rt3090_rf_read(sc, 31); 2685 rt3090_rf_write(sc, 31, rf | 0x20); 2686 2687 /* calibrate filter for 40MHz bandwidth */ 2688 sc->rf24_40mhz = 0x2f; /* default value */ 2689 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2690 2691 /* go back to 20MHz bandwidth */ 2692 bbp = rt2860_mcu_bbp_read(sc, 4); 2693 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2694 } 2695 if (sc->mac_rev < 0x0211) 2696 rt3090_rf_write(sc, 27, 0x03); 2697 2698 tmp = RAL_READ(sc, RT3070_OPT_14); 2699 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2700 2701 if (sc->rf_rev == RT3070_RF_3020) 2702 rt3090_set_rx_antenna(sc, 0); 2703 2704 bbp = rt2860_mcu_bbp_read(sc, 138); 2705 if (sc->mac_ver == 0x3593) { 2706 if (sc->ntxchains == 1) 2707 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2708 else if (sc->ntxchains == 2) 2709 bbp |= 0x40; /* turn off DAC2 */ 2710 if (sc->nrxchains == 1) 2711 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2712 else if (sc->nrxchains == 2) 2713 bbp &= ~0x04; /* turn off ADC2 */ 2714 } else { 2715 if (sc->ntxchains == 1) 2716 bbp |= 0x20; /* turn off DAC1 */ 2717 if (sc->nrxchains == 1) 2718 bbp &= ~0x02; /* turn off ADC1 */ 2719 } 2720 rt2860_mcu_bbp_write(sc, 138, bbp); 2721 2722 rf = rt3090_rf_read(sc, 1); 2723 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2724 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2725 rt3090_rf_write(sc, 1, rf); 2726 2727 rf = rt3090_rf_read(sc, 15); 2728 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2729 2730 rf = rt3090_rf_read(sc, 17); 2731 rf &= ~RT3070_TX_LO1; 2732 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2733 rf |= 0x20; /* fix for long range Rx issue */ 2734 if (sc->txmixgain_2ghz >= 2) 2735 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2736 rt3090_rf_write(sc, 17, rf); 2737 2738 rf = rt3090_rf_read(sc, 20); 2739 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2740 2741 rf = rt3090_rf_read(sc, 21); 2742 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2743 2744 return (0); 2745 } 2746 2747 static void 2748 rt5390_rf_init(struct rt2860_softc *sc) 2749 { 2750 uint8_t rf, bbp; 2751 int i; 2752 2753 rf = rt3090_rf_read(sc, 2); 2754 /* Toggle RF R2 bit 7. */ 2755 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2756 DELAY(1000); 2757 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2758 2759 /* Initialize RF registers to default value. */ 2760 if (sc->mac_ver == 0x5392) { 2761 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2762 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2763 rt5392_def_rf[i].val); 2764 } 2765 } else { 2766 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2767 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2768 rt5390_def_rf[i].val); 2769 } 2770 } 2771 2772 sc->rf24_20mhz = 0x1f; 2773 sc->rf24_40mhz = 0x2f; 2774 2775 if (sc->mac_rev < 0x0211) 2776 rt3090_rf_write(sc, 27, 0x03); 2777 2778 /* Set led open drain enable. */ 2779 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2780 2781 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2782 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2783 2784 if (sc->mac_ver == 0x5390) 2785 rt3090_set_rx_antenna(sc, 0); 2786 2787 /* Patch RSSI inaccurate issue. */ 2788 rt2860_mcu_bbp_write(sc, 79, 0x13); 2789 rt2860_mcu_bbp_write(sc, 80, 0x05); 2790 rt2860_mcu_bbp_write(sc, 81, 0x33); 2791 2792 /* Enable DC filter. */ 2793 if (sc->mac_rev >= 0x0211) 2794 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2795 2796 bbp = rt2860_mcu_bbp_read(sc, 138); 2797 if (sc->ntxchains == 1) 2798 bbp |= 0x20; /* Turn off DAC1. */ 2799 if (sc->nrxchains == 1) 2800 bbp &= ~0x02; /* Turn off ADC1. */ 2801 rt2860_mcu_bbp_write(sc, 138, bbp); 2802 2803 /* Enable RX LO1 and LO2. */ 2804 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2805 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2806 2807 /* Avoid data lost and CRC error. */ 2808 rt2860_mcu_bbp_write(sc, 4, 2809 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2810 2811 rf = rt3090_rf_read(sc, 30); 2812 rf = (rf & ~0x18) | 0x10; 2813 rt3090_rf_write(sc, 30, rf); 2814 } 2815 2816 static void 2817 rt3090_rf_wakeup(struct rt2860_softc *sc) 2818 { 2819 uint32_t tmp; 2820 uint8_t rf; 2821 2822 if (sc->mac_ver == 0x3593) { 2823 /* enable VCO */ 2824 rf = rt3090_rf_read(sc, 1); 2825 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2826 2827 /* initiate VCO calibration */ 2828 rf = rt3090_rf_read(sc, 3); 2829 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2830 2831 /* enable VCO bias current control */ 2832 rf = rt3090_rf_read(sc, 6); 2833 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2834 2835 /* initiate res calibration */ 2836 rf = rt3090_rf_read(sc, 2); 2837 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2838 2839 /* set reference current control to 0.33 mA */ 2840 rf = rt3090_rf_read(sc, 22); 2841 rf &= ~RT3593_CP_IC_MASK; 2842 rf |= 1 << RT3593_CP_IC_SHIFT; 2843 rt3090_rf_write(sc, 22, rf); 2844 2845 /* enable RX CTB */ 2846 rf = rt3090_rf_read(sc, 46); 2847 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2848 2849 rf = rt3090_rf_read(sc, 20); 2850 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2851 rt3090_rf_write(sc, 20, rf); 2852 } else { 2853 /* enable RF block */ 2854 rf = rt3090_rf_read(sc, 1); 2855 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2856 2857 /* enable VCO bias current control */ 2858 rf = rt3090_rf_read(sc, 7); 2859 rt3090_rf_write(sc, 7, rf | 0x30); 2860 2861 rf = rt3090_rf_read(sc, 9); 2862 rt3090_rf_write(sc, 9, rf | 0x0e); 2863 2864 /* enable RX CTB */ 2865 rf = rt3090_rf_read(sc, 21); 2866 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2867 2868 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2869 rf = rt3090_rf_read(sc, 27); 2870 rf &= ~0x77; 2871 if (sc->mac_rev < 0x0211) 2872 rf |= 0x03; 2873 rt3090_rf_write(sc, 27, rf); 2874 } 2875 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2876 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2877 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2878 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2879 } 2880 } 2881 2882 static void 2883 rt5390_rf_wakeup(struct rt2860_softc *sc) 2884 { 2885 uint32_t tmp; 2886 uint8_t rf; 2887 2888 rf = rt3090_rf_read(sc, 1); 2889 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2890 RT3070_TX0_PD; 2891 if (sc->mac_ver == 0x5392) 2892 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2893 rt3090_rf_write(sc, 1, rf); 2894 2895 rf = rt3090_rf_read(sc, 6); 2896 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2897 if (sc->mac_ver == 0x5390) 2898 rf &= ~RT3593_VCO_IC; 2899 rt3090_rf_write(sc, 6, rf); 2900 2901 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2902 2903 rf = rt3090_rf_read(sc, 22); 2904 rf = (rf & ~0xe0) | 0x20; 2905 rt3090_rf_write(sc, 22, rf); 2906 2907 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2908 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2909 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2910 2911 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2912 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2913 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2914 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2915 } 2916 } 2917 2918 static int 2919 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2920 uint8_t *val) 2921 { 2922 uint8_t rf22, rf24; 2923 uint8_t bbp55_pb, bbp55_sb, delta; 2924 int ntries; 2925 2926 /* program filter */ 2927 rf24 = rt3090_rf_read(sc, 24); 2928 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2929 rt3090_rf_write(sc, 24, rf24); 2930 2931 /* enable baseband loopback mode */ 2932 rf22 = rt3090_rf_read(sc, 22); 2933 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2934 2935 /* set power and frequency of passband test tone */ 2936 rt2860_mcu_bbp_write(sc, 24, 0x00); 2937 for (ntries = 0; ntries < 100; ntries++) { 2938 /* transmit test tone */ 2939 rt2860_mcu_bbp_write(sc, 25, 0x90); 2940 DELAY(1000); 2941 /* read received power */ 2942 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2943 if (bbp55_pb != 0) 2944 break; 2945 } 2946 if (ntries == 100) 2947 return (ETIMEDOUT); 2948 2949 /* set power and frequency of stopband test tone */ 2950 rt2860_mcu_bbp_write(sc, 24, 0x06); 2951 for (ntries = 0; ntries < 100; ntries++) { 2952 /* transmit test tone */ 2953 rt2860_mcu_bbp_write(sc, 25, 0x90); 2954 DELAY(1000); 2955 /* read received power */ 2956 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2957 2958 delta = bbp55_pb - bbp55_sb; 2959 if (delta > target) 2960 break; 2961 2962 /* reprogram filter */ 2963 rf24++; 2964 rt3090_rf_write(sc, 24, rf24); 2965 } 2966 if (ntries < 100) { 2967 if (rf24 != init) 2968 rf24--; /* backtrack */ 2969 *val = rf24; 2970 rt3090_rf_write(sc, 24, rf24); 2971 } 2972 2973 /* restore initial state */ 2974 rt2860_mcu_bbp_write(sc, 24, 0x00); 2975 2976 /* disable baseband loopback mode */ 2977 rf22 = rt3090_rf_read(sc, 22); 2978 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2979 2980 return (0); 2981 } 2982 2983 static void 2984 rt3090_rf_setup(struct rt2860_softc *sc) 2985 { 2986 uint8_t bbp; 2987 int i; 2988 2989 if (sc->mac_rev >= 0x0211) { 2990 /* enable DC filter */ 2991 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2992 2993 /* improve power consumption */ 2994 bbp = rt2860_mcu_bbp_read(sc, 31); 2995 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2996 } 2997 2998 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2999 if (sc->mac_rev < 0x0211) { 3000 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 3001 sc->patch_dac ? 0x2c : 0x0f); 3002 } else 3003 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 3004 3005 /* initialize RF registers from ROM */ 3006 if (sc->mac_ver < 0x5390) { 3007 for (i = 0; i < 10; i++) { 3008 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 3009 continue; 3010 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3011 } 3012 } 3013 } 3014 3015 static void 3016 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3017 { 3018 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3019 which | (sc->leds & 0x7f), 0); 3020 } 3021 3022 /* 3023 * Hardware has a general-purpose programmable timer interrupt that can 3024 * periodically raise MAC_INT_4. 3025 */ 3026 static void 3027 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3028 { 3029 uint32_t tmp; 3030 3031 /* disable GP timer before reprogramming it */ 3032 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3033 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3034 3035 if (ms == 0) 3036 return; 3037 3038 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3039 ms *= 16; /* Unit: 64us */ 3040 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3041 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3042 3043 /* enable GP timer */ 3044 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3045 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3046 } 3047 3048 static void 3049 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3050 { 3051 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3052 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3053 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3054 bssid[4] | bssid[5] << 8); 3055 } 3056 3057 static void 3058 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3059 { 3060 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3061 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3062 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3063 addr[4] | addr[5] << 8 | 0xff << 16); 3064 } 3065 3066 static void 3067 rt2860_updateslot(struct ieee80211com *ic) 3068 { 3069 struct rt2860_softc *sc = ic->ic_softc; 3070 uint32_t tmp; 3071 3072 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3073 tmp &= ~0xff; 3074 tmp |= IEEE80211_GET_SLOTTIME(ic); 3075 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3076 } 3077 3078 static void 3079 rt2860_updateprot(struct rt2860_softc *sc) 3080 { 3081 struct ieee80211com *ic = &sc->sc_ic; 3082 uint32_t tmp; 3083 3084 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3085 /* setup protection frame rate (MCS code) */ 3086 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3087 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3088 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3089 3090 /* CCK frames don't require protection */ 3091 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3092 3093 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3094 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3095 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3096 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3097 tmp |= RT2860_PROT_CTRL_CTS; 3098 } 3099 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3100 } 3101 3102 static void 3103 rt2860_update_promisc(struct ieee80211com *ic) 3104 { 3105 struct rt2860_softc *sc = ic->ic_softc; 3106 uint32_t tmp; 3107 3108 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3109 tmp &= ~RT2860_DROP_NOT_MYBSS; 3110 if (ic->ic_promisc == 0) 3111 tmp |= RT2860_DROP_NOT_MYBSS; 3112 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3113 } 3114 3115 static int 3116 rt2860_updateedca(struct ieee80211com *ic) 3117 { 3118 struct rt2860_softc *sc = ic->ic_softc; 3119 const struct wmeParams *wmep; 3120 int aci; 3121 3122 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 3123 3124 /* update MAC TX configuration registers */ 3125 for (aci = 0; aci < WME_NUM_AC; aci++) { 3126 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3127 wmep[aci].wmep_logcwmax << 16 | 3128 wmep[aci].wmep_logcwmin << 12 | 3129 wmep[aci].wmep_aifsn << 8 | 3130 wmep[aci].wmep_txopLimit); 3131 } 3132 3133 /* update SCH/DMA registers too */ 3134 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3135 wmep[WME_AC_VO].wmep_aifsn << 12 | 3136 wmep[WME_AC_VI].wmep_aifsn << 8 | 3137 wmep[WME_AC_BK].wmep_aifsn << 4 | 3138 wmep[WME_AC_BE].wmep_aifsn); 3139 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3140 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3141 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3142 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3143 wmep[WME_AC_BE].wmep_logcwmin); 3144 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3145 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3146 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3147 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3148 wmep[WME_AC_BE].wmep_logcwmax); 3149 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3150 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3151 wmep[WME_AC_BE].wmep_txopLimit); 3152 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3153 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3154 wmep[WME_AC_VI].wmep_txopLimit); 3155 3156 return 0; 3157 } 3158 3159 #ifdef HW_CRYPTO 3160 static int 3161 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3162 struct ieee80211_key *k) 3163 { 3164 struct rt2860_softc *sc = ic->ic_softc; 3165 bus_size_t base; 3166 uint32_t attr; 3167 uint8_t mode, wcid, iv[8]; 3168 3169 /* defer setting of WEP keys until interface is brought up */ 3170 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3171 (IFF_UP | IFF_RUNNING)) 3172 return 0; 3173 3174 /* map net80211 cipher to RT2860 security mode */ 3175 switch (k->k_cipher) { 3176 case IEEE80211_CIPHER_WEP40: 3177 mode = RT2860_MODE_WEP40; 3178 break; 3179 case IEEE80211_CIPHER_WEP104: 3180 mode = RT2860_MODE_WEP104; 3181 break; 3182 case IEEE80211_CIPHER_TKIP: 3183 mode = RT2860_MODE_TKIP; 3184 break; 3185 case IEEE80211_CIPHER_CCMP: 3186 mode = RT2860_MODE_AES_CCMP; 3187 break; 3188 default: 3189 return EINVAL; 3190 } 3191 3192 if (k->k_flags & IEEE80211_KEY_GROUP) { 3193 wcid = 0; /* NB: update WCID0 for group keys */ 3194 base = RT2860_SKEY(0, k->k_id); 3195 } else { 3196 wcid = ((struct rt2860_node *)ni)->wcid; 3197 base = RT2860_PKEY(wcid); 3198 } 3199 3200 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3201 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3202 #ifndef IEEE80211_STA_ONLY 3203 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3204 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3205 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3206 } else 3207 #endif 3208 { 3209 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3210 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3211 } 3212 } else 3213 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3214 3215 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3216 (k->k_flags & IEEE80211_KEY_TX)) { 3217 /* set initial packet number in IV+EIV */ 3218 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3219 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3220 uint32_t val = arc4random(); 3221 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3222 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3223 val += 0x000100; 3224 iv[0] = val; 3225 iv[1] = val >> 8; 3226 iv[2] = val >> 16; 3227 iv[3] = k->k_id << 6; 3228 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3229 } else { 3230 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3231 iv[0] = k->k_tsc >> 8; 3232 iv[1] = (iv[0] | 0x20) & 0x7f; 3233 iv[2] = k->k_tsc; 3234 } else /* CCMP */ { 3235 iv[0] = k->k_tsc; 3236 iv[1] = k->k_tsc >> 8; 3237 iv[2] = 0; 3238 } 3239 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3240 iv[4] = k->k_tsc >> 16; 3241 iv[5] = k->k_tsc >> 24; 3242 iv[6] = k->k_tsc >> 32; 3243 iv[7] = k->k_tsc >> 40; 3244 } 3245 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3246 } 3247 3248 if (k->k_flags & IEEE80211_KEY_GROUP) { 3249 /* install group key */ 3250 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3251 attr &= ~(0xf << (k->k_id * 4)); 3252 attr |= mode << (k->k_id * 4); 3253 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3254 } else { 3255 /* install pairwise key */ 3256 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3257 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3258 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3259 } 3260 return 0; 3261 } 3262 3263 static void 3264 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3265 struct ieee80211_key *k) 3266 { 3267 struct rt2860_softc *sc = ic->ic_softc; 3268 uint32_t attr; 3269 uint8_t wcid; 3270 3271 if (k->k_flags & IEEE80211_KEY_GROUP) { 3272 /* remove group key */ 3273 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3274 attr &= ~(0xf << (k->k_id * 4)); 3275 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3276 3277 } else { 3278 /* remove pairwise key */ 3279 wcid = ((struct rt2860_node *)ni)->wcid; 3280 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3281 attr &= ~0xf; 3282 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3283 } 3284 } 3285 #endif 3286 3287 static int8_t 3288 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3289 { 3290 struct ieee80211com *ic = &sc->sc_ic; 3291 struct ieee80211_channel *c = ic->ic_curchan; 3292 int delta; 3293 3294 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3295 u_int chan = ieee80211_chan2ieee(ic, c); 3296 delta = sc->rssi_5ghz[rxchain]; 3297 3298 /* determine channel group */ 3299 if (chan <= 64) 3300 delta -= sc->lna[1]; 3301 else if (chan <= 128) 3302 delta -= sc->lna[2]; 3303 else 3304 delta -= sc->lna[3]; 3305 } else 3306 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3307 3308 return -12 - delta - rssi; 3309 } 3310 3311 /* 3312 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3313 * Used to adjust per-rate Tx power registers. 3314 */ 3315 static __inline uint32_t 3316 b4inc(uint32_t b32, int8_t delta) 3317 { 3318 int8_t i, b4; 3319 3320 for (i = 0; i < 8; i++) { 3321 b4 = b32 & 0xf; 3322 b4 += delta; 3323 if (b4 < 0) 3324 b4 = 0; 3325 else if (b4 > 0xf) 3326 b4 = 0xf; 3327 b32 = b32 >> 4 | b4 << 28; 3328 } 3329 return b32; 3330 } 3331 3332 static const char * 3333 rt2860_get_rf(uint16_t rev) 3334 { 3335 switch (rev) { 3336 case RT2860_RF_2820: return "RT2820"; 3337 case RT2860_RF_2850: return "RT2850"; 3338 case RT2860_RF_2720: return "RT2720"; 3339 case RT2860_RF_2750: return "RT2750"; 3340 case RT3070_RF_3020: return "RT3020"; 3341 case RT3070_RF_2020: return "RT2020"; 3342 case RT3070_RF_3021: return "RT3021"; 3343 case RT3070_RF_3022: return "RT3022"; 3344 case RT3070_RF_3052: return "RT3052"; 3345 case RT3070_RF_3320: return "RT3320"; 3346 case RT3070_RF_3053: return "RT3053"; 3347 case RT5390_RF_5360: return "RT5360"; 3348 case RT5390_RF_5390: return "RT5390"; 3349 default: return "unknown"; 3350 } 3351 } 3352 3353 static int 3354 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3355 { 3356 int8_t delta_2ghz, delta_5ghz; 3357 uint32_t tmp; 3358 uint16_t val; 3359 int ridx, ant, i; 3360 3361 /* check whether the ROM is eFUSE ROM or EEPROM */ 3362 sc->sc_srom_read = rt2860_eeprom_read_2; 3363 if (sc->mac_ver >= 0x3071) { 3364 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3365 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3366 if (tmp & RT3070_SEL_EFUSE) 3367 sc->sc_srom_read = rt3090_efuse_read_2; 3368 } 3369 3370 #ifdef RAL_DEBUG 3371 /* read EEPROM version */ 3372 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3373 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3374 #endif 3375 3376 /* read MAC address */ 3377 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3378 macaddr[0] = val & 0xff; 3379 macaddr[1] = val >> 8; 3380 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3381 macaddr[2] = val & 0xff; 3382 macaddr[3] = val >> 8; 3383 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3384 macaddr[4] = val & 0xff; 3385 macaddr[5] = val >> 8; 3386 3387 #ifdef RAL_DEBUG 3388 /* read country code */ 3389 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3390 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3391 #endif 3392 3393 /* read vendor BBP settings */ 3394 for (i = 0; i < 8; i++) { 3395 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3396 sc->bbp[i].val = val & 0xff; 3397 sc->bbp[i].reg = val >> 8; 3398 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3399 } 3400 if (sc->mac_ver >= 0x3071) { 3401 /* read vendor RF settings */ 3402 for (i = 0; i < 10; i++) { 3403 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3404 sc->rf[i].val = val & 0xff; 3405 sc->rf[i].reg = val >> 8; 3406 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3407 sc->rf[i].val)); 3408 } 3409 } 3410 3411 /* read RF frequency offset from EEPROM */ 3412 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3413 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3414 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3415 if ((val >> 8) != 0xff) { 3416 /* read LEDs operating mode */ 3417 sc->leds = val >> 8; 3418 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3419 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3420 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3421 } else { 3422 /* broken EEPROM, use default settings */ 3423 sc->leds = 0x01; 3424 sc->led[0] = 0x5555; 3425 sc->led[1] = 0x2221; 3426 sc->led[2] = 0xa9f8; 3427 } 3428 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3429 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3430 3431 /* read RF information */ 3432 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3433 if (sc->mac_ver >= 0x5390) 3434 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3435 else 3436 sc->rf_rev = (val >> 8) & 0xf; 3437 sc->ntxchains = (val >> 4) & 0xf; 3438 sc->nrxchains = val & 0xf; 3439 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3440 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3441 3442 /* check if RF supports automatic Tx access gain control */ 3443 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3444 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3445 /* check if driver should patch the DAC issue */ 3446 if ((val >> 8) != 0xff) 3447 sc->patch_dac = (val >> 15) & 1; 3448 if ((val & 0xff) != 0xff) { 3449 sc->ext_5ghz_lna = (val >> 3) & 1; 3450 sc->ext_2ghz_lna = (val >> 2) & 1; 3451 /* check if RF supports automatic Tx access gain control */ 3452 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3453 /* check if we have a hardware radio switch */ 3454 sc->rfswitch = val & 1; 3455 } 3456 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3457 /* read PCIe power save level */ 3458 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3459 if ((val & 0xff) != 0xff) { 3460 sc->pslevel = val & 0x3; 3461 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3462 if ((val & 0xff80) != 0x9280) 3463 sc->pslevel = MIN(sc->pslevel, 1); 3464 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3465 } 3466 } 3467 3468 /* read power settings for 2GHz channels */ 3469 for (i = 0; i < 14; i += 2) { 3470 val = rt2860_srom_read(sc, 3471 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3472 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3473 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3474 3475 if (sc->mac_ver != 0x5390) { 3476 val = rt2860_srom_read(sc, 3477 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3478 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3479 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3480 } 3481 } 3482 /* fix broken Tx power entries */ 3483 for (i = 0; i < 14; i++) { 3484 if (sc->txpow1[i] < 0 || 3485 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3486 sc->txpow1[i] = 5; 3487 if (sc->mac_ver != 0x5390) { 3488 if (sc->txpow2[i] < 0 || 3489 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3490 sc->txpow2[i] = 5; 3491 } 3492 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3493 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3494 } 3495 /* read power settings for 5GHz channels */ 3496 for (i = 0; i < 40; i += 2) { 3497 val = rt2860_srom_read(sc, 3498 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3499 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3500 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3501 3502 val = rt2860_srom_read(sc, 3503 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3504 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3505 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3506 } 3507 /* fix broken Tx power entries */ 3508 for (i = 0; i < 40; i++) { 3509 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3510 sc->txpow1[14 + i] = 5; 3511 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3512 sc->txpow2[14 + i] = 5; 3513 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3514 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3515 sc->txpow2[14 + i])); 3516 } 3517 3518 /* read Tx power compensation for each Tx rate */ 3519 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3520 delta_2ghz = delta_5ghz = 0; 3521 if ((val & 0xff) != 0xff && (val & 0x80)) { 3522 delta_2ghz = val & 0xf; 3523 if (!(val & 0x40)) /* negative number */ 3524 delta_2ghz = -delta_2ghz; 3525 } 3526 val >>= 8; 3527 if ((val & 0xff) != 0xff && (val & 0x80)) { 3528 delta_5ghz = val & 0xf; 3529 if (!(val & 0x40)) /* negative number */ 3530 delta_5ghz = -delta_5ghz; 3531 } 3532 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3533 delta_2ghz, delta_5ghz)); 3534 3535 for (ridx = 0; ridx < 5; ridx++) { 3536 uint32_t reg; 3537 3538 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3539 reg = val; 3540 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3541 reg |= (uint32_t)val << 16; 3542 3543 sc->txpow20mhz[ridx] = reg; 3544 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3545 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3546 3547 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3548 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3549 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3550 } 3551 3552 /* read factory-calibrated samples for temperature compensation */ 3553 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3554 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3555 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3556 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3557 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3558 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3559 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3560 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3561 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3562 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3563 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3564 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3565 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3566 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3567 sc->step_2ghz = val >> 8; 3568 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3569 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3570 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3571 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3572 sc->tssi_2ghz[8], sc->step_2ghz)); 3573 /* check that ref value is correct, otherwise disable calibration */ 3574 if (sc->tssi_2ghz[4] == 0xff) 3575 sc->calib_2ghz = 0; 3576 3577 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3578 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3579 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3580 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3581 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3582 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3583 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3584 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3585 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3586 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3587 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3588 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3589 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3590 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3591 sc->step_5ghz = val >> 8; 3592 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3593 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3594 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3595 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3596 sc->tssi_5ghz[8], sc->step_5ghz)); 3597 /* check that ref value is correct, otherwise disable calibration */ 3598 if (sc->tssi_5ghz[4] == 0xff) 3599 sc->calib_5ghz = 0; 3600 3601 /* read RSSI offsets and LNA gains from EEPROM */ 3602 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3603 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3604 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3605 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3606 if (sc->mac_ver >= 0x3071) { 3607 /* 3608 * On RT3090 chips (limited to 2 Rx chains), this ROM 3609 * field contains the Tx mixer gain for the 2GHz band. 3610 */ 3611 if ((val & 0xff) != 0xff) 3612 sc->txmixgain_2ghz = val & 0x7; 3613 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3614 } else 3615 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3616 sc->lna[2] = val >> 8; /* channel group 2 */ 3617 3618 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3619 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3620 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3621 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3622 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3623 sc->lna[3] = val >> 8; /* channel group 3 */ 3624 3625 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3626 if (sc->mac_ver >= 0x3071) 3627 sc->lna[0] = RT3090_DEF_LNA; 3628 else /* channel group 0 */ 3629 sc->lna[0] = val & 0xff; 3630 sc->lna[1] = val >> 8; /* channel group 1 */ 3631 3632 /* fix broken 5GHz LNA entries */ 3633 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3634 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3635 sc->lna[2] = sc->lna[1]; 3636 } 3637 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3638 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3639 sc->lna[3] = sc->lna[1]; 3640 } 3641 3642 /* fix broken RSSI offset entries */ 3643 for (ant = 0; ant < 3; ant++) { 3644 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3645 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3646 ant + 1, sc->rssi_2ghz[ant])); 3647 sc->rssi_2ghz[ant] = 0; 3648 } 3649 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3650 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3651 ant + 1, sc->rssi_5ghz[ant])); 3652 sc->rssi_5ghz[ant] = 0; 3653 } 3654 } 3655 3656 return 0; 3657 } 3658 3659 static int 3660 rt2860_bbp_init(struct rt2860_softc *sc) 3661 { 3662 int i, ntries; 3663 3664 /* wait for BBP to wake up */ 3665 for (ntries = 0; ntries < 20; ntries++) { 3666 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3667 if (bbp0 != 0 && bbp0 != 0xff) 3668 break; 3669 } 3670 if (ntries == 20) { 3671 device_printf(sc->sc_dev, 3672 "timeout waiting for BBP to wake up\n"); 3673 return (ETIMEDOUT); 3674 } 3675 3676 /* initialize BBP registers to default values */ 3677 if (sc->mac_ver >= 0x5390) 3678 rt5390_bbp_init(sc); 3679 else { 3680 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3681 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3682 rt2860_def_bbp[i].val); 3683 } 3684 } 3685 3686 /* fix BBP84 for RT2860E */ 3687 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3688 rt2860_mcu_bbp_write(sc, 84, 0x19); 3689 3690 if (sc->mac_ver >= 0x3071) { 3691 rt2860_mcu_bbp_write(sc, 79, 0x13); 3692 rt2860_mcu_bbp_write(sc, 80, 0x05); 3693 rt2860_mcu_bbp_write(sc, 81, 0x33); 3694 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3695 rt2860_mcu_bbp_write(sc, 69, 0x16); 3696 rt2860_mcu_bbp_write(sc, 73, 0x12); 3697 } 3698 3699 return 0; 3700 } 3701 3702 static void 3703 rt5390_bbp_init(struct rt2860_softc *sc) 3704 { 3705 uint8_t bbp; 3706 int i; 3707 3708 /* Apply maximum likelihood detection for 2 stream case. */ 3709 if (sc->nrxchains > 1) { 3710 bbp = rt2860_mcu_bbp_read(sc, 105); 3711 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3712 } 3713 3714 /* Avoid data lost and CRC error. */ 3715 bbp = rt2860_mcu_bbp_read(sc, 4); 3716 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3717 3718 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3719 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3720 rt5390_def_bbp[i].val); 3721 } 3722 3723 if (sc->mac_ver == 0x5392) { 3724 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3725 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3726 rt2860_mcu_bbp_write(sc, 98, 0x12); 3727 rt2860_mcu_bbp_write(sc, 106, 0x05); 3728 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3729 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3730 } 3731 3732 bbp = rt2860_mcu_bbp_read(sc, 152); 3733 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3734 3735 /* Disable hardware antenna diversity. */ 3736 if (sc->mac_ver == 0x5390) 3737 rt2860_mcu_bbp_write(sc, 154, 0); 3738 } 3739 3740 static int 3741 rt2860_txrx_enable(struct rt2860_softc *sc) 3742 { 3743 struct ieee80211com *ic = &sc->sc_ic; 3744 uint32_t tmp; 3745 int ntries; 3746 3747 /* enable Tx/Rx DMA engine */ 3748 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3749 RAL_BARRIER_READ_WRITE(sc); 3750 for (ntries = 0; ntries < 200; ntries++) { 3751 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3752 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3753 break; 3754 DELAY(1000); 3755 } 3756 if (ntries == 200) { 3757 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3758 return ETIMEDOUT; 3759 } 3760 3761 DELAY(50); 3762 3763 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3764 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3765 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3766 3767 /* set Rx filter */ 3768 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3769 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3770 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3771 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3772 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3773 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3774 if (ic->ic_opmode == IEEE80211_M_STA) 3775 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3776 } 3777 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3778 3779 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3780 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3781 3782 return 0; 3783 } 3784 3785 static void 3786 rt2860_init(void *arg) 3787 { 3788 struct rt2860_softc *sc = arg; 3789 struct ieee80211com *ic = &sc->sc_ic; 3790 3791 RAL_LOCK(sc); 3792 rt2860_init_locked(sc); 3793 RAL_UNLOCK(sc); 3794 3795 if (sc->sc_flags & RT2860_RUNNING) 3796 ieee80211_start_all(ic); 3797 } 3798 3799 static void 3800 rt2860_init_locked(struct rt2860_softc *sc) 3801 { 3802 struct ieee80211com *ic = &sc->sc_ic; 3803 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3804 uint32_t tmp; 3805 uint8_t bbp1, bbp3; 3806 int i, qid, ridx, ntries, error; 3807 3808 RAL_LOCK_ASSERT(sc); 3809 3810 if (sc->rfswitch) { 3811 /* hardware has a radio switch on GPIO pin 2 */ 3812 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3813 device_printf(sc->sc_dev, 3814 "radio is disabled by hardware switch\n"); 3815 #ifdef notyet 3816 rt2860_stop_locked(sc); 3817 return; 3818 #endif 3819 } 3820 } 3821 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3822 3823 /* disable DMA */ 3824 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3825 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3826 RT2860_TX_DMA_EN); 3827 tmp |= RT2860_TX_WB_DDONE; 3828 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3829 3830 /* reset DMA indexes */ 3831 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3832 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3833 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3834 3835 /* PBF hardware reset */ 3836 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3837 RAL_BARRIER_WRITE(sc); 3838 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3839 3840 if ((error = rt2860_load_microcode(sc)) != 0) { 3841 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3842 rt2860_stop_locked(sc); 3843 return; 3844 } 3845 3846 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3847 3848 /* init Tx power for all Tx rates (from EEPROM) */ 3849 for (ridx = 0; ridx < 5; ridx++) { 3850 if (sc->txpow20mhz[ridx] == 0xffffffff) 3851 continue; 3852 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3853 } 3854 3855 for (ntries = 0; ntries < 100; ntries++) { 3856 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3857 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3858 break; 3859 DELAY(1000); 3860 } 3861 if (ntries == 100) { 3862 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3863 rt2860_stop_locked(sc); 3864 return; 3865 } 3866 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3867 RT2860_TX_DMA_EN); 3868 tmp |= RT2860_TX_WB_DDONE; 3869 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3870 3871 /* reset Rx ring and all 6 Tx rings */ 3872 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3873 3874 /* PBF hardware reset */ 3875 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3876 RAL_BARRIER_WRITE(sc); 3877 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3878 3879 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3880 3881 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3882 RAL_BARRIER_WRITE(sc); 3883 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3884 3885 for (i = 0; i < nitems(rt2860_def_mac); i++) 3886 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3887 if (sc->mac_ver >= 0x5390) 3888 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3889 else if (sc->mac_ver >= 0x3071) { 3890 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3891 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3892 4 << RT2860_DLY_PAPE_EN_SHIFT); 3893 } 3894 3895 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3896 sc->sc_flags |= RT2860_PCIE; 3897 /* PCIe has different clock cycle count than PCI */ 3898 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3899 tmp = (tmp & ~0xff) | 0x7d; 3900 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3901 } 3902 3903 /* wait while MAC is busy */ 3904 for (ntries = 0; ntries < 100; ntries++) { 3905 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3906 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3907 break; 3908 DELAY(1000); 3909 } 3910 if (ntries == 100) { 3911 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3912 rt2860_stop_locked(sc); 3913 return; 3914 } 3915 3916 /* clear Host to MCU mailbox */ 3917 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3918 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3919 3920 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3921 DELAY(1000); 3922 3923 if ((error = rt2860_bbp_init(sc)) != 0) { 3924 rt2860_stop_locked(sc); 3925 return; 3926 } 3927 3928 /* clear RX WCID search table */ 3929 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3930 /* clear pairwise key table */ 3931 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3932 /* clear IV/EIV table */ 3933 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3934 /* clear WCID attribute table */ 3935 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3936 /* clear shared key table */ 3937 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3938 /* clear shared key mode */ 3939 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3940 3941 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3942 for (qid = 0; qid < 6; qid++) { 3943 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3944 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3945 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3946 } 3947 3948 /* init Rx ring */ 3949 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3950 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3951 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3952 3953 /* setup maximum buffer sizes */ 3954 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3955 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3956 3957 for (ntries = 0; ntries < 100; ntries++) { 3958 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3959 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3960 break; 3961 DELAY(1000); 3962 } 3963 if (ntries == 100) { 3964 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3965 rt2860_stop_locked(sc); 3966 return; 3967 } 3968 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3969 RT2860_TX_DMA_EN); 3970 tmp |= RT2860_TX_WB_DDONE; 3971 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3972 3973 /* disable interrupts mitigation */ 3974 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3975 3976 /* write vendor-specific BBP values (from EEPROM) */ 3977 for (i = 0; i < 8; i++) { 3978 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3979 continue; 3980 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3981 } 3982 3983 /* select Main antenna for 1T1R devices */ 3984 if (sc->rf_rev == RT3070_RF_2020 || 3985 sc->rf_rev == RT3070_RF_3020 || 3986 sc->rf_rev == RT3070_RF_3320 || 3987 sc->mac_ver == 0x5390) 3988 rt3090_set_rx_antenna(sc, 0); 3989 3990 /* send LEDs operating mode to microcontroller */ 3991 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3992 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3993 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3994 3995 if (sc->mac_ver >= 0x5390) 3996 rt5390_rf_init(sc); 3997 else if (sc->mac_ver >= 0x3071) { 3998 if ((error = rt3090_rf_init(sc)) != 0) { 3999 rt2860_stop_locked(sc); 4000 return; 4001 } 4002 } 4003 4004 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 4005 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 4006 4007 if (sc->mac_ver >= 0x5390) 4008 rt5390_rf_wakeup(sc); 4009 else if (sc->mac_ver >= 0x3071) 4010 rt3090_rf_wakeup(sc); 4011 4012 /* disable non-existing Rx chains */ 4013 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4014 bbp3 &= ~(1 << 3 | 1 << 4); 4015 if (sc->nrxchains == 2) 4016 bbp3 |= 1 << 3; 4017 else if (sc->nrxchains == 3) 4018 bbp3 |= 1 << 4; 4019 rt2860_mcu_bbp_write(sc, 3, bbp3); 4020 4021 /* disable non-existing Tx chains */ 4022 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4023 if (sc->ntxchains == 1) 4024 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4025 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4026 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4027 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4028 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4029 rt2860_mcu_bbp_write(sc, 1, bbp1); 4030 4031 if (sc->mac_ver >= 0x3071) 4032 rt3090_rf_setup(sc); 4033 4034 /* select default channel */ 4035 rt2860_switch_chan(sc, ic->ic_curchan); 4036 4037 /* reset RF from MCU */ 4038 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4039 4040 /* set RTS threshold */ 4041 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4042 tmp &= ~0xffff00; 4043 tmp |= IEEE80211_RTS_DEFAULT << 8; 4044 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4045 4046 /* setup initial protection mode */ 4047 rt2860_updateprot(sc); 4048 4049 /* turn radio LED on */ 4050 rt2860_set_leds(sc, RT2860_LED_RADIO); 4051 4052 /* enable Tx/Rx DMA engine */ 4053 if ((error = rt2860_txrx_enable(sc)) != 0) { 4054 rt2860_stop_locked(sc); 4055 return; 4056 } 4057 4058 /* clear pending interrupts */ 4059 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4060 /* enable interrupts */ 4061 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4062 4063 if (sc->sc_flags & RT2860_ADVANCED_PS) 4064 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4065 4066 sc->sc_flags |= RT2860_RUNNING; 4067 4068 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4069 } 4070 4071 static void 4072 rt2860_stop(void *arg) 4073 { 4074 struct rt2860_softc *sc = arg; 4075 4076 RAL_LOCK(sc); 4077 rt2860_stop_locked(sc); 4078 RAL_UNLOCK(sc); 4079 } 4080 4081 static void 4082 rt2860_stop_locked(struct rt2860_softc *sc) 4083 { 4084 uint32_t tmp; 4085 int qid; 4086 4087 if (sc->sc_flags & RT2860_RUNNING) 4088 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4089 4090 callout_stop(&sc->watchdog_ch); 4091 sc->sc_tx_timer = 0; 4092 sc->sc_flags &= ~RT2860_RUNNING; 4093 4094 /* disable interrupts */ 4095 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4096 4097 /* disable GP timer */ 4098 rt2860_set_gp_timer(sc, 0); 4099 4100 /* disable Rx */ 4101 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4102 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4103 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4104 4105 /* reset adapter */ 4106 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4107 RAL_BARRIER_WRITE(sc); 4108 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4109 4110 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4111 sc->qfullmsk = 0; 4112 for (qid = 0; qid < 6; qid++) 4113 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4114 rt2860_reset_rx_ring(sc, &sc->rxq); 4115 } 4116 4117 int 4118 rt2860_load_microcode(struct rt2860_softc *sc) 4119 { 4120 const struct firmware *fp; 4121 int ntries, error; 4122 4123 RAL_LOCK_ASSERT(sc); 4124 4125 RAL_UNLOCK(sc); 4126 fp = firmware_get("rt2860fw"); 4127 RAL_LOCK(sc); 4128 if (fp == NULL) { 4129 device_printf(sc->sc_dev, 4130 "unable to receive rt2860fw firmware image\n"); 4131 return EINVAL; 4132 } 4133 4134 /* set "host program ram write selection" bit */ 4135 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4136 /* write microcode image */ 4137 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4138 /* kick microcontroller unit */ 4139 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4140 RAL_BARRIER_WRITE(sc); 4141 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4142 4143 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4144 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4145 4146 /* wait until microcontroller is ready */ 4147 RAL_BARRIER_READ_WRITE(sc); 4148 for (ntries = 0; ntries < 1000; ntries++) { 4149 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4150 break; 4151 DELAY(1000); 4152 } 4153 if (ntries == 1000) { 4154 device_printf(sc->sc_dev, 4155 "timeout waiting for MCU to initialize\n"); 4156 error = ETIMEDOUT; 4157 } else 4158 error = 0; 4159 4160 firmware_put(fp, FIRMWARE_UNLOAD); 4161 return error; 4162 } 4163 4164 /* 4165 * This function is called periodically to adjust Tx power based on 4166 * temperature variation. 4167 */ 4168 #ifdef NOT_YET 4169 static void 4170 rt2860_calib(struct rt2860_softc *sc) 4171 { 4172 struct ieee80211com *ic = &sc->sc_ic; 4173 const uint8_t *tssi; 4174 uint8_t step, bbp49; 4175 int8_t ridx, d; 4176 4177 /* read current temperature */ 4178 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4179 4180 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4181 tssi = &sc->tssi_2ghz[4]; 4182 step = sc->step_2ghz; 4183 } else { 4184 tssi = &sc->tssi_5ghz[4]; 4185 step = sc->step_5ghz; 4186 } 4187 4188 if (bbp49 < tssi[0]) { /* lower than reference */ 4189 /* use higher Tx power than default */ 4190 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4191 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4192 /* use lower Tx power than default */ 4193 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4194 } else { 4195 /* use default Tx power */ 4196 d = 0; 4197 } 4198 d *= step; 4199 4200 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4201 4202 /* write adjusted Tx power values for each Tx rate */ 4203 for (ridx = 0; ridx < 5; ridx++) { 4204 if (sc->txpow20mhz[ridx] == 0xffffffff) 4205 continue; 4206 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4207 b4inc(sc->txpow20mhz[ridx], d)); 4208 } 4209 } 4210 #endif 4211 4212 static void 4213 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4214 { 4215 uint32_t tmp; 4216 4217 if (aux) { 4218 if (sc->mac_ver == 0x5390) { 4219 rt2860_mcu_bbp_write(sc, 152, 4220 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4221 } else { 4222 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4223 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4224 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4225 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4226 } 4227 } else { 4228 if (sc->mac_ver == 0x5390) { 4229 rt2860_mcu_bbp_write(sc, 152, 4230 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4231 } else { 4232 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4233 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4234 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4235 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4236 } 4237 } 4238 } 4239 4240 static void 4241 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4242 { 4243 struct ieee80211com *ic = &sc->sc_ic; 4244 u_int chan, group; 4245 4246 chan = ieee80211_chan2ieee(ic, c); 4247 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4248 return; 4249 4250 if (sc->mac_ver >= 0x5390) 4251 rt5390_set_chan(sc, chan); 4252 else if (sc->mac_ver >= 0x3071) 4253 rt3090_set_chan(sc, chan); 4254 else 4255 rt2860_set_chan(sc, chan); 4256 4257 /* determine channel group */ 4258 if (chan <= 14) 4259 group = 0; 4260 else if (chan <= 64) 4261 group = 1; 4262 else if (chan <= 128) 4263 group = 2; 4264 else 4265 group = 3; 4266 4267 /* XXX necessary only when group has changed! */ 4268 if (sc->mac_ver < 0x5390) 4269 rt2860_select_chan_group(sc, group); 4270 4271 DELAY(1000); 4272 } 4273 4274 static int 4275 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4276 { 4277 struct ieee80211com *ic = vap->iv_ic; 4278 struct rt2860_txwi txwi; 4279 struct mbuf *m; 4280 int ridx; 4281 4282 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4283 return ENOBUFS; 4284 4285 memset(&txwi, 0, sizeof txwi); 4286 txwi.wcid = 0xff; 4287 txwi.len = htole16(m->m_pkthdr.len); 4288 /* send beacons at the lowest available rate */ 4289 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4290 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4291 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4292 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4293 txwi.phy |= htole16(RT2860_PHY_OFDM); 4294 txwi.txop = RT2860_TX_TXOP_HT; 4295 txwi.flags = RT2860_TX_TS; 4296 txwi.xflags = RT2860_TX_NSEQ; 4297 4298 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4299 (uint8_t *)&txwi, sizeof txwi); 4300 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4301 mtod(m, uint8_t *), m->m_pkthdr.len); 4302 4303 m_freem(m); 4304 4305 return 0; 4306 } 4307 4308 static void 4309 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4310 { 4311 struct ieee80211com *ic = &sc->sc_ic; 4312 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4313 uint32_t tmp; 4314 4315 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4316 4317 tmp &= ~0x1fffff; 4318 tmp |= vap->iv_bss->ni_intval * 16; 4319 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4320 if (vap->iv_opmode == IEEE80211_M_STA) { 4321 /* 4322 * Local TSF is always updated with remote TSF on beacon 4323 * reception. 4324 */ 4325 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4326 } 4327 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4328 vap->iv_opmode == IEEE80211_M_MBSS) { 4329 tmp |= RT2860_BCN_TX_EN; 4330 /* 4331 * Local TSF is updated with remote TSF on beacon reception 4332 * only if the remote TSF is greater than local TSF. 4333 */ 4334 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4335 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4336 tmp |= RT2860_BCN_TX_EN; 4337 /* SYNC with nobody */ 4338 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4339 } 4340 4341 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4342 } 4343