1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_radiotap.h> 58 #include <net80211/ieee80211_regdomain.h> 59 #include <net80211/ieee80211_ratectl.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_ether.h> 66 67 #include <dev/ral/rt2860reg.h> 68 #include <dev/ral/rt2860var.h> 69 70 #define RAL_DEBUG 71 #ifdef RAL_DEBUG 72 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 73 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n, x) 77 #endif 78 79 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 80 const char [IFNAMSIZ], int, enum ieee80211_opmode, 81 int, const uint8_t [IEEE80211_ADDR_LEN], 82 const uint8_t [IEEE80211_ADDR_LEN]); 83 static void rt2860_vap_delete(struct ieee80211vap *); 84 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 85 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_reset_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static void rt2860_free_tx_ring(struct rt2860_softc *, 90 struct rt2860_tx_ring *); 91 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 92 static void rt2860_free_tx_pool(struct rt2860_softc *); 93 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_reset_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_free_rx_ring(struct rt2860_softc *, 98 struct rt2860_rx_ring *); 99 static void rt2860_updatestats(struct rt2860_softc *); 100 static void rt2860_newassoc(struct ieee80211_node *, int); 101 static void rt2860_node_free(struct ieee80211_node *); 102 #ifdef IEEE80211_HT 103 static int rt2860_ampdu_rx_start(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 106 struct ieee80211_node *, uint8_t); 107 #endif 108 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 109 int); 110 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 111 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 112 static void rt2860_intr_coherent(struct rt2860_softc *); 113 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 114 static void rt2860_tx_intr(struct rt2860_softc *, int); 115 static void rt2860_rx_intr(struct rt2860_softc *); 116 static void rt2860_tbtt_intr(struct rt2860_softc *); 117 static void rt2860_gp_intr(struct rt2860_softc *); 118 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 119 struct ieee80211_node *); 120 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 121 const struct ieee80211_bpf_params *); 122 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 123 struct ieee80211_node *, 124 const struct ieee80211_bpf_params *params); 125 static void rt2860_start(struct ifnet *); 126 static void rt2860_start_locked(struct ifnet *); 127 static void rt2860_watchdog(void *); 128 static int rt2860_ioctl(struct ifnet *, u_long, caddr_t); 129 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 130 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 131 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 132 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 133 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 134 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 135 static void rt2860_enable_mrr(struct rt2860_softc *); 136 static void rt2860_set_txpreamble(struct rt2860_softc *); 137 static void rt2860_set_basicrates(struct rt2860_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2860_scan_start(struct ieee80211com *); 140 static void rt2860_scan_end(struct ieee80211com *); 141 static void rt2860_set_channel(struct ieee80211com *); 142 static void rt2860_select_chan_group(struct rt2860_softc *, int); 143 static void rt2860_set_chan(struct rt2860_softc *, u_int); 144 static void rt3090_set_chan(struct rt2860_softc *, u_int); 145 static void rt5390_set_chan(struct rt2860_softc *, u_int); 146 static int rt3090_rf_init(struct rt2860_softc *); 147 static void rt5390_rf_init(struct rt2860_softc *); 148 static void rt3090_rf_wakeup(struct rt2860_softc *); 149 static void rt5390_rf_wakeup(struct rt2860_softc *); 150 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 151 uint8_t *); 152 static void rt3090_rf_setup(struct rt2860_softc *); 153 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 154 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 155 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 156 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 157 static void rt2860_update_promisc(struct ieee80211com *); 158 static void rt2860_updateslot(struct ieee80211com *); 159 static void rt2860_updateprot(struct ifnet *); 160 static int rt2860_updateedca(struct ieee80211com *); 161 #ifdef HW_CRYPTO 162 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 163 struct ieee80211_key *); 164 static void rt2860_delete_key(struct ieee80211com *, 165 struct ieee80211_node *, struct ieee80211_key *); 166 #endif 167 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 168 static const char *rt2860_get_rf(uint8_t); 169 static int rt2860_read_eeprom(struct rt2860_softc *, 170 uint8_t macaddr[IEEE80211_ADDR_LEN]); 171 static int rt2860_bbp_init(struct rt2860_softc *); 172 static void rt5390_bbp_init(struct rt2860_softc *); 173 static int rt2860_txrx_enable(struct rt2860_softc *); 174 static void rt2860_init(void *); 175 static void rt2860_init_locked(struct rt2860_softc *); 176 static void rt2860_stop(void *); 177 static void rt2860_stop_locked(struct rt2860_softc *); 178 static int rt2860_load_microcode(struct rt2860_softc *); 179 #ifdef NOT_YET 180 static void rt2860_calib(struct rt2860_softc *); 181 #endif 182 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 183 static void rt2860_switch_chan(struct rt2860_softc *, 184 struct ieee80211_channel *); 185 static int rt2860_setup_beacon(struct rt2860_softc *, 186 struct ieee80211vap *); 187 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 188 189 static const struct { 190 uint32_t reg; 191 uint32_t val; 192 } rt2860_def_mac[] = { 193 RT2860_DEF_MAC 194 }; 195 196 static const struct { 197 uint8_t reg; 198 uint8_t val; 199 } rt2860_def_bbp[] = { 200 RT2860_DEF_BBP 201 }, rt5390_def_bbp[] = { 202 RT5390_DEF_BBP 203 }; 204 205 static const struct rfprog { 206 uint8_t chan; 207 uint32_t r1, r2, r3, r4; 208 } rt2860_rf2850[] = { 209 RT2860_RF2850 210 }; 211 212 struct { 213 uint8_t n, r, k; 214 } rt3090_freqs[] = { 215 RT3070_RF3052 216 }; 217 218 static const struct { 219 uint8_t reg; 220 uint8_t val; 221 } rt3090_def_rf[] = { 222 RT3070_DEF_RF 223 }, rt5390_def_rf[] = { 224 RT5390_DEF_RF 225 }, rt5392_def_rf[] = { 226 RT5392_DEF_RF 227 }; 228 229 int 230 rt2860_attach(device_t dev, int id) 231 { 232 struct rt2860_softc *sc = device_get_softc(dev); 233 struct ieee80211com *ic; 234 struct ifnet *ifp; 235 uint32_t tmp; 236 int error, ntries, qid; 237 uint8_t bands; 238 uint8_t macaddr[IEEE80211_ADDR_LEN]; 239 240 sc->sc_dev = dev; 241 sc->sc_debug = 0; 242 243 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 244 if (ifp == NULL) { 245 device_printf(sc->sc_dev, "can not if_alloc()\n"); 246 return ENOMEM; 247 } 248 ic = ifp->if_l2com; 249 250 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 251 MTX_DEF | MTX_RECURSE); 252 253 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 254 255 /* wait for NIC to initialize */ 256 for (ntries = 0; ntries < 100; ntries++) { 257 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 258 if (tmp != 0 && tmp != 0xffffffff) 259 break; 260 DELAY(10); 261 } 262 if (ntries == 100) { 263 device_printf(sc->sc_dev, 264 "timeout waiting for NIC to initialize\n"); 265 error = EIO; 266 goto fail1; 267 } 268 sc->mac_ver = tmp >> 16; 269 sc->mac_rev = tmp & 0xffff; 270 271 if (sc->mac_ver != 0x2860 && 272 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 273 sc->sc_flags |= RT2860_ADVANCED_PS; 274 275 /* retrieve RF rev. no and various other things from EEPROM */ 276 rt2860_read_eeprom(sc, macaddr); 277 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 278 "RF %s (MIMO %dT%dR), address %6D\n", 279 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 280 sc->ntxchains, sc->nrxchains, macaddr, ":"); 281 282 /* 283 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 284 */ 285 for (qid = 0; qid < 6; qid++) { 286 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 287 device_printf(sc->sc_dev, 288 "could not allocate Tx ring %d\n", qid); 289 goto fail2; 290 } 291 } 292 293 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 294 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 295 goto fail2; 296 } 297 298 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 299 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 300 goto fail3; 301 } 302 303 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 304 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 305 WME_AC_VO : 5; 306 307 ifp->if_softc = sc; 308 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 309 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 310 ifp->if_init = rt2860_init; 311 ifp->if_ioctl = rt2860_ioctl; 312 ifp->if_start = rt2860_start; 313 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 314 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 315 IFQ_SET_READY(&ifp->if_snd); 316 317 ic->ic_ifp = ifp; 318 ic->ic_softc = sc; 319 ic->ic_name = device_get_nameunit(dev); 320 ic->ic_opmode = IEEE80211_M_STA; 321 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 322 323 /* set device capabilities */ 324 ic->ic_caps = 325 IEEE80211_C_STA /* station mode */ 326 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 327 | IEEE80211_C_HOSTAP /* hostap mode */ 328 | IEEE80211_C_MONITOR /* monitor mode */ 329 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 330 | IEEE80211_C_WDS /* 4-address traffic works */ 331 | IEEE80211_C_MBSS /* mesh point link mode */ 332 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 333 | IEEE80211_C_SHSLOT /* short slot time supported */ 334 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 335 #if 0 336 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 337 #endif 338 | IEEE80211_C_WME /* 802.11e */ 339 ; 340 341 bands = 0; 342 setbit(&bands, IEEE80211_MODE_11B); 343 setbit(&bands, IEEE80211_MODE_11G); 344 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) 345 setbit(&bands, IEEE80211_MODE_11A); 346 ieee80211_init_channels(ic, NULL, &bands); 347 348 ieee80211_ifattach(ic, macaddr); 349 350 ic->ic_wme.wme_update = rt2860_updateedca; 351 ic->ic_scan_start = rt2860_scan_start; 352 ic->ic_scan_end = rt2860_scan_end; 353 ic->ic_set_channel = rt2860_set_channel; 354 ic->ic_updateslot = rt2860_updateslot; 355 ic->ic_update_promisc = rt2860_update_promisc; 356 ic->ic_raw_xmit = rt2860_raw_xmit; 357 sc->sc_node_free = ic->ic_node_free; 358 ic->ic_node_free = rt2860_node_free; 359 ic->ic_newassoc = rt2860_newassoc; 360 361 ic->ic_vap_create = rt2860_vap_create; 362 ic->ic_vap_delete = rt2860_vap_delete; 363 364 ieee80211_radiotap_attach(ic, 365 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 366 RT2860_TX_RADIOTAP_PRESENT, 367 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 368 RT2860_RX_RADIOTAP_PRESENT); 369 370 #ifdef RAL_DEBUG 371 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 372 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 373 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 374 #endif 375 if (bootverbose) 376 ieee80211_announce(ic); 377 378 return 0; 379 380 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 381 fail2: while (--qid >= 0) 382 rt2860_free_tx_ring(sc, &sc->txq[qid]); 383 fail1: mtx_destroy(&sc->sc_mtx); 384 if_free(ifp); 385 return error; 386 } 387 388 int 389 rt2860_detach(void *xsc) 390 { 391 struct rt2860_softc *sc = xsc; 392 struct ifnet *ifp = sc->sc_ifp; 393 struct ieee80211com *ic = ifp->if_l2com; 394 int qid; 395 396 RAL_LOCK(sc); 397 rt2860_stop_locked(sc); 398 RAL_UNLOCK(sc); 399 400 ieee80211_ifdetach(ic); 401 402 for (qid = 0; qid < 6; qid++) 403 rt2860_free_tx_ring(sc, &sc->txq[qid]); 404 rt2860_free_rx_ring(sc, &sc->rxq); 405 rt2860_free_tx_pool(sc); 406 407 if_free(ifp); 408 409 mtx_destroy(&sc->sc_mtx); 410 411 return 0; 412 } 413 414 void 415 rt2860_shutdown(void *xsc) 416 { 417 struct rt2860_softc *sc = xsc; 418 419 rt2860_stop(sc); 420 } 421 422 void 423 rt2860_suspend(void *xsc) 424 { 425 struct rt2860_softc *sc = xsc; 426 427 rt2860_stop(sc); 428 } 429 430 void 431 rt2860_resume(void *xsc) 432 { 433 struct rt2860_softc *sc = xsc; 434 struct ifnet *ifp = sc->sc_ifp; 435 436 if (ifp->if_flags & IFF_UP) 437 rt2860_init(sc); 438 } 439 440 static struct ieee80211vap * 441 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 442 enum ieee80211_opmode opmode, int flags, 443 const uint8_t bssid[IEEE80211_ADDR_LEN], 444 const uint8_t mac[IEEE80211_ADDR_LEN]) 445 { 446 struct ifnet *ifp = ic->ic_ifp; 447 struct rt2860_vap *rvp; 448 struct ieee80211vap *vap; 449 450 switch (opmode) { 451 case IEEE80211_M_STA: 452 case IEEE80211_M_IBSS: 453 case IEEE80211_M_AHDEMO: 454 case IEEE80211_M_MONITOR: 455 case IEEE80211_M_HOSTAP: 456 case IEEE80211_M_MBSS: 457 /* XXXRP: TBD */ 458 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 459 if_printf(ifp, "only 1 vap supported\n"); 460 return NULL; 461 } 462 if (opmode == IEEE80211_M_STA) 463 flags |= IEEE80211_CLONE_NOBEACONS; 464 break; 465 case IEEE80211_M_WDS: 466 if (TAILQ_EMPTY(&ic->ic_vaps) || 467 ic->ic_opmode != IEEE80211_M_HOSTAP) { 468 if_printf(ifp, "wds only supported in ap mode\n"); 469 return NULL; 470 } 471 /* 472 * Silently remove any request for a unique 473 * bssid; WDS vap's always share the local 474 * mac address. 475 */ 476 flags &= ~IEEE80211_CLONE_BSSID; 477 break; 478 default: 479 if_printf(ifp, "unknown opmode %d\n", opmode); 480 return NULL; 481 } 482 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_NOWAIT | M_ZERO); 483 if (rvp == NULL) 484 return NULL; 485 vap = &rvp->ral_vap; 486 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 487 488 /* override state transition machine */ 489 rvp->ral_newstate = vap->iv_newstate; 490 vap->iv_newstate = rt2860_newstate; 491 #if 0 492 vap->iv_update_beacon = rt2860_beacon_update; 493 #endif 494 495 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 496 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 497 498 ieee80211_ratectl_init(vap); 499 /* complete setup */ 500 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 501 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 502 ic->ic_opmode = opmode; 503 return vap; 504 } 505 506 static void 507 rt2860_vap_delete(struct ieee80211vap *vap) 508 { 509 struct rt2860_vap *rvp = RT2860_VAP(vap); 510 511 ieee80211_ratectl_deinit(vap); 512 ieee80211_vap_detach(vap); 513 free(rvp, M_80211_VAP); 514 } 515 516 static void 517 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 518 { 519 if (error != 0) 520 return; 521 522 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 523 524 *(bus_addr_t *)arg = segs[0].ds_addr; 525 } 526 527 528 static int 529 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 530 { 531 int size, error; 532 533 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 534 535 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 536 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 537 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 538 if (error != 0) { 539 device_printf(sc->sc_dev, "could not create desc DMA map\n"); 540 goto fail; 541 } 542 543 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 544 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 545 if (error != 0) { 546 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 547 goto fail; 548 } 549 550 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 551 size, rt2860_dma_map_addr, &ring->paddr, 0); 552 if (error != 0) { 553 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 554 goto fail; 555 } 556 557 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 558 559 return 0; 560 561 fail: rt2860_free_tx_ring(sc, ring); 562 return error; 563 } 564 565 void 566 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 567 { 568 struct rt2860_tx_data *data; 569 int i; 570 571 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 572 if ((data = ring->data[i]) == NULL) 573 continue; /* nothing mapped in this slot */ 574 575 if (data->m != NULL) { 576 bus_dmamap_sync(sc->txwi_dmat, data->map, 577 BUS_DMASYNC_POSTWRITE); 578 bus_dmamap_unload(sc->txwi_dmat, data->map); 579 m_freem(data->m); 580 data->m = NULL; 581 } 582 if (data->ni != NULL) { 583 ieee80211_free_node(data->ni); 584 data->ni = NULL; 585 } 586 587 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 588 ring->data[i] = NULL; 589 } 590 591 ring->queued = 0; 592 ring->cur = ring->next = 0; 593 } 594 595 void 596 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 597 { 598 struct rt2860_tx_data *data; 599 int i; 600 601 if (ring->txd != NULL) { 602 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 603 BUS_DMASYNC_POSTWRITE); 604 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 605 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 606 } 607 if (ring->desc_dmat != NULL) 608 bus_dma_tag_destroy(ring->desc_dmat); 609 610 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 611 if ((data = ring->data[i]) == NULL) 612 continue; /* nothing mapped in this slot */ 613 614 if (data->m != NULL) { 615 bus_dmamap_sync(sc->txwi_dmat, data->map, 616 BUS_DMASYNC_POSTWRITE); 617 bus_dmamap_unload(sc->txwi_dmat, data->map); 618 m_freem(data->m); 619 } 620 if (data->ni != NULL) 621 ieee80211_free_node(data->ni); 622 623 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 624 } 625 } 626 627 /* 628 * Allocate a pool of TX Wireless Information blocks. 629 */ 630 int 631 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 632 { 633 caddr_t vaddr; 634 bus_addr_t paddr; 635 int i, size, error; 636 637 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 638 639 /* init data_pool early in case of failure.. */ 640 SLIST_INIT(&sc->data_pool); 641 642 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 643 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 644 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 645 if (error != 0) { 646 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 647 goto fail; 648 } 649 650 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 651 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 652 if (error != 0) { 653 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 654 goto fail; 655 } 656 657 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 658 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 659 if (error != 0) { 660 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 661 goto fail; 662 } 663 664 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 665 666 vaddr = sc->txwi_vaddr; 667 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 668 struct rt2860_tx_data *data = &sc->data[i]; 669 670 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 671 if (error != 0) { 672 device_printf(sc->sc_dev, "could not create DMA map\n"); 673 goto fail; 674 } 675 data->txwi = (struct rt2860_txwi *)vaddr; 676 data->paddr = paddr; 677 vaddr += RT2860_TXWI_DMASZ; 678 paddr += RT2860_TXWI_DMASZ; 679 680 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 681 } 682 683 return 0; 684 685 fail: rt2860_free_tx_pool(sc); 686 return error; 687 } 688 689 void 690 rt2860_free_tx_pool(struct rt2860_softc *sc) 691 { 692 if (sc->txwi_vaddr != NULL) { 693 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 694 BUS_DMASYNC_POSTWRITE); 695 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 696 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 697 } 698 if (sc->txwi_dmat != NULL) 699 bus_dma_tag_destroy(sc->txwi_dmat); 700 701 while (!SLIST_EMPTY(&sc->data_pool)) { 702 struct rt2860_tx_data *data; 703 data = SLIST_FIRST(&sc->data_pool); 704 bus_dmamap_destroy(sc->txwi_dmat, data->map); 705 SLIST_REMOVE_HEAD(&sc->data_pool, next); 706 } 707 } 708 709 int 710 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 711 { 712 bus_addr_t physaddr; 713 int i, size, error; 714 715 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 716 717 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 718 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 719 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 720 if (error != 0) { 721 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 722 goto fail; 723 } 724 725 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 726 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 727 if (error != 0) { 728 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 729 goto fail; 730 } 731 732 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 733 size, rt2860_dma_map_addr, &ring->paddr, 0); 734 if (error != 0) { 735 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 736 goto fail; 737 } 738 739 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 740 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 741 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 742 if (error != 0) { 743 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 744 goto fail; 745 } 746 747 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 748 struct rt2860_rx_data *data = &ring->data[i]; 749 struct rt2860_rxd *rxd = &ring->rxd[i]; 750 751 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 752 if (error != 0) { 753 device_printf(sc->sc_dev, "could not create DMA map\n"); 754 goto fail; 755 } 756 757 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 758 if (data->m == NULL) { 759 device_printf(sc->sc_dev, 760 "could not allocate rx mbuf\n"); 761 error = ENOMEM; 762 goto fail; 763 } 764 765 error = bus_dmamap_load(ring->data_dmat, data->map, 766 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 767 &physaddr, 0); 768 if (error != 0) { 769 device_printf(sc->sc_dev, 770 "could not load rx buf DMA map"); 771 goto fail; 772 } 773 774 rxd->sdp0 = htole32(physaddr); 775 rxd->sdl0 = htole16(MCLBYTES); 776 } 777 778 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 779 780 return 0; 781 782 fail: rt2860_free_rx_ring(sc, ring); 783 return error; 784 } 785 786 void 787 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 788 { 789 int i; 790 791 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 792 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 793 794 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 795 796 ring->cur = 0; 797 } 798 799 void 800 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 801 { 802 int i; 803 804 if (ring->rxd != NULL) { 805 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 806 BUS_DMASYNC_POSTWRITE); 807 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 808 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 809 } 810 if (ring->desc_dmat != NULL) 811 bus_dma_tag_destroy(ring->desc_dmat); 812 813 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 814 struct rt2860_rx_data *data = &ring->data[i]; 815 816 if (data->m != NULL) { 817 bus_dmamap_sync(ring->data_dmat, data->map, 818 BUS_DMASYNC_POSTREAD); 819 bus_dmamap_unload(ring->data_dmat, data->map); 820 m_freem(data->m); 821 } 822 if (data->map != NULL) 823 bus_dmamap_destroy(ring->data_dmat, data->map); 824 } 825 if (ring->data_dmat != NULL) 826 bus_dma_tag_destroy(ring->data_dmat); 827 } 828 829 static void 830 rt2860_updatestats(struct rt2860_softc *sc) 831 { 832 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 833 834 /* 835 * In IBSS or HostAP modes (when the hardware sends beacons), the 836 * MAC can run into a livelock and start sending CTS-to-self frames 837 * like crazy if protection is enabled. Fortunately, we can detect 838 * when such a situation occurs and reset the MAC. 839 */ 840 if (ic->ic_curmode != IEEE80211_M_STA) { 841 /* check if we're in a livelock situation.. */ 842 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 843 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 844 /* ..and reset MAC/BBP for a while.. */ 845 DPRINTF(("CTS-to-self livelock detected\n")); 846 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 847 RAL_BARRIER_WRITE(sc); 848 DELAY(1); 849 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 850 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 851 } 852 } 853 } 854 855 static void 856 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 857 { 858 struct ieee80211com *ic = ni->ni_ic; 859 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 860 uint8_t wcid; 861 862 wcid = IEEE80211_AID(ni->ni_associd); 863 if (isnew && ni->ni_associd != 0) { 864 sc->wcid2ni[wcid] = ni; 865 866 /* init WCID table entry */ 867 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 868 ni->ni_macaddr, IEEE80211_ADDR_LEN); 869 } 870 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 871 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 872 } 873 874 static void 875 rt2860_node_free(struct ieee80211_node *ni) 876 { 877 struct ieee80211com *ic = ni->ni_ic; 878 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 879 uint8_t wcid; 880 881 if (ni->ni_associd != 0) { 882 wcid = IEEE80211_AID(ni->ni_associd); 883 884 /* clear Rx WCID search table entry */ 885 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 886 } 887 sc->sc_node_free(ni); 888 } 889 890 #ifdef IEEE80211_HT 891 static int 892 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 893 uint8_t tid) 894 { 895 struct rt2860_softc *sc = ic->ic_softc; 896 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 897 uint32_t tmp; 898 899 /* update BA session mask */ 900 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 901 tmp |= (1 << tid) << 16; 902 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 903 return 0; 904 } 905 906 static void 907 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 908 uint8_t tid) 909 { 910 struct rt2860_softc *sc = ic->ic_softc; 911 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 912 uint32_t tmp; 913 914 /* update BA session mask */ 915 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 916 tmp &= ~((1 << tid) << 16); 917 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 918 } 919 #endif 920 921 int 922 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 923 { 924 struct rt2860_vap *rvp = RT2860_VAP(vap); 925 struct ieee80211com *ic = vap->iv_ic; 926 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 927 uint32_t tmp; 928 int error; 929 930 if (vap->iv_state == IEEE80211_S_RUN) { 931 /* turn link LED off */ 932 rt2860_set_leds(sc, RT2860_LED_RADIO); 933 } 934 935 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 936 /* abort TSF synchronization */ 937 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 938 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 939 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 940 RT2860_TBTT_TIMER_EN)); 941 } 942 943 rt2860_set_gp_timer(sc, 0); 944 945 error = rvp->ral_newstate(vap, nstate, arg); 946 if (error != 0) 947 return (error); 948 949 if (nstate == IEEE80211_S_RUN) { 950 struct ieee80211_node *ni = vap->iv_bss; 951 952 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 953 rt2860_enable_mrr(sc); 954 rt2860_set_txpreamble(sc); 955 rt2860_set_basicrates(sc, &ni->ni_rates); 956 rt2860_set_bssid(sc, ni->ni_bssid); 957 } 958 959 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 960 vap->iv_opmode == IEEE80211_M_IBSS || 961 vap->iv_opmode == IEEE80211_M_MBSS) { 962 error = rt2860_setup_beacon(sc, vap); 963 if (error != 0) 964 return error; 965 } 966 967 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 968 rt2860_enable_tsf_sync(sc); 969 rt2860_set_gp_timer(sc, 500); 970 } 971 972 /* turn link LED on */ 973 rt2860_set_leds(sc, RT2860_LED_RADIO | 974 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 975 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 976 } 977 return error; 978 } 979 980 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 981 static uint16_t 982 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 983 { 984 uint32_t tmp; 985 uint16_t reg; 986 int ntries; 987 988 addr *= 2; 989 /*- 990 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 991 * DATA0: F E D C 992 * DATA1: B A 9 8 993 * DATA2: 7 6 5 4 994 * DATA3: 3 2 1 0 995 */ 996 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 997 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 998 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 999 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 1000 for (ntries = 0; ntries < 500; ntries++) { 1001 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 1002 if (!(tmp & RT3070_EFSROM_KICK)) 1003 break; 1004 DELAY(2); 1005 } 1006 if (ntries == 500) 1007 return 0xffff; 1008 1009 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 1010 return 0xffff; /* address not found */ 1011 1012 /* determine to which 32-bit register our 16-bit word belongs */ 1013 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 1014 tmp = RAL_READ(sc, reg); 1015 1016 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 1017 } 1018 1019 /* 1020 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1021 * 93C66 or 93C86). 1022 */ 1023 static uint16_t 1024 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1025 { 1026 uint32_t tmp; 1027 uint16_t val; 1028 int n; 1029 1030 /* clock C once before the first command */ 1031 RT2860_EEPROM_CTL(sc, 0); 1032 1033 RT2860_EEPROM_CTL(sc, RT2860_S); 1034 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1035 RT2860_EEPROM_CTL(sc, RT2860_S); 1036 1037 /* write start bit (1) */ 1038 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1039 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1040 1041 /* write READ opcode (10) */ 1042 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1043 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1044 RT2860_EEPROM_CTL(sc, RT2860_S); 1045 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1046 1047 /* write address (A5-A0 or A7-A0) */ 1048 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1049 for (; n >= 0; n--) { 1050 RT2860_EEPROM_CTL(sc, RT2860_S | 1051 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1052 RT2860_EEPROM_CTL(sc, RT2860_S | 1053 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1054 } 1055 1056 RT2860_EEPROM_CTL(sc, RT2860_S); 1057 1058 /* read data Q15-Q0 */ 1059 val = 0; 1060 for (n = 15; n >= 0; n--) { 1061 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1062 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1063 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1064 RT2860_EEPROM_CTL(sc, RT2860_S); 1065 } 1066 1067 RT2860_EEPROM_CTL(sc, 0); 1068 1069 /* clear Chip Select and clock C */ 1070 RT2860_EEPROM_CTL(sc, RT2860_S); 1071 RT2860_EEPROM_CTL(sc, 0); 1072 RT2860_EEPROM_CTL(sc, RT2860_C); 1073 1074 return val; 1075 } 1076 1077 static __inline uint16_t 1078 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1079 { 1080 /* either eFUSE ROM or EEPROM */ 1081 return sc->sc_srom_read(sc, addr); 1082 } 1083 1084 static void 1085 rt2860_intr_coherent(struct rt2860_softc *sc) 1086 { 1087 uint32_t tmp; 1088 1089 /* DMA finds data coherent event when checking the DDONE bit */ 1090 1091 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1092 1093 /* restart DMA engine */ 1094 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1095 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1096 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1097 1098 (void)rt2860_txrx_enable(sc); 1099 } 1100 1101 static void 1102 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1103 { 1104 struct ifnet *ifp = sc->sc_ifp; 1105 struct ieee80211_node *ni; 1106 uint32_t stat; 1107 int retrycnt; 1108 uint8_t wcid, mcs, pid; 1109 1110 /* drain Tx status FIFO (maxsize = 16) */ 1111 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1112 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1113 1114 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1115 ni = sc->wcid2ni[wcid]; 1116 1117 /* if no ACK was requested, no feedback is available */ 1118 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL) 1119 continue; 1120 1121 /* update per-STA AMRR stats */ 1122 if (stat & RT2860_TXQ_OK) { 1123 /* 1124 * Check if there were retries, ie if the Tx success 1125 * rate is different from the requested rate. Note 1126 * that it works only because we do not allow rate 1127 * fallback from OFDM to CCK. 1128 */ 1129 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1130 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1131 if (mcs + 1 != pid) 1132 retrycnt = 1; 1133 else 1134 retrycnt = 0; 1135 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1136 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL); 1137 } else { 1138 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1139 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL); 1140 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1141 } 1142 } 1143 } 1144 1145 static void 1146 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1147 { 1148 struct ifnet *ifp = sc->sc_ifp; 1149 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1150 uint32_t hw; 1151 1152 rt2860_drain_stats_fifo(sc); 1153 1154 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1155 while (ring->next != hw) { 1156 struct rt2860_tx_data *data = ring->data[ring->next]; 1157 1158 if (data != NULL) { 1159 bus_dmamap_sync(sc->txwi_dmat, data->map, 1160 BUS_DMASYNC_POSTWRITE); 1161 bus_dmamap_unload(sc->txwi_dmat, data->map); 1162 if (data->m->m_flags & M_TXCB) { 1163 ieee80211_process_callback(data->ni, data->m, 1164 0); 1165 } 1166 m_freem(data->m); 1167 ieee80211_free_node(data->ni); 1168 data->m = NULL; 1169 data->ni = NULL; 1170 1171 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1172 ring->data[ring->next] = NULL; 1173 1174 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1175 } 1176 ring->queued--; 1177 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1178 } 1179 1180 sc->sc_tx_timer = 0; 1181 if (ring->queued < RT2860_TX_RING_COUNT) 1182 sc->qfullmsk &= ~(1 << qid); 1183 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1184 rt2860_start_locked(ifp); 1185 } 1186 1187 /* 1188 * Return the Rx chain with the highest RSSI for a given frame. 1189 */ 1190 static __inline uint8_t 1191 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1192 { 1193 uint8_t rxchain = 0; 1194 1195 if (sc->nrxchains > 1) { 1196 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1197 rxchain = 1; 1198 if (sc->nrxchains > 2) 1199 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1200 rxchain = 2; 1201 } 1202 return rxchain; 1203 } 1204 1205 static void 1206 rt2860_rx_intr(struct rt2860_softc *sc) 1207 { 1208 struct rt2860_rx_radiotap_header *tap; 1209 struct ifnet *ifp = sc->sc_ifp; 1210 struct ieee80211com *ic = ifp->if_l2com; 1211 struct ieee80211_frame *wh; 1212 struct ieee80211_node *ni; 1213 struct mbuf *m, *m1; 1214 bus_addr_t physaddr; 1215 uint32_t hw; 1216 uint16_t phy; 1217 uint8_t ant; 1218 int8_t rssi, nf; 1219 int error; 1220 1221 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1222 while (sc->rxq.cur != hw) { 1223 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1224 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1225 struct rt2860_rxwi *rxwi; 1226 1227 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1228 BUS_DMASYNC_POSTREAD); 1229 1230 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1231 DPRINTF(("RXD DDONE bit not set!\n")); 1232 break; /* should not happen */ 1233 } 1234 1235 if (__predict_false(rxd->flags & 1236 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1237 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1238 goto skip; 1239 } 1240 1241 #ifdef HW_CRYPTO 1242 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1243 /* report MIC failures to net80211 for TKIP */ 1244 ic->ic_stats.is_rx_locmicfail++; 1245 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1246 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1247 goto skip; 1248 } 1249 #endif 1250 1251 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1252 if (__predict_false(m1 == NULL)) { 1253 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1254 goto skip; 1255 } 1256 1257 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1258 BUS_DMASYNC_POSTREAD); 1259 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1260 1261 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1262 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1263 &physaddr, 0); 1264 if (__predict_false(error != 0)) { 1265 m_freem(m1); 1266 1267 /* try to reload the old mbuf */ 1268 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1269 mtod(data->m, void *), MCLBYTES, 1270 rt2860_dma_map_addr, &physaddr, 0); 1271 if (__predict_false(error != 0)) { 1272 panic("%s: could not load old rx mbuf", 1273 device_get_name(sc->sc_dev)); 1274 } 1275 /* physical address may have changed */ 1276 rxd->sdp0 = htole32(physaddr); 1277 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1278 goto skip; 1279 } 1280 1281 /* 1282 * New mbuf successfully loaded, update Rx ring and continue 1283 * processing. 1284 */ 1285 m = data->m; 1286 data->m = m1; 1287 rxd->sdp0 = htole32(physaddr); 1288 1289 rxwi = mtod(m, struct rt2860_rxwi *); 1290 1291 /* finalize mbuf */ 1292 m->m_pkthdr.rcvif = ifp; 1293 m->m_data = (caddr_t)(rxwi + 1); 1294 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1295 1296 wh = mtod(m, struct ieee80211_frame *); 1297 #ifdef HW_CRYPTO 1298 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1299 /* frame is decrypted by hardware */ 1300 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1301 } 1302 #endif 1303 1304 /* HW may insert 2 padding bytes after 802.11 header */ 1305 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1306 u_int hdrlen = ieee80211_hdrsize(wh); 1307 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1308 m->m_data += 2; 1309 wh = mtod(m, struct ieee80211_frame *); 1310 } 1311 1312 ant = rt2860_maxrssi_chain(sc, rxwi); 1313 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1314 nf = RT2860_NOISE_FLOOR; 1315 1316 if (ieee80211_radiotap_active(ic)) { 1317 tap = &sc->sc_rxtap; 1318 tap->wr_flags = 0; 1319 tap->wr_antenna = ant; 1320 tap->wr_antsignal = nf + rssi; 1321 tap->wr_antnoise = nf; 1322 /* in case it can't be found below */ 1323 tap->wr_rate = 2; 1324 phy = le16toh(rxwi->phy); 1325 switch (phy & RT2860_PHY_MODE) { 1326 case RT2860_PHY_CCK: 1327 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1328 case 0: tap->wr_rate = 2; break; 1329 case 1: tap->wr_rate = 4; break; 1330 case 2: tap->wr_rate = 11; break; 1331 case 3: tap->wr_rate = 22; break; 1332 } 1333 if (phy & RT2860_PHY_SHPRE) 1334 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1335 break; 1336 case RT2860_PHY_OFDM: 1337 switch (phy & RT2860_PHY_MCS) { 1338 case 0: tap->wr_rate = 12; break; 1339 case 1: tap->wr_rate = 18; break; 1340 case 2: tap->wr_rate = 24; break; 1341 case 3: tap->wr_rate = 36; break; 1342 case 4: tap->wr_rate = 48; break; 1343 case 5: tap->wr_rate = 72; break; 1344 case 6: tap->wr_rate = 96; break; 1345 case 7: tap->wr_rate = 108; break; 1346 } 1347 break; 1348 } 1349 } 1350 1351 RAL_UNLOCK(sc); 1352 wh = mtod(m, struct ieee80211_frame *); 1353 1354 /* send the frame to the 802.11 layer */ 1355 ni = ieee80211_find_rxnode(ic, 1356 (struct ieee80211_frame_min *)wh); 1357 if (ni != NULL) { 1358 (void)ieee80211_input(ni, m, rssi - nf, nf); 1359 ieee80211_free_node(ni); 1360 } else 1361 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1362 1363 RAL_LOCK(sc); 1364 1365 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1366 1367 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1368 BUS_DMASYNC_PREWRITE); 1369 1370 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1371 } 1372 1373 /* tell HW what we have processed */ 1374 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1375 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1376 } 1377 1378 static void 1379 rt2860_tbtt_intr(struct rt2860_softc *sc) 1380 { 1381 #if 0 1382 struct ieee80211com *ic = &sc->sc_ic; 1383 1384 #ifndef IEEE80211_STA_ONLY 1385 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1386 /* one less beacon until next DTIM */ 1387 if (ic->ic_dtim_count == 0) 1388 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1389 else 1390 ic->ic_dtim_count--; 1391 1392 /* update dynamic parts of beacon */ 1393 rt2860_setup_beacon(sc); 1394 1395 /* flush buffered multicast frames */ 1396 if (ic->ic_dtim_count == 0) 1397 ieee80211_notify_dtim(ic); 1398 } 1399 #endif 1400 /* check if protection mode has changed */ 1401 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1402 rt2860_updateprot(ic); 1403 sc->sc_ic_flags = ic->ic_flags; 1404 } 1405 #endif 1406 } 1407 1408 static void 1409 rt2860_gp_intr(struct rt2860_softc *sc) 1410 { 1411 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1412 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1413 1414 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1415 1416 if (vap->iv_state == IEEE80211_S_RUN) 1417 rt2860_updatestats(sc); 1418 } 1419 1420 void 1421 rt2860_intr(void *arg) 1422 { 1423 struct rt2860_softc *sc = arg; 1424 uint32_t r; 1425 1426 RAL_LOCK(sc); 1427 1428 r = RAL_READ(sc, RT2860_INT_STATUS); 1429 if (__predict_false(r == 0xffffffff)) { 1430 RAL_UNLOCK(sc); 1431 return; /* device likely went away */ 1432 } 1433 if (r == 0) { 1434 RAL_UNLOCK(sc); 1435 return; /* not for us */ 1436 } 1437 1438 /* acknowledge interrupts */ 1439 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1440 1441 if (r & RT2860_TX_RX_COHERENT) 1442 rt2860_intr_coherent(sc); 1443 1444 if (r & RT2860_MAC_INT_2) /* TX status */ 1445 rt2860_drain_stats_fifo(sc); 1446 1447 if (r & RT2860_TX_DONE_INT5) 1448 rt2860_tx_intr(sc, 5); 1449 1450 if (r & RT2860_RX_DONE_INT) 1451 rt2860_rx_intr(sc); 1452 1453 if (r & RT2860_TX_DONE_INT4) 1454 rt2860_tx_intr(sc, 4); 1455 1456 if (r & RT2860_TX_DONE_INT3) 1457 rt2860_tx_intr(sc, 3); 1458 1459 if (r & RT2860_TX_DONE_INT2) 1460 rt2860_tx_intr(sc, 2); 1461 1462 if (r & RT2860_TX_DONE_INT1) 1463 rt2860_tx_intr(sc, 1); 1464 1465 if (r & RT2860_TX_DONE_INT0) 1466 rt2860_tx_intr(sc, 0); 1467 1468 if (r & RT2860_MAC_INT_0) /* TBTT */ 1469 rt2860_tbtt_intr(sc); 1470 1471 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1472 /* TBD wakeup */; 1473 1474 if (r & RT2860_MAC_INT_4) /* GP timer */ 1475 rt2860_gp_intr(sc); 1476 1477 RAL_UNLOCK(sc); 1478 } 1479 1480 static int 1481 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1482 { 1483 struct ifnet *ifp = sc->sc_ifp; 1484 struct ieee80211com *ic = ifp->if_l2com; 1485 struct ieee80211vap *vap = ni->ni_vap; 1486 struct rt2860_tx_ring *ring; 1487 struct rt2860_tx_data *data; 1488 struct rt2860_txd *txd; 1489 struct rt2860_txwi *txwi; 1490 struct ieee80211_frame *wh; 1491 const struct ieee80211_txparam *tp; 1492 struct ieee80211_key *k; 1493 struct mbuf *m1; 1494 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1495 bus_dma_segment_t *seg; 1496 u_int hdrlen; 1497 uint16_t qos, dur; 1498 uint8_t type, qsel, mcs, pid, tid, qid; 1499 int i, nsegs, ntxds, pad, rate, ridx, error; 1500 1501 /* the data pool contains at least one element, pick the first */ 1502 data = SLIST_FIRST(&sc->data_pool); 1503 1504 wh = mtod(m, struct ieee80211_frame *); 1505 1506 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1507 k = ieee80211_crypto_encap(ni, m); 1508 if (k == NULL) { 1509 m_freem(m); 1510 return ENOBUFS; 1511 } 1512 1513 /* packet header may have moved, reset our local pointer */ 1514 wh = mtod(m, struct ieee80211_frame *); 1515 } 1516 1517 hdrlen = ieee80211_anyhdrsize(wh); 1518 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1519 1520 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1521 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1522 rate = tp->mcastrate; 1523 } else if (m->m_flags & M_EAPOL) { 1524 rate = tp->mgmtrate; 1525 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1526 rate = tp->ucastrate; 1527 } else { 1528 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1529 rate = ni->ni_txrate; 1530 } 1531 rate &= IEEE80211_RATE_VAL; 1532 1533 qid = M_WME_GETAC(m); 1534 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1535 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1536 tid = qos & IEEE80211_QOS_TID; 1537 } else { 1538 qos = 0; 1539 tid = 0; 1540 } 1541 ring = &sc->txq[qid]; 1542 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1543 1544 /* get MCS code from rate index */ 1545 mcs = rt2860_rates[ridx].mcs; 1546 1547 /* setup TX Wireless Information */ 1548 txwi = data->txwi; 1549 txwi->flags = 0; 1550 /* let HW generate seq numbers for non-QoS frames */ 1551 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1552 if (type == IEEE80211_FC0_TYPE_DATA) 1553 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1554 else 1555 txwi->wcid = 0xff; 1556 txwi->len = htole16(m->m_pkthdr.len); 1557 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1558 txwi->phy = htole16(RT2860_PHY_CCK); 1559 if (ridx != RT2860_RIDX_CCK1 && 1560 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1561 mcs |= RT2860_PHY_SHPRE; 1562 } else 1563 txwi->phy = htole16(RT2860_PHY_OFDM); 1564 txwi->phy |= htole16(mcs); 1565 1566 /* 1567 * We store the MCS code into the driver-private PacketID field. 1568 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1569 * that we know at which initial rate the frame was transmitted. 1570 * We add 1 to the MCS code because setting the PacketID field to 1571 * 0 means that we don't want feedback in TX_STAT_FIFO. 1572 */ 1573 pid = (mcs + 1) & 0xf; 1574 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1575 1576 /* check if RTS/CTS or CTS-to-self protection is required */ 1577 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1578 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1579 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1580 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1581 txwi->txop = RT2860_TX_TXOP_HT; 1582 else 1583 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1584 1585 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1586 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1587 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1588 txwi->xflags |= RT2860_TX_ACK; 1589 1590 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1591 dur = rt2860_rates[ridx].sp_ack_dur; 1592 else 1593 dur = rt2860_rates[ridx].lp_ack_dur; 1594 *(uint16_t *)wh->i_dur = htole16(dur); 1595 } 1596 /* ask MAC to insert timestamp into probe responses */ 1597 if ((wh->i_fc[0] & 1598 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1599 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1600 /* NOTE: beacons do not pass through tx_data() */ 1601 txwi->flags |= RT2860_TX_TS; 1602 1603 if (ieee80211_radiotap_active_vap(vap)) { 1604 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1605 1606 tap->wt_flags = 0; 1607 tap->wt_rate = rate; 1608 if (mcs & RT2860_PHY_SHPRE) 1609 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1610 1611 ieee80211_radiotap_tx(vap, m); 1612 } 1613 1614 pad = (hdrlen + 3) & ~3; 1615 1616 /* copy and trim 802.11 header */ 1617 memcpy(txwi + 1, wh, hdrlen); 1618 m_adj(m, hdrlen); 1619 1620 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1621 &nsegs, 0); 1622 if (__predict_false(error != 0 && error != EFBIG)) { 1623 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1624 error); 1625 m_freem(m); 1626 return error; 1627 } 1628 if (__predict_true(error == 0)) { 1629 /* determine how many TXDs are required */ 1630 ntxds = 1 + (nsegs / 2); 1631 1632 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1633 /* not enough free TXDs, force mbuf defrag */ 1634 bus_dmamap_unload(sc->txwi_dmat, data->map); 1635 error = EFBIG; 1636 } 1637 } 1638 if (__predict_false(error != 0)) { 1639 m1 = m_defrag(m, M_NOWAIT); 1640 if (m1 == NULL) { 1641 device_printf(sc->sc_dev, 1642 "could not defragment mbuf\n"); 1643 m_freem(m); 1644 return ENOBUFS; 1645 } 1646 m = m1; 1647 1648 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1649 segs, &nsegs, 0); 1650 if (__predict_false(error != 0)) { 1651 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1652 error); 1653 m_freem(m); 1654 return error; 1655 } 1656 1657 /* determine how many TXDs are now required */ 1658 ntxds = 1 + (nsegs / 2); 1659 1660 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1661 /* this is a hopeless case, drop the mbuf! */ 1662 bus_dmamap_unload(sc->txwi_dmat, data->map); 1663 m_freem(m); 1664 return ENOBUFS; 1665 } 1666 } 1667 1668 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1669 1670 /* first segment is TXWI + 802.11 header */ 1671 txd = &ring->txd[ring->cur]; 1672 txd->sdp0 = htole32(data->paddr); 1673 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1674 txd->flags = qsel; 1675 1676 /* setup payload segments */ 1677 seg = &segs[0]; 1678 for (i = nsegs; i >= 2; i -= 2) { 1679 txd->sdp1 = htole32(seg->ds_addr); 1680 txd->sdl1 = htole16(seg->ds_len); 1681 seg++; 1682 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1683 /* grab a new Tx descriptor */ 1684 txd = &ring->txd[ring->cur]; 1685 txd->sdp0 = htole32(seg->ds_addr); 1686 txd->sdl0 = htole16(seg->ds_len); 1687 txd->flags = qsel; 1688 seg++; 1689 } 1690 /* finalize last segment */ 1691 if (i > 0) { 1692 txd->sdp1 = htole32(seg->ds_addr); 1693 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1694 } else { 1695 txd->sdl0 |= htole16(RT2860_TX_LS0); 1696 txd->sdl1 = 0; 1697 } 1698 1699 /* remove from the free pool and link it into the SW Tx slot */ 1700 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1701 data->m = m; 1702 data->ni = ni; 1703 ring->data[ring->cur] = data; 1704 1705 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1706 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1707 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1708 1709 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1710 qid, txwi->wcid, nsegs, ridx)); 1711 1712 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1713 ring->queued += ntxds; 1714 if (ring->queued >= RT2860_TX_RING_COUNT) 1715 sc->qfullmsk |= 1 << qid; 1716 1717 /* kick Tx */ 1718 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1719 1720 return 0; 1721 } 1722 1723 static int 1724 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1725 const struct ieee80211_bpf_params *params) 1726 { 1727 struct ieee80211com *ic = ni->ni_ic; 1728 struct ifnet *ifp = ic->ic_ifp; 1729 struct rt2860_softc *sc = ifp->if_softc; 1730 int error; 1731 1732 RAL_LOCK(sc); 1733 1734 /* prevent management frames from being sent if we're not ready */ 1735 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1736 RAL_UNLOCK(sc); 1737 m_freem(m); 1738 ieee80211_free_node(ni); 1739 return ENETDOWN; 1740 } 1741 if (params == NULL) { 1742 /* 1743 * Legacy path; interpret frame contents to decide 1744 * precisely how to send the frame. 1745 */ 1746 error = rt2860_tx(sc, m, ni); 1747 } else { 1748 /* 1749 * Caller supplied explicit parameters to use in 1750 * sending the frame. 1751 */ 1752 error = rt2860_tx_raw(sc, m, ni, params); 1753 } 1754 if (error != 0) { 1755 /* NB: m is reclaimed on tx failure */ 1756 ieee80211_free_node(ni); 1757 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1758 } 1759 sc->sc_tx_timer = 5; 1760 RAL_UNLOCK(sc); 1761 return error; 1762 } 1763 1764 static int 1765 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1766 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1767 { 1768 struct ifnet *ifp = sc->sc_ifp; 1769 struct ieee80211com *ic = ifp->if_l2com; 1770 struct ieee80211vap *vap = ni->ni_vap; 1771 struct rt2860_tx_ring *ring; 1772 struct rt2860_tx_data *data; 1773 struct rt2860_txd *txd; 1774 struct rt2860_txwi *txwi; 1775 struct ieee80211_frame *wh; 1776 struct mbuf *m1; 1777 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1778 bus_dma_segment_t *seg; 1779 u_int hdrlen; 1780 uint16_t dur; 1781 uint8_t type, qsel, mcs, pid, tid, qid; 1782 int i, nsegs, ntxds, pad, rate, ridx, error; 1783 1784 /* the data pool contains at least one element, pick the first */ 1785 data = SLIST_FIRST(&sc->data_pool); 1786 1787 wh = mtod(m, struct ieee80211_frame *); 1788 hdrlen = ieee80211_hdrsize(wh); 1789 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1790 1791 /* Choose a TX rate index. */ 1792 rate = params->ibp_rate0; 1793 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1794 rate & IEEE80211_RATE_VAL); 1795 if (ridx == (uint8_t)-1) { 1796 /* XXX fall back to mcast/mgmt rate? */ 1797 m_freem(m); 1798 return EINVAL; 1799 } 1800 1801 qid = params->ibp_pri & 3; 1802 tid = 0; 1803 ring = &sc->txq[qid]; 1804 1805 /* get MCS code from rate index */ 1806 mcs = rt2860_rates[ridx].mcs; 1807 1808 /* setup TX Wireless Information */ 1809 txwi = data->txwi; 1810 txwi->flags = 0; 1811 /* let HW generate seq numbers for non-QoS frames */ 1812 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1813 txwi->wcid = 0xff; 1814 txwi->len = htole16(m->m_pkthdr.len); 1815 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1816 txwi->phy = htole16(RT2860_PHY_CCK); 1817 if (ridx != RT2860_RIDX_CCK1 && 1818 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1819 mcs |= RT2860_PHY_SHPRE; 1820 } else 1821 txwi->phy = htole16(RT2860_PHY_OFDM); 1822 txwi->phy |= htole16(mcs); 1823 1824 /* 1825 * We store the MCS code into the driver-private PacketID field. 1826 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1827 * that we know at which initial rate the frame was transmitted. 1828 * We add 1 to the MCS code because setting the PacketID field to 1829 * 0 means that we don't want feedback in TX_STAT_FIFO. 1830 */ 1831 pid = (mcs + 1) & 0xf; 1832 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1833 1834 /* check if RTS/CTS or CTS-to-self protection is required */ 1835 if (params->ibp_flags & IEEE80211_BPF_RTS || 1836 params->ibp_flags & IEEE80211_BPF_CTS) 1837 txwi->txop = RT2860_TX_TXOP_HT; 1838 else 1839 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1840 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1841 txwi->xflags |= RT2860_TX_ACK; 1842 1843 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1844 dur = rt2860_rates[ridx].sp_ack_dur; 1845 else 1846 dur = rt2860_rates[ridx].lp_ack_dur; 1847 *(uint16_t *)wh->i_dur = htole16(dur); 1848 } 1849 /* ask MAC to insert timestamp into probe responses */ 1850 if ((wh->i_fc[0] & 1851 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1852 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1853 /* NOTE: beacons do not pass through tx_data() */ 1854 txwi->flags |= RT2860_TX_TS; 1855 1856 if (ieee80211_radiotap_active_vap(vap)) { 1857 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1858 1859 tap->wt_flags = 0; 1860 tap->wt_rate = rate; 1861 if (mcs & RT2860_PHY_SHPRE) 1862 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1863 1864 ieee80211_radiotap_tx(vap, m); 1865 } 1866 1867 pad = (hdrlen + 3) & ~3; 1868 1869 /* copy and trim 802.11 header */ 1870 memcpy(txwi + 1, wh, hdrlen); 1871 m_adj(m, hdrlen); 1872 1873 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1874 &nsegs, 0); 1875 if (__predict_false(error != 0 && error != EFBIG)) { 1876 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1877 error); 1878 m_freem(m); 1879 return error; 1880 } 1881 if (__predict_true(error == 0)) { 1882 /* determine how many TXDs are required */ 1883 ntxds = 1 + (nsegs / 2); 1884 1885 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1886 /* not enough free TXDs, force mbuf defrag */ 1887 bus_dmamap_unload(sc->txwi_dmat, data->map); 1888 error = EFBIG; 1889 } 1890 } 1891 if (__predict_false(error != 0)) { 1892 m1 = m_defrag(m, M_NOWAIT); 1893 if (m1 == NULL) { 1894 device_printf(sc->sc_dev, 1895 "could not defragment mbuf\n"); 1896 m_freem(m); 1897 return ENOBUFS; 1898 } 1899 m = m1; 1900 1901 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1902 segs, &nsegs, 0); 1903 if (__predict_false(error != 0)) { 1904 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1905 error); 1906 m_freem(m); 1907 return error; 1908 } 1909 1910 /* determine how many TXDs are now required */ 1911 ntxds = 1 + (nsegs / 2); 1912 1913 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1914 /* this is a hopeless case, drop the mbuf! */ 1915 bus_dmamap_unload(sc->txwi_dmat, data->map); 1916 m_freem(m); 1917 return ENOBUFS; 1918 } 1919 } 1920 1921 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1922 1923 /* first segment is TXWI + 802.11 header */ 1924 txd = &ring->txd[ring->cur]; 1925 txd->sdp0 = htole32(data->paddr); 1926 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1927 txd->flags = qsel; 1928 1929 /* setup payload segments */ 1930 seg = &segs[0]; 1931 for (i = nsegs; i >= 2; i -= 2) { 1932 txd->sdp1 = htole32(seg->ds_addr); 1933 txd->sdl1 = htole16(seg->ds_len); 1934 seg++; 1935 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1936 /* grab a new Tx descriptor */ 1937 txd = &ring->txd[ring->cur]; 1938 txd->sdp0 = htole32(seg->ds_addr); 1939 txd->sdl0 = htole16(seg->ds_len); 1940 txd->flags = qsel; 1941 seg++; 1942 } 1943 /* finalize last segment */ 1944 if (i > 0) { 1945 txd->sdp1 = htole32(seg->ds_addr); 1946 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1947 } else { 1948 txd->sdl0 |= htole16(RT2860_TX_LS0); 1949 txd->sdl1 = 0; 1950 } 1951 1952 /* remove from the free pool and link it into the SW Tx slot */ 1953 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1954 data->m = m; 1955 data->ni = ni; 1956 ring->data[ring->cur] = data; 1957 1958 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1959 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1960 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1961 1962 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1963 qid, txwi->wcid, nsegs, ridx)); 1964 1965 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1966 ring->queued += ntxds; 1967 if (ring->queued >= RT2860_TX_RING_COUNT) 1968 sc->qfullmsk |= 1 << qid; 1969 1970 /* kick Tx */ 1971 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1972 1973 return 0; 1974 } 1975 1976 static void 1977 rt2860_start(struct ifnet *ifp) 1978 { 1979 struct rt2860_softc *sc = ifp->if_softc; 1980 1981 RAL_LOCK(sc); 1982 rt2860_start_locked(ifp); 1983 RAL_UNLOCK(sc); 1984 } 1985 1986 static void 1987 rt2860_start_locked(struct ifnet *ifp) 1988 { 1989 struct rt2860_softc *sc = ifp->if_softc; 1990 struct ieee80211_node *ni; 1991 struct mbuf *m; 1992 1993 RAL_LOCK_ASSERT(sc); 1994 1995 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1996 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) 1997 return; 1998 1999 for (;;) { 2000 if (SLIST_EMPTY(&sc->data_pool) || sc->qfullmsk != 0) { 2001 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2002 break; 2003 } 2004 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2005 if (m == NULL) 2006 break; 2007 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 2008 if (rt2860_tx(sc, m, ni) != 0) { 2009 ieee80211_free_node(ni); 2010 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2011 continue; 2012 } 2013 sc->sc_tx_timer = 5; 2014 } 2015 } 2016 2017 static void 2018 rt2860_watchdog(void *arg) 2019 { 2020 struct rt2860_softc *sc = arg; 2021 struct ifnet *ifp = sc->sc_ifp; 2022 2023 RAL_LOCK_ASSERT(sc); 2024 2025 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 2026 2027 if (sc->sc_invalid) /* card ejected */ 2028 return; 2029 2030 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 2031 if_printf(ifp, "device timeout\n"); 2032 rt2860_stop_locked(sc); 2033 rt2860_init_locked(sc); 2034 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2035 return; 2036 } 2037 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2038 } 2039 2040 static int 2041 rt2860_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2042 { 2043 struct rt2860_softc *sc = ifp->if_softc; 2044 struct ieee80211com *ic = ifp->if_l2com; 2045 struct ifreq *ifr = (struct ifreq *)data; 2046 int error = 0, startall = 0; 2047 2048 switch (cmd) { 2049 case SIOCSIFFLAGS: 2050 RAL_LOCK(sc); 2051 if (ifp->if_flags & IFF_UP) { 2052 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2053 rt2860_init_locked(sc); 2054 startall = 1; 2055 } else 2056 rt2860_update_promisc(ic); 2057 } else { 2058 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2059 rt2860_stop_locked(sc); 2060 } 2061 RAL_UNLOCK(sc); 2062 if (startall) 2063 ieee80211_start_all(ic); 2064 break; 2065 case SIOCGIFMEDIA: 2066 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 2067 break; 2068 case SIOCSIFADDR: 2069 error = ether_ioctl(ifp, cmd, data); 2070 break; 2071 default: 2072 error = EINVAL; 2073 break; 2074 } 2075 return error; 2076 } 2077 2078 /* 2079 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2080 * We access the BBP through the 8051 microcontroller unit which means that 2081 * the microcode must be loaded first. 2082 */ 2083 void 2084 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2085 { 2086 int ntries; 2087 2088 for (ntries = 0; ntries < 100; ntries++) { 2089 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2090 break; 2091 DELAY(1); 2092 } 2093 if (ntries == 100) { 2094 device_printf(sc->sc_dev, 2095 "could not write to BBP through MCU\n"); 2096 return; 2097 } 2098 2099 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2100 RT2860_BBP_CSR_KICK | reg << 8 | val); 2101 RAL_BARRIER_WRITE(sc); 2102 2103 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2104 DELAY(1000); 2105 } 2106 2107 uint8_t 2108 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2109 { 2110 uint32_t val; 2111 int ntries; 2112 2113 for (ntries = 0; ntries < 100; ntries++) { 2114 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2115 break; 2116 DELAY(1); 2117 } 2118 if (ntries == 100) { 2119 device_printf(sc->sc_dev, 2120 "could not read from BBP through MCU\n"); 2121 return 0; 2122 } 2123 2124 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2125 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2126 RAL_BARRIER_WRITE(sc); 2127 2128 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2129 DELAY(1000); 2130 2131 for (ntries = 0; ntries < 100; ntries++) { 2132 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2133 if (!(val & RT2860_BBP_CSR_KICK)) 2134 return val & 0xff; 2135 DELAY(1); 2136 } 2137 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2138 2139 return 0; 2140 } 2141 2142 /* 2143 * Write to one of the 4 programmable 24-bit RF registers. 2144 */ 2145 static void 2146 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2147 { 2148 uint32_t tmp; 2149 int ntries; 2150 2151 for (ntries = 0; ntries < 100; ntries++) { 2152 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2153 break; 2154 DELAY(1); 2155 } 2156 if (ntries == 100) { 2157 device_printf(sc->sc_dev, "could not write to RF\n"); 2158 return; 2159 } 2160 2161 /* RF registers are 24-bit on the RT2860 */ 2162 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2163 (val & 0x3fffff) << 2 | (reg & 3); 2164 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2165 } 2166 2167 static uint8_t 2168 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2169 { 2170 uint32_t tmp; 2171 int ntries; 2172 2173 for (ntries = 0; ntries < 100; ntries++) { 2174 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2175 break; 2176 DELAY(1); 2177 } 2178 if (ntries == 100) { 2179 device_printf(sc->sc_dev, "could not read RF register\n"); 2180 return 0xff; 2181 } 2182 tmp = RT3070_RF_KICK | reg << 8; 2183 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2184 2185 for (ntries = 0; ntries < 100; ntries++) { 2186 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2187 if (!(tmp & RT3070_RF_KICK)) 2188 break; 2189 DELAY(1); 2190 } 2191 if (ntries == 100) { 2192 device_printf(sc->sc_dev, "could not read RF register\n"); 2193 return 0xff; 2194 } 2195 return tmp & 0xff; 2196 } 2197 2198 void 2199 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2200 { 2201 uint32_t tmp; 2202 int ntries; 2203 2204 for (ntries = 0; ntries < 10; ntries++) { 2205 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2206 break; 2207 DELAY(10); 2208 } 2209 if (ntries == 10) { 2210 device_printf(sc->sc_dev, "could not write to RF\n"); 2211 return; 2212 } 2213 2214 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2215 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2216 } 2217 2218 /* 2219 * Send a command to the 8051 microcontroller unit. 2220 */ 2221 int 2222 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2223 { 2224 int slot, ntries; 2225 uint32_t tmp; 2226 uint8_t cid; 2227 2228 for (ntries = 0; ntries < 100; ntries++) { 2229 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2230 break; 2231 DELAY(2); 2232 } 2233 if (ntries == 100) 2234 return EIO; 2235 2236 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2237 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2238 RAL_BARRIER_WRITE(sc); 2239 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2240 2241 if (!wait) 2242 return 0; 2243 /* wait for the command to complete */ 2244 for (ntries = 0; ntries < 200; ntries++) { 2245 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2246 /* find the command slot */ 2247 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2248 if ((tmp & 0xff) == cid) 2249 break; 2250 if (slot < 4) 2251 break; 2252 DELAY(100); 2253 } 2254 if (ntries == 200) { 2255 /* clear command and status */ 2256 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2257 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2258 return ETIMEDOUT; 2259 } 2260 /* get command status (1 means success) */ 2261 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2262 tmp = (tmp >> (slot * 8)) & 0xff; 2263 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2264 cmd, slot, tmp)); 2265 /* clear command and status */ 2266 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2267 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2268 return (tmp == 1) ? 0 : EIO; 2269 } 2270 2271 static void 2272 rt2860_enable_mrr(struct rt2860_softc *sc) 2273 { 2274 #define CCK(mcs) (mcs) 2275 #define OFDM(mcs) (1 << 3 | (mcs)) 2276 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2277 OFDM(6) << 28 | /* 54->48 */ 2278 OFDM(5) << 24 | /* 48->36 */ 2279 OFDM(4) << 20 | /* 36->24 */ 2280 OFDM(3) << 16 | /* 24->18 */ 2281 OFDM(2) << 12 | /* 18->12 */ 2282 OFDM(1) << 8 | /* 12-> 9 */ 2283 OFDM(0) << 4 | /* 9-> 6 */ 2284 OFDM(0)); /* 6-> 6 */ 2285 2286 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2287 CCK(2) << 12 | /* 11->5.5 */ 2288 CCK(1) << 8 | /* 5.5-> 2 */ 2289 CCK(0) << 4 | /* 2-> 1 */ 2290 CCK(0)); /* 1-> 1 */ 2291 #undef OFDM 2292 #undef CCK 2293 } 2294 2295 static void 2296 rt2860_set_txpreamble(struct rt2860_softc *sc) 2297 { 2298 struct ifnet *ifp = sc->sc_ifp; 2299 struct ieee80211com *ic = ifp->if_l2com; 2300 uint32_t tmp; 2301 2302 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2303 tmp &= ~RT2860_CCK_SHORT_EN; 2304 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2305 tmp |= RT2860_CCK_SHORT_EN; 2306 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2307 } 2308 2309 void 2310 rt2860_set_basicrates(struct rt2860_softc *sc, 2311 const struct ieee80211_rateset *rs) 2312 { 2313 #define RV(r) ((r) & IEEE80211_RATE_VAL) 2314 struct ifnet *ifp = sc->sc_ifp; 2315 struct ieee80211com *ic = ifp->if_l2com; 2316 uint32_t mask = 0; 2317 uint8_t rate; 2318 int i; 2319 2320 for (i = 0; i < rs->rs_nrates; i++) { 2321 rate = rs->rs_rates[i]; 2322 2323 if (!(rate & IEEE80211_RATE_BASIC)) 2324 continue; 2325 2326 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, RV(rate)); 2327 } 2328 2329 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2330 #undef RV 2331 } 2332 2333 static void 2334 rt2860_scan_start(struct ieee80211com *ic) 2335 { 2336 struct ifnet *ifp = ic->ic_ifp; 2337 struct rt2860_softc *sc = ifp->if_softc; 2338 uint32_t tmp; 2339 2340 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2341 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2342 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2343 RT2860_TBTT_TIMER_EN)); 2344 rt2860_set_gp_timer(sc, 0); 2345 } 2346 2347 static void 2348 rt2860_scan_end(struct ieee80211com *ic) 2349 { 2350 struct ifnet *ifp = ic->ic_ifp; 2351 struct rt2860_softc *sc = ifp->if_softc; 2352 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2353 2354 if (vap->iv_state == IEEE80211_S_RUN) { 2355 rt2860_enable_tsf_sync(sc); 2356 rt2860_set_gp_timer(sc, 500); 2357 } 2358 } 2359 2360 static void 2361 rt2860_set_channel(struct ieee80211com *ic) 2362 { 2363 struct ifnet *ifp = ic->ic_ifp; 2364 struct rt2860_softc *sc = ifp->if_softc; 2365 2366 RAL_LOCK(sc); 2367 rt2860_switch_chan(sc, ic->ic_curchan); 2368 RAL_UNLOCK(sc); 2369 } 2370 2371 static void 2372 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2373 { 2374 uint32_t tmp; 2375 uint8_t agc; 2376 2377 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2378 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2379 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2380 rt2860_mcu_bbp_write(sc, 86, 0x00); 2381 2382 if (group == 0) { 2383 if (sc->ext_2ghz_lna) { 2384 rt2860_mcu_bbp_write(sc, 82, 0x62); 2385 rt2860_mcu_bbp_write(sc, 75, 0x46); 2386 } else { 2387 rt2860_mcu_bbp_write(sc, 82, 0x84); 2388 rt2860_mcu_bbp_write(sc, 75, 0x50); 2389 } 2390 } else { 2391 if (sc->ext_5ghz_lna) { 2392 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2393 rt2860_mcu_bbp_write(sc, 75, 0x46); 2394 } else { 2395 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2396 rt2860_mcu_bbp_write(sc, 75, 0x50); 2397 } 2398 } 2399 2400 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2401 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2402 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2403 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2404 2405 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2406 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2407 if (sc->nrxchains > 1) 2408 tmp |= RT2860_LNA_PE1_EN; 2409 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2410 tmp |= RT3593_LNA_PE2_EN; 2411 if (group == 0) { /* 2GHz */ 2412 tmp |= RT2860_PA_PE_G0_EN; 2413 if (sc->ntxchains > 1) 2414 tmp |= RT2860_PA_PE_G1_EN; 2415 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2416 tmp |= RT3593_PA_PE_G2_EN; 2417 } else { /* 5GHz */ 2418 tmp |= RT2860_PA_PE_A0_EN; 2419 if (sc->ntxchains > 1) 2420 tmp |= RT2860_PA_PE_A1_EN; 2421 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2422 tmp |= RT3593_PA_PE_A2_EN; 2423 } 2424 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2425 2426 if (sc->mac_ver == 0x3593) { 2427 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2428 if (sc->sc_flags & RT2860_PCIE) { 2429 tmp &= ~0x01010000; 2430 if (group == 0) 2431 tmp |= 0x00010000; 2432 } else { 2433 tmp &= ~0x00008080; 2434 if (group == 0) 2435 tmp |= 0x00000080; 2436 } 2437 tmp = (tmp & ~0x00001000) | 0x00000010; 2438 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2439 } 2440 2441 /* set initial AGC value */ 2442 if (group == 0) { /* 2GHz band */ 2443 if (sc->mac_ver >= 0x3071) 2444 agc = 0x1c + sc->lna[0] * 2; 2445 else 2446 agc = 0x2e + sc->lna[0]; 2447 } else { /* 5GHz band */ 2448 agc = 0x32 + (sc->lna[group] * 5) / 3; 2449 } 2450 rt2860_mcu_bbp_write(sc, 66, agc); 2451 2452 DELAY(1000); 2453 } 2454 2455 static void 2456 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2457 { 2458 const struct rfprog *rfprog = rt2860_rf2850; 2459 uint32_t r2, r3, r4; 2460 int8_t txpow1, txpow2; 2461 u_int i; 2462 2463 /* find the settings for this channel (we know it exists) */ 2464 for (i = 0; rfprog[i].chan != chan; i++); 2465 2466 r2 = rfprog[i].r2; 2467 if (sc->ntxchains == 1) 2468 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2469 if (sc->nrxchains == 1) 2470 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2471 else if (sc->nrxchains == 2) 2472 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2473 2474 /* use Tx power values from EEPROM */ 2475 txpow1 = sc->txpow1[i]; 2476 txpow2 = sc->txpow2[i]; 2477 if (chan > 14) { 2478 if (txpow1 >= 0) 2479 txpow1 = txpow1 << 1 | 1; 2480 else 2481 txpow1 = (7 + txpow1) << 1; 2482 if (txpow2 >= 0) 2483 txpow2 = txpow2 << 1 | 1; 2484 else 2485 txpow2 = (7 + txpow2) << 1; 2486 } 2487 r3 = rfprog[i].r3 | txpow1 << 7; 2488 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2489 2490 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2491 rt2860_rf_write(sc, RT2860_RF2, r2); 2492 rt2860_rf_write(sc, RT2860_RF3, r3); 2493 rt2860_rf_write(sc, RT2860_RF4, r4); 2494 2495 DELAY(200); 2496 2497 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2498 rt2860_rf_write(sc, RT2860_RF2, r2); 2499 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2500 rt2860_rf_write(sc, RT2860_RF4, r4); 2501 2502 DELAY(200); 2503 2504 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2505 rt2860_rf_write(sc, RT2860_RF2, r2); 2506 rt2860_rf_write(sc, RT2860_RF3, r3); 2507 rt2860_rf_write(sc, RT2860_RF4, r4); 2508 } 2509 2510 static void 2511 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2512 { 2513 int8_t txpow1, txpow2; 2514 uint8_t rf; 2515 int i; 2516 2517 /* RT3090 is 2GHz only */ 2518 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2519 2520 /* find the settings for this channel (we know it exists) */ 2521 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2522 2523 /* use Tx power values from EEPROM */ 2524 txpow1 = sc->txpow1[i]; 2525 txpow2 = sc->txpow2[i]; 2526 2527 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2528 rf = rt3090_rf_read(sc, 3); 2529 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2530 rt3090_rf_write(sc, 3, rf); 2531 rf = rt3090_rf_read(sc, 6); 2532 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2533 rt3090_rf_write(sc, 6, rf); 2534 2535 /* set Tx0 power */ 2536 rf = rt3090_rf_read(sc, 12); 2537 rf = (rf & ~0x1f) | txpow1; 2538 rt3090_rf_write(sc, 12, rf); 2539 2540 /* set Tx1 power */ 2541 rf = rt3090_rf_read(sc, 13); 2542 rf = (rf & ~0x1f) | txpow2; 2543 rt3090_rf_write(sc, 13, rf); 2544 2545 rf = rt3090_rf_read(sc, 1); 2546 rf &= ~0xfc; 2547 if (sc->ntxchains == 1) 2548 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2549 else if (sc->ntxchains == 2) 2550 rf |= RT3070_TX2_PD; 2551 if (sc->nrxchains == 1) 2552 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2553 else if (sc->nrxchains == 2) 2554 rf |= RT3070_RX2_PD; 2555 rt3090_rf_write(sc, 1, rf); 2556 2557 /* set RF offset */ 2558 rf = rt3090_rf_read(sc, 23); 2559 rf = (rf & ~0x7f) | sc->freq; 2560 rt3090_rf_write(sc, 23, rf); 2561 2562 /* program RF filter */ 2563 rf = rt3090_rf_read(sc, 24); /* Tx */ 2564 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2565 rt3090_rf_write(sc, 24, rf); 2566 rf = rt3090_rf_read(sc, 31); /* Rx */ 2567 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2568 rt3090_rf_write(sc, 31, rf); 2569 2570 /* enable RF tuning */ 2571 rf = rt3090_rf_read(sc, 7); 2572 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2573 } 2574 2575 static void 2576 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2577 { 2578 uint8_t h20mhz, rf, tmp; 2579 int8_t txpow1, txpow2; 2580 int i; 2581 2582 /* RT5390 is 2GHz only */ 2583 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2584 2585 /* find the settings for this channel (we know it exists) */ 2586 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2587 2588 /* use Tx power values from EEPROM */ 2589 txpow1 = sc->txpow1[i]; 2590 txpow2 = sc->txpow2[i]; 2591 2592 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2593 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2594 rf = rt3090_rf_read(sc, 11); 2595 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2596 rt3090_rf_write(sc, 11, rf); 2597 2598 rf = rt3090_rf_read(sc, 49); 2599 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2600 /* the valid range of the RF R49 is 0x00~0x27 */ 2601 if ((rf & 0x3f) > 0x27) 2602 rf = (rf & ~0x3f) | 0x27; 2603 rt3090_rf_write(sc, 49, rf); 2604 if (sc->mac_ver == 0x5392) { 2605 rf = rt3090_rf_read(sc, 50); 2606 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2607 /* the valid range of the RF R50 is 0x00~0x27 */ 2608 if ((rf & 0x3f) > 0x27) 2609 rf = (rf & ~0x3f) | 0x27; 2610 rt3090_rf_write(sc, 50, rf); 2611 } 2612 2613 rf = rt3090_rf_read(sc, 1); 2614 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2615 if (sc->mac_ver == 0x5392) 2616 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2617 rt3090_rf_write(sc, 1, rf); 2618 2619 rf = rt3090_rf_read(sc, 2); 2620 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2621 DELAY(1000); 2622 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2623 2624 rf = rt3090_rf_read(sc, 17); 2625 tmp = rf; 2626 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2627 rf = MIN(rf, 0x5f); 2628 if (tmp != rf) 2629 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2630 2631 if (sc->mac_ver == 0x5390) { 2632 if (chan <= 4) 2633 rf = 0x73; 2634 else if (chan >= 5 && chan <= 6) 2635 rf = 0x63; 2636 else if (chan >= 7 && chan <= 10) 2637 rf = 0x53; 2638 else 2639 rf = 43; 2640 rt3090_rf_write(sc, 55, rf); 2641 2642 if (chan == 1) 2643 rf = 0x0c; 2644 else if (chan == 2) 2645 rf = 0x0b; 2646 else if (chan == 3) 2647 rf = 0x0a; 2648 else if (chan >= 4 && chan <= 6) 2649 rf = 0x09; 2650 else if (chan >= 7 && chan <= 12) 2651 rf = 0x08; 2652 else if (chan == 13) 2653 rf = 0x07; 2654 else 2655 rf = 0x06; 2656 rt3090_rf_write(sc, 59, rf); 2657 } 2658 2659 /* Tx/Rx h20M */ 2660 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2661 rf = rt3090_rf_read(sc, 30); 2662 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2663 rt3090_rf_write(sc, 30, rf); 2664 2665 /* Rx BB filter VCM */ 2666 rf = rt3090_rf_read(sc, 30); 2667 rf = (rf & ~0x18) | 0x10; 2668 rt3090_rf_write(sc, 30, rf); 2669 2670 /* Initiate VCO calibration. */ 2671 rf = rt3090_rf_read(sc, 3); 2672 rf |= RT3593_VCOCAL; 2673 rt3090_rf_write(sc, 3, rf); 2674 } 2675 2676 static int 2677 rt3090_rf_init(struct rt2860_softc *sc) 2678 { 2679 uint32_t tmp; 2680 uint8_t rf, bbp; 2681 int i; 2682 2683 rf = rt3090_rf_read(sc, 30); 2684 /* toggle RF R30 bit 7 */ 2685 rt3090_rf_write(sc, 30, rf | 0x80); 2686 DELAY(1000); 2687 rt3090_rf_write(sc, 30, rf & ~0x80); 2688 2689 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2690 tmp &= ~0x1f000000; 2691 if (sc->patch_dac && sc->mac_rev < 0x0211) 2692 tmp |= 0x0d000000; /* 1.35V */ 2693 else 2694 tmp |= 0x01000000; /* 1.2V */ 2695 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2696 2697 /* patch LNA_PE_G1 */ 2698 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2699 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2700 2701 /* initialize RF registers to default value */ 2702 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2703 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2704 rt3090_def_rf[i].val); 2705 } 2706 2707 /* select 20MHz bandwidth */ 2708 rt3090_rf_write(sc, 31, 0x14); 2709 2710 rf = rt3090_rf_read(sc, 6); 2711 rt3090_rf_write(sc, 6, rf | 0x40); 2712 2713 if (sc->mac_ver != 0x3593) { 2714 /* calibrate filter for 20MHz bandwidth */ 2715 sc->rf24_20mhz = 0x1f; /* default value */ 2716 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2717 2718 /* select 40MHz bandwidth */ 2719 bbp = rt2860_mcu_bbp_read(sc, 4); 2720 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2721 rf = rt3090_rf_read(sc, 31); 2722 rt3090_rf_write(sc, 31, rf | 0x20); 2723 2724 /* calibrate filter for 40MHz bandwidth */ 2725 sc->rf24_40mhz = 0x2f; /* default value */ 2726 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2727 2728 /* go back to 20MHz bandwidth */ 2729 bbp = rt2860_mcu_bbp_read(sc, 4); 2730 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2731 } 2732 if (sc->mac_rev < 0x0211) 2733 rt3090_rf_write(sc, 27, 0x03); 2734 2735 tmp = RAL_READ(sc, RT3070_OPT_14); 2736 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2737 2738 if (sc->rf_rev == RT3070_RF_3020) 2739 rt3090_set_rx_antenna(sc, 0); 2740 2741 bbp = rt2860_mcu_bbp_read(sc, 138); 2742 if (sc->mac_ver == 0x3593) { 2743 if (sc->ntxchains == 1) 2744 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2745 else if (sc->ntxchains == 2) 2746 bbp |= 0x40; /* turn off DAC2 */ 2747 if (sc->nrxchains == 1) 2748 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2749 else if (sc->nrxchains == 2) 2750 bbp &= ~0x04; /* turn off ADC2 */ 2751 } else { 2752 if (sc->ntxchains == 1) 2753 bbp |= 0x20; /* turn off DAC1 */ 2754 if (sc->nrxchains == 1) 2755 bbp &= ~0x02; /* turn off ADC1 */ 2756 } 2757 rt2860_mcu_bbp_write(sc, 138, bbp); 2758 2759 rf = rt3090_rf_read(sc, 1); 2760 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2761 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2762 rt3090_rf_write(sc, 1, rf); 2763 2764 rf = rt3090_rf_read(sc, 15); 2765 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2766 2767 rf = rt3090_rf_read(sc, 17); 2768 rf &= ~RT3070_TX_LO1; 2769 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2770 rf |= 0x20; /* fix for long range Rx issue */ 2771 if (sc->txmixgain_2ghz >= 2) 2772 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2773 rt3090_rf_write(sc, 17, rf); 2774 2775 rf = rt3090_rf_read(sc, 20); 2776 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2777 2778 rf = rt3090_rf_read(sc, 21); 2779 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2780 2781 return (0); 2782 } 2783 2784 static void 2785 rt5390_rf_init(struct rt2860_softc *sc) 2786 { 2787 uint8_t rf, bbp; 2788 int i; 2789 2790 rf = rt3090_rf_read(sc, 2); 2791 /* Toggle RF R2 bit 7. */ 2792 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2793 DELAY(1000); 2794 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2795 2796 /* Initialize RF registers to default value. */ 2797 if (sc->mac_ver == 0x5392) { 2798 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2799 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2800 rt5392_def_rf[i].val); 2801 } 2802 } else { 2803 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2804 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2805 rt5390_def_rf[i].val); 2806 } 2807 } 2808 2809 sc->rf24_20mhz = 0x1f; 2810 sc->rf24_40mhz = 0x2f; 2811 2812 if (sc->mac_rev < 0x0211) 2813 rt3090_rf_write(sc, 27, 0x03); 2814 2815 /* Set led open drain enable. */ 2816 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2817 2818 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2819 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2820 2821 if (sc->mac_ver == 0x5390) 2822 rt3090_set_rx_antenna(sc, 0); 2823 2824 /* Patch RSSI inaccurate issue. */ 2825 rt2860_mcu_bbp_write(sc, 79, 0x13); 2826 rt2860_mcu_bbp_write(sc, 80, 0x05); 2827 rt2860_mcu_bbp_write(sc, 81, 0x33); 2828 2829 /* Enable DC filter. */ 2830 if (sc->mac_rev >= 0x0211) 2831 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2832 2833 bbp = rt2860_mcu_bbp_read(sc, 138); 2834 if (sc->ntxchains == 1) 2835 bbp |= 0x20; /* Turn off DAC1. */ 2836 if (sc->nrxchains == 1) 2837 bbp &= ~0x02; /* Turn off ADC1. */ 2838 rt2860_mcu_bbp_write(sc, 138, bbp); 2839 2840 /* Enable RX LO1 and LO2. */ 2841 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2842 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2843 2844 /* Avoid data lost and CRC error. */ 2845 rt2860_mcu_bbp_write(sc, 4, 2846 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2847 2848 rf = rt3090_rf_read(sc, 30); 2849 rf = (rf & ~0x18) | 0x10; 2850 rt3090_rf_write(sc, 30, rf); 2851 } 2852 2853 static void 2854 rt3090_rf_wakeup(struct rt2860_softc *sc) 2855 { 2856 uint32_t tmp; 2857 uint8_t rf; 2858 2859 if (sc->mac_ver == 0x3593) { 2860 /* enable VCO */ 2861 rf = rt3090_rf_read(sc, 1); 2862 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2863 2864 /* initiate VCO calibration */ 2865 rf = rt3090_rf_read(sc, 3); 2866 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2867 2868 /* enable VCO bias current control */ 2869 rf = rt3090_rf_read(sc, 6); 2870 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2871 2872 /* initiate res calibration */ 2873 rf = rt3090_rf_read(sc, 2); 2874 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2875 2876 /* set reference current control to 0.33 mA */ 2877 rf = rt3090_rf_read(sc, 22); 2878 rf &= ~RT3593_CP_IC_MASK; 2879 rf |= 1 << RT3593_CP_IC_SHIFT; 2880 rt3090_rf_write(sc, 22, rf); 2881 2882 /* enable RX CTB */ 2883 rf = rt3090_rf_read(sc, 46); 2884 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2885 2886 rf = rt3090_rf_read(sc, 20); 2887 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2888 rt3090_rf_write(sc, 20, rf); 2889 } else { 2890 /* enable RF block */ 2891 rf = rt3090_rf_read(sc, 1); 2892 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2893 2894 /* enable VCO bias current control */ 2895 rf = rt3090_rf_read(sc, 7); 2896 rt3090_rf_write(sc, 7, rf | 0x30); 2897 2898 rf = rt3090_rf_read(sc, 9); 2899 rt3090_rf_write(sc, 9, rf | 0x0e); 2900 2901 /* enable RX CTB */ 2902 rf = rt3090_rf_read(sc, 21); 2903 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2904 2905 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2906 rf = rt3090_rf_read(sc, 27); 2907 rf &= ~0x77; 2908 if (sc->mac_rev < 0x0211) 2909 rf |= 0x03; 2910 rt3090_rf_write(sc, 27, rf); 2911 } 2912 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2913 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2914 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2915 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2916 } 2917 } 2918 2919 static void 2920 rt5390_rf_wakeup(struct rt2860_softc *sc) 2921 { 2922 uint32_t tmp; 2923 uint8_t rf; 2924 2925 rf = rt3090_rf_read(sc, 1); 2926 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2927 RT3070_TX0_PD; 2928 if (sc->mac_ver == 0x5392) 2929 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2930 rt3090_rf_write(sc, 1, rf); 2931 2932 rf = rt3090_rf_read(sc, 6); 2933 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2934 if (sc->mac_ver == 0x5390) 2935 rf &= ~RT3593_VCO_IC; 2936 rt3090_rf_write(sc, 6, rf); 2937 2938 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2939 2940 rf = rt3090_rf_read(sc, 22); 2941 rf = (rf & ~0xe0) | 0x20; 2942 rt3090_rf_write(sc, 22, rf); 2943 2944 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2945 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2946 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2947 2948 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2949 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2950 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2951 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2952 } 2953 } 2954 2955 static int 2956 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2957 uint8_t *val) 2958 { 2959 uint8_t rf22, rf24; 2960 uint8_t bbp55_pb, bbp55_sb, delta; 2961 int ntries; 2962 2963 /* program filter */ 2964 rf24 = rt3090_rf_read(sc, 24); 2965 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2966 rt3090_rf_write(sc, 24, rf24); 2967 2968 /* enable baseband loopback mode */ 2969 rf22 = rt3090_rf_read(sc, 22); 2970 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2971 2972 /* set power and frequency of passband test tone */ 2973 rt2860_mcu_bbp_write(sc, 24, 0x00); 2974 for (ntries = 0; ntries < 100; ntries++) { 2975 /* transmit test tone */ 2976 rt2860_mcu_bbp_write(sc, 25, 0x90); 2977 DELAY(1000); 2978 /* read received power */ 2979 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2980 if (bbp55_pb != 0) 2981 break; 2982 } 2983 if (ntries == 100) 2984 return (ETIMEDOUT); 2985 2986 /* set power and frequency of stopband test tone */ 2987 rt2860_mcu_bbp_write(sc, 24, 0x06); 2988 for (ntries = 0; ntries < 100; ntries++) { 2989 /* transmit test tone */ 2990 rt2860_mcu_bbp_write(sc, 25, 0x90); 2991 DELAY(1000); 2992 /* read received power */ 2993 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2994 2995 delta = bbp55_pb - bbp55_sb; 2996 if (delta > target) 2997 break; 2998 2999 /* reprogram filter */ 3000 rf24++; 3001 rt3090_rf_write(sc, 24, rf24); 3002 } 3003 if (ntries < 100) { 3004 if (rf24 != init) 3005 rf24--; /* backtrack */ 3006 *val = rf24; 3007 rt3090_rf_write(sc, 24, rf24); 3008 } 3009 3010 /* restore initial state */ 3011 rt2860_mcu_bbp_write(sc, 24, 0x00); 3012 3013 /* disable baseband loopback mode */ 3014 rf22 = rt3090_rf_read(sc, 22); 3015 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 3016 3017 return (0); 3018 } 3019 3020 static void 3021 rt3090_rf_setup(struct rt2860_softc *sc) 3022 { 3023 uint8_t bbp; 3024 int i; 3025 3026 if (sc->mac_rev >= 0x0211) { 3027 /* enable DC filter */ 3028 rt2860_mcu_bbp_write(sc, 103, 0xc0); 3029 3030 /* improve power consumption */ 3031 bbp = rt2860_mcu_bbp_read(sc, 31); 3032 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 3033 } 3034 3035 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 3036 if (sc->mac_rev < 0x0211) { 3037 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 3038 sc->patch_dac ? 0x2c : 0x0f); 3039 } else 3040 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 3041 3042 /* initialize RF registers from ROM */ 3043 if (sc->mac_ver < 0x5390) { 3044 for (i = 0; i < 10; i++) { 3045 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 3046 continue; 3047 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3048 } 3049 } 3050 } 3051 3052 static void 3053 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3054 { 3055 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3056 which | (sc->leds & 0x7f), 0); 3057 } 3058 3059 /* 3060 * Hardware has a general-purpose programmable timer interrupt that can 3061 * periodically raise MAC_INT_4. 3062 */ 3063 static void 3064 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3065 { 3066 uint32_t tmp; 3067 3068 /* disable GP timer before reprogramming it */ 3069 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3070 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3071 3072 if (ms == 0) 3073 return; 3074 3075 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3076 ms *= 16; /* Unit: 64us */ 3077 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3078 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3079 3080 /* enable GP timer */ 3081 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3082 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3083 } 3084 3085 static void 3086 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3087 { 3088 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3089 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3090 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3091 bssid[4] | bssid[5] << 8); 3092 } 3093 3094 static void 3095 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3096 { 3097 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3098 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3099 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3100 addr[4] | addr[5] << 8 | 0xff << 16); 3101 } 3102 3103 static void 3104 rt2860_updateslot(struct ieee80211com *ic) 3105 { 3106 struct rt2860_softc *sc = ic->ic_softc; 3107 uint32_t tmp; 3108 3109 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3110 tmp &= ~0xff; 3111 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3112 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3113 } 3114 3115 static void 3116 rt2860_updateprot(struct ifnet *ifp) 3117 { 3118 struct rt2860_softc *sc = ifp->if_softc; 3119 struct ieee80211com *ic = ifp->if_l2com; 3120 uint32_t tmp; 3121 3122 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3123 /* setup protection frame rate (MCS code) */ 3124 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3125 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3126 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3127 3128 /* CCK frames don't require protection */ 3129 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3130 3131 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3132 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3133 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3134 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3135 tmp |= RT2860_PROT_CTRL_CTS; 3136 } 3137 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3138 } 3139 3140 static void 3141 rt2860_update_promisc(struct ieee80211com *ic) 3142 { 3143 struct rt2860_softc *sc = ic->ic_softc; 3144 uint32_t tmp; 3145 3146 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3147 tmp &= ~RT2860_DROP_NOT_MYBSS; 3148 if (!(ic->ic_ifp->if_flags & IFF_PROMISC)) 3149 tmp |= RT2860_DROP_NOT_MYBSS; 3150 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3151 } 3152 3153 static int 3154 rt2860_updateedca(struct ieee80211com *ic) 3155 { 3156 struct rt2860_softc *sc = ic->ic_ifp->if_softc; 3157 const struct wmeParams *wmep; 3158 int aci; 3159 3160 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 3161 3162 /* update MAC TX configuration registers */ 3163 for (aci = 0; aci < WME_NUM_AC; aci++) { 3164 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3165 wmep[aci].wmep_logcwmax << 16 | 3166 wmep[aci].wmep_logcwmin << 12 | 3167 wmep[aci].wmep_aifsn << 8 | 3168 wmep[aci].wmep_txopLimit); 3169 } 3170 3171 /* update SCH/DMA registers too */ 3172 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3173 wmep[WME_AC_VO].wmep_aifsn << 12 | 3174 wmep[WME_AC_VI].wmep_aifsn << 8 | 3175 wmep[WME_AC_BK].wmep_aifsn << 4 | 3176 wmep[WME_AC_BE].wmep_aifsn); 3177 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3178 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3179 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3180 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3181 wmep[WME_AC_BE].wmep_logcwmin); 3182 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3183 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3184 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3185 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3186 wmep[WME_AC_BE].wmep_logcwmax); 3187 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3188 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3189 wmep[WME_AC_BE].wmep_txopLimit); 3190 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3191 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3192 wmep[WME_AC_VI].wmep_txopLimit); 3193 3194 return 0; 3195 } 3196 3197 #ifdef HW_CRYPTO 3198 static int 3199 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3200 struct ieee80211_key *k) 3201 { 3202 struct rt2860_softc *sc = ic->ic_softc; 3203 bus_size_t base; 3204 uint32_t attr; 3205 uint8_t mode, wcid, iv[8]; 3206 3207 /* defer setting of WEP keys until interface is brought up */ 3208 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3209 (IFF_UP | IFF_RUNNING)) 3210 return 0; 3211 3212 /* map net80211 cipher to RT2860 security mode */ 3213 switch (k->k_cipher) { 3214 case IEEE80211_CIPHER_WEP40: 3215 mode = RT2860_MODE_WEP40; 3216 break; 3217 case IEEE80211_CIPHER_WEP104: 3218 mode = RT2860_MODE_WEP104; 3219 break; 3220 case IEEE80211_CIPHER_TKIP: 3221 mode = RT2860_MODE_TKIP; 3222 break; 3223 case IEEE80211_CIPHER_CCMP: 3224 mode = RT2860_MODE_AES_CCMP; 3225 break; 3226 default: 3227 return EINVAL; 3228 } 3229 3230 if (k->k_flags & IEEE80211_KEY_GROUP) { 3231 wcid = 0; /* NB: update WCID0 for group keys */ 3232 base = RT2860_SKEY(0, k->k_id); 3233 } else { 3234 wcid = ((struct rt2860_node *)ni)->wcid; 3235 base = RT2860_PKEY(wcid); 3236 } 3237 3238 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3239 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3240 #ifndef IEEE80211_STA_ONLY 3241 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3242 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3243 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3244 } else 3245 #endif 3246 { 3247 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3248 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3249 } 3250 } else 3251 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3252 3253 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3254 (k->k_flags & IEEE80211_KEY_TX)) { 3255 /* set initial packet number in IV+EIV */ 3256 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3257 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3258 uint32_t val = arc4random(); 3259 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3260 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3261 val += 0x000100; 3262 iv[0] = val; 3263 iv[1] = val >> 8; 3264 iv[2] = val >> 16; 3265 iv[3] = k->k_id << 6; 3266 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3267 } else { 3268 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3269 iv[0] = k->k_tsc >> 8; 3270 iv[1] = (iv[0] | 0x20) & 0x7f; 3271 iv[2] = k->k_tsc; 3272 } else /* CCMP */ { 3273 iv[0] = k->k_tsc; 3274 iv[1] = k->k_tsc >> 8; 3275 iv[2] = 0; 3276 } 3277 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3278 iv[4] = k->k_tsc >> 16; 3279 iv[5] = k->k_tsc >> 24; 3280 iv[6] = k->k_tsc >> 32; 3281 iv[7] = k->k_tsc >> 40; 3282 } 3283 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3284 } 3285 3286 if (k->k_flags & IEEE80211_KEY_GROUP) { 3287 /* install group key */ 3288 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3289 attr &= ~(0xf << (k->k_id * 4)); 3290 attr |= mode << (k->k_id * 4); 3291 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3292 } else { 3293 /* install pairwise key */ 3294 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3295 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3296 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3297 } 3298 return 0; 3299 } 3300 3301 static void 3302 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3303 struct ieee80211_key *k) 3304 { 3305 struct rt2860_softc *sc = ic->ic_softc; 3306 uint32_t attr; 3307 uint8_t wcid; 3308 3309 if (k->k_flags & IEEE80211_KEY_GROUP) { 3310 /* remove group key */ 3311 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3312 attr &= ~(0xf << (k->k_id * 4)); 3313 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3314 3315 } else { 3316 /* remove pairwise key */ 3317 wcid = ((struct rt2860_node *)ni)->wcid; 3318 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3319 attr &= ~0xf; 3320 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3321 } 3322 } 3323 #endif 3324 3325 static int8_t 3326 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3327 { 3328 struct ifnet *ifp = sc->sc_ifp; 3329 struct ieee80211com *ic = ifp->if_l2com; 3330 struct ieee80211_channel *c = ic->ic_curchan; 3331 int delta; 3332 3333 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3334 u_int chan = ieee80211_chan2ieee(ic, c); 3335 delta = sc->rssi_5ghz[rxchain]; 3336 3337 /* determine channel group */ 3338 if (chan <= 64) 3339 delta -= sc->lna[1]; 3340 else if (chan <= 128) 3341 delta -= sc->lna[2]; 3342 else 3343 delta -= sc->lna[3]; 3344 } else 3345 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3346 3347 return -12 - delta - rssi; 3348 } 3349 3350 /* 3351 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3352 * Used to adjust per-rate Tx power registers. 3353 */ 3354 static __inline uint32_t 3355 b4inc(uint32_t b32, int8_t delta) 3356 { 3357 int8_t i, b4; 3358 3359 for (i = 0; i < 8; i++) { 3360 b4 = b32 & 0xf; 3361 b4 += delta; 3362 if (b4 < 0) 3363 b4 = 0; 3364 else if (b4 > 0xf) 3365 b4 = 0xf; 3366 b32 = b32 >> 4 | b4 << 28; 3367 } 3368 return b32; 3369 } 3370 3371 static const char * 3372 rt2860_get_rf(uint8_t rev) 3373 { 3374 switch (rev) { 3375 case RT2860_RF_2820: return "RT2820"; 3376 case RT2860_RF_2850: return "RT2850"; 3377 case RT2860_RF_2720: return "RT2720"; 3378 case RT2860_RF_2750: return "RT2750"; 3379 case RT3070_RF_3020: return "RT3020"; 3380 case RT3070_RF_2020: return "RT2020"; 3381 case RT3070_RF_3021: return "RT3021"; 3382 case RT3070_RF_3022: return "RT3022"; 3383 case RT3070_RF_3052: return "RT3052"; 3384 case RT3070_RF_3320: return "RT3320"; 3385 case RT3070_RF_3053: return "RT3053"; 3386 case RT5390_RF_5390: return "RT5390"; 3387 default: return "unknown"; 3388 } 3389 } 3390 3391 static int 3392 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3393 { 3394 int8_t delta_2ghz, delta_5ghz; 3395 uint32_t tmp; 3396 uint16_t val; 3397 int ridx, ant, i; 3398 3399 /* check whether the ROM is eFUSE ROM or EEPROM */ 3400 sc->sc_srom_read = rt2860_eeprom_read_2; 3401 if (sc->mac_ver >= 0x3071) { 3402 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3403 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3404 if (tmp & RT3070_SEL_EFUSE) 3405 sc->sc_srom_read = rt3090_efuse_read_2; 3406 } 3407 3408 /* read EEPROM version */ 3409 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3410 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8)); 3411 3412 /* read MAC address */ 3413 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3414 macaddr[0] = val & 0xff; 3415 macaddr[1] = val >> 8; 3416 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3417 macaddr[2] = val & 0xff; 3418 macaddr[3] = val >> 8; 3419 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3420 macaddr[4] = val & 0xff; 3421 macaddr[5] = val >> 8; 3422 3423 /* read country code */ 3424 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3425 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3426 3427 /* read vendor BBP settings */ 3428 for (i = 0; i < 8; i++) { 3429 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3430 sc->bbp[i].val = val & 0xff; 3431 sc->bbp[i].reg = val >> 8; 3432 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3433 } 3434 if (sc->mac_ver >= 0x3071) { 3435 /* read vendor RF settings */ 3436 for (i = 0; i < 10; i++) { 3437 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3438 sc->rf[i].val = val & 0xff; 3439 sc->rf[i].reg = val >> 8; 3440 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3441 sc->rf[i].val)); 3442 } 3443 } 3444 3445 /* read RF frequency offset from EEPROM */ 3446 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3447 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3448 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3449 if ((val >> 8) != 0xff) { 3450 /* read LEDs operating mode */ 3451 sc->leds = val >> 8; 3452 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3453 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3454 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3455 } else { 3456 /* broken EEPROM, use default settings */ 3457 sc->leds = 0x01; 3458 sc->led[0] = 0x5555; 3459 sc->led[1] = 0x2221; 3460 sc->led[2] = 0xa9f8; 3461 } 3462 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3463 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3464 3465 /* read RF information */ 3466 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3467 if (val == 0xffff) { 3468 DPRINTF(("invalid EEPROM antenna info, using default\n")); 3469 if (sc->mac_ver >= 0x5390) { 3470 /* default to RF5390 */ 3471 sc->rf_rev = RT5390_RF_5390; 3472 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3473 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3474 } else if (sc->mac_ver == 0x3593) { 3475 /* default to RF3053 3T3R */ 3476 sc->rf_rev = RT3070_RF_3053; 3477 sc->ntxchains = 3; 3478 sc->nrxchains = 3; 3479 } else if (sc->mac_ver >= 0x3071) { 3480 /* default to RF3020 1T1R */ 3481 sc->rf_rev = RT3070_RF_3020; 3482 sc->ntxchains = 1; 3483 sc->nrxchains = 1; 3484 } else { 3485 /* default to RF2820 1T2R */ 3486 sc->rf_rev = RT2860_RF_2820; 3487 sc->ntxchains = 1; 3488 sc->nrxchains = 2; 3489 } 3490 } else { 3491 sc->rf_rev = (val >> 8) & 0xf; 3492 if (sc->mac_ver >= 0x5390) { 3493 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3494 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3495 } else { 3496 sc->ntxchains = (val >> 4) & 0xf; 3497 sc->nrxchains = val & 0xf; 3498 } 3499 } 3500 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3501 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3502 3503 /* check if RF supports automatic Tx access gain control */ 3504 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3505 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3506 /* check if driver should patch the DAC issue */ 3507 if ((val >> 8) != 0xff) 3508 sc->patch_dac = (val >> 15) & 1; 3509 if ((val & 0xff) != 0xff) { 3510 sc->ext_5ghz_lna = (val >> 3) & 1; 3511 sc->ext_2ghz_lna = (val >> 2) & 1; 3512 /* check if RF supports automatic Tx access gain control */ 3513 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3514 /* check if we have a hardware radio switch */ 3515 sc->rfswitch = val & 1; 3516 } 3517 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3518 /* read PCIe power save level */ 3519 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3520 if ((val & 0xff) != 0xff) { 3521 sc->pslevel = val & 0x3; 3522 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3523 if ((val & 0xff80) != 0x9280) 3524 sc->pslevel = MIN(sc->pslevel, 1); 3525 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3526 } 3527 } 3528 3529 /* read power settings for 2GHz channels */ 3530 for (i = 0; i < 14; i += 2) { 3531 val = rt2860_srom_read(sc, 3532 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3533 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3534 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3535 3536 if (sc->mac_ver != 0x5390) { 3537 val = rt2860_srom_read(sc, 3538 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3539 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3540 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3541 } 3542 } 3543 /* fix broken Tx power entries */ 3544 for (i = 0; i < 14; i++) { 3545 if (sc->txpow1[i] < 0 || 3546 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3547 sc->txpow1[i] = 5; 3548 if (sc->mac_ver != 0x5390) { 3549 if (sc->txpow2[i] < 0 || 3550 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3551 sc->txpow2[i] = 5; 3552 } 3553 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3554 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3555 } 3556 /* read power settings for 5GHz channels */ 3557 for (i = 0; i < 40; i += 2) { 3558 val = rt2860_srom_read(sc, 3559 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3560 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3561 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3562 3563 val = rt2860_srom_read(sc, 3564 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3565 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3566 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3567 } 3568 /* fix broken Tx power entries */ 3569 for (i = 0; i < 40; i++) { 3570 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3571 sc->txpow1[14 + i] = 5; 3572 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3573 sc->txpow2[14 + i] = 5; 3574 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3575 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3576 sc->txpow2[14 + i])); 3577 } 3578 3579 /* read Tx power compensation for each Tx rate */ 3580 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3581 delta_2ghz = delta_5ghz = 0; 3582 if ((val & 0xff) != 0xff && (val & 0x80)) { 3583 delta_2ghz = val & 0xf; 3584 if (!(val & 0x40)) /* negative number */ 3585 delta_2ghz = -delta_2ghz; 3586 } 3587 val >>= 8; 3588 if ((val & 0xff) != 0xff && (val & 0x80)) { 3589 delta_5ghz = val & 0xf; 3590 if (!(val & 0x40)) /* negative number */ 3591 delta_5ghz = -delta_5ghz; 3592 } 3593 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3594 delta_2ghz, delta_5ghz)); 3595 3596 for (ridx = 0; ridx < 5; ridx++) { 3597 uint32_t reg; 3598 3599 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3600 reg = val; 3601 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3602 reg |= (uint32_t)val << 16; 3603 3604 sc->txpow20mhz[ridx] = reg; 3605 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3606 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3607 3608 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3609 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3610 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3611 } 3612 3613 /* read factory-calibrated samples for temperature compensation */ 3614 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3615 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3616 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3617 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3618 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3619 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3620 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3621 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3622 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3623 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3624 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3625 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3626 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3627 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3628 sc->step_2ghz = val >> 8; 3629 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3630 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3631 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3632 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3633 sc->tssi_2ghz[8], sc->step_2ghz)); 3634 /* check that ref value is correct, otherwise disable calibration */ 3635 if (sc->tssi_2ghz[4] == 0xff) 3636 sc->calib_2ghz = 0; 3637 3638 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3639 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3640 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3641 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3642 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3643 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3644 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3645 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3646 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3647 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3648 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3649 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3650 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3651 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3652 sc->step_5ghz = val >> 8; 3653 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3654 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3655 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3656 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3657 sc->tssi_5ghz[8], sc->step_5ghz)); 3658 /* check that ref value is correct, otherwise disable calibration */ 3659 if (sc->tssi_5ghz[4] == 0xff) 3660 sc->calib_5ghz = 0; 3661 3662 /* read RSSI offsets and LNA gains from EEPROM */ 3663 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3664 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3665 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3666 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3667 if (sc->mac_ver >= 0x3071) { 3668 /* 3669 * On RT3090 chips (limited to 2 Rx chains), this ROM 3670 * field contains the Tx mixer gain for the 2GHz band. 3671 */ 3672 if ((val & 0xff) != 0xff) 3673 sc->txmixgain_2ghz = val & 0x7; 3674 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3675 } else 3676 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3677 sc->lna[2] = val >> 8; /* channel group 2 */ 3678 3679 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3680 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3681 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3682 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3683 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3684 sc->lna[3] = val >> 8; /* channel group 3 */ 3685 3686 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3687 if (sc->mac_ver >= 0x3071) 3688 sc->lna[0] = RT3090_DEF_LNA; 3689 else /* channel group 0 */ 3690 sc->lna[0] = val & 0xff; 3691 sc->lna[1] = val >> 8; /* channel group 1 */ 3692 3693 /* fix broken 5GHz LNA entries */ 3694 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3695 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3696 sc->lna[2] = sc->lna[1]; 3697 } 3698 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3699 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3700 sc->lna[3] = sc->lna[1]; 3701 } 3702 3703 /* fix broken RSSI offset entries */ 3704 for (ant = 0; ant < 3; ant++) { 3705 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3706 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3707 ant + 1, sc->rssi_2ghz[ant])); 3708 sc->rssi_2ghz[ant] = 0; 3709 } 3710 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3711 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3712 ant + 1, sc->rssi_5ghz[ant])); 3713 sc->rssi_5ghz[ant] = 0; 3714 } 3715 } 3716 3717 return 0; 3718 } 3719 3720 static int 3721 rt2860_bbp_init(struct rt2860_softc *sc) 3722 { 3723 int i, ntries; 3724 3725 /* wait for BBP to wake up */ 3726 for (ntries = 0; ntries < 20; ntries++) { 3727 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3728 if (bbp0 != 0 && bbp0 != 0xff) 3729 break; 3730 } 3731 if (ntries == 20) { 3732 device_printf(sc->sc_dev, 3733 "timeout waiting for BBP to wake up\n"); 3734 return (ETIMEDOUT); 3735 } 3736 3737 /* initialize BBP registers to default values */ 3738 if (sc->mac_ver >= 0x5390) 3739 rt5390_bbp_init(sc); 3740 else { 3741 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3742 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3743 rt2860_def_bbp[i].val); 3744 } 3745 } 3746 3747 /* fix BBP84 for RT2860E */ 3748 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3749 rt2860_mcu_bbp_write(sc, 84, 0x19); 3750 3751 if (sc->mac_ver >= 0x3071) { 3752 rt2860_mcu_bbp_write(sc, 79, 0x13); 3753 rt2860_mcu_bbp_write(sc, 80, 0x05); 3754 rt2860_mcu_bbp_write(sc, 81, 0x33); 3755 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3756 rt2860_mcu_bbp_write(sc, 69, 0x16); 3757 rt2860_mcu_bbp_write(sc, 73, 0x12); 3758 } 3759 3760 return 0; 3761 } 3762 3763 static void 3764 rt5390_bbp_init(struct rt2860_softc *sc) 3765 { 3766 uint8_t bbp; 3767 int i; 3768 3769 /* Apply maximum likelihood detection for 2 stream case. */ 3770 if (sc->nrxchains > 1) { 3771 bbp = rt2860_mcu_bbp_read(sc, 105); 3772 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3773 } 3774 3775 /* Avoid data lost and CRC error. */ 3776 bbp = rt2860_mcu_bbp_read(sc, 4); 3777 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3778 3779 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3780 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3781 rt5390_def_bbp[i].val); 3782 } 3783 3784 if (sc->mac_ver == 0x5392) { 3785 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3786 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3787 rt2860_mcu_bbp_write(sc, 98, 0x12); 3788 rt2860_mcu_bbp_write(sc, 106, 0x05); 3789 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3790 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3791 } 3792 3793 bbp = rt2860_mcu_bbp_read(sc, 152); 3794 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3795 3796 /* Disable hardware antenna diversity. */ 3797 if (sc->mac_ver == 0x5390) 3798 rt2860_mcu_bbp_write(sc, 154, 0); 3799 } 3800 3801 static int 3802 rt2860_txrx_enable(struct rt2860_softc *sc) 3803 { 3804 struct ifnet *ifp = sc->sc_ifp; 3805 struct ieee80211com *ic = ifp->if_l2com; 3806 uint32_t tmp; 3807 int ntries; 3808 3809 /* enable Tx/Rx DMA engine */ 3810 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3811 RAL_BARRIER_READ_WRITE(sc); 3812 for (ntries = 0; ntries < 200; ntries++) { 3813 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3814 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3815 break; 3816 DELAY(1000); 3817 } 3818 if (ntries == 200) { 3819 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3820 return ETIMEDOUT; 3821 } 3822 3823 DELAY(50); 3824 3825 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3826 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3827 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3828 3829 /* set Rx filter */ 3830 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3831 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3832 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3833 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3834 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3835 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3836 if (ic->ic_opmode == IEEE80211_M_STA) 3837 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3838 } 3839 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3840 3841 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3842 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3843 3844 return 0; 3845 } 3846 3847 static void 3848 rt2860_init(void *arg) 3849 { 3850 struct rt2860_softc *sc = arg; 3851 struct ifnet *ifp = sc->sc_ifp; 3852 struct ieee80211com *ic = ifp->if_l2com; 3853 3854 RAL_LOCK(sc); 3855 rt2860_init_locked(sc); 3856 RAL_UNLOCK(sc); 3857 3858 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3859 ieee80211_start_all(ic); 3860 } 3861 3862 static void 3863 rt2860_init_locked(struct rt2860_softc *sc) 3864 { 3865 struct ifnet *ifp = sc->sc_ifp; 3866 struct ieee80211com *ic = ifp->if_l2com; 3867 uint32_t tmp; 3868 uint8_t bbp1, bbp3; 3869 int i, qid, ridx, ntries, error; 3870 3871 RAL_LOCK_ASSERT(sc); 3872 3873 if (sc->rfswitch) { 3874 /* hardware has a radio switch on GPIO pin 2 */ 3875 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3876 device_printf(sc->sc_dev, 3877 "radio is disabled by hardware switch\n"); 3878 #ifdef notyet 3879 rt2860_stop_locked(sc); 3880 return; 3881 #endif 3882 } 3883 } 3884 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3885 3886 /* disable DMA */ 3887 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3888 tmp &= 0xff0; 3889 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3890 3891 /* PBF hardware reset */ 3892 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3893 RAL_BARRIER_WRITE(sc); 3894 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3895 3896 if ((error = rt2860_load_microcode(sc)) != 0) { 3897 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3898 rt2860_stop_locked(sc); 3899 return; 3900 } 3901 3902 rt2860_set_macaddr(sc, IF_LLADDR(ifp)); 3903 3904 /* init Tx power for all Tx rates (from EEPROM) */ 3905 for (ridx = 0; ridx < 5; ridx++) { 3906 if (sc->txpow20mhz[ridx] == 0xffffffff) 3907 continue; 3908 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3909 } 3910 3911 for (ntries = 0; ntries < 100; ntries++) { 3912 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3913 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3914 break; 3915 DELAY(1000); 3916 } 3917 if (ntries == 100) { 3918 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3919 rt2860_stop_locked(sc); 3920 return; 3921 } 3922 tmp &= 0xff0; 3923 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3924 3925 /* reset Rx ring and all 6 Tx rings */ 3926 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3927 3928 /* PBF hardware reset */ 3929 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3930 RAL_BARRIER_WRITE(sc); 3931 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3932 3933 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3934 3935 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3936 RAL_BARRIER_WRITE(sc); 3937 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3938 3939 for (i = 0; i < nitems(rt2860_def_mac); i++) 3940 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3941 if (sc->mac_ver >= 0x5390) 3942 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3943 else if (sc->mac_ver >= 0x3071) { 3944 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3945 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3946 4 << RT2860_DLY_PAPE_EN_SHIFT); 3947 } 3948 3949 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3950 sc->sc_flags |= RT2860_PCIE; 3951 /* PCIe has different clock cycle count than PCI */ 3952 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3953 tmp = (tmp & ~0xff) | 0x7d; 3954 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3955 } 3956 3957 /* wait while MAC is busy */ 3958 for (ntries = 0; ntries < 100; ntries++) { 3959 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3960 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3961 break; 3962 DELAY(1000); 3963 } 3964 if (ntries == 100) { 3965 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3966 rt2860_stop_locked(sc); 3967 return; 3968 } 3969 3970 /* clear Host to MCU mailbox */ 3971 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3972 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3973 3974 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3975 DELAY(1000); 3976 3977 if ((error = rt2860_bbp_init(sc)) != 0) { 3978 rt2860_stop_locked(sc); 3979 return; 3980 } 3981 3982 /* clear RX WCID search table */ 3983 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3984 /* clear pairwise key table */ 3985 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3986 /* clear IV/EIV table */ 3987 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3988 /* clear WCID attribute table */ 3989 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3990 /* clear shared key table */ 3991 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3992 /* clear shared key mode */ 3993 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3994 3995 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3996 for (qid = 0; qid < 6; qid++) { 3997 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3998 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3999 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 4000 } 4001 4002 /* init Rx ring */ 4003 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 4004 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 4005 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 4006 4007 /* setup maximum buffer sizes */ 4008 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 4009 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 4010 4011 for (ntries = 0; ntries < 100; ntries++) { 4012 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 4013 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 4014 break; 4015 DELAY(1000); 4016 } 4017 if (ntries == 100) { 4018 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 4019 rt2860_stop_locked(sc); 4020 return; 4021 } 4022 tmp &= 0xff0; 4023 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 4024 4025 /* disable interrupts mitigation */ 4026 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 4027 4028 /* write vendor-specific BBP values (from EEPROM) */ 4029 for (i = 0; i < 8; i++) { 4030 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 4031 continue; 4032 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 4033 } 4034 4035 /* select Main antenna for 1T1R devices */ 4036 if (sc->rf_rev == RT3070_RF_2020 || 4037 sc->rf_rev == RT3070_RF_3020 || 4038 sc->rf_rev == RT3070_RF_3320 || 4039 sc->mac_ver == 0x5390) 4040 rt3090_set_rx_antenna(sc, 0); 4041 4042 /* send LEDs operating mode to microcontroller */ 4043 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 4044 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 4045 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 4046 4047 if (sc->mac_ver >= 0x5390) 4048 rt5390_rf_init(sc); 4049 else if (sc->mac_ver >= 0x3071) { 4050 if ((error = rt3090_rf_init(sc)) != 0) { 4051 rt2860_stop_locked(sc); 4052 return; 4053 } 4054 } 4055 4056 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 4057 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 4058 4059 if (sc->mac_ver >= 0x5390) 4060 rt5390_rf_wakeup(sc); 4061 else if (sc->mac_ver >= 0x3071) 4062 rt3090_rf_wakeup(sc); 4063 4064 /* disable non-existing Rx chains */ 4065 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4066 bbp3 &= ~(1 << 3 | 1 << 4); 4067 if (sc->nrxchains == 2) 4068 bbp3 |= 1 << 3; 4069 else if (sc->nrxchains == 3) 4070 bbp3 |= 1 << 4; 4071 rt2860_mcu_bbp_write(sc, 3, bbp3); 4072 4073 /* disable non-existing Tx chains */ 4074 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4075 if (sc->ntxchains == 1) 4076 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4077 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4078 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4079 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4080 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4081 rt2860_mcu_bbp_write(sc, 1, bbp1); 4082 4083 if (sc->mac_ver >= 0x3071) 4084 rt3090_rf_setup(sc); 4085 4086 /* select default channel */ 4087 rt2860_switch_chan(sc, ic->ic_curchan); 4088 4089 /* reset RF from MCU */ 4090 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4091 4092 /* set RTS threshold */ 4093 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4094 tmp &= ~0xffff00; 4095 tmp |= IEEE80211_RTS_DEFAULT << 8; 4096 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4097 4098 /* setup initial protection mode */ 4099 rt2860_updateprot(ifp); 4100 4101 /* turn radio LED on */ 4102 rt2860_set_leds(sc, RT2860_LED_RADIO); 4103 4104 /* enable Tx/Rx DMA engine */ 4105 if ((error = rt2860_txrx_enable(sc)) != 0) { 4106 rt2860_stop_locked(sc); 4107 return; 4108 } 4109 4110 /* clear pending interrupts */ 4111 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4112 /* enable interrupts */ 4113 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4114 4115 if (sc->sc_flags & RT2860_ADVANCED_PS) 4116 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4117 4118 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4119 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4120 4121 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4122 } 4123 4124 static void 4125 rt2860_stop(void *arg) 4126 { 4127 struct rt2860_softc *sc = arg; 4128 4129 RAL_LOCK(sc); 4130 rt2860_stop_locked(sc); 4131 RAL_UNLOCK(sc); 4132 } 4133 4134 static void 4135 rt2860_stop_locked(struct rt2860_softc *sc) 4136 { 4137 struct ifnet *ifp = sc->sc_ifp; 4138 uint32_t tmp; 4139 int qid; 4140 4141 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4142 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4143 4144 callout_stop(&sc->watchdog_ch); 4145 sc->sc_tx_timer = 0; 4146 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4147 4148 /* disable interrupts */ 4149 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4150 4151 /* disable GP timer */ 4152 rt2860_set_gp_timer(sc, 0); 4153 4154 /* disable Rx */ 4155 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4156 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4157 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4158 4159 /* reset adapter */ 4160 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4161 RAL_BARRIER_WRITE(sc); 4162 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4163 4164 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4165 sc->qfullmsk = 0; 4166 for (qid = 0; qid < 6; qid++) 4167 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4168 rt2860_reset_rx_ring(sc, &sc->rxq); 4169 } 4170 4171 int 4172 rt2860_load_microcode(struct rt2860_softc *sc) 4173 { 4174 const struct firmware *fp; 4175 int ntries, error; 4176 4177 RAL_LOCK_ASSERT(sc); 4178 4179 RAL_UNLOCK(sc); 4180 fp = firmware_get("rt2860fw"); 4181 RAL_LOCK(sc); 4182 if (fp == NULL) { 4183 device_printf(sc->sc_dev, 4184 "unable to receive rt2860fw firmware image\n"); 4185 return EINVAL; 4186 } 4187 4188 /* set "host program ram write selection" bit */ 4189 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4190 /* write microcode image */ 4191 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4192 /* kick microcontroller unit */ 4193 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4194 RAL_BARRIER_WRITE(sc); 4195 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4196 4197 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4198 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4199 4200 /* wait until microcontroller is ready */ 4201 RAL_BARRIER_READ_WRITE(sc); 4202 for (ntries = 0; ntries < 1000; ntries++) { 4203 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4204 break; 4205 DELAY(1000); 4206 } 4207 if (ntries == 1000) { 4208 device_printf(sc->sc_dev, 4209 "timeout waiting for MCU to initialize\n"); 4210 error = ETIMEDOUT; 4211 } else 4212 error = 0; 4213 4214 firmware_put(fp, FIRMWARE_UNLOAD); 4215 return error; 4216 } 4217 4218 /* 4219 * This function is called periodically to adjust Tx power based on 4220 * temperature variation. 4221 */ 4222 #ifdef NOT_YET 4223 static void 4224 rt2860_calib(struct rt2860_softc *sc) 4225 { 4226 struct ieee80211com *ic = &sc->sc_ic; 4227 const uint8_t *tssi; 4228 uint8_t step, bbp49; 4229 int8_t ridx, d; 4230 4231 /* read current temperature */ 4232 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4233 4234 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4235 tssi = &sc->tssi_2ghz[4]; 4236 step = sc->step_2ghz; 4237 } else { 4238 tssi = &sc->tssi_5ghz[4]; 4239 step = sc->step_5ghz; 4240 } 4241 4242 if (bbp49 < tssi[0]) { /* lower than reference */ 4243 /* use higher Tx power than default */ 4244 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4245 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4246 /* use lower Tx power than default */ 4247 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4248 } else { 4249 /* use default Tx power */ 4250 d = 0; 4251 } 4252 d *= step; 4253 4254 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4255 4256 /* write adjusted Tx power values for each Tx rate */ 4257 for (ridx = 0; ridx < 5; ridx++) { 4258 if (sc->txpow20mhz[ridx] == 0xffffffff) 4259 continue; 4260 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4261 b4inc(sc->txpow20mhz[ridx], d)); 4262 } 4263 } 4264 #endif 4265 4266 static void 4267 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4268 { 4269 uint32_t tmp; 4270 4271 if (aux) { 4272 if (sc->mac_ver == 0x5390) { 4273 rt2860_mcu_bbp_write(sc, 152, 4274 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4275 } else { 4276 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4277 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4278 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4279 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4280 } 4281 } else { 4282 if (sc->mac_ver == 0x5390) { 4283 rt2860_mcu_bbp_write(sc, 152, 4284 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4285 } else { 4286 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4287 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4288 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4289 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4290 } 4291 } 4292 } 4293 4294 static void 4295 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4296 { 4297 struct ifnet *ifp = sc->sc_ifp; 4298 struct ieee80211com *ic = ifp->if_l2com; 4299 u_int chan, group; 4300 4301 chan = ieee80211_chan2ieee(ic, c); 4302 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4303 return; 4304 4305 if (sc->mac_ver >= 0x5390) 4306 rt5390_set_chan(sc, chan); 4307 else if (sc->mac_ver >= 0x3071) 4308 rt3090_set_chan(sc, chan); 4309 else 4310 rt2860_set_chan(sc, chan); 4311 4312 /* determine channel group */ 4313 if (chan <= 14) 4314 group = 0; 4315 else if (chan <= 64) 4316 group = 1; 4317 else if (chan <= 128) 4318 group = 2; 4319 else 4320 group = 3; 4321 4322 /* XXX necessary only when group has changed! */ 4323 if (sc->mac_ver < 0x5390) 4324 rt2860_select_chan_group(sc, group); 4325 4326 DELAY(1000); 4327 } 4328 4329 static int 4330 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4331 { 4332 struct ieee80211com *ic = vap->iv_ic; 4333 struct ieee80211_beacon_offsets bo; 4334 struct rt2860_txwi txwi; 4335 struct mbuf *m; 4336 int ridx; 4337 4338 if ((m = ieee80211_beacon_alloc(vap->iv_bss, &bo)) == NULL) 4339 return ENOBUFS; 4340 4341 memset(&txwi, 0, sizeof txwi); 4342 txwi.wcid = 0xff; 4343 txwi.len = htole16(m->m_pkthdr.len); 4344 /* send beacons at the lowest available rate */ 4345 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4346 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4347 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4348 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4349 txwi.phy |= htole16(RT2860_PHY_OFDM); 4350 txwi.txop = RT2860_TX_TXOP_HT; 4351 txwi.flags = RT2860_TX_TS; 4352 txwi.xflags = RT2860_TX_NSEQ; 4353 4354 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4355 (uint8_t *)&txwi, sizeof txwi); 4356 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4357 mtod(m, uint8_t *), m->m_pkthdr.len); 4358 4359 m_freem(m); 4360 4361 return 0; 4362 } 4363 4364 static void 4365 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4366 { 4367 struct ifnet *ifp = sc->sc_ifp; 4368 struct ieee80211com *ic = ifp->if_l2com; 4369 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4370 uint32_t tmp; 4371 4372 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4373 4374 tmp &= ~0x1fffff; 4375 tmp |= vap->iv_bss->ni_intval * 16; 4376 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4377 if (vap->iv_opmode == IEEE80211_M_STA) { 4378 /* 4379 * Local TSF is always updated with remote TSF on beacon 4380 * reception. 4381 */ 4382 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4383 } 4384 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4385 vap->iv_opmode == IEEE80211_M_MBSS) { 4386 tmp |= RT2860_BCN_TX_EN; 4387 /* 4388 * Local TSF is updated with remote TSF on beacon reception 4389 * only if the remote TSF is greater than local TSF. 4390 */ 4391 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4392 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4393 tmp |= RT2860_BCN_TX_EN; 4394 /* SYNC with nobody */ 4395 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4396 } 4397 4398 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4399 } 4400