1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 /*- 22 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 23 * http://www.ralinktech.com/ 24 */ 25 26 #include <sys/param.h> 27 #include <sys/sysctl.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/firmware.h> 40 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_radiotap.h> 56 #include <net80211/ieee80211_regdomain.h> 57 #include <net80211/ieee80211_ratectl.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_ether.h> 64 65 #include <dev/ral/rt2860reg.h> 66 #include <dev/ral/rt2860var.h> 67 68 #define RAL_DEBUG 69 #ifdef RAL_DEBUG 70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n, x) 75 #endif 76 77 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 78 const char [IFNAMSIZ], int, enum ieee80211_opmode, 79 int, const uint8_t [IEEE80211_ADDR_LEN], 80 const uint8_t [IEEE80211_ADDR_LEN]); 81 static void rt2860_vap_delete(struct ieee80211vap *); 82 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 83 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 84 struct rt2860_tx_ring *); 85 static void rt2860_reset_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_free_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 90 static void rt2860_free_tx_pool(struct rt2860_softc *); 91 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 92 struct rt2860_rx_ring *); 93 static void rt2860_reset_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_free_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_updatestats(struct rt2860_softc *); 98 static void rt2860_newassoc(struct ieee80211_node *, int); 99 static void rt2860_node_free(struct ieee80211_node *); 100 #ifdef IEEE80211_HT 101 static int rt2860_ampdu_rx_start(struct ieee80211com *, 102 struct ieee80211_node *, uint8_t); 103 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 #endif 106 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 107 int); 108 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 109 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 110 static void rt2860_intr_coherent(struct rt2860_softc *); 111 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 112 static void rt2860_tx_intr(struct rt2860_softc *, int); 113 static void rt2860_rx_intr(struct rt2860_softc *); 114 static void rt2860_tbtt_intr(struct rt2860_softc *); 115 static void rt2860_gp_intr(struct rt2860_softc *); 116 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 117 struct ieee80211_node *); 118 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 119 const struct ieee80211_bpf_params *); 120 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 121 struct ieee80211_node *, 122 const struct ieee80211_bpf_params *params); 123 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 124 static void rt2860_start(struct rt2860_softc *); 125 static void rt2860_watchdog(void *); 126 static void rt2860_parent(struct ieee80211com *); 127 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 128 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 129 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 130 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 131 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 132 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 133 static void rt2860_enable_mrr(struct rt2860_softc *); 134 static void rt2860_set_txpreamble(struct rt2860_softc *); 135 static void rt2860_set_basicrates(struct rt2860_softc *, 136 const struct ieee80211_rateset *); 137 static void rt2860_scan_start(struct ieee80211com *); 138 static void rt2860_scan_end(struct ieee80211com *); 139 static void rt2860_getradiocaps(struct ieee80211com *, int, int *, 140 struct ieee80211_channel[]); 141 static void rt2860_set_channel(struct ieee80211com *); 142 static void rt2860_select_chan_group(struct rt2860_softc *, int); 143 static void rt2860_set_chan(struct rt2860_softc *, u_int); 144 static void rt3090_set_chan(struct rt2860_softc *, u_int); 145 static void rt5390_set_chan(struct rt2860_softc *, u_int); 146 static int rt3090_rf_init(struct rt2860_softc *); 147 static void rt5390_rf_init(struct rt2860_softc *); 148 static void rt3090_rf_wakeup(struct rt2860_softc *); 149 static void rt5390_rf_wakeup(struct rt2860_softc *); 150 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 151 uint8_t *); 152 static void rt3090_rf_setup(struct rt2860_softc *); 153 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 154 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 155 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 156 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 157 static void rt2860_update_promisc(struct ieee80211com *); 158 static void rt2860_updateslot(struct ieee80211com *); 159 static void rt2860_updateprot(struct rt2860_softc *); 160 static int rt2860_updateedca(struct ieee80211com *); 161 #ifdef HW_CRYPTO 162 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 163 struct ieee80211_key *); 164 static void rt2860_delete_key(struct ieee80211com *, 165 struct ieee80211_node *, struct ieee80211_key *); 166 #endif 167 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 168 static const char *rt2860_get_rf(uint16_t); 169 static int rt2860_read_eeprom(struct rt2860_softc *, 170 uint8_t macaddr[IEEE80211_ADDR_LEN]); 171 static int rt2860_bbp_init(struct rt2860_softc *); 172 static void rt5390_bbp_init(struct rt2860_softc *); 173 static int rt2860_txrx_enable(struct rt2860_softc *); 174 static void rt2860_init(void *); 175 static void rt2860_init_locked(struct rt2860_softc *); 176 static void rt2860_stop(void *); 177 static void rt2860_stop_locked(struct rt2860_softc *); 178 static int rt2860_load_microcode(struct rt2860_softc *); 179 #ifdef NOT_YET 180 static void rt2860_calib(struct rt2860_softc *); 181 #endif 182 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 183 static void rt2860_switch_chan(struct rt2860_softc *, 184 struct ieee80211_channel *); 185 static int rt2860_setup_beacon(struct rt2860_softc *, 186 struct ieee80211vap *); 187 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 188 189 static const struct { 190 uint32_t reg; 191 uint32_t val; 192 } rt2860_def_mac[] = { 193 RT2860_DEF_MAC 194 }; 195 196 static const struct { 197 uint8_t reg; 198 uint8_t val; 199 } rt2860_def_bbp[] = { 200 RT2860_DEF_BBP 201 }, rt5390_def_bbp[] = { 202 RT5390_DEF_BBP 203 }; 204 205 static const struct rfprog { 206 uint8_t chan; 207 uint32_t r1, r2, r3, r4; 208 } rt2860_rf2850[] = { 209 RT2860_RF2850 210 }; 211 212 struct { 213 uint8_t n, r, k; 214 } rt3090_freqs[] = { 215 RT3070_RF3052 216 }; 217 218 static const struct { 219 uint8_t reg; 220 uint8_t val; 221 } rt3090_def_rf[] = { 222 RT3070_DEF_RF 223 }, rt5390_def_rf[] = { 224 RT5390_DEF_RF 225 }, rt5392_def_rf[] = { 226 RT5392_DEF_RF 227 }; 228 229 static const uint8_t rt2860_chan_5ghz[] = 230 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 231 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 232 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 }; 233 234 int 235 rt2860_attach(device_t dev, int id) 236 { 237 struct rt2860_softc *sc = device_get_softc(dev); 238 struct ieee80211com *ic = &sc->sc_ic; 239 uint32_t tmp; 240 int error, ntries, qid; 241 242 sc->sc_dev = dev; 243 sc->sc_debug = 0; 244 245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 246 MTX_DEF | MTX_RECURSE); 247 248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 249 mbufq_init(&sc->sc_snd, ifqmaxlen); 250 251 /* wait for NIC to initialize */ 252 for (ntries = 0; ntries < 100; ntries++) { 253 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 254 if (tmp != 0 && tmp != 0xffffffff) 255 break; 256 DELAY(10); 257 } 258 if (ntries == 100) { 259 device_printf(sc->sc_dev, 260 "timeout waiting for NIC to initialize\n"); 261 error = EIO; 262 goto fail1; 263 } 264 sc->mac_ver = tmp >> 16; 265 sc->mac_rev = tmp & 0xffff; 266 267 if (sc->mac_ver != 0x2860 && 268 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 269 sc->sc_flags |= RT2860_ADVANCED_PS; 270 271 /* retrieve RF rev. no and various other things from EEPROM */ 272 rt2860_read_eeprom(sc, ic->ic_macaddr); 273 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 274 "RF %s (MIMO %dT%dR), address %6D\n", 275 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 276 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 277 278 /* 279 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 280 */ 281 for (qid = 0; qid < 6; qid++) { 282 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 283 device_printf(sc->sc_dev, 284 "could not allocate Tx ring %d\n", qid); 285 goto fail2; 286 } 287 } 288 289 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 290 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 291 goto fail2; 292 } 293 294 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 295 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 296 goto fail3; 297 } 298 299 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 300 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 301 WME_AC_VO : 5; 302 303 ic->ic_softc = sc; 304 ic->ic_name = device_get_nameunit(dev); 305 ic->ic_opmode = IEEE80211_M_STA; 306 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 307 308 /* set device capabilities */ 309 ic->ic_caps = 310 IEEE80211_C_STA /* station mode */ 311 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 312 | IEEE80211_C_HOSTAP /* hostap mode */ 313 | IEEE80211_C_MONITOR /* monitor mode */ 314 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 315 | IEEE80211_C_WDS /* 4-address traffic works */ 316 | IEEE80211_C_MBSS /* mesh point link mode */ 317 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 318 | IEEE80211_C_SHSLOT /* short slot time supported */ 319 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 320 #if 0 321 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 322 #endif 323 | IEEE80211_C_WME /* 802.11e */ 324 ; 325 326 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 327 ic->ic_channels); 328 329 ieee80211_ifattach(ic); 330 331 ic->ic_wme.wme_update = rt2860_updateedca; 332 ic->ic_scan_start = rt2860_scan_start; 333 ic->ic_scan_end = rt2860_scan_end; 334 ic->ic_getradiocaps = rt2860_getradiocaps; 335 ic->ic_set_channel = rt2860_set_channel; 336 ic->ic_updateslot = rt2860_updateslot; 337 ic->ic_update_promisc = rt2860_update_promisc; 338 ic->ic_raw_xmit = rt2860_raw_xmit; 339 sc->sc_node_free = ic->ic_node_free; 340 ic->ic_node_free = rt2860_node_free; 341 ic->ic_newassoc = rt2860_newassoc; 342 ic->ic_transmit = rt2860_transmit; 343 ic->ic_parent = rt2860_parent; 344 ic->ic_vap_create = rt2860_vap_create; 345 ic->ic_vap_delete = rt2860_vap_delete; 346 347 ieee80211_radiotap_attach(ic, 348 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 349 RT2860_TX_RADIOTAP_PRESENT, 350 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 351 RT2860_RX_RADIOTAP_PRESENT); 352 353 #ifdef RAL_DEBUG 354 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 355 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 356 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 357 #endif 358 if (bootverbose) 359 ieee80211_announce(ic); 360 361 return 0; 362 363 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 364 fail2: while (--qid >= 0) 365 rt2860_free_tx_ring(sc, &sc->txq[qid]); 366 fail1: mtx_destroy(&sc->sc_mtx); 367 return error; 368 } 369 370 int 371 rt2860_detach(void *xsc) 372 { 373 struct rt2860_softc *sc = xsc; 374 struct ieee80211com *ic = &sc->sc_ic; 375 int qid; 376 377 RAL_LOCK(sc); 378 rt2860_stop_locked(sc); 379 RAL_UNLOCK(sc); 380 381 ieee80211_ifdetach(ic); 382 mbufq_drain(&sc->sc_snd); 383 for (qid = 0; qid < 6; qid++) 384 rt2860_free_tx_ring(sc, &sc->txq[qid]); 385 rt2860_free_rx_ring(sc, &sc->rxq); 386 rt2860_free_tx_pool(sc); 387 388 mtx_destroy(&sc->sc_mtx); 389 390 return 0; 391 } 392 393 void 394 rt2860_shutdown(void *xsc) 395 { 396 struct rt2860_softc *sc = xsc; 397 398 rt2860_stop(sc); 399 } 400 401 void 402 rt2860_suspend(void *xsc) 403 { 404 struct rt2860_softc *sc = xsc; 405 406 rt2860_stop(sc); 407 } 408 409 void 410 rt2860_resume(void *xsc) 411 { 412 struct rt2860_softc *sc = xsc; 413 414 if (sc->sc_ic.ic_nrunning > 0) 415 rt2860_init(sc); 416 } 417 418 static struct ieee80211vap * 419 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 420 enum ieee80211_opmode opmode, int flags, 421 const uint8_t bssid[IEEE80211_ADDR_LEN], 422 const uint8_t mac[IEEE80211_ADDR_LEN]) 423 { 424 struct rt2860_softc *sc = ic->ic_softc; 425 struct rt2860_vap *rvp; 426 struct ieee80211vap *vap; 427 428 switch (opmode) { 429 case IEEE80211_M_STA: 430 case IEEE80211_M_IBSS: 431 case IEEE80211_M_AHDEMO: 432 case IEEE80211_M_MONITOR: 433 case IEEE80211_M_HOSTAP: 434 case IEEE80211_M_MBSS: 435 /* XXXRP: TBD */ 436 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 437 device_printf(sc->sc_dev, "only 1 vap supported\n"); 438 return NULL; 439 } 440 if (opmode == IEEE80211_M_STA) 441 flags |= IEEE80211_CLONE_NOBEACONS; 442 break; 443 case IEEE80211_M_WDS: 444 if (TAILQ_EMPTY(&ic->ic_vaps) || 445 ic->ic_opmode != IEEE80211_M_HOSTAP) { 446 device_printf(sc->sc_dev, 447 "wds only supported in ap mode\n"); 448 return NULL; 449 } 450 /* 451 * Silently remove any request for a unique 452 * bssid; WDS vap's always share the local 453 * mac address. 454 */ 455 flags &= ~IEEE80211_CLONE_BSSID; 456 break; 457 default: 458 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 459 return NULL; 460 } 461 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 462 vap = &rvp->ral_vap; 463 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 464 465 /* override state transition machine */ 466 rvp->ral_newstate = vap->iv_newstate; 467 vap->iv_newstate = rt2860_newstate; 468 #if 0 469 vap->iv_update_beacon = rt2860_beacon_update; 470 #endif 471 472 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 473 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 474 475 ieee80211_ratectl_init(vap); 476 /* complete setup */ 477 ieee80211_vap_attach(vap, ieee80211_media_change, 478 ieee80211_media_status, mac); 479 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 480 ic->ic_opmode = opmode; 481 return vap; 482 } 483 484 static void 485 rt2860_vap_delete(struct ieee80211vap *vap) 486 { 487 struct rt2860_vap *rvp = RT2860_VAP(vap); 488 489 ieee80211_ratectl_deinit(vap); 490 ieee80211_vap_detach(vap); 491 free(rvp, M_80211_VAP); 492 } 493 494 static void 495 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 496 { 497 if (error != 0) 498 return; 499 500 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 501 502 *(bus_addr_t *)arg = segs[0].ds_addr; 503 } 504 505 static int 506 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 507 { 508 int size, error; 509 510 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 511 512 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 513 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 514 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 517 goto fail; 518 } 519 520 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 521 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 522 if (error != 0) { 523 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 524 goto fail; 525 } 526 527 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 528 size, rt2860_dma_map_addr, &ring->paddr, 0); 529 if (error != 0) { 530 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 531 goto fail; 532 } 533 534 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 535 536 return 0; 537 538 fail: rt2860_free_tx_ring(sc, ring); 539 return error; 540 } 541 542 void 543 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 544 { 545 struct rt2860_tx_data *data; 546 int i; 547 548 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 549 if ((data = ring->data[i]) == NULL) 550 continue; /* nothing mapped in this slot */ 551 552 if (data->m != NULL) { 553 bus_dmamap_sync(sc->txwi_dmat, data->map, 554 BUS_DMASYNC_POSTWRITE); 555 bus_dmamap_unload(sc->txwi_dmat, data->map); 556 m_freem(data->m); 557 data->m = NULL; 558 } 559 if (data->ni != NULL) { 560 ieee80211_free_node(data->ni); 561 data->ni = NULL; 562 } 563 564 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 565 ring->data[i] = NULL; 566 } 567 568 ring->queued = 0; 569 ring->cur = ring->next = 0; 570 } 571 572 void 573 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 574 { 575 struct rt2860_tx_data *data; 576 int i; 577 578 if (ring->txd != NULL) { 579 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 580 BUS_DMASYNC_POSTWRITE); 581 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 582 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 583 } 584 if (ring->desc_dmat != NULL) 585 bus_dma_tag_destroy(ring->desc_dmat); 586 587 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 588 if ((data = ring->data[i]) == NULL) 589 continue; /* nothing mapped in this slot */ 590 591 if (data->m != NULL) { 592 bus_dmamap_sync(sc->txwi_dmat, data->map, 593 BUS_DMASYNC_POSTWRITE); 594 bus_dmamap_unload(sc->txwi_dmat, data->map); 595 m_freem(data->m); 596 } 597 if (data->ni != NULL) 598 ieee80211_free_node(data->ni); 599 600 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 601 } 602 } 603 604 /* 605 * Allocate a pool of TX Wireless Information blocks. 606 */ 607 int 608 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 609 { 610 caddr_t vaddr; 611 bus_addr_t paddr; 612 int i, size, error; 613 614 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 615 616 /* init data_pool early in case of failure.. */ 617 SLIST_INIT(&sc->data_pool); 618 619 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 620 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 621 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 622 if (error != 0) { 623 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 624 goto fail; 625 } 626 627 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 628 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 629 if (error != 0) { 630 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 631 goto fail; 632 } 633 634 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 635 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 636 if (error != 0) { 637 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 638 goto fail; 639 } 640 641 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 642 643 vaddr = sc->txwi_vaddr; 644 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 645 struct rt2860_tx_data *data = &sc->data[i]; 646 647 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 648 if (error != 0) { 649 device_printf(sc->sc_dev, "could not create DMA map\n"); 650 goto fail; 651 } 652 data->txwi = (struct rt2860_txwi *)vaddr; 653 data->paddr = paddr; 654 vaddr += RT2860_TXWI_DMASZ; 655 paddr += RT2860_TXWI_DMASZ; 656 657 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 658 } 659 660 return 0; 661 662 fail: rt2860_free_tx_pool(sc); 663 return error; 664 } 665 666 void 667 rt2860_free_tx_pool(struct rt2860_softc *sc) 668 { 669 if (sc->txwi_vaddr != NULL) { 670 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 671 BUS_DMASYNC_POSTWRITE); 672 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 673 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 674 } 675 if (sc->txwi_dmat != NULL) 676 bus_dma_tag_destroy(sc->txwi_dmat); 677 678 while (!SLIST_EMPTY(&sc->data_pool)) { 679 struct rt2860_tx_data *data; 680 data = SLIST_FIRST(&sc->data_pool); 681 bus_dmamap_destroy(sc->txwi_dmat, data->map); 682 SLIST_REMOVE_HEAD(&sc->data_pool, next); 683 } 684 } 685 686 int 687 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 688 { 689 bus_addr_t physaddr; 690 int i, size, error; 691 692 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 693 694 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 695 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 696 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 697 if (error != 0) { 698 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 699 goto fail; 700 } 701 702 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 703 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 704 if (error != 0) { 705 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 706 goto fail; 707 } 708 709 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 710 size, rt2860_dma_map_addr, &ring->paddr, 0); 711 if (error != 0) { 712 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 713 goto fail; 714 } 715 716 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 717 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 718 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 719 if (error != 0) { 720 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 721 goto fail; 722 } 723 724 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 725 struct rt2860_rx_data *data = &ring->data[i]; 726 struct rt2860_rxd *rxd = &ring->rxd[i]; 727 728 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 729 if (error != 0) { 730 device_printf(sc->sc_dev, "could not create DMA map\n"); 731 goto fail; 732 } 733 734 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 735 if (data->m == NULL) { 736 device_printf(sc->sc_dev, 737 "could not allocate rx mbuf\n"); 738 error = ENOMEM; 739 goto fail; 740 } 741 742 error = bus_dmamap_load(ring->data_dmat, data->map, 743 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 744 &physaddr, 0); 745 if (error != 0) { 746 device_printf(sc->sc_dev, 747 "could not load rx buf DMA map"); 748 goto fail; 749 } 750 751 rxd->sdp0 = htole32(physaddr); 752 rxd->sdl0 = htole16(MCLBYTES); 753 } 754 755 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 756 757 return 0; 758 759 fail: rt2860_free_rx_ring(sc, ring); 760 return error; 761 } 762 763 void 764 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 765 { 766 int i; 767 768 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 769 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 770 771 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 772 773 ring->cur = 0; 774 } 775 776 void 777 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 778 { 779 int i; 780 781 if (ring->rxd != NULL) { 782 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 783 BUS_DMASYNC_POSTWRITE); 784 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 785 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 786 } 787 if (ring->desc_dmat != NULL) 788 bus_dma_tag_destroy(ring->desc_dmat); 789 790 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 791 struct rt2860_rx_data *data = &ring->data[i]; 792 793 if (data->m != NULL) { 794 bus_dmamap_sync(ring->data_dmat, data->map, 795 BUS_DMASYNC_POSTREAD); 796 bus_dmamap_unload(ring->data_dmat, data->map); 797 m_freem(data->m); 798 } 799 if (data->map != NULL) 800 bus_dmamap_destroy(ring->data_dmat, data->map); 801 } 802 if (ring->data_dmat != NULL) 803 bus_dma_tag_destroy(ring->data_dmat); 804 } 805 806 static void 807 rt2860_updatestats(struct rt2860_softc *sc) 808 { 809 struct ieee80211com *ic = &sc->sc_ic; 810 811 /* 812 * In IBSS or HostAP modes (when the hardware sends beacons), the 813 * MAC can run into a livelock and start sending CTS-to-self frames 814 * like crazy if protection is enabled. Fortunately, we can detect 815 * when such a situation occurs and reset the MAC. 816 */ 817 if (ic->ic_curmode != IEEE80211_M_STA) { 818 /* check if we're in a livelock situation.. */ 819 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 820 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 821 /* ..and reset MAC/BBP for a while.. */ 822 DPRINTF(("CTS-to-self livelock detected\n")); 823 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 824 RAL_BARRIER_WRITE(sc); 825 DELAY(1); 826 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 827 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 828 } 829 } 830 } 831 832 static void 833 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 834 { 835 struct ieee80211com *ic = ni->ni_ic; 836 struct rt2860_softc *sc = ic->ic_softc; 837 uint8_t wcid; 838 839 wcid = IEEE80211_AID(ni->ni_associd); 840 if (isnew && ni->ni_associd != 0) { 841 sc->wcid2ni[wcid] = ni; 842 843 /* init WCID table entry */ 844 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 845 ni->ni_macaddr, IEEE80211_ADDR_LEN); 846 } 847 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 848 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 849 } 850 851 static void 852 rt2860_node_free(struct ieee80211_node *ni) 853 { 854 struct ieee80211com *ic = ni->ni_ic; 855 struct rt2860_softc *sc = ic->ic_softc; 856 uint8_t wcid; 857 858 if (ni->ni_associd != 0) { 859 wcid = IEEE80211_AID(ni->ni_associd); 860 861 /* clear Rx WCID search table entry */ 862 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 863 } 864 sc->sc_node_free(ni); 865 } 866 867 #ifdef IEEE80211_HT 868 static int 869 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 870 uint8_t tid) 871 { 872 struct rt2860_softc *sc = ic->ic_softc; 873 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 874 uint32_t tmp; 875 876 /* update BA session mask */ 877 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 878 tmp |= (1 << tid) << 16; 879 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 880 return 0; 881 } 882 883 static void 884 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 885 uint8_t tid) 886 { 887 struct rt2860_softc *sc = ic->ic_softc; 888 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 889 uint32_t tmp; 890 891 /* update BA session mask */ 892 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 893 tmp &= ~((1 << tid) << 16); 894 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 895 } 896 #endif 897 898 static int 899 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 900 { 901 struct rt2860_vap *rvp = RT2860_VAP(vap); 902 struct ieee80211com *ic = vap->iv_ic; 903 struct rt2860_softc *sc = ic->ic_softc; 904 uint32_t tmp; 905 int error; 906 907 if (vap->iv_state == IEEE80211_S_RUN) { 908 /* turn link LED off */ 909 rt2860_set_leds(sc, RT2860_LED_RADIO); 910 } 911 912 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 913 /* abort TSF synchronization */ 914 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 915 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 916 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 917 RT2860_TBTT_TIMER_EN)); 918 } 919 920 rt2860_set_gp_timer(sc, 0); 921 922 error = rvp->ral_newstate(vap, nstate, arg); 923 if (error != 0) 924 return (error); 925 926 if (nstate == IEEE80211_S_RUN) { 927 struct ieee80211_node *ni = vap->iv_bss; 928 929 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 930 rt2860_enable_mrr(sc); 931 rt2860_set_txpreamble(sc); 932 rt2860_set_basicrates(sc, &ni->ni_rates); 933 rt2860_set_bssid(sc, ni->ni_bssid); 934 } 935 936 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 937 vap->iv_opmode == IEEE80211_M_IBSS || 938 vap->iv_opmode == IEEE80211_M_MBSS) { 939 error = rt2860_setup_beacon(sc, vap); 940 if (error != 0) 941 return error; 942 } 943 944 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 945 rt2860_enable_tsf_sync(sc); 946 rt2860_set_gp_timer(sc, 500); 947 } 948 949 /* turn link LED on */ 950 rt2860_set_leds(sc, RT2860_LED_RADIO | 951 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 952 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 953 } 954 return error; 955 } 956 957 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 958 static uint16_t 959 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 960 { 961 uint32_t tmp; 962 uint16_t reg; 963 int ntries; 964 965 addr *= 2; 966 /*- 967 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 968 * DATA0: F E D C 969 * DATA1: B A 9 8 970 * DATA2: 7 6 5 4 971 * DATA3: 3 2 1 0 972 */ 973 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 974 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 975 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 976 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 977 for (ntries = 0; ntries < 500; ntries++) { 978 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 979 if (!(tmp & RT3070_EFSROM_KICK)) 980 break; 981 DELAY(2); 982 } 983 if (ntries == 500) 984 return 0xffff; 985 986 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 987 return 0xffff; /* address not found */ 988 989 /* determine to which 32-bit register our 16-bit word belongs */ 990 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 991 tmp = RAL_READ(sc, reg); 992 993 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 994 } 995 996 /* 997 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 998 * 93C66 or 93C86). 999 */ 1000 static uint16_t 1001 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1002 { 1003 uint32_t tmp; 1004 uint16_t val; 1005 int n; 1006 1007 /* clock C once before the first command */ 1008 RT2860_EEPROM_CTL(sc, 0); 1009 1010 RT2860_EEPROM_CTL(sc, RT2860_S); 1011 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1012 RT2860_EEPROM_CTL(sc, RT2860_S); 1013 1014 /* write start bit (1) */ 1015 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1016 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1017 1018 /* write READ opcode (10) */ 1019 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1020 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1021 RT2860_EEPROM_CTL(sc, RT2860_S); 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1023 1024 /* write address (A5-A0 or A7-A0) */ 1025 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1026 for (; n >= 0; n--) { 1027 RT2860_EEPROM_CTL(sc, RT2860_S | 1028 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1029 RT2860_EEPROM_CTL(sc, RT2860_S | 1030 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1031 } 1032 1033 RT2860_EEPROM_CTL(sc, RT2860_S); 1034 1035 /* read data Q15-Q0 */ 1036 val = 0; 1037 for (n = 15; n >= 0; n--) { 1038 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1039 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1040 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1041 RT2860_EEPROM_CTL(sc, RT2860_S); 1042 } 1043 1044 RT2860_EEPROM_CTL(sc, 0); 1045 1046 /* clear Chip Select and clock C */ 1047 RT2860_EEPROM_CTL(sc, RT2860_S); 1048 RT2860_EEPROM_CTL(sc, 0); 1049 RT2860_EEPROM_CTL(sc, RT2860_C); 1050 1051 return val; 1052 } 1053 1054 static __inline uint16_t 1055 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1056 { 1057 /* either eFUSE ROM or EEPROM */ 1058 return sc->sc_srom_read(sc, addr); 1059 } 1060 1061 static void 1062 rt2860_intr_coherent(struct rt2860_softc *sc) 1063 { 1064 uint32_t tmp; 1065 1066 /* DMA finds data coherent event when checking the DDONE bit */ 1067 1068 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1069 1070 /* restart DMA engine */ 1071 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1072 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1073 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1074 1075 (void)rt2860_txrx_enable(sc); 1076 } 1077 1078 static void 1079 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1080 { 1081 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 1082 struct ieee80211_node *ni; 1083 uint32_t stat; 1084 uint8_t wcid, mcs, pid; 1085 1086 /* drain Tx status FIFO (maxsize = 16) */ 1087 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 1088 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1089 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1090 1091 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1092 if (wcid > RT2860_WCID_MAX) 1093 continue; 1094 ni = sc->wcid2ni[wcid]; 1095 1096 /* if no ACK was requested, no feedback is available */ 1097 if (!(stat & RT2860_TXQ_ACKREQ) || ni == NULL) 1098 continue; 1099 1100 /* update per-STA AMRR stats */ 1101 if (stat & RT2860_TXQ_OK) { 1102 /* 1103 * Check if there were retries, ie if the Tx success 1104 * rate is different from the requested rate. Note 1105 * that it works only because we do not allow rate 1106 * fallback from OFDM to CCK. 1107 */ 1108 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1109 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1110 if (mcs + 1 != pid) 1111 txs->long_retries = 1; 1112 else 1113 txs->long_retries = 0; 1114 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 1115 ieee80211_ratectl_tx_complete(ni, txs); 1116 } else { 1117 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 1118 txs->long_retries = 1; /* XXX */ 1119 ieee80211_ratectl_tx_complete(ni, txs); 1120 if_inc_counter(ni->ni_vap->iv_ifp, 1121 IFCOUNTER_OERRORS, 1); 1122 } 1123 } 1124 } 1125 1126 static void 1127 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1128 { 1129 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1130 uint32_t hw; 1131 1132 rt2860_drain_stats_fifo(sc); 1133 1134 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1135 while (ring->next != hw) { 1136 struct rt2860_tx_data *data = ring->data[ring->next]; 1137 1138 if (data != NULL) { 1139 bus_dmamap_sync(sc->txwi_dmat, data->map, 1140 BUS_DMASYNC_POSTWRITE); 1141 bus_dmamap_unload(sc->txwi_dmat, data->map); 1142 ieee80211_tx_complete(data->ni, data->m, 0); 1143 data->ni = NULL; 1144 data->m = NULL; 1145 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1146 ring->data[ring->next] = NULL; 1147 } 1148 ring->queued--; 1149 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1150 } 1151 1152 sc->sc_tx_timer = 0; 1153 if (ring->queued < RT2860_TX_RING_COUNT) 1154 sc->qfullmsk &= ~(1 << qid); 1155 rt2860_start(sc); 1156 } 1157 1158 /* 1159 * Return the Rx chain with the highest RSSI for a given frame. 1160 */ 1161 static __inline uint8_t 1162 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1163 { 1164 uint8_t rxchain = 0; 1165 1166 if (sc->nrxchains > 1) { 1167 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1168 rxchain = 1; 1169 if (sc->nrxchains > 2) 1170 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1171 rxchain = 2; 1172 } 1173 return rxchain; 1174 } 1175 1176 static void 1177 rt2860_rx_intr(struct rt2860_softc *sc) 1178 { 1179 struct rt2860_rx_radiotap_header *tap; 1180 struct ieee80211com *ic = &sc->sc_ic; 1181 struct ieee80211_frame *wh; 1182 struct ieee80211_node *ni; 1183 struct mbuf *m, *m1; 1184 bus_addr_t physaddr; 1185 uint32_t hw; 1186 uint16_t phy; 1187 uint8_t ant; 1188 int8_t rssi, nf; 1189 int error; 1190 1191 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1192 while (sc->rxq.cur != hw) { 1193 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1194 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1195 struct rt2860_rxwi *rxwi; 1196 1197 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1198 BUS_DMASYNC_POSTREAD); 1199 1200 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1201 DPRINTF(("RXD DDONE bit not set!\n")); 1202 break; /* should not happen */ 1203 } 1204 1205 if (__predict_false(rxd->flags & 1206 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1207 counter_u64_add(ic->ic_ierrors, 1); 1208 goto skip; 1209 } 1210 1211 #ifdef HW_CRYPTO 1212 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1213 /* report MIC failures to net80211 for TKIP */ 1214 ic->ic_stats.is_rx_locmicfail++; 1215 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1216 counter_u64_add(ic->ic_ierrors, 1); 1217 goto skip; 1218 } 1219 #endif 1220 1221 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1222 if (__predict_false(m1 == NULL)) { 1223 counter_u64_add(ic->ic_ierrors, 1); 1224 goto skip; 1225 } 1226 1227 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1228 BUS_DMASYNC_POSTREAD); 1229 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1230 1231 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1232 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1233 &physaddr, 0); 1234 if (__predict_false(error != 0)) { 1235 m_freem(m1); 1236 1237 /* try to reload the old mbuf */ 1238 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1239 mtod(data->m, void *), MCLBYTES, 1240 rt2860_dma_map_addr, &physaddr, 0); 1241 if (__predict_false(error != 0)) { 1242 panic("%s: could not load old rx mbuf", 1243 device_get_name(sc->sc_dev)); 1244 } 1245 /* physical address may have changed */ 1246 rxd->sdp0 = htole32(physaddr); 1247 counter_u64_add(ic->ic_ierrors, 1); 1248 goto skip; 1249 } 1250 1251 /* 1252 * New mbuf successfully loaded, update Rx ring and continue 1253 * processing. 1254 */ 1255 m = data->m; 1256 data->m = m1; 1257 rxd->sdp0 = htole32(physaddr); 1258 1259 rxwi = mtod(m, struct rt2860_rxwi *); 1260 1261 /* finalize mbuf */ 1262 m->m_data = (caddr_t)(rxwi + 1); 1263 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1264 1265 wh = mtod(m, struct ieee80211_frame *); 1266 #ifdef HW_CRYPTO 1267 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1268 /* frame is decrypted by hardware */ 1269 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1270 } 1271 #endif 1272 1273 /* HW may insert 2 padding bytes after 802.11 header */ 1274 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1275 u_int hdrlen = ieee80211_hdrsize(wh); 1276 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1277 m->m_data += 2; 1278 wh = mtod(m, struct ieee80211_frame *); 1279 } 1280 1281 ant = rt2860_maxrssi_chain(sc, rxwi); 1282 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1283 nf = RT2860_NOISE_FLOOR; 1284 1285 if (ieee80211_radiotap_active(ic)) { 1286 tap = &sc->sc_rxtap; 1287 tap->wr_flags = 0; 1288 tap->wr_antenna = ant; 1289 tap->wr_antsignal = nf + rssi; 1290 tap->wr_antnoise = nf; 1291 /* in case it can't be found below */ 1292 tap->wr_rate = 2; 1293 phy = le16toh(rxwi->phy); 1294 switch (phy & RT2860_PHY_MODE) { 1295 case RT2860_PHY_CCK: 1296 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1297 case 0: tap->wr_rate = 2; break; 1298 case 1: tap->wr_rate = 4; break; 1299 case 2: tap->wr_rate = 11; break; 1300 case 3: tap->wr_rate = 22; break; 1301 } 1302 if (phy & RT2860_PHY_SHPRE) 1303 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1304 break; 1305 case RT2860_PHY_OFDM: 1306 switch (phy & RT2860_PHY_MCS) { 1307 case 0: tap->wr_rate = 12; break; 1308 case 1: tap->wr_rate = 18; break; 1309 case 2: tap->wr_rate = 24; break; 1310 case 3: tap->wr_rate = 36; break; 1311 case 4: tap->wr_rate = 48; break; 1312 case 5: tap->wr_rate = 72; break; 1313 case 6: tap->wr_rate = 96; break; 1314 case 7: tap->wr_rate = 108; break; 1315 } 1316 break; 1317 } 1318 } 1319 1320 RAL_UNLOCK(sc); 1321 wh = mtod(m, struct ieee80211_frame *); 1322 1323 /* send the frame to the 802.11 layer */ 1324 ni = ieee80211_find_rxnode(ic, 1325 (struct ieee80211_frame_min *)wh); 1326 if (ni != NULL) { 1327 (void)ieee80211_input(ni, m, rssi - nf, nf); 1328 ieee80211_free_node(ni); 1329 } else 1330 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1331 1332 RAL_LOCK(sc); 1333 1334 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1335 1336 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1337 BUS_DMASYNC_PREWRITE); 1338 1339 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1340 } 1341 1342 /* tell HW what we have processed */ 1343 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1344 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1345 } 1346 1347 static void 1348 rt2860_tbtt_intr(struct rt2860_softc *sc) 1349 { 1350 #if 0 1351 struct ieee80211com *ic = &sc->sc_ic; 1352 1353 #ifndef IEEE80211_STA_ONLY 1354 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1355 /* one less beacon until next DTIM */ 1356 if (ic->ic_dtim_count == 0) 1357 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1358 else 1359 ic->ic_dtim_count--; 1360 1361 /* update dynamic parts of beacon */ 1362 rt2860_setup_beacon(sc); 1363 1364 /* flush buffered multicast frames */ 1365 if (ic->ic_dtim_count == 0) 1366 ieee80211_notify_dtim(ic); 1367 } 1368 #endif 1369 /* check if protection mode has changed */ 1370 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1371 rt2860_updateprot(sc); 1372 sc->sc_ic_flags = ic->ic_flags; 1373 } 1374 #endif 1375 } 1376 1377 static void 1378 rt2860_gp_intr(struct rt2860_softc *sc) 1379 { 1380 struct ieee80211com *ic = &sc->sc_ic; 1381 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1382 1383 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1384 1385 if (vap->iv_state == IEEE80211_S_RUN) 1386 rt2860_updatestats(sc); 1387 } 1388 1389 void 1390 rt2860_intr(void *arg) 1391 { 1392 struct rt2860_softc *sc = arg; 1393 uint32_t r; 1394 1395 RAL_LOCK(sc); 1396 1397 r = RAL_READ(sc, RT2860_INT_STATUS); 1398 if (__predict_false(r == 0xffffffff)) { 1399 RAL_UNLOCK(sc); 1400 return; /* device likely went away */ 1401 } 1402 if (r == 0) { 1403 RAL_UNLOCK(sc); 1404 return; /* not for us */ 1405 } 1406 1407 /* acknowledge interrupts */ 1408 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1409 1410 if (r & RT2860_TX_RX_COHERENT) 1411 rt2860_intr_coherent(sc); 1412 1413 if (r & RT2860_MAC_INT_2) /* TX status */ 1414 rt2860_drain_stats_fifo(sc); 1415 1416 if (r & RT2860_TX_DONE_INT5) 1417 rt2860_tx_intr(sc, 5); 1418 1419 if (r & RT2860_RX_DONE_INT) 1420 rt2860_rx_intr(sc); 1421 1422 if (r & RT2860_TX_DONE_INT4) 1423 rt2860_tx_intr(sc, 4); 1424 1425 if (r & RT2860_TX_DONE_INT3) 1426 rt2860_tx_intr(sc, 3); 1427 1428 if (r & RT2860_TX_DONE_INT2) 1429 rt2860_tx_intr(sc, 2); 1430 1431 if (r & RT2860_TX_DONE_INT1) 1432 rt2860_tx_intr(sc, 1); 1433 1434 if (r & RT2860_TX_DONE_INT0) 1435 rt2860_tx_intr(sc, 0); 1436 1437 if (r & RT2860_MAC_INT_0) /* TBTT */ 1438 rt2860_tbtt_intr(sc); 1439 1440 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1441 /* TBD wakeup */; 1442 1443 if (r & RT2860_MAC_INT_4) /* GP timer */ 1444 rt2860_gp_intr(sc); 1445 1446 RAL_UNLOCK(sc); 1447 } 1448 1449 static int 1450 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1451 { 1452 struct ieee80211com *ic = &sc->sc_ic; 1453 struct ieee80211vap *vap = ni->ni_vap; 1454 struct rt2860_tx_ring *ring; 1455 struct rt2860_tx_data *data; 1456 struct rt2860_txd *txd; 1457 struct rt2860_txwi *txwi; 1458 struct ieee80211_frame *wh; 1459 const struct ieee80211_txparam *tp = ni->ni_txparms; 1460 struct ieee80211_key *k; 1461 struct mbuf *m1; 1462 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1463 bus_dma_segment_t *seg; 1464 u_int hdrlen; 1465 uint16_t qos, dur; 1466 uint8_t type, qsel, mcs, pid, qid; 1467 int i, nsegs, ntxds, pad, rate, ridx, error; 1468 1469 /* the data pool contains at least one element, pick the first */ 1470 data = SLIST_FIRST(&sc->data_pool); 1471 1472 wh = mtod(m, struct ieee80211_frame *); 1473 1474 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1475 k = ieee80211_crypto_encap(ni, m); 1476 if (k == NULL) { 1477 m_freem(m); 1478 return ENOBUFS; 1479 } 1480 1481 /* packet header may have moved, reset our local pointer */ 1482 wh = mtod(m, struct ieee80211_frame *); 1483 } 1484 1485 hdrlen = ieee80211_anyhdrsize(wh); 1486 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1487 1488 if (m->m_flags & M_EAPOL) { 1489 rate = tp->mgmtrate; 1490 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1491 rate = tp->mcastrate; 1492 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1493 rate = tp->ucastrate; 1494 } else { 1495 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1496 rate = ni->ni_txrate; 1497 } 1498 rate &= IEEE80211_RATE_VAL; 1499 1500 qid = M_WME_GETAC(m); 1501 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1502 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1503 } else { 1504 qos = 0; 1505 } 1506 ring = &sc->txq[qid]; 1507 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1508 1509 /* get MCS code from rate index */ 1510 mcs = rt2860_rates[ridx].mcs; 1511 1512 /* setup TX Wireless Information */ 1513 txwi = data->txwi; 1514 txwi->flags = 0; 1515 /* let HW generate seq numbers for non-QoS frames */ 1516 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1517 if (type == IEEE80211_FC0_TYPE_DATA) 1518 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1519 else 1520 txwi->wcid = 0xff; 1521 txwi->len = htole16(m->m_pkthdr.len); 1522 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1523 txwi->phy = htole16(RT2860_PHY_CCK); 1524 if (ridx != RT2860_RIDX_CCK1 && 1525 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1526 mcs |= RT2860_PHY_SHPRE; 1527 } else 1528 txwi->phy = htole16(RT2860_PHY_OFDM); 1529 txwi->phy |= htole16(mcs); 1530 1531 /* 1532 * We store the MCS code into the driver-private PacketID field. 1533 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1534 * that we know at which initial rate the frame was transmitted. 1535 * We add 1 to the MCS code because setting the PacketID field to 1536 * 0 means that we don't want feedback in TX_STAT_FIFO. 1537 */ 1538 pid = (mcs + 1) & 0xf; 1539 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1540 1541 /* check if RTS/CTS or CTS-to-self protection is required */ 1542 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1543 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1544 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1545 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1546 txwi->txop = RT2860_TX_TXOP_HT; 1547 else 1548 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1549 1550 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1551 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1552 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1553 txwi->xflags |= RT2860_TX_ACK; 1554 1555 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1556 dur = rt2860_rates[ridx].sp_ack_dur; 1557 else 1558 dur = rt2860_rates[ridx].lp_ack_dur; 1559 *(uint16_t *)wh->i_dur = htole16(dur); 1560 } 1561 /* ask MAC to insert timestamp into probe responses */ 1562 if (IEEE80211_IS_MGMT_PROBE_RESP(wh)) 1563 /* NOTE: beacons do not pass through tx_data() */ 1564 txwi->flags |= RT2860_TX_TS; 1565 1566 if (ieee80211_radiotap_active_vap(vap)) { 1567 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1568 1569 tap->wt_flags = 0; 1570 tap->wt_rate = rate; 1571 if (mcs & RT2860_PHY_SHPRE) 1572 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1573 1574 ieee80211_radiotap_tx(vap, m); 1575 } 1576 1577 pad = (hdrlen + 3) & ~3; 1578 1579 /* copy and trim 802.11 header */ 1580 memcpy(txwi + 1, wh, hdrlen); 1581 m_adj(m, hdrlen); 1582 1583 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1584 &nsegs, 0); 1585 if (__predict_false(error != 0 && error != EFBIG)) { 1586 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1587 error); 1588 m_freem(m); 1589 return error; 1590 } 1591 if (__predict_true(error == 0)) { 1592 /* determine how many TXDs are required */ 1593 ntxds = 1 + (nsegs / 2); 1594 1595 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1596 /* not enough free TXDs, force mbuf defrag */ 1597 bus_dmamap_unload(sc->txwi_dmat, data->map); 1598 error = EFBIG; 1599 } 1600 } 1601 if (__predict_false(error != 0)) { 1602 m1 = m_defrag(m, M_NOWAIT); 1603 if (m1 == NULL) { 1604 device_printf(sc->sc_dev, 1605 "could not defragment mbuf\n"); 1606 m_freem(m); 1607 return ENOBUFS; 1608 } 1609 m = m1; 1610 1611 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1612 segs, &nsegs, 0); 1613 if (__predict_false(error != 0)) { 1614 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1615 error); 1616 m_freem(m); 1617 return error; 1618 } 1619 1620 /* determine how many TXDs are now required */ 1621 ntxds = 1 + (nsegs / 2); 1622 1623 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1624 /* this is a hopeless case, drop the mbuf! */ 1625 bus_dmamap_unload(sc->txwi_dmat, data->map); 1626 m_freem(m); 1627 return ENOBUFS; 1628 } 1629 } 1630 1631 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1632 1633 /* first segment is TXWI + 802.11 header */ 1634 txd = &ring->txd[ring->cur]; 1635 txd->sdp0 = htole32(data->paddr); 1636 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1637 txd->flags = qsel; 1638 1639 /* setup payload segments */ 1640 seg = &segs[0]; 1641 for (i = nsegs; i >= 2; i -= 2) { 1642 txd->sdp1 = htole32(seg->ds_addr); 1643 txd->sdl1 = htole16(seg->ds_len); 1644 seg++; 1645 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1646 /* grab a new Tx descriptor */ 1647 txd = &ring->txd[ring->cur]; 1648 txd->sdp0 = htole32(seg->ds_addr); 1649 txd->sdl0 = htole16(seg->ds_len); 1650 txd->flags = qsel; 1651 seg++; 1652 } 1653 /* finalize last segment */ 1654 if (i > 0) { 1655 txd->sdp1 = htole32(seg->ds_addr); 1656 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1657 } else { 1658 txd->sdl0 |= htole16(RT2860_TX_LS0); 1659 txd->sdl1 = 0; 1660 } 1661 1662 /* remove from the free pool and link it into the SW Tx slot */ 1663 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1664 data->m = m; 1665 data->ni = ni; 1666 ring->data[ring->cur] = data; 1667 1668 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1669 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1670 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1671 1672 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1673 qid, txwi->wcid, nsegs, ridx)); 1674 1675 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1676 ring->queued += ntxds; 1677 if (ring->queued >= RT2860_TX_RING_COUNT) 1678 sc->qfullmsk |= 1 << qid; 1679 1680 /* kick Tx */ 1681 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1682 1683 return 0; 1684 } 1685 1686 static int 1687 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1688 const struct ieee80211_bpf_params *params) 1689 { 1690 struct ieee80211com *ic = ni->ni_ic; 1691 struct rt2860_softc *sc = ic->ic_softc; 1692 int error; 1693 1694 RAL_LOCK(sc); 1695 1696 /* prevent management frames from being sent if we're not ready */ 1697 if (!(sc->sc_flags & RT2860_RUNNING)) { 1698 RAL_UNLOCK(sc); 1699 m_freem(m); 1700 return ENETDOWN; 1701 } 1702 if (params == NULL) { 1703 /* 1704 * Legacy path; interpret frame contents to decide 1705 * precisely how to send the frame. 1706 */ 1707 error = rt2860_tx(sc, m, ni); 1708 } else { 1709 /* 1710 * Caller supplied explicit parameters to use in 1711 * sending the frame. 1712 */ 1713 error = rt2860_tx_raw(sc, m, ni, params); 1714 } 1715 sc->sc_tx_timer = 5; 1716 RAL_UNLOCK(sc); 1717 return error; 1718 } 1719 1720 static int 1721 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1722 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1723 { 1724 struct ieee80211com *ic = &sc->sc_ic; 1725 struct ieee80211vap *vap = ni->ni_vap; 1726 struct rt2860_tx_ring *ring; 1727 struct rt2860_tx_data *data; 1728 struct rt2860_txd *txd; 1729 struct rt2860_txwi *txwi; 1730 struct ieee80211_frame *wh; 1731 struct mbuf *m1; 1732 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1733 bus_dma_segment_t *seg; 1734 u_int hdrlen; 1735 uint16_t dur; 1736 uint8_t qsel, mcs, pid, qid; 1737 int i, nsegs, ntxds, pad, rate, ridx, error; 1738 1739 /* the data pool contains at least one element, pick the first */ 1740 data = SLIST_FIRST(&sc->data_pool); 1741 1742 wh = mtod(m, struct ieee80211_frame *); 1743 hdrlen = ieee80211_hdrsize(wh); 1744 1745 /* Choose a TX rate index. */ 1746 rate = params->ibp_rate0; 1747 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1748 rate & IEEE80211_RATE_VAL); 1749 if (ridx == (uint8_t)-1) { 1750 /* XXX fall back to mcast/mgmt rate? */ 1751 m_freem(m); 1752 return EINVAL; 1753 } 1754 1755 qid = params->ibp_pri & 3; 1756 ring = &sc->txq[qid]; 1757 1758 /* get MCS code from rate index */ 1759 mcs = rt2860_rates[ridx].mcs; 1760 1761 /* setup TX Wireless Information */ 1762 txwi = data->txwi; 1763 txwi->flags = 0; 1764 /* let HW generate seq numbers for non-QoS frames */ 1765 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1766 txwi->wcid = 0xff; 1767 txwi->len = htole16(m->m_pkthdr.len); 1768 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1769 txwi->phy = htole16(RT2860_PHY_CCK); 1770 if (ridx != RT2860_RIDX_CCK1 && 1771 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1772 mcs |= RT2860_PHY_SHPRE; 1773 } else 1774 txwi->phy = htole16(RT2860_PHY_OFDM); 1775 txwi->phy |= htole16(mcs); 1776 1777 /* 1778 * We store the MCS code into the driver-private PacketID field. 1779 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1780 * that we know at which initial rate the frame was transmitted. 1781 * We add 1 to the MCS code because setting the PacketID field to 1782 * 0 means that we don't want feedback in TX_STAT_FIFO. 1783 */ 1784 pid = (mcs + 1) & 0xf; 1785 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1786 1787 /* check if RTS/CTS or CTS-to-self protection is required */ 1788 if (params->ibp_flags & IEEE80211_BPF_RTS || 1789 params->ibp_flags & IEEE80211_BPF_CTS) 1790 txwi->txop = RT2860_TX_TXOP_HT; 1791 else 1792 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1793 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1794 txwi->xflags |= RT2860_TX_ACK; 1795 1796 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1797 dur = rt2860_rates[ridx].sp_ack_dur; 1798 else 1799 dur = rt2860_rates[ridx].lp_ack_dur; 1800 *(uint16_t *)wh->i_dur = htole16(dur); 1801 } 1802 /* ask MAC to insert timestamp into probe responses */ 1803 if (IEEE80211_IS_MGMT_PROBE_RESP(wh)) 1804 /* NOTE: beacons do not pass through tx_data() */ 1805 txwi->flags |= RT2860_TX_TS; 1806 1807 if (ieee80211_radiotap_active_vap(vap)) { 1808 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1809 1810 tap->wt_flags = 0; 1811 tap->wt_rate = rate; 1812 if (mcs & RT2860_PHY_SHPRE) 1813 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1814 1815 ieee80211_radiotap_tx(vap, m); 1816 } 1817 1818 pad = (hdrlen + 3) & ~3; 1819 1820 /* copy and trim 802.11 header */ 1821 memcpy(txwi + 1, wh, hdrlen); 1822 m_adj(m, hdrlen); 1823 1824 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1825 &nsegs, 0); 1826 if (__predict_false(error != 0 && error != EFBIG)) { 1827 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1828 error); 1829 m_freem(m); 1830 return error; 1831 } 1832 if (__predict_true(error == 0)) { 1833 /* determine how many TXDs are required */ 1834 ntxds = 1 + (nsegs / 2); 1835 1836 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1837 /* not enough free TXDs, force mbuf defrag */ 1838 bus_dmamap_unload(sc->txwi_dmat, data->map); 1839 error = EFBIG; 1840 } 1841 } 1842 if (__predict_false(error != 0)) { 1843 m1 = m_defrag(m, M_NOWAIT); 1844 if (m1 == NULL) { 1845 device_printf(sc->sc_dev, 1846 "could not defragment mbuf\n"); 1847 m_freem(m); 1848 return ENOBUFS; 1849 } 1850 m = m1; 1851 1852 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1853 segs, &nsegs, 0); 1854 if (__predict_false(error != 0)) { 1855 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1856 error); 1857 m_freem(m); 1858 return error; 1859 } 1860 1861 /* determine how many TXDs are now required */ 1862 ntxds = 1 + (nsegs / 2); 1863 1864 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1865 /* this is a hopeless case, drop the mbuf! */ 1866 bus_dmamap_unload(sc->txwi_dmat, data->map); 1867 m_freem(m); 1868 return ENOBUFS; 1869 } 1870 } 1871 1872 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1873 1874 /* first segment is TXWI + 802.11 header */ 1875 txd = &ring->txd[ring->cur]; 1876 txd->sdp0 = htole32(data->paddr); 1877 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1878 txd->flags = qsel; 1879 1880 /* setup payload segments */ 1881 seg = &segs[0]; 1882 for (i = nsegs; i >= 2; i -= 2) { 1883 txd->sdp1 = htole32(seg->ds_addr); 1884 txd->sdl1 = htole16(seg->ds_len); 1885 seg++; 1886 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1887 /* grab a new Tx descriptor */ 1888 txd = &ring->txd[ring->cur]; 1889 txd->sdp0 = htole32(seg->ds_addr); 1890 txd->sdl0 = htole16(seg->ds_len); 1891 txd->flags = qsel; 1892 seg++; 1893 } 1894 /* finalize last segment */ 1895 if (i > 0) { 1896 txd->sdp1 = htole32(seg->ds_addr); 1897 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1898 } else { 1899 txd->sdl0 |= htole16(RT2860_TX_LS0); 1900 txd->sdl1 = 0; 1901 } 1902 1903 /* remove from the free pool and link it into the SW Tx slot */ 1904 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1905 data->m = m; 1906 data->ni = ni; 1907 ring->data[ring->cur] = data; 1908 1909 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1910 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1911 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1912 1913 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1914 qid, txwi->wcid, nsegs, ridx)); 1915 1916 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1917 ring->queued += ntxds; 1918 if (ring->queued >= RT2860_TX_RING_COUNT) 1919 sc->qfullmsk |= 1 << qid; 1920 1921 /* kick Tx */ 1922 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1923 1924 return 0; 1925 } 1926 1927 static int 1928 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1929 { 1930 struct rt2860_softc *sc = ic->ic_softc; 1931 int error; 1932 1933 RAL_LOCK(sc); 1934 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 1935 RAL_UNLOCK(sc); 1936 return (ENXIO); 1937 } 1938 error = mbufq_enqueue(&sc->sc_snd, m); 1939 if (error) { 1940 RAL_UNLOCK(sc); 1941 return (error); 1942 } 1943 rt2860_start(sc); 1944 RAL_UNLOCK(sc); 1945 1946 return (0); 1947 } 1948 1949 static void 1950 rt2860_start(struct rt2860_softc *sc) 1951 { 1952 struct ieee80211_node *ni; 1953 struct mbuf *m; 1954 1955 RAL_LOCK_ASSERT(sc); 1956 1957 if ((sc->sc_flags & RT2860_RUNNING) == 0) 1958 return; 1959 1960 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1961 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1962 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1963 if (rt2860_tx(sc, m, ni) != 0) { 1964 if_inc_counter(ni->ni_vap->iv_ifp, 1965 IFCOUNTER_OERRORS, 1); 1966 ieee80211_free_node(ni); 1967 continue; 1968 } 1969 sc->sc_tx_timer = 5; 1970 } 1971 } 1972 1973 static void 1974 rt2860_watchdog(void *arg) 1975 { 1976 struct rt2860_softc *sc = arg; 1977 1978 RAL_LOCK_ASSERT(sc); 1979 1980 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 1981 1982 if (sc->sc_invalid) /* card ejected */ 1983 return; 1984 1985 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1986 device_printf(sc->sc_dev, "device timeout\n"); 1987 rt2860_stop_locked(sc); 1988 rt2860_init_locked(sc); 1989 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1990 return; 1991 } 1992 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 1993 } 1994 1995 static void 1996 rt2860_parent(struct ieee80211com *ic) 1997 { 1998 struct rt2860_softc *sc = ic->ic_softc; 1999 int startall = 0; 2000 2001 RAL_LOCK(sc); 2002 if (ic->ic_nrunning> 0) { 2003 if (!(sc->sc_flags & RT2860_RUNNING)) { 2004 rt2860_init_locked(sc); 2005 startall = 1; 2006 } else 2007 rt2860_update_promisc(ic); 2008 } else if (sc->sc_flags & RT2860_RUNNING) 2009 rt2860_stop_locked(sc); 2010 RAL_UNLOCK(sc); 2011 if (startall) 2012 ieee80211_start_all(ic); 2013 } 2014 2015 /* 2016 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2017 * We access the BBP through the 8051 microcontroller unit which means that 2018 * the microcode must be loaded first. 2019 */ 2020 void 2021 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2022 { 2023 int ntries; 2024 2025 for (ntries = 0; ntries < 100; ntries++) { 2026 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2027 break; 2028 DELAY(1); 2029 } 2030 if (ntries == 100) { 2031 device_printf(sc->sc_dev, 2032 "could not write to BBP through MCU\n"); 2033 return; 2034 } 2035 2036 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2037 RT2860_BBP_CSR_KICK | reg << 8 | val); 2038 RAL_BARRIER_WRITE(sc); 2039 2040 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2041 DELAY(1000); 2042 } 2043 2044 uint8_t 2045 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2046 { 2047 uint32_t val; 2048 int ntries; 2049 2050 for (ntries = 0; ntries < 100; ntries++) { 2051 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2052 break; 2053 DELAY(1); 2054 } 2055 if (ntries == 100) { 2056 device_printf(sc->sc_dev, 2057 "could not read from BBP through MCU\n"); 2058 return 0; 2059 } 2060 2061 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2062 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2063 RAL_BARRIER_WRITE(sc); 2064 2065 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2066 DELAY(1000); 2067 2068 for (ntries = 0; ntries < 100; ntries++) { 2069 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2070 if (!(val & RT2860_BBP_CSR_KICK)) 2071 return val & 0xff; 2072 DELAY(1); 2073 } 2074 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2075 2076 return 0; 2077 } 2078 2079 /* 2080 * Write to one of the 4 programmable 24-bit RF registers. 2081 */ 2082 static void 2083 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2084 { 2085 uint32_t tmp; 2086 int ntries; 2087 2088 for (ntries = 0; ntries < 100; ntries++) { 2089 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2090 break; 2091 DELAY(1); 2092 } 2093 if (ntries == 100) { 2094 device_printf(sc->sc_dev, "could not write to RF\n"); 2095 return; 2096 } 2097 2098 /* RF registers are 24-bit on the RT2860 */ 2099 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2100 (val & 0x3fffff) << 2 | (reg & 3); 2101 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2102 } 2103 2104 static uint8_t 2105 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2106 { 2107 uint32_t tmp; 2108 int ntries; 2109 2110 for (ntries = 0; ntries < 100; ntries++) { 2111 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2112 break; 2113 DELAY(1); 2114 } 2115 if (ntries == 100) { 2116 device_printf(sc->sc_dev, "could not read RF register\n"); 2117 return 0xff; 2118 } 2119 tmp = RT3070_RF_KICK | reg << 8; 2120 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2121 2122 for (ntries = 0; ntries < 100; ntries++) { 2123 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2124 if (!(tmp & RT3070_RF_KICK)) 2125 break; 2126 DELAY(1); 2127 } 2128 if (ntries == 100) { 2129 device_printf(sc->sc_dev, "could not read RF register\n"); 2130 return 0xff; 2131 } 2132 return tmp & 0xff; 2133 } 2134 2135 void 2136 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2137 { 2138 uint32_t tmp; 2139 int ntries; 2140 2141 for (ntries = 0; ntries < 10; ntries++) { 2142 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2143 break; 2144 DELAY(10); 2145 } 2146 if (ntries == 10) { 2147 device_printf(sc->sc_dev, "could not write to RF\n"); 2148 return; 2149 } 2150 2151 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2152 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2153 } 2154 2155 /* 2156 * Send a command to the 8051 microcontroller unit. 2157 */ 2158 int 2159 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2160 { 2161 int slot, ntries; 2162 uint32_t tmp; 2163 uint8_t cid; 2164 2165 for (ntries = 0; ntries < 100; ntries++) { 2166 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2167 break; 2168 DELAY(2); 2169 } 2170 if (ntries == 100) 2171 return EIO; 2172 2173 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2174 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2175 RAL_BARRIER_WRITE(sc); 2176 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2177 2178 if (!wait) 2179 return 0; 2180 /* wait for the command to complete */ 2181 for (ntries = 0; ntries < 200; ntries++) { 2182 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2183 /* find the command slot */ 2184 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2185 if ((tmp & 0xff) == cid) 2186 break; 2187 if (slot < 4) 2188 break; 2189 DELAY(100); 2190 } 2191 if (ntries == 200) { 2192 /* clear command and status */ 2193 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2194 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2195 return ETIMEDOUT; 2196 } 2197 /* get command status (1 means success) */ 2198 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2199 tmp = (tmp >> (slot * 8)) & 0xff; 2200 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2201 cmd, slot, tmp)); 2202 /* clear command and status */ 2203 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2204 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2205 return (tmp == 1) ? 0 : EIO; 2206 } 2207 2208 static void 2209 rt2860_enable_mrr(struct rt2860_softc *sc) 2210 { 2211 #define CCK(mcs) (mcs) 2212 #define OFDM(mcs) (1U << 3 | (mcs)) 2213 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2214 OFDM(6) << 28 | /* 54->48 */ 2215 OFDM(5) << 24 | /* 48->36 */ 2216 OFDM(4) << 20 | /* 36->24 */ 2217 OFDM(3) << 16 | /* 24->18 */ 2218 OFDM(2) << 12 | /* 18->12 */ 2219 OFDM(1) << 8 | /* 12-> 9 */ 2220 OFDM(0) << 4 | /* 9-> 6 */ 2221 OFDM(0)); /* 6-> 6 */ 2222 2223 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2224 CCK(2) << 12 | /* 11->5.5 */ 2225 CCK(1) << 8 | /* 5.5-> 2 */ 2226 CCK(0) << 4 | /* 2-> 1 */ 2227 CCK(0)); /* 1-> 1 */ 2228 #undef OFDM 2229 #undef CCK 2230 } 2231 2232 static void 2233 rt2860_set_txpreamble(struct rt2860_softc *sc) 2234 { 2235 struct ieee80211com *ic = &sc->sc_ic; 2236 uint32_t tmp; 2237 2238 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2239 tmp &= ~RT2860_CCK_SHORT_EN; 2240 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2241 tmp |= RT2860_CCK_SHORT_EN; 2242 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2243 } 2244 2245 void 2246 rt2860_set_basicrates(struct rt2860_softc *sc, 2247 const struct ieee80211_rateset *rs) 2248 { 2249 struct ieee80211com *ic = &sc->sc_ic; 2250 uint32_t mask = 0; 2251 uint8_t rate; 2252 int i; 2253 2254 for (i = 0; i < rs->rs_nrates; i++) { 2255 rate = rs->rs_rates[i]; 2256 2257 if (!(rate & IEEE80211_RATE_BASIC)) 2258 continue; 2259 2260 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2261 IEEE80211_RV(rate)); 2262 } 2263 2264 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2265 } 2266 2267 static void 2268 rt2860_scan_start(struct ieee80211com *ic) 2269 { 2270 struct rt2860_softc *sc = ic->ic_softc; 2271 uint32_t tmp; 2272 2273 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2274 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2275 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2276 RT2860_TBTT_TIMER_EN)); 2277 rt2860_set_gp_timer(sc, 0); 2278 } 2279 2280 static void 2281 rt2860_scan_end(struct ieee80211com *ic) 2282 { 2283 struct rt2860_softc *sc = ic->ic_softc; 2284 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2285 2286 if (vap->iv_state == IEEE80211_S_RUN) { 2287 rt2860_enable_tsf_sync(sc); 2288 rt2860_set_gp_timer(sc, 500); 2289 } 2290 } 2291 2292 static void 2293 rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, 2294 struct ieee80211_channel chans[]) 2295 { 2296 struct rt2860_softc *sc = ic->ic_softc; 2297 uint8_t bands[IEEE80211_MODE_BYTES]; 2298 2299 memset(bands, 0, sizeof(bands)); 2300 setbit(bands, IEEE80211_MODE_11B); 2301 setbit(bands, IEEE80211_MODE_11G); 2302 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2303 2304 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 2305 setbit(bands, IEEE80211_MODE_11A); 2306 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2307 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0); 2308 } 2309 } 2310 2311 static void 2312 rt2860_set_channel(struct ieee80211com *ic) 2313 { 2314 struct rt2860_softc *sc = ic->ic_softc; 2315 2316 RAL_LOCK(sc); 2317 rt2860_switch_chan(sc, ic->ic_curchan); 2318 RAL_UNLOCK(sc); 2319 } 2320 2321 static void 2322 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2323 { 2324 uint32_t tmp; 2325 uint8_t agc; 2326 2327 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2328 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2329 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2330 rt2860_mcu_bbp_write(sc, 86, 0x00); 2331 2332 if (group == 0) { 2333 if (sc->ext_2ghz_lna) { 2334 rt2860_mcu_bbp_write(sc, 82, 0x62); 2335 rt2860_mcu_bbp_write(sc, 75, 0x46); 2336 } else { 2337 rt2860_mcu_bbp_write(sc, 82, 0x84); 2338 rt2860_mcu_bbp_write(sc, 75, 0x50); 2339 } 2340 } else { 2341 if (sc->ext_5ghz_lna) { 2342 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2343 rt2860_mcu_bbp_write(sc, 75, 0x46); 2344 } else { 2345 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2346 rt2860_mcu_bbp_write(sc, 75, 0x50); 2347 } 2348 } 2349 2350 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2351 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2352 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2353 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2354 2355 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2356 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2357 if (sc->nrxchains > 1) 2358 tmp |= RT2860_LNA_PE1_EN; 2359 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2360 tmp |= RT3593_LNA_PE2_EN; 2361 if (group == 0) { /* 2GHz */ 2362 tmp |= RT2860_PA_PE_G0_EN; 2363 if (sc->ntxchains > 1) 2364 tmp |= RT2860_PA_PE_G1_EN; 2365 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2366 tmp |= RT3593_PA_PE_G2_EN; 2367 } else { /* 5GHz */ 2368 tmp |= RT2860_PA_PE_A0_EN; 2369 if (sc->ntxchains > 1) 2370 tmp |= RT2860_PA_PE_A1_EN; 2371 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2372 tmp |= RT3593_PA_PE_A2_EN; 2373 } 2374 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2375 2376 if (sc->mac_ver == 0x3593) { 2377 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2378 if (sc->sc_flags & RT2860_PCIE) { 2379 tmp &= ~0x01010000; 2380 if (group == 0) 2381 tmp |= 0x00010000; 2382 } else { 2383 tmp &= ~0x00008080; 2384 if (group == 0) 2385 tmp |= 0x00000080; 2386 } 2387 tmp = (tmp & ~0x00001000) | 0x00000010; 2388 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2389 } 2390 2391 /* set initial AGC value */ 2392 if (group == 0) { /* 2GHz band */ 2393 if (sc->mac_ver >= 0x3071) 2394 agc = 0x1c + sc->lna[0] * 2; 2395 else 2396 agc = 0x2e + sc->lna[0]; 2397 } else { /* 5GHz band */ 2398 agc = 0x32 + (sc->lna[group] * 5) / 3; 2399 } 2400 rt2860_mcu_bbp_write(sc, 66, agc); 2401 2402 DELAY(1000); 2403 } 2404 2405 static void 2406 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2407 { 2408 const struct rfprog *rfprog = rt2860_rf2850; 2409 uint32_t r2, r3, r4; 2410 int8_t txpow1, txpow2; 2411 u_int i; 2412 2413 /* find the settings for this channel (we know it exists) */ 2414 for (i = 0; rfprog[i].chan != chan; i++); 2415 2416 r2 = rfprog[i].r2; 2417 if (sc->ntxchains == 1) 2418 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2419 if (sc->nrxchains == 1) 2420 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2421 else if (sc->nrxchains == 2) 2422 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2423 2424 /* use Tx power values from EEPROM */ 2425 txpow1 = sc->txpow1[i]; 2426 txpow2 = sc->txpow2[i]; 2427 if (chan > 14) { 2428 if (txpow1 >= 0) 2429 txpow1 = txpow1 << 1 | 1; 2430 else 2431 txpow1 = (7 + txpow1) << 1; 2432 if (txpow2 >= 0) 2433 txpow2 = txpow2 << 1 | 1; 2434 else 2435 txpow2 = (7 + txpow2) << 1; 2436 } 2437 r3 = rfprog[i].r3 | txpow1 << 7; 2438 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2439 2440 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2441 rt2860_rf_write(sc, RT2860_RF2, r2); 2442 rt2860_rf_write(sc, RT2860_RF3, r3); 2443 rt2860_rf_write(sc, RT2860_RF4, r4); 2444 2445 DELAY(200); 2446 2447 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2448 rt2860_rf_write(sc, RT2860_RF2, r2); 2449 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2450 rt2860_rf_write(sc, RT2860_RF4, r4); 2451 2452 DELAY(200); 2453 2454 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2455 rt2860_rf_write(sc, RT2860_RF2, r2); 2456 rt2860_rf_write(sc, RT2860_RF3, r3); 2457 rt2860_rf_write(sc, RT2860_RF4, r4); 2458 } 2459 2460 static void 2461 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2462 { 2463 int8_t txpow1, txpow2; 2464 uint8_t rf; 2465 int i; 2466 2467 /* RT3090 is 2GHz only */ 2468 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2469 2470 /* find the settings for this channel (we know it exists) */ 2471 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2472 2473 /* use Tx power values from EEPROM */ 2474 txpow1 = sc->txpow1[i]; 2475 txpow2 = sc->txpow2[i]; 2476 2477 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2478 rf = rt3090_rf_read(sc, 3); 2479 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2480 rt3090_rf_write(sc, 3, rf); 2481 rf = rt3090_rf_read(sc, 6); 2482 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2483 rt3090_rf_write(sc, 6, rf); 2484 2485 /* set Tx0 power */ 2486 rf = rt3090_rf_read(sc, 12); 2487 rf = (rf & ~0x1f) | txpow1; 2488 rt3090_rf_write(sc, 12, rf); 2489 2490 /* set Tx1 power */ 2491 rf = rt3090_rf_read(sc, 13); 2492 rf = (rf & ~0x1f) | txpow2; 2493 rt3090_rf_write(sc, 13, rf); 2494 2495 rf = rt3090_rf_read(sc, 1); 2496 rf &= ~0xfc; 2497 if (sc->ntxchains == 1) 2498 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2499 else if (sc->ntxchains == 2) 2500 rf |= RT3070_TX2_PD; 2501 if (sc->nrxchains == 1) 2502 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2503 else if (sc->nrxchains == 2) 2504 rf |= RT3070_RX2_PD; 2505 rt3090_rf_write(sc, 1, rf); 2506 2507 /* set RF offset */ 2508 rf = rt3090_rf_read(sc, 23); 2509 rf = (rf & ~0x7f) | sc->freq; 2510 rt3090_rf_write(sc, 23, rf); 2511 2512 /* program RF filter */ 2513 rf = rt3090_rf_read(sc, 24); /* Tx */ 2514 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2515 rt3090_rf_write(sc, 24, rf); 2516 rf = rt3090_rf_read(sc, 31); /* Rx */ 2517 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2518 rt3090_rf_write(sc, 31, rf); 2519 2520 /* enable RF tuning */ 2521 rf = rt3090_rf_read(sc, 7); 2522 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2523 } 2524 2525 static void 2526 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2527 { 2528 uint8_t h20mhz, rf, tmp; 2529 int8_t txpow1, txpow2; 2530 int i; 2531 2532 /* RT5390 is 2GHz only */ 2533 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2534 2535 /* find the settings for this channel (we know it exists) */ 2536 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2537 2538 /* use Tx power values from EEPROM */ 2539 txpow1 = sc->txpow1[i]; 2540 txpow2 = sc->txpow2[i]; 2541 2542 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2543 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2544 rf = rt3090_rf_read(sc, 11); 2545 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2546 rt3090_rf_write(sc, 11, rf); 2547 2548 rf = rt3090_rf_read(sc, 49); 2549 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2550 /* the valid range of the RF R49 is 0x00~0x27 */ 2551 if ((rf & 0x3f) > 0x27) 2552 rf = (rf & ~0x3f) | 0x27; 2553 rt3090_rf_write(sc, 49, rf); 2554 if (sc->mac_ver == 0x5392) { 2555 rf = rt3090_rf_read(sc, 50); 2556 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2557 /* the valid range of the RF R50 is 0x00~0x27 */ 2558 if ((rf & 0x3f) > 0x27) 2559 rf = (rf & ~0x3f) | 0x27; 2560 rt3090_rf_write(sc, 50, rf); 2561 } 2562 2563 rf = rt3090_rf_read(sc, 1); 2564 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2565 if (sc->mac_ver == 0x5392) 2566 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2567 rt3090_rf_write(sc, 1, rf); 2568 2569 rf = rt3090_rf_read(sc, 2); 2570 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2571 DELAY(1000); 2572 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2573 2574 rf = rt3090_rf_read(sc, 17); 2575 tmp = rf; 2576 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2577 rf = MIN(rf, 0x5f); 2578 if (tmp != rf) 2579 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2580 2581 if (sc->mac_ver == 0x5390) { 2582 if (chan <= 4) 2583 rf = 0x73; 2584 else if (chan >= 5 && chan <= 6) 2585 rf = 0x63; 2586 else if (chan >= 7 && chan <= 10) 2587 rf = 0x53; 2588 else 2589 rf = 43; 2590 rt3090_rf_write(sc, 55, rf); 2591 2592 if (chan == 1) 2593 rf = 0x0c; 2594 else if (chan == 2) 2595 rf = 0x0b; 2596 else if (chan == 3) 2597 rf = 0x0a; 2598 else if (chan >= 4 && chan <= 6) 2599 rf = 0x09; 2600 else if (chan >= 7 && chan <= 12) 2601 rf = 0x08; 2602 else if (chan == 13) 2603 rf = 0x07; 2604 else 2605 rf = 0x06; 2606 rt3090_rf_write(sc, 59, rf); 2607 } 2608 2609 /* Tx/Rx h20M */ 2610 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2611 rf = rt3090_rf_read(sc, 30); 2612 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2613 rt3090_rf_write(sc, 30, rf); 2614 2615 /* Rx BB filter VCM */ 2616 rf = rt3090_rf_read(sc, 30); 2617 rf = (rf & ~0x18) | 0x10; 2618 rt3090_rf_write(sc, 30, rf); 2619 2620 /* Initiate VCO calibration. */ 2621 rf = rt3090_rf_read(sc, 3); 2622 rf |= RT3593_VCOCAL; 2623 rt3090_rf_write(sc, 3, rf); 2624 } 2625 2626 static int 2627 rt3090_rf_init(struct rt2860_softc *sc) 2628 { 2629 uint32_t tmp; 2630 uint8_t rf, bbp; 2631 int i; 2632 2633 rf = rt3090_rf_read(sc, 30); 2634 /* toggle RF R30 bit 7 */ 2635 rt3090_rf_write(sc, 30, rf | 0x80); 2636 DELAY(1000); 2637 rt3090_rf_write(sc, 30, rf & ~0x80); 2638 2639 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2640 tmp &= ~0x1f000000; 2641 if (sc->patch_dac && sc->mac_rev < 0x0211) 2642 tmp |= 0x0d000000; /* 1.35V */ 2643 else 2644 tmp |= 0x01000000; /* 1.2V */ 2645 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2646 2647 /* patch LNA_PE_G1 */ 2648 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2649 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2650 2651 /* initialize RF registers to default value */ 2652 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2653 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2654 rt3090_def_rf[i].val); 2655 } 2656 2657 /* select 20MHz bandwidth */ 2658 rt3090_rf_write(sc, 31, 0x14); 2659 2660 rf = rt3090_rf_read(sc, 6); 2661 rt3090_rf_write(sc, 6, rf | 0x40); 2662 2663 if (sc->mac_ver != 0x3593) { 2664 /* calibrate filter for 20MHz bandwidth */ 2665 sc->rf24_20mhz = 0x1f; /* default value */ 2666 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2667 2668 /* select 40MHz bandwidth */ 2669 bbp = rt2860_mcu_bbp_read(sc, 4); 2670 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2671 rf = rt3090_rf_read(sc, 31); 2672 rt3090_rf_write(sc, 31, rf | 0x20); 2673 2674 /* calibrate filter for 40MHz bandwidth */ 2675 sc->rf24_40mhz = 0x2f; /* default value */ 2676 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2677 2678 /* go back to 20MHz bandwidth */ 2679 bbp = rt2860_mcu_bbp_read(sc, 4); 2680 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2681 } 2682 if (sc->mac_rev < 0x0211) 2683 rt3090_rf_write(sc, 27, 0x03); 2684 2685 tmp = RAL_READ(sc, RT3070_OPT_14); 2686 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2687 2688 if (sc->rf_rev == RT3070_RF_3020) 2689 rt3090_set_rx_antenna(sc, 0); 2690 2691 bbp = rt2860_mcu_bbp_read(sc, 138); 2692 if (sc->mac_ver == 0x3593) { 2693 if (sc->ntxchains == 1) 2694 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2695 else if (sc->ntxchains == 2) 2696 bbp |= 0x40; /* turn off DAC2 */ 2697 if (sc->nrxchains == 1) 2698 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2699 else if (sc->nrxchains == 2) 2700 bbp &= ~0x04; /* turn off ADC2 */ 2701 } else { 2702 if (sc->ntxchains == 1) 2703 bbp |= 0x20; /* turn off DAC1 */ 2704 if (sc->nrxchains == 1) 2705 bbp &= ~0x02; /* turn off ADC1 */ 2706 } 2707 rt2860_mcu_bbp_write(sc, 138, bbp); 2708 2709 rf = rt3090_rf_read(sc, 1); 2710 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2711 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2712 rt3090_rf_write(sc, 1, rf); 2713 2714 rf = rt3090_rf_read(sc, 15); 2715 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2716 2717 rf = rt3090_rf_read(sc, 17); 2718 rf &= ~RT3070_TX_LO1; 2719 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2720 rf |= 0x20; /* fix for long range Rx issue */ 2721 if (sc->txmixgain_2ghz >= 2) 2722 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2723 rt3090_rf_write(sc, 17, rf); 2724 2725 rf = rt3090_rf_read(sc, 20); 2726 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2727 2728 rf = rt3090_rf_read(sc, 21); 2729 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2730 2731 return (0); 2732 } 2733 2734 static void 2735 rt5390_rf_init(struct rt2860_softc *sc) 2736 { 2737 uint8_t rf, bbp; 2738 int i; 2739 2740 rf = rt3090_rf_read(sc, 2); 2741 /* Toggle RF R2 bit 7. */ 2742 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2743 DELAY(1000); 2744 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2745 2746 /* Initialize RF registers to default value. */ 2747 if (sc->mac_ver == 0x5392) { 2748 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2749 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2750 rt5392_def_rf[i].val); 2751 } 2752 } else { 2753 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2754 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2755 rt5390_def_rf[i].val); 2756 } 2757 } 2758 2759 sc->rf24_20mhz = 0x1f; 2760 sc->rf24_40mhz = 0x2f; 2761 2762 if (sc->mac_rev < 0x0211) 2763 rt3090_rf_write(sc, 27, 0x03); 2764 2765 /* Set led open drain enable. */ 2766 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2767 2768 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2769 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2770 2771 if (sc->mac_ver == 0x5390) 2772 rt3090_set_rx_antenna(sc, 0); 2773 2774 /* Patch RSSI inaccurate issue. */ 2775 rt2860_mcu_bbp_write(sc, 79, 0x13); 2776 rt2860_mcu_bbp_write(sc, 80, 0x05); 2777 rt2860_mcu_bbp_write(sc, 81, 0x33); 2778 2779 /* Enable DC filter. */ 2780 if (sc->mac_rev >= 0x0211) 2781 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2782 2783 bbp = rt2860_mcu_bbp_read(sc, 138); 2784 if (sc->ntxchains == 1) 2785 bbp |= 0x20; /* Turn off DAC1. */ 2786 if (sc->nrxchains == 1) 2787 bbp &= ~0x02; /* Turn off ADC1. */ 2788 rt2860_mcu_bbp_write(sc, 138, bbp); 2789 2790 /* Enable RX LO1 and LO2. */ 2791 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2792 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2793 2794 /* Avoid data lost and CRC error. */ 2795 rt2860_mcu_bbp_write(sc, 4, 2796 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2797 2798 rf = rt3090_rf_read(sc, 30); 2799 rf = (rf & ~0x18) | 0x10; 2800 rt3090_rf_write(sc, 30, rf); 2801 } 2802 2803 static void 2804 rt3090_rf_wakeup(struct rt2860_softc *sc) 2805 { 2806 uint32_t tmp; 2807 uint8_t rf; 2808 2809 if (sc->mac_ver == 0x3593) { 2810 /* enable VCO */ 2811 rf = rt3090_rf_read(sc, 1); 2812 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2813 2814 /* initiate VCO calibration */ 2815 rf = rt3090_rf_read(sc, 3); 2816 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2817 2818 /* enable VCO bias current control */ 2819 rf = rt3090_rf_read(sc, 6); 2820 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2821 2822 /* initiate res calibration */ 2823 rf = rt3090_rf_read(sc, 2); 2824 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2825 2826 /* set reference current control to 0.33 mA */ 2827 rf = rt3090_rf_read(sc, 22); 2828 rf &= ~RT3593_CP_IC_MASK; 2829 rf |= 1 << RT3593_CP_IC_SHIFT; 2830 rt3090_rf_write(sc, 22, rf); 2831 2832 /* enable RX CTB */ 2833 rf = rt3090_rf_read(sc, 46); 2834 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2835 2836 rf = rt3090_rf_read(sc, 20); 2837 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2838 rt3090_rf_write(sc, 20, rf); 2839 } else { 2840 /* enable RF block */ 2841 rf = rt3090_rf_read(sc, 1); 2842 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2843 2844 /* enable VCO bias current control */ 2845 rf = rt3090_rf_read(sc, 7); 2846 rt3090_rf_write(sc, 7, rf | 0x30); 2847 2848 rf = rt3090_rf_read(sc, 9); 2849 rt3090_rf_write(sc, 9, rf | 0x0e); 2850 2851 /* enable RX CTB */ 2852 rf = rt3090_rf_read(sc, 21); 2853 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2854 2855 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2856 rf = rt3090_rf_read(sc, 27); 2857 rf &= ~0x77; 2858 if (sc->mac_rev < 0x0211) 2859 rf |= 0x03; 2860 rt3090_rf_write(sc, 27, rf); 2861 } 2862 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2863 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2864 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2865 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2866 } 2867 } 2868 2869 static void 2870 rt5390_rf_wakeup(struct rt2860_softc *sc) 2871 { 2872 uint32_t tmp; 2873 uint8_t rf; 2874 2875 rf = rt3090_rf_read(sc, 1); 2876 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2877 RT3070_TX0_PD; 2878 if (sc->mac_ver == 0x5392) 2879 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2880 rt3090_rf_write(sc, 1, rf); 2881 2882 rf = rt3090_rf_read(sc, 6); 2883 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2884 if (sc->mac_ver == 0x5390) 2885 rf &= ~RT3593_VCO_IC; 2886 rt3090_rf_write(sc, 6, rf); 2887 2888 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2889 2890 rf = rt3090_rf_read(sc, 22); 2891 rf = (rf & ~0xe0) | 0x20; 2892 rt3090_rf_write(sc, 22, rf); 2893 2894 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2895 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2896 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2897 2898 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2899 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2900 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2901 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2902 } 2903 } 2904 2905 static int 2906 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2907 uint8_t *val) 2908 { 2909 uint8_t rf22, rf24; 2910 uint8_t bbp55_pb, bbp55_sb, delta; 2911 int ntries; 2912 2913 /* program filter */ 2914 rf24 = rt3090_rf_read(sc, 24); 2915 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2916 rt3090_rf_write(sc, 24, rf24); 2917 2918 /* enable baseband loopback mode */ 2919 rf22 = rt3090_rf_read(sc, 22); 2920 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2921 2922 /* set power and frequency of passband test tone */ 2923 rt2860_mcu_bbp_write(sc, 24, 0x00); 2924 for (ntries = 0; ntries < 100; ntries++) { 2925 /* transmit test tone */ 2926 rt2860_mcu_bbp_write(sc, 25, 0x90); 2927 DELAY(1000); 2928 /* read received power */ 2929 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2930 if (bbp55_pb != 0) 2931 break; 2932 } 2933 if (ntries == 100) 2934 return (ETIMEDOUT); 2935 2936 /* set power and frequency of stopband test tone */ 2937 rt2860_mcu_bbp_write(sc, 24, 0x06); 2938 for (ntries = 0; ntries < 100; ntries++) { 2939 /* transmit test tone */ 2940 rt2860_mcu_bbp_write(sc, 25, 0x90); 2941 DELAY(1000); 2942 /* read received power */ 2943 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2944 2945 delta = bbp55_pb - bbp55_sb; 2946 if (delta > target) 2947 break; 2948 2949 /* reprogram filter */ 2950 rf24++; 2951 rt3090_rf_write(sc, 24, rf24); 2952 } 2953 if (ntries < 100) { 2954 if (rf24 != init) 2955 rf24--; /* backtrack */ 2956 *val = rf24; 2957 rt3090_rf_write(sc, 24, rf24); 2958 } 2959 2960 /* restore initial state */ 2961 rt2860_mcu_bbp_write(sc, 24, 0x00); 2962 2963 /* disable baseband loopback mode */ 2964 rf22 = rt3090_rf_read(sc, 22); 2965 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2966 2967 return (0); 2968 } 2969 2970 static void 2971 rt3090_rf_setup(struct rt2860_softc *sc) 2972 { 2973 uint8_t bbp; 2974 int i; 2975 2976 if (sc->mac_rev >= 0x0211) { 2977 /* enable DC filter */ 2978 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2979 2980 /* improve power consumption */ 2981 bbp = rt2860_mcu_bbp_read(sc, 31); 2982 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2983 } 2984 2985 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2986 if (sc->mac_rev < 0x0211) { 2987 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2988 sc->patch_dac ? 0x2c : 0x0f); 2989 } else 2990 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2991 2992 /* initialize RF registers from ROM */ 2993 if (sc->mac_ver < 0x5390) { 2994 for (i = 0; i < 10; i++) { 2995 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2996 continue; 2997 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2998 } 2999 } 3000 } 3001 3002 static void 3003 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3004 { 3005 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3006 which | (sc->leds & 0x7f), 0); 3007 } 3008 3009 /* 3010 * Hardware has a general-purpose programmable timer interrupt that can 3011 * periodically raise MAC_INT_4. 3012 */ 3013 static void 3014 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3015 { 3016 uint32_t tmp; 3017 3018 /* disable GP timer before reprogramming it */ 3019 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3020 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3021 3022 if (ms == 0) 3023 return; 3024 3025 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3026 ms *= 16; /* Unit: 64us */ 3027 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3028 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3029 3030 /* enable GP timer */ 3031 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3032 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3033 } 3034 3035 static void 3036 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3037 { 3038 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3039 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3040 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3041 bssid[4] | bssid[5] << 8); 3042 } 3043 3044 static void 3045 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3046 { 3047 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3048 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3049 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3050 addr[4] | addr[5] << 8 | 0xff << 16); 3051 } 3052 3053 static void 3054 rt2860_updateslot(struct ieee80211com *ic) 3055 { 3056 struct rt2860_softc *sc = ic->ic_softc; 3057 uint32_t tmp; 3058 3059 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3060 tmp &= ~0xff; 3061 tmp |= IEEE80211_GET_SLOTTIME(ic); 3062 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3063 } 3064 3065 static void 3066 rt2860_updateprot(struct rt2860_softc *sc) 3067 { 3068 struct ieee80211com *ic = &sc->sc_ic; 3069 uint32_t tmp; 3070 3071 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3072 /* setup protection frame rate (MCS code) */ 3073 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3074 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3075 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3076 3077 /* CCK frames don't require protection */ 3078 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3079 3080 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3081 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3082 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3083 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3084 tmp |= RT2860_PROT_CTRL_CTS; 3085 } 3086 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3087 } 3088 3089 static void 3090 rt2860_update_promisc(struct ieee80211com *ic) 3091 { 3092 struct rt2860_softc *sc = ic->ic_softc; 3093 uint32_t tmp; 3094 3095 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3096 tmp &= ~RT2860_DROP_NOT_MYBSS; 3097 if (ic->ic_promisc == 0) 3098 tmp |= RT2860_DROP_NOT_MYBSS; 3099 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3100 } 3101 3102 static int 3103 rt2860_updateedca(struct ieee80211com *ic) 3104 { 3105 struct rt2860_softc *sc = ic->ic_softc; 3106 struct chanAccParams chp; 3107 const struct wmeParams *wmep; 3108 int aci; 3109 3110 ieee80211_wme_ic_getparams(ic, &chp); 3111 3112 wmep = chp.cap_wmeParams; 3113 3114 /* update MAC TX configuration registers */ 3115 for (aci = 0; aci < WME_NUM_AC; aci++) { 3116 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3117 wmep[aci].wmep_logcwmax << 16 | 3118 wmep[aci].wmep_logcwmin << 12 | 3119 wmep[aci].wmep_aifsn << 8 | 3120 wmep[aci].wmep_txopLimit); 3121 } 3122 3123 /* update SCH/DMA registers too */ 3124 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3125 wmep[WME_AC_VO].wmep_aifsn << 12 | 3126 wmep[WME_AC_VI].wmep_aifsn << 8 | 3127 wmep[WME_AC_BK].wmep_aifsn << 4 | 3128 wmep[WME_AC_BE].wmep_aifsn); 3129 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3130 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3131 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3132 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3133 wmep[WME_AC_BE].wmep_logcwmin); 3134 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3135 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3136 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3137 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3138 wmep[WME_AC_BE].wmep_logcwmax); 3139 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3140 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3141 wmep[WME_AC_BE].wmep_txopLimit); 3142 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3143 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3144 wmep[WME_AC_VI].wmep_txopLimit); 3145 3146 return 0; 3147 } 3148 3149 #ifdef HW_CRYPTO 3150 static int 3151 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3152 struct ieee80211_key *k) 3153 { 3154 struct rt2860_softc *sc = ic->ic_softc; 3155 bus_size_t base; 3156 uint32_t attr; 3157 uint8_t mode, wcid, iv[8]; 3158 3159 /* defer setting of WEP keys until interface is brought up */ 3160 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3161 (IFF_UP | IFF_RUNNING)) 3162 return 0; 3163 3164 /* map net80211 cipher to RT2860 security mode */ 3165 switch (k->k_cipher) { 3166 case IEEE80211_CIPHER_WEP40: 3167 mode = RT2860_MODE_WEP40; 3168 break; 3169 case IEEE80211_CIPHER_WEP104: 3170 mode = RT2860_MODE_WEP104; 3171 break; 3172 case IEEE80211_CIPHER_TKIP: 3173 mode = RT2860_MODE_TKIP; 3174 break; 3175 case IEEE80211_CIPHER_CCMP: 3176 mode = RT2860_MODE_AES_CCMP; 3177 break; 3178 default: 3179 return EINVAL; 3180 } 3181 3182 if (k->k_flags & IEEE80211_KEY_GROUP) { 3183 wcid = 0; /* NB: update WCID0 for group keys */ 3184 base = RT2860_SKEY(0, k->k_id); 3185 } else { 3186 wcid = ((struct rt2860_node *)ni)->wcid; 3187 base = RT2860_PKEY(wcid); 3188 } 3189 3190 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3191 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3192 #ifndef IEEE80211_STA_ONLY 3193 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3194 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3195 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3196 } else 3197 #endif 3198 { 3199 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3200 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3201 } 3202 } else 3203 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3204 3205 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3206 (k->k_flags & IEEE80211_KEY_TX)) { 3207 /* set initial packet number in IV+EIV */ 3208 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3209 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3210 uint32_t val = arc4random(); 3211 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3212 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3213 val += 0x000100; 3214 iv[0] = val; 3215 iv[1] = val >> 8; 3216 iv[2] = val >> 16; 3217 iv[3] = k->k_id << 6; 3218 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3219 } else { 3220 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3221 iv[0] = k->k_tsc >> 8; 3222 iv[1] = (iv[0] | 0x20) & 0x7f; 3223 iv[2] = k->k_tsc; 3224 } else /* CCMP */ { 3225 iv[0] = k->k_tsc; 3226 iv[1] = k->k_tsc >> 8; 3227 iv[2] = 0; 3228 } 3229 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3230 iv[4] = k->k_tsc >> 16; 3231 iv[5] = k->k_tsc >> 24; 3232 iv[6] = k->k_tsc >> 32; 3233 iv[7] = k->k_tsc >> 40; 3234 } 3235 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3236 } 3237 3238 if (k->k_flags & IEEE80211_KEY_GROUP) { 3239 /* install group key */ 3240 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3241 attr &= ~(0xf << (k->k_id * 4)); 3242 attr |= mode << (k->k_id * 4); 3243 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3244 } else { 3245 /* install pairwise key */ 3246 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3247 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3248 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3249 } 3250 return 0; 3251 } 3252 3253 static void 3254 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3255 struct ieee80211_key *k) 3256 { 3257 struct rt2860_softc *sc = ic->ic_softc; 3258 uint32_t attr; 3259 uint8_t wcid; 3260 3261 if (k->k_flags & IEEE80211_KEY_GROUP) { 3262 /* remove group key */ 3263 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3264 attr &= ~(0xf << (k->k_id * 4)); 3265 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3266 3267 } else { 3268 /* remove pairwise key */ 3269 wcid = ((struct rt2860_node *)ni)->wcid; 3270 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3271 attr &= ~0xf; 3272 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3273 } 3274 } 3275 #endif 3276 3277 static int8_t 3278 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3279 { 3280 struct ieee80211com *ic = &sc->sc_ic; 3281 struct ieee80211_channel *c = ic->ic_curchan; 3282 int delta; 3283 3284 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3285 u_int chan = ieee80211_chan2ieee(ic, c); 3286 delta = sc->rssi_5ghz[rxchain]; 3287 3288 /* determine channel group */ 3289 if (chan <= 64) 3290 delta -= sc->lna[1]; 3291 else if (chan <= 128) 3292 delta -= sc->lna[2]; 3293 else 3294 delta -= sc->lna[3]; 3295 } else 3296 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3297 3298 return -12 - delta - rssi; 3299 } 3300 3301 /* 3302 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3303 * Used to adjust per-rate Tx power registers. 3304 */ 3305 static __inline uint32_t 3306 b4inc(uint32_t b32, int8_t delta) 3307 { 3308 int8_t i, b4; 3309 3310 for (i = 0; i < 8; i++) { 3311 b4 = b32 & 0xf; 3312 b4 += delta; 3313 if (b4 < 0) 3314 b4 = 0; 3315 else if (b4 > 0xf) 3316 b4 = 0xf; 3317 b32 = b32 >> 4 | (uint32_t)b4 << 28; 3318 } 3319 return b32; 3320 } 3321 3322 static const char * 3323 rt2860_get_rf(uint16_t rev) 3324 { 3325 switch (rev) { 3326 case RT2860_RF_2820: return "RT2820"; 3327 case RT2860_RF_2850: return "RT2850"; 3328 case RT2860_RF_2720: return "RT2720"; 3329 case RT2860_RF_2750: return "RT2750"; 3330 case RT3070_RF_3020: return "RT3020"; 3331 case RT3070_RF_2020: return "RT2020"; 3332 case RT3070_RF_3021: return "RT3021"; 3333 case RT3070_RF_3022: return "RT3022"; 3334 case RT3070_RF_3052: return "RT3052"; 3335 case RT3070_RF_3320: return "RT3320"; 3336 case RT3070_RF_3053: return "RT3053"; 3337 case RT5390_RF_5360: return "RT5360"; 3338 case RT5390_RF_5390: return "RT5390"; 3339 default: return "unknown"; 3340 } 3341 } 3342 3343 static int 3344 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3345 { 3346 int8_t delta_2ghz, delta_5ghz; 3347 uint32_t tmp; 3348 uint16_t val; 3349 int ridx, ant, i; 3350 3351 /* check whether the ROM is eFUSE ROM or EEPROM */ 3352 sc->sc_srom_read = rt2860_eeprom_read_2; 3353 if (sc->mac_ver >= 0x3071) { 3354 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3355 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3356 if (tmp & RT3070_SEL_EFUSE) 3357 sc->sc_srom_read = rt3090_efuse_read_2; 3358 } 3359 3360 #ifdef RAL_DEBUG 3361 /* read EEPROM version */ 3362 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3363 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3364 #endif 3365 3366 /* read MAC address */ 3367 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3368 macaddr[0] = val & 0xff; 3369 macaddr[1] = val >> 8; 3370 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3371 macaddr[2] = val & 0xff; 3372 macaddr[3] = val >> 8; 3373 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3374 macaddr[4] = val & 0xff; 3375 macaddr[5] = val >> 8; 3376 3377 #ifdef RAL_DEBUG 3378 /* read country code */ 3379 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3380 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3381 #endif 3382 3383 /* read vendor BBP settings */ 3384 for (i = 0; i < 8; i++) { 3385 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3386 sc->bbp[i].val = val & 0xff; 3387 sc->bbp[i].reg = val >> 8; 3388 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3389 } 3390 if (sc->mac_ver >= 0x3071) { 3391 /* read vendor RF settings */ 3392 for (i = 0; i < 10; i++) { 3393 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3394 sc->rf[i].val = val & 0xff; 3395 sc->rf[i].reg = val >> 8; 3396 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3397 sc->rf[i].val)); 3398 } 3399 } 3400 3401 /* read RF frequency offset from EEPROM */ 3402 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3403 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3404 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3405 if ((val >> 8) != 0xff) { 3406 /* read LEDs operating mode */ 3407 sc->leds = val >> 8; 3408 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3409 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3410 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3411 } else { 3412 /* broken EEPROM, use default settings */ 3413 sc->leds = 0x01; 3414 sc->led[0] = 0x5555; 3415 sc->led[1] = 0x2221; 3416 sc->led[2] = 0xa9f8; 3417 } 3418 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3419 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3420 3421 /* read RF information */ 3422 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3423 if (sc->mac_ver >= 0x5390) 3424 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3425 else 3426 sc->rf_rev = (val >> 8) & 0xf; 3427 sc->ntxchains = (val >> 4) & 0xf; 3428 sc->nrxchains = val & 0xf; 3429 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3430 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3431 3432 /* check if RF supports automatic Tx access gain control */ 3433 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3434 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3435 /* check if driver should patch the DAC issue */ 3436 if ((val >> 8) != 0xff) 3437 sc->patch_dac = (val >> 15) & 1; 3438 if ((val & 0xff) != 0xff) { 3439 sc->ext_5ghz_lna = (val >> 3) & 1; 3440 sc->ext_2ghz_lna = (val >> 2) & 1; 3441 /* check if RF supports automatic Tx access gain control */ 3442 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3443 /* check if we have a hardware radio switch */ 3444 sc->rfswitch = val & 1; 3445 } 3446 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3447 /* read PCIe power save level */ 3448 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3449 if ((val & 0xff) != 0xff) { 3450 sc->pslevel = val & 0x3; 3451 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3452 if ((val & 0xff80) != 0x9280) 3453 sc->pslevel = MIN(sc->pslevel, 1); 3454 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3455 } 3456 } 3457 3458 /* read power settings for 2GHz channels */ 3459 for (i = 0; i < 14; i += 2) { 3460 val = rt2860_srom_read(sc, 3461 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3462 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3463 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3464 3465 if (sc->mac_ver != 0x5390) { 3466 val = rt2860_srom_read(sc, 3467 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3468 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3469 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3470 } 3471 } 3472 /* fix broken Tx power entries */ 3473 for (i = 0; i < 14; i++) { 3474 if (sc->txpow1[i] < 0 || 3475 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3476 sc->txpow1[i] = 5; 3477 if (sc->mac_ver != 0x5390) { 3478 if (sc->txpow2[i] < 0 || 3479 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3480 sc->txpow2[i] = 5; 3481 } 3482 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3483 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3484 } 3485 /* read power settings for 5GHz channels */ 3486 for (i = 0; i < 40; i += 2) { 3487 val = rt2860_srom_read(sc, 3488 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3489 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3490 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3491 3492 val = rt2860_srom_read(sc, 3493 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3494 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3495 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3496 } 3497 /* fix broken Tx power entries */ 3498 for (i = 0; i < 40; i++) { 3499 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3500 sc->txpow1[14 + i] = 5; 3501 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3502 sc->txpow2[14 + i] = 5; 3503 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3504 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3505 sc->txpow2[14 + i])); 3506 } 3507 3508 /* read Tx power compensation for each Tx rate */ 3509 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3510 delta_2ghz = delta_5ghz = 0; 3511 if ((val & 0xff) != 0xff && (val & 0x80)) { 3512 delta_2ghz = val & 0xf; 3513 if (!(val & 0x40)) /* negative number */ 3514 delta_2ghz = -delta_2ghz; 3515 } 3516 val >>= 8; 3517 if ((val & 0xff) != 0xff && (val & 0x80)) { 3518 delta_5ghz = val & 0xf; 3519 if (!(val & 0x40)) /* negative number */ 3520 delta_5ghz = -delta_5ghz; 3521 } 3522 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3523 delta_2ghz, delta_5ghz)); 3524 3525 for (ridx = 0; ridx < 5; ridx++) { 3526 uint32_t reg; 3527 3528 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3529 reg = val; 3530 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3531 reg |= (uint32_t)val << 16; 3532 3533 sc->txpow20mhz[ridx] = reg; 3534 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3535 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3536 3537 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3538 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3539 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3540 } 3541 3542 /* read factory-calibrated samples for temperature compensation */ 3543 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3544 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3545 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3546 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3547 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3548 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3549 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3550 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3551 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3552 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3553 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3554 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3555 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3556 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3557 sc->step_2ghz = val >> 8; 3558 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3559 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3560 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3561 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3562 sc->tssi_2ghz[8], sc->step_2ghz)); 3563 /* check that ref value is correct, otherwise disable calibration */ 3564 if (sc->tssi_2ghz[4] == 0xff) 3565 sc->calib_2ghz = 0; 3566 3567 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3568 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3569 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3570 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3571 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3572 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3573 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3574 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3575 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3576 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3577 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3578 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3579 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3580 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3581 sc->step_5ghz = val >> 8; 3582 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3583 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3584 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3585 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3586 sc->tssi_5ghz[8], sc->step_5ghz)); 3587 /* check that ref value is correct, otherwise disable calibration */ 3588 if (sc->tssi_5ghz[4] == 0xff) 3589 sc->calib_5ghz = 0; 3590 3591 /* read RSSI offsets and LNA gains from EEPROM */ 3592 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3593 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3594 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3595 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3596 if (sc->mac_ver >= 0x3071) { 3597 /* 3598 * On RT3090 chips (limited to 2 Rx chains), this ROM 3599 * field contains the Tx mixer gain for the 2GHz band. 3600 */ 3601 if ((val & 0xff) != 0xff) 3602 sc->txmixgain_2ghz = val & 0x7; 3603 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3604 } else 3605 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3606 sc->lna[2] = val >> 8; /* channel group 2 */ 3607 3608 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3609 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3610 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3611 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3612 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3613 sc->lna[3] = val >> 8; /* channel group 3 */ 3614 3615 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3616 if (sc->mac_ver >= 0x3071) 3617 sc->lna[0] = RT3090_DEF_LNA; 3618 else /* channel group 0 */ 3619 sc->lna[0] = val & 0xff; 3620 sc->lna[1] = val >> 8; /* channel group 1 */ 3621 3622 /* fix broken 5GHz LNA entries */ 3623 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3624 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3625 sc->lna[2] = sc->lna[1]; 3626 } 3627 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3628 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3629 sc->lna[3] = sc->lna[1]; 3630 } 3631 3632 /* fix broken RSSI offset entries */ 3633 for (ant = 0; ant < 3; ant++) { 3634 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3635 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3636 ant + 1, sc->rssi_2ghz[ant])); 3637 sc->rssi_2ghz[ant] = 0; 3638 } 3639 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3640 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3641 ant + 1, sc->rssi_5ghz[ant])); 3642 sc->rssi_5ghz[ant] = 0; 3643 } 3644 } 3645 3646 return 0; 3647 } 3648 3649 static int 3650 rt2860_bbp_init(struct rt2860_softc *sc) 3651 { 3652 int i, ntries; 3653 3654 /* wait for BBP to wake up */ 3655 for (ntries = 0; ntries < 20; ntries++) { 3656 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3657 if (bbp0 != 0 && bbp0 != 0xff) 3658 break; 3659 } 3660 if (ntries == 20) { 3661 device_printf(sc->sc_dev, 3662 "timeout waiting for BBP to wake up\n"); 3663 return (ETIMEDOUT); 3664 } 3665 3666 /* initialize BBP registers to default values */ 3667 if (sc->mac_ver >= 0x5390) 3668 rt5390_bbp_init(sc); 3669 else { 3670 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3671 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3672 rt2860_def_bbp[i].val); 3673 } 3674 } 3675 3676 /* fix BBP84 for RT2860E */ 3677 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3678 rt2860_mcu_bbp_write(sc, 84, 0x19); 3679 3680 if (sc->mac_ver >= 0x3071) { 3681 rt2860_mcu_bbp_write(sc, 79, 0x13); 3682 rt2860_mcu_bbp_write(sc, 80, 0x05); 3683 rt2860_mcu_bbp_write(sc, 81, 0x33); 3684 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3685 rt2860_mcu_bbp_write(sc, 69, 0x16); 3686 rt2860_mcu_bbp_write(sc, 73, 0x12); 3687 } 3688 3689 return 0; 3690 } 3691 3692 static void 3693 rt5390_bbp_init(struct rt2860_softc *sc) 3694 { 3695 uint8_t bbp; 3696 int i; 3697 3698 /* Apply maximum likelihood detection for 2 stream case. */ 3699 if (sc->nrxchains > 1) { 3700 bbp = rt2860_mcu_bbp_read(sc, 105); 3701 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3702 } 3703 3704 /* Avoid data lost and CRC error. */ 3705 bbp = rt2860_mcu_bbp_read(sc, 4); 3706 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3707 3708 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3709 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3710 rt5390_def_bbp[i].val); 3711 } 3712 3713 if (sc->mac_ver == 0x5392) { 3714 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3715 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3716 rt2860_mcu_bbp_write(sc, 98, 0x12); 3717 rt2860_mcu_bbp_write(sc, 106, 0x05); 3718 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3719 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3720 } 3721 3722 bbp = rt2860_mcu_bbp_read(sc, 152); 3723 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3724 3725 /* Disable hardware antenna diversity. */ 3726 if (sc->mac_ver == 0x5390) 3727 rt2860_mcu_bbp_write(sc, 154, 0); 3728 } 3729 3730 static int 3731 rt2860_txrx_enable(struct rt2860_softc *sc) 3732 { 3733 struct ieee80211com *ic = &sc->sc_ic; 3734 uint32_t tmp; 3735 int ntries; 3736 3737 /* enable Tx/Rx DMA engine */ 3738 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3739 RAL_BARRIER_READ_WRITE(sc); 3740 for (ntries = 0; ntries < 200; ntries++) { 3741 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3742 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3743 break; 3744 DELAY(1000); 3745 } 3746 if (ntries == 200) { 3747 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3748 return ETIMEDOUT; 3749 } 3750 3751 DELAY(50); 3752 3753 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3754 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3755 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3756 3757 /* set Rx filter */ 3758 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3759 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3760 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3761 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3762 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3763 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3764 if (ic->ic_opmode == IEEE80211_M_STA) 3765 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3766 } 3767 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3768 3769 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3770 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3771 3772 return 0; 3773 } 3774 3775 static void 3776 rt2860_init(void *arg) 3777 { 3778 struct rt2860_softc *sc = arg; 3779 struct ieee80211com *ic = &sc->sc_ic; 3780 3781 RAL_LOCK(sc); 3782 rt2860_init_locked(sc); 3783 RAL_UNLOCK(sc); 3784 3785 if (sc->sc_flags & RT2860_RUNNING) 3786 ieee80211_start_all(ic); 3787 } 3788 3789 static void 3790 rt2860_init_locked(struct rt2860_softc *sc) 3791 { 3792 struct ieee80211com *ic = &sc->sc_ic; 3793 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3794 uint32_t tmp; 3795 uint8_t bbp1, bbp3; 3796 int i, qid, ridx, ntries, error; 3797 3798 RAL_LOCK_ASSERT(sc); 3799 3800 if (sc->rfswitch) { 3801 /* hardware has a radio switch on GPIO pin 2 */ 3802 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3803 device_printf(sc->sc_dev, 3804 "radio is disabled by hardware switch\n"); 3805 #ifdef notyet 3806 rt2860_stop_locked(sc); 3807 return; 3808 #endif 3809 } 3810 } 3811 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3812 3813 /* disable DMA */ 3814 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3815 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3816 RT2860_TX_DMA_EN); 3817 tmp |= RT2860_TX_WB_DDONE; 3818 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3819 3820 /* reset DMA indexes */ 3821 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3822 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3823 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3824 3825 /* PBF hardware reset */ 3826 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3827 RAL_BARRIER_WRITE(sc); 3828 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3829 3830 if ((error = rt2860_load_microcode(sc)) != 0) { 3831 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3832 rt2860_stop_locked(sc); 3833 return; 3834 } 3835 3836 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3837 3838 /* init Tx power for all Tx rates (from EEPROM) */ 3839 for (ridx = 0; ridx < 5; ridx++) { 3840 if (sc->txpow20mhz[ridx] == 0xffffffff) 3841 continue; 3842 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3843 } 3844 3845 for (ntries = 0; ntries < 100; ntries++) { 3846 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3847 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3848 break; 3849 DELAY(1000); 3850 } 3851 if (ntries == 100) { 3852 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3853 rt2860_stop_locked(sc); 3854 return; 3855 } 3856 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3857 RT2860_TX_DMA_EN); 3858 tmp |= RT2860_TX_WB_DDONE; 3859 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3860 3861 /* reset Rx ring and all 6 Tx rings */ 3862 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3863 3864 /* PBF hardware reset */ 3865 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3866 RAL_BARRIER_WRITE(sc); 3867 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3868 3869 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3870 3871 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3872 RAL_BARRIER_WRITE(sc); 3873 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3874 3875 for (i = 0; i < nitems(rt2860_def_mac); i++) 3876 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3877 if (sc->mac_ver >= 0x5390) 3878 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3879 else if (sc->mac_ver >= 0x3071) { 3880 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3881 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3882 4 << RT2860_DLY_PAPE_EN_SHIFT); 3883 } 3884 3885 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3886 sc->sc_flags |= RT2860_PCIE; 3887 /* PCIe has different clock cycle count than PCI */ 3888 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3889 tmp = (tmp & ~0xff) | 0x7d; 3890 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3891 } 3892 3893 /* wait while MAC is busy */ 3894 for (ntries = 0; ntries < 100; ntries++) { 3895 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3896 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3897 break; 3898 DELAY(1000); 3899 } 3900 if (ntries == 100) { 3901 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3902 rt2860_stop_locked(sc); 3903 return; 3904 } 3905 3906 /* clear Host to MCU mailbox */ 3907 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3908 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3909 3910 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3911 DELAY(1000); 3912 3913 if ((error = rt2860_bbp_init(sc)) != 0) { 3914 rt2860_stop_locked(sc); 3915 return; 3916 } 3917 3918 /* clear RX WCID search table */ 3919 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3920 /* clear pairwise key table */ 3921 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3922 /* clear IV/EIV table */ 3923 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3924 /* clear WCID attribute table */ 3925 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3926 /* clear shared key table */ 3927 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3928 /* clear shared key mode */ 3929 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3930 3931 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3932 for (qid = 0; qid < 6; qid++) { 3933 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3934 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3935 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3936 } 3937 3938 /* init Rx ring */ 3939 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3940 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3941 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3942 3943 /* setup maximum buffer sizes */ 3944 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3945 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3946 3947 for (ntries = 0; ntries < 100; ntries++) { 3948 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3949 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3950 break; 3951 DELAY(1000); 3952 } 3953 if (ntries == 100) { 3954 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3955 rt2860_stop_locked(sc); 3956 return; 3957 } 3958 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3959 RT2860_TX_DMA_EN); 3960 tmp |= RT2860_TX_WB_DDONE; 3961 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3962 3963 /* disable interrupts mitigation */ 3964 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3965 3966 /* write vendor-specific BBP values (from EEPROM) */ 3967 for (i = 0; i < 8; i++) { 3968 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3969 continue; 3970 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3971 } 3972 3973 /* select Main antenna for 1T1R devices */ 3974 if (sc->rf_rev == RT3070_RF_2020 || 3975 sc->rf_rev == RT3070_RF_3020 || 3976 sc->rf_rev == RT3070_RF_3320 || 3977 sc->mac_ver == 0x5390) 3978 rt3090_set_rx_antenna(sc, 0); 3979 3980 /* send LEDs operating mode to microcontroller */ 3981 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3982 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3983 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3984 3985 if (sc->mac_ver >= 0x5390) 3986 rt5390_rf_init(sc); 3987 else if (sc->mac_ver >= 0x3071) { 3988 if ((error = rt3090_rf_init(sc)) != 0) { 3989 rt2860_stop_locked(sc); 3990 return; 3991 } 3992 } 3993 3994 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3995 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3996 3997 if (sc->mac_ver >= 0x5390) 3998 rt5390_rf_wakeup(sc); 3999 else if (sc->mac_ver >= 0x3071) 4000 rt3090_rf_wakeup(sc); 4001 4002 /* disable non-existing Rx chains */ 4003 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4004 bbp3 &= ~(1 << 3 | 1 << 4); 4005 if (sc->nrxchains == 2) 4006 bbp3 |= 1 << 3; 4007 else if (sc->nrxchains == 3) 4008 bbp3 |= 1 << 4; 4009 rt2860_mcu_bbp_write(sc, 3, bbp3); 4010 4011 /* disable non-existing Tx chains */ 4012 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4013 if (sc->ntxchains == 1) 4014 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4015 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4016 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4017 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4018 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4019 rt2860_mcu_bbp_write(sc, 1, bbp1); 4020 4021 if (sc->mac_ver >= 0x3071) 4022 rt3090_rf_setup(sc); 4023 4024 /* select default channel */ 4025 rt2860_switch_chan(sc, ic->ic_curchan); 4026 4027 /* reset RF from MCU */ 4028 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4029 4030 /* set RTS threshold */ 4031 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4032 tmp &= ~0xffff00; 4033 tmp |= IEEE80211_RTS_DEFAULT << 8; 4034 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4035 4036 /* setup initial protection mode */ 4037 rt2860_updateprot(sc); 4038 4039 /* turn radio LED on */ 4040 rt2860_set_leds(sc, RT2860_LED_RADIO); 4041 4042 /* enable Tx/Rx DMA engine */ 4043 if ((error = rt2860_txrx_enable(sc)) != 0) { 4044 rt2860_stop_locked(sc); 4045 return; 4046 } 4047 4048 /* clear pending interrupts */ 4049 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4050 /* enable interrupts */ 4051 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4052 4053 if (sc->sc_flags & RT2860_ADVANCED_PS) 4054 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4055 4056 sc->sc_flags |= RT2860_RUNNING; 4057 4058 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4059 } 4060 4061 static void 4062 rt2860_stop(void *arg) 4063 { 4064 struct rt2860_softc *sc = arg; 4065 4066 RAL_LOCK(sc); 4067 rt2860_stop_locked(sc); 4068 RAL_UNLOCK(sc); 4069 } 4070 4071 static void 4072 rt2860_stop_locked(struct rt2860_softc *sc) 4073 { 4074 uint32_t tmp; 4075 int qid; 4076 4077 if (sc->sc_flags & RT2860_RUNNING) 4078 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4079 4080 callout_stop(&sc->watchdog_ch); 4081 sc->sc_tx_timer = 0; 4082 sc->sc_flags &= ~RT2860_RUNNING; 4083 4084 /* disable interrupts */ 4085 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4086 4087 /* disable GP timer */ 4088 rt2860_set_gp_timer(sc, 0); 4089 4090 /* disable Rx */ 4091 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4092 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4093 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4094 4095 /* reset adapter */ 4096 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4097 RAL_BARRIER_WRITE(sc); 4098 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4099 4100 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4101 sc->qfullmsk = 0; 4102 for (qid = 0; qid < 6; qid++) 4103 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4104 rt2860_reset_rx_ring(sc, &sc->rxq); 4105 } 4106 4107 int 4108 rt2860_load_microcode(struct rt2860_softc *sc) 4109 { 4110 const struct firmware *fp; 4111 int ntries, error; 4112 4113 RAL_LOCK_ASSERT(sc); 4114 4115 RAL_UNLOCK(sc); 4116 fp = firmware_get("rt2860fw"); 4117 RAL_LOCK(sc); 4118 if (fp == NULL) { 4119 device_printf(sc->sc_dev, 4120 "unable to receive rt2860fw firmware image\n"); 4121 return EINVAL; 4122 } 4123 4124 /* set "host program ram write selection" bit */ 4125 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4126 /* write microcode image */ 4127 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4128 /* kick microcontroller unit */ 4129 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4130 RAL_BARRIER_WRITE(sc); 4131 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4132 4133 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4134 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4135 4136 /* wait until microcontroller is ready */ 4137 RAL_BARRIER_READ_WRITE(sc); 4138 for (ntries = 0; ntries < 1000; ntries++) { 4139 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4140 break; 4141 DELAY(1000); 4142 } 4143 if (ntries == 1000) { 4144 device_printf(sc->sc_dev, 4145 "timeout waiting for MCU to initialize\n"); 4146 error = ETIMEDOUT; 4147 } else 4148 error = 0; 4149 4150 firmware_put(fp, FIRMWARE_UNLOAD); 4151 return error; 4152 } 4153 4154 /* 4155 * This function is called periodically to adjust Tx power based on 4156 * temperature variation. 4157 */ 4158 #ifdef NOT_YET 4159 static void 4160 rt2860_calib(struct rt2860_softc *sc) 4161 { 4162 struct ieee80211com *ic = &sc->sc_ic; 4163 const uint8_t *tssi; 4164 uint8_t step, bbp49; 4165 int8_t ridx, d; 4166 4167 /* read current temperature */ 4168 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4169 4170 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4171 tssi = &sc->tssi_2ghz[4]; 4172 step = sc->step_2ghz; 4173 } else { 4174 tssi = &sc->tssi_5ghz[4]; 4175 step = sc->step_5ghz; 4176 } 4177 4178 if (bbp49 < tssi[0]) { /* lower than reference */ 4179 /* use higher Tx power than default */ 4180 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4181 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4182 /* use lower Tx power than default */ 4183 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4184 } else { 4185 /* use default Tx power */ 4186 d = 0; 4187 } 4188 d *= step; 4189 4190 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4191 4192 /* write adjusted Tx power values for each Tx rate */ 4193 for (ridx = 0; ridx < 5; ridx++) { 4194 if (sc->txpow20mhz[ridx] == 0xffffffff) 4195 continue; 4196 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4197 b4inc(sc->txpow20mhz[ridx], d)); 4198 } 4199 } 4200 #endif 4201 4202 static void 4203 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4204 { 4205 uint32_t tmp; 4206 4207 if (aux) { 4208 if (sc->mac_ver == 0x5390) { 4209 rt2860_mcu_bbp_write(sc, 152, 4210 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4211 } else { 4212 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4213 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4214 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4215 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4216 } 4217 } else { 4218 if (sc->mac_ver == 0x5390) { 4219 rt2860_mcu_bbp_write(sc, 152, 4220 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4221 } else { 4222 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4223 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4224 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4225 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4226 } 4227 } 4228 } 4229 4230 static void 4231 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4232 { 4233 struct ieee80211com *ic = &sc->sc_ic; 4234 u_int chan, group; 4235 4236 chan = ieee80211_chan2ieee(ic, c); 4237 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4238 return; 4239 4240 if (sc->mac_ver >= 0x5390) 4241 rt5390_set_chan(sc, chan); 4242 else if (sc->mac_ver >= 0x3071) 4243 rt3090_set_chan(sc, chan); 4244 else 4245 rt2860_set_chan(sc, chan); 4246 4247 /* determine channel group */ 4248 if (chan <= 14) 4249 group = 0; 4250 else if (chan <= 64) 4251 group = 1; 4252 else if (chan <= 128) 4253 group = 2; 4254 else 4255 group = 3; 4256 4257 /* XXX necessary only when group has changed! */ 4258 if (sc->mac_ver < 0x5390) 4259 rt2860_select_chan_group(sc, group); 4260 4261 DELAY(1000); 4262 } 4263 4264 static int 4265 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4266 { 4267 struct ieee80211com *ic = vap->iv_ic; 4268 struct rt2860_txwi txwi; 4269 struct mbuf *m; 4270 int ridx; 4271 4272 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4273 return ENOBUFS; 4274 4275 memset(&txwi, 0, sizeof txwi); 4276 txwi.wcid = 0xff; 4277 txwi.len = htole16(m->m_pkthdr.len); 4278 /* send beacons at the lowest available rate */ 4279 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4280 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4281 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4282 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4283 txwi.phy |= htole16(RT2860_PHY_OFDM); 4284 txwi.txop = RT2860_TX_TXOP_HT; 4285 txwi.flags = RT2860_TX_TS; 4286 txwi.xflags = RT2860_TX_NSEQ; 4287 4288 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4289 (uint8_t *)&txwi, sizeof txwi); 4290 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4291 mtod(m, uint8_t *), m->m_pkthdr.len); 4292 4293 m_freem(m); 4294 4295 return 0; 4296 } 4297 4298 static void 4299 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4300 { 4301 struct ieee80211com *ic = &sc->sc_ic; 4302 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4303 uint32_t tmp; 4304 4305 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4306 4307 tmp &= ~0x1fffff; 4308 tmp |= vap->iv_bss->ni_intval * 16; 4309 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4310 if (vap->iv_opmode == IEEE80211_M_STA) { 4311 /* 4312 * Local TSF is always updated with remote TSF on beacon 4313 * reception. 4314 */ 4315 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4316 } 4317 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4318 vap->iv_opmode == IEEE80211_M_MBSS) { 4319 tmp |= RT2860_BCN_TX_EN; 4320 /* 4321 * Local TSF is updated with remote TSF on beacon reception 4322 * only if the remote TSF is greater than local TSF. 4323 */ 4324 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4325 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4326 tmp |= RT2860_BCN_TX_EN; 4327 /* SYNC with nobody */ 4328 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4329 } 4330 4331 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4332 } 4333