1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /*- 24 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 56 #include <net80211/ieee80211_var.h> 57 #include <net80211/ieee80211_radiotap.h> 58 #include <net80211/ieee80211_regdomain.h> 59 #include <net80211/ieee80211_ratectl.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_ether.h> 66 67 #include <dev/ral/rt2860reg.h> 68 #include <dev/ral/rt2860var.h> 69 70 #define RAL_DEBUG 71 #ifdef RAL_DEBUG 72 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 73 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n, x) 77 #endif 78 79 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 80 const char [IFNAMSIZ], int, enum ieee80211_opmode, 81 int, const uint8_t [IEEE80211_ADDR_LEN], 82 const uint8_t [IEEE80211_ADDR_LEN]); 83 static void rt2860_vap_delete(struct ieee80211vap *); 84 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 85 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_reset_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static void rt2860_free_tx_ring(struct rt2860_softc *, 90 struct rt2860_tx_ring *); 91 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 92 static void rt2860_free_tx_pool(struct rt2860_softc *); 93 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_reset_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_free_rx_ring(struct rt2860_softc *, 98 struct rt2860_rx_ring *); 99 static void rt2860_updatestats(struct rt2860_softc *); 100 static void rt2860_newassoc(struct ieee80211_node *, int); 101 static void rt2860_node_free(struct ieee80211_node *); 102 #ifdef IEEE80211_HT 103 static int rt2860_ampdu_rx_start(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 106 struct ieee80211_node *, uint8_t); 107 #endif 108 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 109 int); 110 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 111 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 112 static void rt2860_intr_coherent(struct rt2860_softc *); 113 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 114 static void rt2860_tx_intr(struct rt2860_softc *, int); 115 static void rt2860_rx_intr(struct rt2860_softc *); 116 static void rt2860_tbtt_intr(struct rt2860_softc *); 117 static void rt2860_gp_intr(struct rt2860_softc *); 118 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 119 struct ieee80211_node *); 120 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 121 const struct ieee80211_bpf_params *); 122 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 123 struct ieee80211_node *, 124 const struct ieee80211_bpf_params *params); 125 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 126 static void rt2860_start(struct rt2860_softc *); 127 static void rt2860_watchdog(void *); 128 static void rt2860_parent(struct ieee80211com *); 129 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 130 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 131 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 132 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 133 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 134 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 135 static void rt2860_enable_mrr(struct rt2860_softc *); 136 static void rt2860_set_txpreamble(struct rt2860_softc *); 137 static void rt2860_set_basicrates(struct rt2860_softc *, 138 const struct ieee80211_rateset *); 139 static void rt2860_scan_start(struct ieee80211com *); 140 static void rt2860_scan_end(struct ieee80211com *); 141 static void rt2860_set_channel(struct ieee80211com *); 142 static void rt2860_select_chan_group(struct rt2860_softc *, int); 143 static void rt2860_set_chan(struct rt2860_softc *, u_int); 144 static void rt3090_set_chan(struct rt2860_softc *, u_int); 145 static void rt5390_set_chan(struct rt2860_softc *, u_int); 146 static int rt3090_rf_init(struct rt2860_softc *); 147 static void rt5390_rf_init(struct rt2860_softc *); 148 static void rt3090_rf_wakeup(struct rt2860_softc *); 149 static void rt5390_rf_wakeup(struct rt2860_softc *); 150 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 151 uint8_t *); 152 static void rt3090_rf_setup(struct rt2860_softc *); 153 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 154 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 155 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 156 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 157 static void rt2860_update_promisc(struct ieee80211com *); 158 static void rt2860_updateslot(struct ieee80211com *); 159 static void rt2860_updateprot(struct rt2860_softc *); 160 static int rt2860_updateedca(struct ieee80211com *); 161 #ifdef HW_CRYPTO 162 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 163 struct ieee80211_key *); 164 static void rt2860_delete_key(struct ieee80211com *, 165 struct ieee80211_node *, struct ieee80211_key *); 166 #endif 167 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 168 static const char *rt2860_get_rf(uint8_t); 169 static int rt2860_read_eeprom(struct rt2860_softc *, 170 uint8_t macaddr[IEEE80211_ADDR_LEN]); 171 static int rt2860_bbp_init(struct rt2860_softc *); 172 static void rt5390_bbp_init(struct rt2860_softc *); 173 static int rt2860_txrx_enable(struct rt2860_softc *); 174 static void rt2860_init(void *); 175 static void rt2860_init_locked(struct rt2860_softc *); 176 static void rt2860_stop(void *); 177 static void rt2860_stop_locked(struct rt2860_softc *); 178 static int rt2860_load_microcode(struct rt2860_softc *); 179 #ifdef NOT_YET 180 static void rt2860_calib(struct rt2860_softc *); 181 #endif 182 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 183 static void rt2860_switch_chan(struct rt2860_softc *, 184 struct ieee80211_channel *); 185 static int rt2860_setup_beacon(struct rt2860_softc *, 186 struct ieee80211vap *); 187 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 188 189 static const struct { 190 uint32_t reg; 191 uint32_t val; 192 } rt2860_def_mac[] = { 193 RT2860_DEF_MAC 194 }; 195 196 static const struct { 197 uint8_t reg; 198 uint8_t val; 199 } rt2860_def_bbp[] = { 200 RT2860_DEF_BBP 201 }, rt5390_def_bbp[] = { 202 RT5390_DEF_BBP 203 }; 204 205 static const struct rfprog { 206 uint8_t chan; 207 uint32_t r1, r2, r3, r4; 208 } rt2860_rf2850[] = { 209 RT2860_RF2850 210 }; 211 212 struct { 213 uint8_t n, r, k; 214 } rt3090_freqs[] = { 215 RT3070_RF3052 216 }; 217 218 static const struct { 219 uint8_t reg; 220 uint8_t val; 221 } rt3090_def_rf[] = { 222 RT3070_DEF_RF 223 }, rt5390_def_rf[] = { 224 RT5390_DEF_RF 225 }, rt5392_def_rf[] = { 226 RT5392_DEF_RF 227 }; 228 229 int 230 rt2860_attach(device_t dev, int id) 231 { 232 struct rt2860_softc *sc = device_get_softc(dev); 233 struct ieee80211com *ic = &sc->sc_ic; 234 uint32_t tmp; 235 int error, ntries, qid; 236 uint8_t bands; 237 238 sc->sc_dev = dev; 239 sc->sc_debug = 0; 240 241 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 242 MTX_DEF | MTX_RECURSE); 243 244 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 245 mbufq_init(&sc->sc_snd, ifqmaxlen); 246 247 /* wait for NIC to initialize */ 248 for (ntries = 0; ntries < 100; ntries++) { 249 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 250 if (tmp != 0 && tmp != 0xffffffff) 251 break; 252 DELAY(10); 253 } 254 if (ntries == 100) { 255 device_printf(sc->sc_dev, 256 "timeout waiting for NIC to initialize\n"); 257 error = EIO; 258 goto fail1; 259 } 260 sc->mac_ver = tmp >> 16; 261 sc->mac_rev = tmp & 0xffff; 262 263 if (sc->mac_ver != 0x2860 && 264 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 265 sc->sc_flags |= RT2860_ADVANCED_PS; 266 267 /* retrieve RF rev. no and various other things from EEPROM */ 268 rt2860_read_eeprom(sc, ic->ic_macaddr); 269 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 270 "RF %s (MIMO %dT%dR), address %6D\n", 271 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 272 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 273 274 /* 275 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 276 */ 277 for (qid = 0; qid < 6; qid++) { 278 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 279 device_printf(sc->sc_dev, 280 "could not allocate Tx ring %d\n", qid); 281 goto fail2; 282 } 283 } 284 285 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 286 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 287 goto fail2; 288 } 289 290 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 291 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 292 goto fail3; 293 } 294 295 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 296 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 297 WME_AC_VO : 5; 298 299 ic->ic_softc = sc; 300 ic->ic_name = device_get_nameunit(dev); 301 ic->ic_opmode = IEEE80211_M_STA; 302 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 303 304 /* set device capabilities */ 305 ic->ic_caps = 306 IEEE80211_C_STA /* station mode */ 307 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 308 | IEEE80211_C_HOSTAP /* hostap mode */ 309 | IEEE80211_C_MONITOR /* monitor mode */ 310 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 311 | IEEE80211_C_WDS /* 4-address traffic works */ 312 | IEEE80211_C_MBSS /* mesh point link mode */ 313 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 314 | IEEE80211_C_SHSLOT /* short slot time supported */ 315 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 316 #if 0 317 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 318 #endif 319 | IEEE80211_C_WME /* 802.11e */ 320 ; 321 322 bands = 0; 323 setbit(&bands, IEEE80211_MODE_11B); 324 setbit(&bands, IEEE80211_MODE_11G); 325 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) 326 setbit(&bands, IEEE80211_MODE_11A); 327 ieee80211_init_channels(ic, NULL, &bands); 328 329 ieee80211_ifattach(ic); 330 331 ic->ic_wme.wme_update = rt2860_updateedca; 332 ic->ic_scan_start = rt2860_scan_start; 333 ic->ic_scan_end = rt2860_scan_end; 334 ic->ic_set_channel = rt2860_set_channel; 335 ic->ic_updateslot = rt2860_updateslot; 336 ic->ic_update_promisc = rt2860_update_promisc; 337 ic->ic_raw_xmit = rt2860_raw_xmit; 338 sc->sc_node_free = ic->ic_node_free; 339 ic->ic_node_free = rt2860_node_free; 340 ic->ic_newassoc = rt2860_newassoc; 341 ic->ic_transmit = rt2860_transmit; 342 ic->ic_parent = rt2860_parent; 343 ic->ic_vap_create = rt2860_vap_create; 344 ic->ic_vap_delete = rt2860_vap_delete; 345 346 ieee80211_radiotap_attach(ic, 347 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 348 RT2860_TX_RADIOTAP_PRESENT, 349 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 350 RT2860_RX_RADIOTAP_PRESENT); 351 352 #ifdef RAL_DEBUG 353 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 354 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 355 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 356 #endif 357 if (bootverbose) 358 ieee80211_announce(ic); 359 360 return 0; 361 362 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 363 fail2: while (--qid >= 0) 364 rt2860_free_tx_ring(sc, &sc->txq[qid]); 365 fail1: mtx_destroy(&sc->sc_mtx); 366 return error; 367 } 368 369 int 370 rt2860_detach(void *xsc) 371 { 372 struct rt2860_softc *sc = xsc; 373 struct ieee80211com *ic = &sc->sc_ic; 374 int qid; 375 376 RAL_LOCK(sc); 377 rt2860_stop_locked(sc); 378 RAL_UNLOCK(sc); 379 380 ieee80211_ifdetach(ic); 381 mbufq_drain(&sc->sc_snd); 382 for (qid = 0; qid < 6; qid++) 383 rt2860_free_tx_ring(sc, &sc->txq[qid]); 384 rt2860_free_rx_ring(sc, &sc->rxq); 385 rt2860_free_tx_pool(sc); 386 387 mtx_destroy(&sc->sc_mtx); 388 389 return 0; 390 } 391 392 void 393 rt2860_shutdown(void *xsc) 394 { 395 struct rt2860_softc *sc = xsc; 396 397 rt2860_stop(sc); 398 } 399 400 void 401 rt2860_suspend(void *xsc) 402 { 403 struct rt2860_softc *sc = xsc; 404 405 rt2860_stop(sc); 406 } 407 408 void 409 rt2860_resume(void *xsc) 410 { 411 struct rt2860_softc *sc = xsc; 412 413 if (sc->sc_ic.ic_nrunning > 0) 414 rt2860_init(sc); 415 } 416 417 static struct ieee80211vap * 418 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 419 enum ieee80211_opmode opmode, int flags, 420 const uint8_t bssid[IEEE80211_ADDR_LEN], 421 const uint8_t mac[IEEE80211_ADDR_LEN]) 422 { 423 struct rt2860_softc *sc = ic->ic_softc; 424 struct rt2860_vap *rvp; 425 struct ieee80211vap *vap; 426 427 switch (opmode) { 428 case IEEE80211_M_STA: 429 case IEEE80211_M_IBSS: 430 case IEEE80211_M_AHDEMO: 431 case IEEE80211_M_MONITOR: 432 case IEEE80211_M_HOSTAP: 433 case IEEE80211_M_MBSS: 434 /* XXXRP: TBD */ 435 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 436 device_printf(sc->sc_dev, "only 1 vap supported\n"); 437 return NULL; 438 } 439 if (opmode == IEEE80211_M_STA) 440 flags |= IEEE80211_CLONE_NOBEACONS; 441 break; 442 case IEEE80211_M_WDS: 443 if (TAILQ_EMPTY(&ic->ic_vaps) || 444 ic->ic_opmode != IEEE80211_M_HOSTAP) { 445 device_printf(sc->sc_dev, 446 "wds only supported in ap mode\n"); 447 return NULL; 448 } 449 /* 450 * Silently remove any request for a unique 451 * bssid; WDS vap's always share the local 452 * mac address. 453 */ 454 flags &= ~IEEE80211_CLONE_BSSID; 455 break; 456 default: 457 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 458 return NULL; 459 } 460 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 461 vap = &rvp->ral_vap; 462 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 463 464 /* override state transition machine */ 465 rvp->ral_newstate = vap->iv_newstate; 466 vap->iv_newstate = rt2860_newstate; 467 #if 0 468 vap->iv_update_beacon = rt2860_beacon_update; 469 #endif 470 471 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 472 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 473 474 ieee80211_ratectl_init(vap); 475 /* complete setup */ 476 ieee80211_vap_attach(vap, ieee80211_media_change, 477 ieee80211_media_status, mac); 478 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 479 ic->ic_opmode = opmode; 480 return vap; 481 } 482 483 static void 484 rt2860_vap_delete(struct ieee80211vap *vap) 485 { 486 struct rt2860_vap *rvp = RT2860_VAP(vap); 487 488 ieee80211_ratectl_deinit(vap); 489 ieee80211_vap_detach(vap); 490 free(rvp, M_80211_VAP); 491 } 492 493 static void 494 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 495 { 496 if (error != 0) 497 return; 498 499 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 500 501 *(bus_addr_t *)arg = segs[0].ds_addr; 502 } 503 504 505 static int 506 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 507 { 508 int size, error; 509 510 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 511 512 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 513 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 514 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not create desc DMA map\n"); 517 goto fail; 518 } 519 520 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 521 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 522 if (error != 0) { 523 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 524 goto fail; 525 } 526 527 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 528 size, rt2860_dma_map_addr, &ring->paddr, 0); 529 if (error != 0) { 530 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 531 goto fail; 532 } 533 534 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 535 536 return 0; 537 538 fail: rt2860_free_tx_ring(sc, ring); 539 return error; 540 } 541 542 void 543 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 544 { 545 struct rt2860_tx_data *data; 546 int i; 547 548 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 549 if ((data = ring->data[i]) == NULL) 550 continue; /* nothing mapped in this slot */ 551 552 if (data->m != NULL) { 553 bus_dmamap_sync(sc->txwi_dmat, data->map, 554 BUS_DMASYNC_POSTWRITE); 555 bus_dmamap_unload(sc->txwi_dmat, data->map); 556 m_freem(data->m); 557 data->m = NULL; 558 } 559 if (data->ni != NULL) { 560 ieee80211_free_node(data->ni); 561 data->ni = NULL; 562 } 563 564 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 565 ring->data[i] = NULL; 566 } 567 568 ring->queued = 0; 569 ring->cur = ring->next = 0; 570 } 571 572 void 573 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 574 { 575 struct rt2860_tx_data *data; 576 int i; 577 578 if (ring->txd != NULL) { 579 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 580 BUS_DMASYNC_POSTWRITE); 581 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 582 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 583 } 584 if (ring->desc_dmat != NULL) 585 bus_dma_tag_destroy(ring->desc_dmat); 586 587 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 588 if ((data = ring->data[i]) == NULL) 589 continue; /* nothing mapped in this slot */ 590 591 if (data->m != NULL) { 592 bus_dmamap_sync(sc->txwi_dmat, data->map, 593 BUS_DMASYNC_POSTWRITE); 594 bus_dmamap_unload(sc->txwi_dmat, data->map); 595 m_freem(data->m); 596 } 597 if (data->ni != NULL) 598 ieee80211_free_node(data->ni); 599 600 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 601 } 602 } 603 604 /* 605 * Allocate a pool of TX Wireless Information blocks. 606 */ 607 int 608 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 609 { 610 caddr_t vaddr; 611 bus_addr_t paddr; 612 int i, size, error; 613 614 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 615 616 /* init data_pool early in case of failure.. */ 617 SLIST_INIT(&sc->data_pool); 618 619 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 620 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 621 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 622 if (error != 0) { 623 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 624 goto fail; 625 } 626 627 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 628 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 629 if (error != 0) { 630 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 631 goto fail; 632 } 633 634 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 635 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 636 if (error != 0) { 637 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 638 goto fail; 639 } 640 641 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 642 643 vaddr = sc->txwi_vaddr; 644 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 645 struct rt2860_tx_data *data = &sc->data[i]; 646 647 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 648 if (error != 0) { 649 device_printf(sc->sc_dev, "could not create DMA map\n"); 650 goto fail; 651 } 652 data->txwi = (struct rt2860_txwi *)vaddr; 653 data->paddr = paddr; 654 vaddr += RT2860_TXWI_DMASZ; 655 paddr += RT2860_TXWI_DMASZ; 656 657 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 658 } 659 660 return 0; 661 662 fail: rt2860_free_tx_pool(sc); 663 return error; 664 } 665 666 void 667 rt2860_free_tx_pool(struct rt2860_softc *sc) 668 { 669 if (sc->txwi_vaddr != NULL) { 670 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 671 BUS_DMASYNC_POSTWRITE); 672 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 673 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 674 } 675 if (sc->txwi_dmat != NULL) 676 bus_dma_tag_destroy(sc->txwi_dmat); 677 678 while (!SLIST_EMPTY(&sc->data_pool)) { 679 struct rt2860_tx_data *data; 680 data = SLIST_FIRST(&sc->data_pool); 681 bus_dmamap_destroy(sc->txwi_dmat, data->map); 682 SLIST_REMOVE_HEAD(&sc->data_pool, next); 683 } 684 } 685 686 int 687 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 688 { 689 bus_addr_t physaddr; 690 int i, size, error; 691 692 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 693 694 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 695 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 696 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 697 if (error != 0) { 698 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 699 goto fail; 700 } 701 702 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 703 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 704 if (error != 0) { 705 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 706 goto fail; 707 } 708 709 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 710 size, rt2860_dma_map_addr, &ring->paddr, 0); 711 if (error != 0) { 712 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 713 goto fail; 714 } 715 716 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 717 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 718 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 719 if (error != 0) { 720 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 721 goto fail; 722 } 723 724 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 725 struct rt2860_rx_data *data = &ring->data[i]; 726 struct rt2860_rxd *rxd = &ring->rxd[i]; 727 728 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 729 if (error != 0) { 730 device_printf(sc->sc_dev, "could not create DMA map\n"); 731 goto fail; 732 } 733 734 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 735 if (data->m == NULL) { 736 device_printf(sc->sc_dev, 737 "could not allocate rx mbuf\n"); 738 error = ENOMEM; 739 goto fail; 740 } 741 742 error = bus_dmamap_load(ring->data_dmat, data->map, 743 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 744 &physaddr, 0); 745 if (error != 0) { 746 device_printf(sc->sc_dev, 747 "could not load rx buf DMA map"); 748 goto fail; 749 } 750 751 rxd->sdp0 = htole32(physaddr); 752 rxd->sdl0 = htole16(MCLBYTES); 753 } 754 755 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 756 757 return 0; 758 759 fail: rt2860_free_rx_ring(sc, ring); 760 return error; 761 } 762 763 void 764 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 765 { 766 int i; 767 768 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 769 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 770 771 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 772 773 ring->cur = 0; 774 } 775 776 void 777 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 778 { 779 int i; 780 781 if (ring->rxd != NULL) { 782 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 783 BUS_DMASYNC_POSTWRITE); 784 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 785 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 786 } 787 if (ring->desc_dmat != NULL) 788 bus_dma_tag_destroy(ring->desc_dmat); 789 790 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 791 struct rt2860_rx_data *data = &ring->data[i]; 792 793 if (data->m != NULL) { 794 bus_dmamap_sync(ring->data_dmat, data->map, 795 BUS_DMASYNC_POSTREAD); 796 bus_dmamap_unload(ring->data_dmat, data->map); 797 m_freem(data->m); 798 } 799 if (data->map != NULL) 800 bus_dmamap_destroy(ring->data_dmat, data->map); 801 } 802 if (ring->data_dmat != NULL) 803 bus_dma_tag_destroy(ring->data_dmat); 804 } 805 806 static void 807 rt2860_updatestats(struct rt2860_softc *sc) 808 { 809 struct ieee80211com *ic = &sc->sc_ic; 810 811 /* 812 * In IBSS or HostAP modes (when the hardware sends beacons), the 813 * MAC can run into a livelock and start sending CTS-to-self frames 814 * like crazy if protection is enabled. Fortunately, we can detect 815 * when such a situation occurs and reset the MAC. 816 */ 817 if (ic->ic_curmode != IEEE80211_M_STA) { 818 /* check if we're in a livelock situation.. */ 819 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 820 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 821 /* ..and reset MAC/BBP for a while.. */ 822 DPRINTF(("CTS-to-self livelock detected\n")); 823 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 824 RAL_BARRIER_WRITE(sc); 825 DELAY(1); 826 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 827 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 828 } 829 } 830 } 831 832 static void 833 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 834 { 835 struct ieee80211com *ic = ni->ni_ic; 836 struct rt2860_softc *sc = ic->ic_softc; 837 uint8_t wcid; 838 839 wcid = IEEE80211_AID(ni->ni_associd); 840 if (isnew && ni->ni_associd != 0) { 841 sc->wcid2ni[wcid] = ni; 842 843 /* init WCID table entry */ 844 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 845 ni->ni_macaddr, IEEE80211_ADDR_LEN); 846 } 847 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 848 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 849 } 850 851 static void 852 rt2860_node_free(struct ieee80211_node *ni) 853 { 854 struct ieee80211com *ic = ni->ni_ic; 855 struct rt2860_softc *sc = ic->ic_softc; 856 uint8_t wcid; 857 858 if (ni->ni_associd != 0) { 859 wcid = IEEE80211_AID(ni->ni_associd); 860 861 /* clear Rx WCID search table entry */ 862 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 863 } 864 sc->sc_node_free(ni); 865 } 866 867 #ifdef IEEE80211_HT 868 static int 869 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 870 uint8_t tid) 871 { 872 struct rt2860_softc *sc = ic->ic_softc; 873 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 874 uint32_t tmp; 875 876 /* update BA session mask */ 877 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 878 tmp |= (1 << tid) << 16; 879 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 880 return 0; 881 } 882 883 static void 884 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 885 uint8_t tid) 886 { 887 struct rt2860_softc *sc = ic->ic_softc; 888 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 889 uint32_t tmp; 890 891 /* update BA session mask */ 892 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 893 tmp &= ~((1 << tid) << 16); 894 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 895 } 896 #endif 897 898 int 899 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 900 { 901 struct rt2860_vap *rvp = RT2860_VAP(vap); 902 struct ieee80211com *ic = vap->iv_ic; 903 struct rt2860_softc *sc = ic->ic_softc; 904 uint32_t tmp; 905 int error; 906 907 if (vap->iv_state == IEEE80211_S_RUN) { 908 /* turn link LED off */ 909 rt2860_set_leds(sc, RT2860_LED_RADIO); 910 } 911 912 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 913 /* abort TSF synchronization */ 914 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 915 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 916 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 917 RT2860_TBTT_TIMER_EN)); 918 } 919 920 rt2860_set_gp_timer(sc, 0); 921 922 error = rvp->ral_newstate(vap, nstate, arg); 923 if (error != 0) 924 return (error); 925 926 if (nstate == IEEE80211_S_RUN) { 927 struct ieee80211_node *ni = vap->iv_bss; 928 929 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 930 rt2860_enable_mrr(sc); 931 rt2860_set_txpreamble(sc); 932 rt2860_set_basicrates(sc, &ni->ni_rates); 933 rt2860_set_bssid(sc, ni->ni_bssid); 934 } 935 936 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 937 vap->iv_opmode == IEEE80211_M_IBSS || 938 vap->iv_opmode == IEEE80211_M_MBSS) { 939 error = rt2860_setup_beacon(sc, vap); 940 if (error != 0) 941 return error; 942 } 943 944 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 945 rt2860_enable_tsf_sync(sc); 946 rt2860_set_gp_timer(sc, 500); 947 } 948 949 /* turn link LED on */ 950 rt2860_set_leds(sc, RT2860_LED_RADIO | 951 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 952 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 953 } 954 return error; 955 } 956 957 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 958 static uint16_t 959 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 960 { 961 uint32_t tmp; 962 uint16_t reg; 963 int ntries; 964 965 addr *= 2; 966 /*- 967 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 968 * DATA0: F E D C 969 * DATA1: B A 9 8 970 * DATA2: 7 6 5 4 971 * DATA3: 3 2 1 0 972 */ 973 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 974 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 975 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 976 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 977 for (ntries = 0; ntries < 500; ntries++) { 978 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 979 if (!(tmp & RT3070_EFSROM_KICK)) 980 break; 981 DELAY(2); 982 } 983 if (ntries == 500) 984 return 0xffff; 985 986 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 987 return 0xffff; /* address not found */ 988 989 /* determine to which 32-bit register our 16-bit word belongs */ 990 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 991 tmp = RAL_READ(sc, reg); 992 993 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 994 } 995 996 /* 997 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 998 * 93C66 or 93C86). 999 */ 1000 static uint16_t 1001 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1002 { 1003 uint32_t tmp; 1004 uint16_t val; 1005 int n; 1006 1007 /* clock C once before the first command */ 1008 RT2860_EEPROM_CTL(sc, 0); 1009 1010 RT2860_EEPROM_CTL(sc, RT2860_S); 1011 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1012 RT2860_EEPROM_CTL(sc, RT2860_S); 1013 1014 /* write start bit (1) */ 1015 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1016 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1017 1018 /* write READ opcode (10) */ 1019 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1020 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1021 RT2860_EEPROM_CTL(sc, RT2860_S); 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1023 1024 /* write address (A5-A0 or A7-A0) */ 1025 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1026 for (; n >= 0; n--) { 1027 RT2860_EEPROM_CTL(sc, RT2860_S | 1028 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1029 RT2860_EEPROM_CTL(sc, RT2860_S | 1030 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1031 } 1032 1033 RT2860_EEPROM_CTL(sc, RT2860_S); 1034 1035 /* read data Q15-Q0 */ 1036 val = 0; 1037 for (n = 15; n >= 0; n--) { 1038 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1039 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1040 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1041 RT2860_EEPROM_CTL(sc, RT2860_S); 1042 } 1043 1044 RT2860_EEPROM_CTL(sc, 0); 1045 1046 /* clear Chip Select and clock C */ 1047 RT2860_EEPROM_CTL(sc, RT2860_S); 1048 RT2860_EEPROM_CTL(sc, 0); 1049 RT2860_EEPROM_CTL(sc, RT2860_C); 1050 1051 return val; 1052 } 1053 1054 static __inline uint16_t 1055 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1056 { 1057 /* either eFUSE ROM or EEPROM */ 1058 return sc->sc_srom_read(sc, addr); 1059 } 1060 1061 static void 1062 rt2860_intr_coherent(struct rt2860_softc *sc) 1063 { 1064 uint32_t tmp; 1065 1066 /* DMA finds data coherent event when checking the DDONE bit */ 1067 1068 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1069 1070 /* restart DMA engine */ 1071 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1072 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1073 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1074 1075 (void)rt2860_txrx_enable(sc); 1076 } 1077 1078 static void 1079 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1080 { 1081 struct ieee80211_node *ni; 1082 uint32_t stat; 1083 int retrycnt; 1084 uint8_t wcid, mcs, pid; 1085 1086 /* drain Tx status FIFO (maxsize = 16) */ 1087 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1088 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1089 1090 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1091 ni = sc->wcid2ni[wcid]; 1092 1093 /* if no ACK was requested, no feedback is available */ 1094 if (!(stat & RT2860_TXQ_ACKREQ) || wcid == 0xff || ni == NULL) 1095 continue; 1096 1097 /* update per-STA AMRR stats */ 1098 if (stat & RT2860_TXQ_OK) { 1099 /* 1100 * Check if there were retries, ie if the Tx success 1101 * rate is different from the requested rate. Note 1102 * that it works only because we do not allow rate 1103 * fallback from OFDM to CCK. 1104 */ 1105 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1106 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1107 if (mcs + 1 != pid) 1108 retrycnt = 1; 1109 else 1110 retrycnt = 0; 1111 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1112 IEEE80211_RATECTL_TX_SUCCESS, &retrycnt, NULL); 1113 } else { 1114 ieee80211_ratectl_tx_complete(ni->ni_vap, ni, 1115 IEEE80211_RATECTL_TX_FAILURE, &retrycnt, NULL); 1116 if_inc_counter(ni->ni_vap->iv_ifp, 1117 IFCOUNTER_OERRORS, 1); 1118 } 1119 } 1120 } 1121 1122 static void 1123 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1124 { 1125 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1126 uint32_t hw; 1127 1128 rt2860_drain_stats_fifo(sc); 1129 1130 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1131 while (ring->next != hw) { 1132 struct rt2860_tx_data *data = ring->data[ring->next]; 1133 1134 if (data != NULL) { 1135 bus_dmamap_sync(sc->txwi_dmat, data->map, 1136 BUS_DMASYNC_POSTWRITE); 1137 bus_dmamap_unload(sc->txwi_dmat, data->map); 1138 if (data->m->m_flags & M_TXCB) { 1139 ieee80211_process_callback(data->ni, data->m, 1140 0); 1141 } 1142 ieee80211_tx_complete(data->ni, data->m, 0); 1143 data->ni = NULL; 1144 data->m = NULL; 1145 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1146 ring->data[ring->next] = NULL; 1147 } 1148 ring->queued--; 1149 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1150 } 1151 1152 sc->sc_tx_timer = 0; 1153 if (ring->queued < RT2860_TX_RING_COUNT) 1154 sc->qfullmsk &= ~(1 << qid); 1155 rt2860_start(sc); 1156 } 1157 1158 /* 1159 * Return the Rx chain with the highest RSSI for a given frame. 1160 */ 1161 static __inline uint8_t 1162 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1163 { 1164 uint8_t rxchain = 0; 1165 1166 if (sc->nrxchains > 1) { 1167 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1168 rxchain = 1; 1169 if (sc->nrxchains > 2) 1170 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1171 rxchain = 2; 1172 } 1173 return rxchain; 1174 } 1175 1176 static void 1177 rt2860_rx_intr(struct rt2860_softc *sc) 1178 { 1179 struct rt2860_rx_radiotap_header *tap; 1180 struct ieee80211com *ic = &sc->sc_ic; 1181 struct ieee80211_frame *wh; 1182 struct ieee80211_node *ni; 1183 struct mbuf *m, *m1; 1184 bus_addr_t physaddr; 1185 uint32_t hw; 1186 uint16_t phy; 1187 uint8_t ant; 1188 int8_t rssi, nf; 1189 int error; 1190 1191 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1192 while (sc->rxq.cur != hw) { 1193 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1194 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1195 struct rt2860_rxwi *rxwi; 1196 1197 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1198 BUS_DMASYNC_POSTREAD); 1199 1200 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1201 DPRINTF(("RXD DDONE bit not set!\n")); 1202 break; /* should not happen */ 1203 } 1204 1205 if (__predict_false(rxd->flags & 1206 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1207 counter_u64_add(ic->ic_ierrors, 1); 1208 goto skip; 1209 } 1210 1211 #ifdef HW_CRYPTO 1212 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1213 /* report MIC failures to net80211 for TKIP */ 1214 ic->ic_stats.is_rx_locmicfail++; 1215 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1216 counter_u64_add(ic->ic_ierrors, 1); 1217 goto skip; 1218 } 1219 #endif 1220 1221 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1222 if (__predict_false(m1 == NULL)) { 1223 counter_u64_add(ic->ic_ierrors, 1); 1224 goto skip; 1225 } 1226 1227 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1228 BUS_DMASYNC_POSTREAD); 1229 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1230 1231 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1232 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1233 &physaddr, 0); 1234 if (__predict_false(error != 0)) { 1235 m_freem(m1); 1236 1237 /* try to reload the old mbuf */ 1238 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1239 mtod(data->m, void *), MCLBYTES, 1240 rt2860_dma_map_addr, &physaddr, 0); 1241 if (__predict_false(error != 0)) { 1242 panic("%s: could not load old rx mbuf", 1243 device_get_name(sc->sc_dev)); 1244 } 1245 /* physical address may have changed */ 1246 rxd->sdp0 = htole32(physaddr); 1247 counter_u64_add(ic->ic_ierrors, 1); 1248 goto skip; 1249 } 1250 1251 /* 1252 * New mbuf successfully loaded, update Rx ring and continue 1253 * processing. 1254 */ 1255 m = data->m; 1256 data->m = m1; 1257 rxd->sdp0 = htole32(physaddr); 1258 1259 rxwi = mtod(m, struct rt2860_rxwi *); 1260 1261 /* finalize mbuf */ 1262 m->m_data = (caddr_t)(rxwi + 1); 1263 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1264 1265 wh = mtod(m, struct ieee80211_frame *); 1266 #ifdef HW_CRYPTO 1267 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1268 /* frame is decrypted by hardware */ 1269 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1270 } 1271 #endif 1272 1273 /* HW may insert 2 padding bytes after 802.11 header */ 1274 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1275 u_int hdrlen = ieee80211_hdrsize(wh); 1276 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1277 m->m_data += 2; 1278 wh = mtod(m, struct ieee80211_frame *); 1279 } 1280 1281 ant = rt2860_maxrssi_chain(sc, rxwi); 1282 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1283 nf = RT2860_NOISE_FLOOR; 1284 1285 if (ieee80211_radiotap_active(ic)) { 1286 tap = &sc->sc_rxtap; 1287 tap->wr_flags = 0; 1288 tap->wr_antenna = ant; 1289 tap->wr_antsignal = nf + rssi; 1290 tap->wr_antnoise = nf; 1291 /* in case it can't be found below */ 1292 tap->wr_rate = 2; 1293 phy = le16toh(rxwi->phy); 1294 switch (phy & RT2860_PHY_MODE) { 1295 case RT2860_PHY_CCK: 1296 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1297 case 0: tap->wr_rate = 2; break; 1298 case 1: tap->wr_rate = 4; break; 1299 case 2: tap->wr_rate = 11; break; 1300 case 3: tap->wr_rate = 22; break; 1301 } 1302 if (phy & RT2860_PHY_SHPRE) 1303 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1304 break; 1305 case RT2860_PHY_OFDM: 1306 switch (phy & RT2860_PHY_MCS) { 1307 case 0: tap->wr_rate = 12; break; 1308 case 1: tap->wr_rate = 18; break; 1309 case 2: tap->wr_rate = 24; break; 1310 case 3: tap->wr_rate = 36; break; 1311 case 4: tap->wr_rate = 48; break; 1312 case 5: tap->wr_rate = 72; break; 1313 case 6: tap->wr_rate = 96; break; 1314 case 7: tap->wr_rate = 108; break; 1315 } 1316 break; 1317 } 1318 } 1319 1320 RAL_UNLOCK(sc); 1321 wh = mtod(m, struct ieee80211_frame *); 1322 1323 /* send the frame to the 802.11 layer */ 1324 ni = ieee80211_find_rxnode(ic, 1325 (struct ieee80211_frame_min *)wh); 1326 if (ni != NULL) { 1327 (void)ieee80211_input(ni, m, rssi - nf, nf); 1328 ieee80211_free_node(ni); 1329 } else 1330 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1331 1332 RAL_LOCK(sc); 1333 1334 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1335 1336 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1337 BUS_DMASYNC_PREWRITE); 1338 1339 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1340 } 1341 1342 /* tell HW what we have processed */ 1343 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1344 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1345 } 1346 1347 static void 1348 rt2860_tbtt_intr(struct rt2860_softc *sc) 1349 { 1350 #if 0 1351 struct ieee80211com *ic = &sc->sc_ic; 1352 1353 #ifndef IEEE80211_STA_ONLY 1354 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1355 /* one less beacon until next DTIM */ 1356 if (ic->ic_dtim_count == 0) 1357 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1358 else 1359 ic->ic_dtim_count--; 1360 1361 /* update dynamic parts of beacon */ 1362 rt2860_setup_beacon(sc); 1363 1364 /* flush buffered multicast frames */ 1365 if (ic->ic_dtim_count == 0) 1366 ieee80211_notify_dtim(ic); 1367 } 1368 #endif 1369 /* check if protection mode has changed */ 1370 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1371 rt2860_updateprot(sc); 1372 sc->sc_ic_flags = ic->ic_flags; 1373 } 1374 #endif 1375 } 1376 1377 static void 1378 rt2860_gp_intr(struct rt2860_softc *sc) 1379 { 1380 struct ieee80211com *ic = &sc->sc_ic; 1381 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1382 1383 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1384 1385 if (vap->iv_state == IEEE80211_S_RUN) 1386 rt2860_updatestats(sc); 1387 } 1388 1389 void 1390 rt2860_intr(void *arg) 1391 { 1392 struct rt2860_softc *sc = arg; 1393 uint32_t r; 1394 1395 RAL_LOCK(sc); 1396 1397 r = RAL_READ(sc, RT2860_INT_STATUS); 1398 if (__predict_false(r == 0xffffffff)) { 1399 RAL_UNLOCK(sc); 1400 return; /* device likely went away */ 1401 } 1402 if (r == 0) { 1403 RAL_UNLOCK(sc); 1404 return; /* not for us */ 1405 } 1406 1407 /* acknowledge interrupts */ 1408 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1409 1410 if (r & RT2860_TX_RX_COHERENT) 1411 rt2860_intr_coherent(sc); 1412 1413 if (r & RT2860_MAC_INT_2) /* TX status */ 1414 rt2860_drain_stats_fifo(sc); 1415 1416 if (r & RT2860_TX_DONE_INT5) 1417 rt2860_tx_intr(sc, 5); 1418 1419 if (r & RT2860_RX_DONE_INT) 1420 rt2860_rx_intr(sc); 1421 1422 if (r & RT2860_TX_DONE_INT4) 1423 rt2860_tx_intr(sc, 4); 1424 1425 if (r & RT2860_TX_DONE_INT3) 1426 rt2860_tx_intr(sc, 3); 1427 1428 if (r & RT2860_TX_DONE_INT2) 1429 rt2860_tx_intr(sc, 2); 1430 1431 if (r & RT2860_TX_DONE_INT1) 1432 rt2860_tx_intr(sc, 1); 1433 1434 if (r & RT2860_TX_DONE_INT0) 1435 rt2860_tx_intr(sc, 0); 1436 1437 if (r & RT2860_MAC_INT_0) /* TBTT */ 1438 rt2860_tbtt_intr(sc); 1439 1440 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1441 /* TBD wakeup */; 1442 1443 if (r & RT2860_MAC_INT_4) /* GP timer */ 1444 rt2860_gp_intr(sc); 1445 1446 RAL_UNLOCK(sc); 1447 } 1448 1449 static int 1450 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1451 { 1452 struct ieee80211com *ic = &sc->sc_ic; 1453 struct ieee80211vap *vap = ni->ni_vap; 1454 struct rt2860_tx_ring *ring; 1455 struct rt2860_tx_data *data; 1456 struct rt2860_txd *txd; 1457 struct rt2860_txwi *txwi; 1458 struct ieee80211_frame *wh; 1459 const struct ieee80211_txparam *tp; 1460 struct ieee80211_key *k; 1461 struct mbuf *m1; 1462 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1463 bus_dma_segment_t *seg; 1464 u_int hdrlen; 1465 uint16_t qos, dur; 1466 uint8_t type, qsel, mcs, pid, tid, qid; 1467 int i, nsegs, ntxds, pad, rate, ridx, error; 1468 1469 /* the data pool contains at least one element, pick the first */ 1470 data = SLIST_FIRST(&sc->data_pool); 1471 1472 wh = mtod(m, struct ieee80211_frame *); 1473 1474 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1475 k = ieee80211_crypto_encap(ni, m); 1476 if (k == NULL) { 1477 m_freem(m); 1478 return ENOBUFS; 1479 } 1480 1481 /* packet header may have moved, reset our local pointer */ 1482 wh = mtod(m, struct ieee80211_frame *); 1483 } 1484 1485 hdrlen = ieee80211_anyhdrsize(wh); 1486 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1487 1488 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1489 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1490 rate = tp->mcastrate; 1491 } else if (m->m_flags & M_EAPOL) { 1492 rate = tp->mgmtrate; 1493 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1494 rate = tp->ucastrate; 1495 } else { 1496 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1497 rate = ni->ni_txrate; 1498 } 1499 rate &= IEEE80211_RATE_VAL; 1500 1501 qid = M_WME_GETAC(m); 1502 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1503 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1504 tid = qos & IEEE80211_QOS_TID; 1505 } else { 1506 qos = 0; 1507 tid = 0; 1508 } 1509 ring = &sc->txq[qid]; 1510 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1511 1512 /* get MCS code from rate index */ 1513 mcs = rt2860_rates[ridx].mcs; 1514 1515 /* setup TX Wireless Information */ 1516 txwi = data->txwi; 1517 txwi->flags = 0; 1518 /* let HW generate seq numbers for non-QoS frames */ 1519 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1520 if (type == IEEE80211_FC0_TYPE_DATA) 1521 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1522 else 1523 txwi->wcid = 0xff; 1524 txwi->len = htole16(m->m_pkthdr.len); 1525 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1526 txwi->phy = htole16(RT2860_PHY_CCK); 1527 if (ridx != RT2860_RIDX_CCK1 && 1528 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1529 mcs |= RT2860_PHY_SHPRE; 1530 } else 1531 txwi->phy = htole16(RT2860_PHY_OFDM); 1532 txwi->phy |= htole16(mcs); 1533 1534 /* 1535 * We store the MCS code into the driver-private PacketID field. 1536 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1537 * that we know at which initial rate the frame was transmitted. 1538 * We add 1 to the MCS code because setting the PacketID field to 1539 * 0 means that we don't want feedback in TX_STAT_FIFO. 1540 */ 1541 pid = (mcs + 1) & 0xf; 1542 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1543 1544 /* check if RTS/CTS or CTS-to-self protection is required */ 1545 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1546 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1547 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1548 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1549 txwi->txop = RT2860_TX_TXOP_HT; 1550 else 1551 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1552 1553 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1554 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1555 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1556 txwi->xflags |= RT2860_TX_ACK; 1557 1558 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1559 dur = rt2860_rates[ridx].sp_ack_dur; 1560 else 1561 dur = rt2860_rates[ridx].lp_ack_dur; 1562 *(uint16_t *)wh->i_dur = htole16(dur); 1563 } 1564 /* ask MAC to insert timestamp into probe responses */ 1565 if ((wh->i_fc[0] & 1566 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1567 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1568 /* NOTE: beacons do not pass through tx_data() */ 1569 txwi->flags |= RT2860_TX_TS; 1570 1571 if (ieee80211_radiotap_active_vap(vap)) { 1572 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1573 1574 tap->wt_flags = 0; 1575 tap->wt_rate = rate; 1576 if (mcs & RT2860_PHY_SHPRE) 1577 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1578 1579 ieee80211_radiotap_tx(vap, m); 1580 } 1581 1582 pad = (hdrlen + 3) & ~3; 1583 1584 /* copy and trim 802.11 header */ 1585 memcpy(txwi + 1, wh, hdrlen); 1586 m_adj(m, hdrlen); 1587 1588 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1589 &nsegs, 0); 1590 if (__predict_false(error != 0 && error != EFBIG)) { 1591 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1592 error); 1593 m_freem(m); 1594 return error; 1595 } 1596 if (__predict_true(error == 0)) { 1597 /* determine how many TXDs are required */ 1598 ntxds = 1 + (nsegs / 2); 1599 1600 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1601 /* not enough free TXDs, force mbuf defrag */ 1602 bus_dmamap_unload(sc->txwi_dmat, data->map); 1603 error = EFBIG; 1604 } 1605 } 1606 if (__predict_false(error != 0)) { 1607 m1 = m_defrag(m, M_NOWAIT); 1608 if (m1 == NULL) { 1609 device_printf(sc->sc_dev, 1610 "could not defragment mbuf\n"); 1611 m_freem(m); 1612 return ENOBUFS; 1613 } 1614 m = m1; 1615 1616 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1617 segs, &nsegs, 0); 1618 if (__predict_false(error != 0)) { 1619 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1620 error); 1621 m_freem(m); 1622 return error; 1623 } 1624 1625 /* determine how many TXDs are now required */ 1626 ntxds = 1 + (nsegs / 2); 1627 1628 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1629 /* this is a hopeless case, drop the mbuf! */ 1630 bus_dmamap_unload(sc->txwi_dmat, data->map); 1631 m_freem(m); 1632 return ENOBUFS; 1633 } 1634 } 1635 1636 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1637 1638 /* first segment is TXWI + 802.11 header */ 1639 txd = &ring->txd[ring->cur]; 1640 txd->sdp0 = htole32(data->paddr); 1641 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1642 txd->flags = qsel; 1643 1644 /* setup payload segments */ 1645 seg = &segs[0]; 1646 for (i = nsegs; i >= 2; i -= 2) { 1647 txd->sdp1 = htole32(seg->ds_addr); 1648 txd->sdl1 = htole16(seg->ds_len); 1649 seg++; 1650 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1651 /* grab a new Tx descriptor */ 1652 txd = &ring->txd[ring->cur]; 1653 txd->sdp0 = htole32(seg->ds_addr); 1654 txd->sdl0 = htole16(seg->ds_len); 1655 txd->flags = qsel; 1656 seg++; 1657 } 1658 /* finalize last segment */ 1659 if (i > 0) { 1660 txd->sdp1 = htole32(seg->ds_addr); 1661 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1662 } else { 1663 txd->sdl0 |= htole16(RT2860_TX_LS0); 1664 txd->sdl1 = 0; 1665 } 1666 1667 /* remove from the free pool and link it into the SW Tx slot */ 1668 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1669 data->m = m; 1670 data->ni = ni; 1671 ring->data[ring->cur] = data; 1672 1673 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1674 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1675 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1676 1677 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1678 qid, txwi->wcid, nsegs, ridx)); 1679 1680 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1681 ring->queued += ntxds; 1682 if (ring->queued >= RT2860_TX_RING_COUNT) 1683 sc->qfullmsk |= 1 << qid; 1684 1685 /* kick Tx */ 1686 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1687 1688 return 0; 1689 } 1690 1691 static int 1692 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1693 const struct ieee80211_bpf_params *params) 1694 { 1695 struct ieee80211com *ic = ni->ni_ic; 1696 struct rt2860_softc *sc = ic->ic_softc; 1697 int error; 1698 1699 RAL_LOCK(sc); 1700 1701 /* prevent management frames from being sent if we're not ready */ 1702 if (!(sc->sc_flags & RT2860_RUNNNING)) { 1703 RAL_UNLOCK(sc); 1704 m_freem(m); 1705 return ENETDOWN; 1706 } 1707 if (params == NULL) { 1708 /* 1709 * Legacy path; interpret frame contents to decide 1710 * precisely how to send the frame. 1711 */ 1712 error = rt2860_tx(sc, m, ni); 1713 } else { 1714 /* 1715 * Caller supplied explicit parameters to use in 1716 * sending the frame. 1717 */ 1718 error = rt2860_tx_raw(sc, m, ni, params); 1719 } 1720 sc->sc_tx_timer = 5; 1721 RAL_UNLOCK(sc); 1722 return error; 1723 } 1724 1725 static int 1726 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1727 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1728 { 1729 struct ieee80211com *ic = &sc->sc_ic; 1730 struct ieee80211vap *vap = ni->ni_vap; 1731 struct rt2860_tx_ring *ring; 1732 struct rt2860_tx_data *data; 1733 struct rt2860_txd *txd; 1734 struct rt2860_txwi *txwi; 1735 struct ieee80211_frame *wh; 1736 struct mbuf *m1; 1737 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1738 bus_dma_segment_t *seg; 1739 u_int hdrlen; 1740 uint16_t dur; 1741 uint8_t type, qsel, mcs, pid, tid, qid; 1742 int i, nsegs, ntxds, pad, rate, ridx, error; 1743 1744 /* the data pool contains at least one element, pick the first */ 1745 data = SLIST_FIRST(&sc->data_pool); 1746 1747 wh = mtod(m, struct ieee80211_frame *); 1748 hdrlen = ieee80211_hdrsize(wh); 1749 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1750 1751 /* Choose a TX rate index. */ 1752 rate = params->ibp_rate0; 1753 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1754 rate & IEEE80211_RATE_VAL); 1755 if (ridx == (uint8_t)-1) { 1756 /* XXX fall back to mcast/mgmt rate? */ 1757 m_freem(m); 1758 return EINVAL; 1759 } 1760 1761 qid = params->ibp_pri & 3; 1762 tid = 0; 1763 ring = &sc->txq[qid]; 1764 1765 /* get MCS code from rate index */ 1766 mcs = rt2860_rates[ridx].mcs; 1767 1768 /* setup TX Wireless Information */ 1769 txwi = data->txwi; 1770 txwi->flags = 0; 1771 /* let HW generate seq numbers for non-QoS frames */ 1772 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1773 txwi->wcid = 0xff; 1774 txwi->len = htole16(m->m_pkthdr.len); 1775 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1776 txwi->phy = htole16(RT2860_PHY_CCK); 1777 if (ridx != RT2860_RIDX_CCK1 && 1778 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1779 mcs |= RT2860_PHY_SHPRE; 1780 } else 1781 txwi->phy = htole16(RT2860_PHY_OFDM); 1782 txwi->phy |= htole16(mcs); 1783 1784 /* 1785 * We store the MCS code into the driver-private PacketID field. 1786 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1787 * that we know at which initial rate the frame was transmitted. 1788 * We add 1 to the MCS code because setting the PacketID field to 1789 * 0 means that we don't want feedback in TX_STAT_FIFO. 1790 */ 1791 pid = (mcs + 1) & 0xf; 1792 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1793 1794 /* check if RTS/CTS or CTS-to-self protection is required */ 1795 if (params->ibp_flags & IEEE80211_BPF_RTS || 1796 params->ibp_flags & IEEE80211_BPF_CTS) 1797 txwi->txop = RT2860_TX_TXOP_HT; 1798 else 1799 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1800 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1801 txwi->xflags |= RT2860_TX_ACK; 1802 1803 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1804 dur = rt2860_rates[ridx].sp_ack_dur; 1805 else 1806 dur = rt2860_rates[ridx].lp_ack_dur; 1807 *(uint16_t *)wh->i_dur = htole16(dur); 1808 } 1809 /* ask MAC to insert timestamp into probe responses */ 1810 if ((wh->i_fc[0] & 1811 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1812 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1813 /* NOTE: beacons do not pass through tx_data() */ 1814 txwi->flags |= RT2860_TX_TS; 1815 1816 if (ieee80211_radiotap_active_vap(vap)) { 1817 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1818 1819 tap->wt_flags = 0; 1820 tap->wt_rate = rate; 1821 if (mcs & RT2860_PHY_SHPRE) 1822 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1823 1824 ieee80211_radiotap_tx(vap, m); 1825 } 1826 1827 pad = (hdrlen + 3) & ~3; 1828 1829 /* copy and trim 802.11 header */ 1830 memcpy(txwi + 1, wh, hdrlen); 1831 m_adj(m, hdrlen); 1832 1833 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1834 &nsegs, 0); 1835 if (__predict_false(error != 0 && error != EFBIG)) { 1836 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1837 error); 1838 m_freem(m); 1839 return error; 1840 } 1841 if (__predict_true(error == 0)) { 1842 /* determine how many TXDs are required */ 1843 ntxds = 1 + (nsegs / 2); 1844 1845 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1846 /* not enough free TXDs, force mbuf defrag */ 1847 bus_dmamap_unload(sc->txwi_dmat, data->map); 1848 error = EFBIG; 1849 } 1850 } 1851 if (__predict_false(error != 0)) { 1852 m1 = m_defrag(m, M_NOWAIT); 1853 if (m1 == NULL) { 1854 device_printf(sc->sc_dev, 1855 "could not defragment mbuf\n"); 1856 m_freem(m); 1857 return ENOBUFS; 1858 } 1859 m = m1; 1860 1861 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1862 segs, &nsegs, 0); 1863 if (__predict_false(error != 0)) { 1864 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1865 error); 1866 m_freem(m); 1867 return error; 1868 } 1869 1870 /* determine how many TXDs are now required */ 1871 ntxds = 1 + (nsegs / 2); 1872 1873 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1874 /* this is a hopeless case, drop the mbuf! */ 1875 bus_dmamap_unload(sc->txwi_dmat, data->map); 1876 m_freem(m); 1877 return ENOBUFS; 1878 } 1879 } 1880 1881 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1882 1883 /* first segment is TXWI + 802.11 header */ 1884 txd = &ring->txd[ring->cur]; 1885 txd->sdp0 = htole32(data->paddr); 1886 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1887 txd->flags = qsel; 1888 1889 /* setup payload segments */ 1890 seg = &segs[0]; 1891 for (i = nsegs; i >= 2; i -= 2) { 1892 txd->sdp1 = htole32(seg->ds_addr); 1893 txd->sdl1 = htole16(seg->ds_len); 1894 seg++; 1895 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1896 /* grab a new Tx descriptor */ 1897 txd = &ring->txd[ring->cur]; 1898 txd->sdp0 = htole32(seg->ds_addr); 1899 txd->sdl0 = htole16(seg->ds_len); 1900 txd->flags = qsel; 1901 seg++; 1902 } 1903 /* finalize last segment */ 1904 if (i > 0) { 1905 txd->sdp1 = htole32(seg->ds_addr); 1906 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1907 } else { 1908 txd->sdl0 |= htole16(RT2860_TX_LS0); 1909 txd->sdl1 = 0; 1910 } 1911 1912 /* remove from the free pool and link it into the SW Tx slot */ 1913 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1914 data->m = m; 1915 data->ni = ni; 1916 ring->data[ring->cur] = data; 1917 1918 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1919 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1920 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1921 1922 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1923 qid, txwi->wcid, nsegs, ridx)); 1924 1925 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1926 ring->queued += ntxds; 1927 if (ring->queued >= RT2860_TX_RING_COUNT) 1928 sc->qfullmsk |= 1 << qid; 1929 1930 /* kick Tx */ 1931 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1932 1933 return 0; 1934 } 1935 1936 static int 1937 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1938 { 1939 struct rt2860_softc *sc = ic->ic_softc; 1940 int error; 1941 1942 RAL_LOCK(sc); 1943 if ((sc->sc_flags & RT2860_RUNNNING) == 0) { 1944 RAL_UNLOCK(sc); 1945 return (ENXIO); 1946 } 1947 error = mbufq_enqueue(&sc->sc_snd, m); 1948 if (error) { 1949 RAL_UNLOCK(sc); 1950 return (error); 1951 } 1952 rt2860_start(sc); 1953 RAL_UNLOCK(sc); 1954 1955 return (0); 1956 } 1957 1958 static void 1959 rt2860_start(struct rt2860_softc *sc) 1960 { 1961 struct ieee80211_node *ni; 1962 struct mbuf *m; 1963 1964 RAL_LOCK_ASSERT(sc); 1965 1966 if ((sc->sc_flags & RT2860_RUNNNING) == 0) 1967 return; 1968 1969 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1970 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1971 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1972 if (rt2860_tx(sc, m, ni) != 0) { 1973 if_inc_counter(ni->ni_vap->iv_ifp, 1974 IFCOUNTER_OERRORS, 1); 1975 ieee80211_free_node(ni); 1976 continue; 1977 } 1978 sc->sc_tx_timer = 5; 1979 } 1980 } 1981 1982 static void 1983 rt2860_watchdog(void *arg) 1984 { 1985 struct rt2860_softc *sc = arg; 1986 1987 RAL_LOCK_ASSERT(sc); 1988 1989 KASSERT(sc->sc_flags & RT2860_RUNNNING, ("not running")); 1990 1991 if (sc->sc_invalid) /* card ejected */ 1992 return; 1993 1994 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1995 device_printf(sc->sc_dev, "device timeout\n"); 1996 rt2860_stop_locked(sc); 1997 rt2860_init_locked(sc); 1998 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1999 return; 2000 } 2001 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2002 } 2003 2004 static void 2005 rt2860_parent(struct ieee80211com *ic) 2006 { 2007 struct rt2860_softc *sc = ic->ic_softc; 2008 int startall = 0; 2009 2010 RAL_LOCK(sc); 2011 if (ic->ic_nrunning> 0) { 2012 if (!(sc->sc_flags & RT2860_RUNNNING)) { 2013 rt2860_init_locked(sc); 2014 startall = 1; 2015 } else 2016 rt2860_update_promisc(ic); 2017 } else if (sc->sc_flags & RT2860_RUNNNING) 2018 rt2860_stop_locked(sc); 2019 RAL_UNLOCK(sc); 2020 if (startall) 2021 ieee80211_start_all(ic); 2022 } 2023 2024 /* 2025 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2026 * We access the BBP through the 8051 microcontroller unit which means that 2027 * the microcode must be loaded first. 2028 */ 2029 void 2030 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2031 { 2032 int ntries; 2033 2034 for (ntries = 0; ntries < 100; ntries++) { 2035 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2036 break; 2037 DELAY(1); 2038 } 2039 if (ntries == 100) { 2040 device_printf(sc->sc_dev, 2041 "could not write to BBP through MCU\n"); 2042 return; 2043 } 2044 2045 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2046 RT2860_BBP_CSR_KICK | reg << 8 | val); 2047 RAL_BARRIER_WRITE(sc); 2048 2049 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2050 DELAY(1000); 2051 } 2052 2053 uint8_t 2054 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2055 { 2056 uint32_t val; 2057 int ntries; 2058 2059 for (ntries = 0; ntries < 100; ntries++) { 2060 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2061 break; 2062 DELAY(1); 2063 } 2064 if (ntries == 100) { 2065 device_printf(sc->sc_dev, 2066 "could not read from BBP through MCU\n"); 2067 return 0; 2068 } 2069 2070 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2071 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2072 RAL_BARRIER_WRITE(sc); 2073 2074 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2075 DELAY(1000); 2076 2077 for (ntries = 0; ntries < 100; ntries++) { 2078 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2079 if (!(val & RT2860_BBP_CSR_KICK)) 2080 return val & 0xff; 2081 DELAY(1); 2082 } 2083 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2084 2085 return 0; 2086 } 2087 2088 /* 2089 * Write to one of the 4 programmable 24-bit RF registers. 2090 */ 2091 static void 2092 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2093 { 2094 uint32_t tmp; 2095 int ntries; 2096 2097 for (ntries = 0; ntries < 100; ntries++) { 2098 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2099 break; 2100 DELAY(1); 2101 } 2102 if (ntries == 100) { 2103 device_printf(sc->sc_dev, "could not write to RF\n"); 2104 return; 2105 } 2106 2107 /* RF registers are 24-bit on the RT2860 */ 2108 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2109 (val & 0x3fffff) << 2 | (reg & 3); 2110 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2111 } 2112 2113 static uint8_t 2114 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2115 { 2116 uint32_t tmp; 2117 int ntries; 2118 2119 for (ntries = 0; ntries < 100; ntries++) { 2120 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2121 break; 2122 DELAY(1); 2123 } 2124 if (ntries == 100) { 2125 device_printf(sc->sc_dev, "could not read RF register\n"); 2126 return 0xff; 2127 } 2128 tmp = RT3070_RF_KICK | reg << 8; 2129 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2130 2131 for (ntries = 0; ntries < 100; ntries++) { 2132 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2133 if (!(tmp & RT3070_RF_KICK)) 2134 break; 2135 DELAY(1); 2136 } 2137 if (ntries == 100) { 2138 device_printf(sc->sc_dev, "could not read RF register\n"); 2139 return 0xff; 2140 } 2141 return tmp & 0xff; 2142 } 2143 2144 void 2145 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2146 { 2147 uint32_t tmp; 2148 int ntries; 2149 2150 for (ntries = 0; ntries < 10; ntries++) { 2151 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2152 break; 2153 DELAY(10); 2154 } 2155 if (ntries == 10) { 2156 device_printf(sc->sc_dev, "could not write to RF\n"); 2157 return; 2158 } 2159 2160 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2161 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2162 } 2163 2164 /* 2165 * Send a command to the 8051 microcontroller unit. 2166 */ 2167 int 2168 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2169 { 2170 int slot, ntries; 2171 uint32_t tmp; 2172 uint8_t cid; 2173 2174 for (ntries = 0; ntries < 100; ntries++) { 2175 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2176 break; 2177 DELAY(2); 2178 } 2179 if (ntries == 100) 2180 return EIO; 2181 2182 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2183 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2184 RAL_BARRIER_WRITE(sc); 2185 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2186 2187 if (!wait) 2188 return 0; 2189 /* wait for the command to complete */ 2190 for (ntries = 0; ntries < 200; ntries++) { 2191 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2192 /* find the command slot */ 2193 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2194 if ((tmp & 0xff) == cid) 2195 break; 2196 if (slot < 4) 2197 break; 2198 DELAY(100); 2199 } 2200 if (ntries == 200) { 2201 /* clear command and status */ 2202 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2203 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2204 return ETIMEDOUT; 2205 } 2206 /* get command status (1 means success) */ 2207 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2208 tmp = (tmp >> (slot * 8)) & 0xff; 2209 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2210 cmd, slot, tmp)); 2211 /* clear command and status */ 2212 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2213 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2214 return (tmp == 1) ? 0 : EIO; 2215 } 2216 2217 static void 2218 rt2860_enable_mrr(struct rt2860_softc *sc) 2219 { 2220 #define CCK(mcs) (mcs) 2221 #define OFDM(mcs) (1 << 3 | (mcs)) 2222 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2223 OFDM(6) << 28 | /* 54->48 */ 2224 OFDM(5) << 24 | /* 48->36 */ 2225 OFDM(4) << 20 | /* 36->24 */ 2226 OFDM(3) << 16 | /* 24->18 */ 2227 OFDM(2) << 12 | /* 18->12 */ 2228 OFDM(1) << 8 | /* 12-> 9 */ 2229 OFDM(0) << 4 | /* 9-> 6 */ 2230 OFDM(0)); /* 6-> 6 */ 2231 2232 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2233 CCK(2) << 12 | /* 11->5.5 */ 2234 CCK(1) << 8 | /* 5.5-> 2 */ 2235 CCK(0) << 4 | /* 2-> 1 */ 2236 CCK(0)); /* 1-> 1 */ 2237 #undef OFDM 2238 #undef CCK 2239 } 2240 2241 static void 2242 rt2860_set_txpreamble(struct rt2860_softc *sc) 2243 { 2244 struct ieee80211com *ic = &sc->sc_ic; 2245 uint32_t tmp; 2246 2247 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2248 tmp &= ~RT2860_CCK_SHORT_EN; 2249 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2250 tmp |= RT2860_CCK_SHORT_EN; 2251 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2252 } 2253 2254 void 2255 rt2860_set_basicrates(struct rt2860_softc *sc, 2256 const struct ieee80211_rateset *rs) 2257 { 2258 struct ieee80211com *ic = &sc->sc_ic; 2259 uint32_t mask = 0; 2260 uint8_t rate; 2261 int i; 2262 2263 for (i = 0; i < rs->rs_nrates; i++) { 2264 rate = rs->rs_rates[i]; 2265 2266 if (!(rate & IEEE80211_RATE_BASIC)) 2267 continue; 2268 2269 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2270 IEEE80211_RV(rate)); 2271 } 2272 2273 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2274 } 2275 2276 static void 2277 rt2860_scan_start(struct ieee80211com *ic) 2278 { 2279 struct rt2860_softc *sc = ic->ic_softc; 2280 uint32_t tmp; 2281 2282 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2283 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2284 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2285 RT2860_TBTT_TIMER_EN)); 2286 rt2860_set_gp_timer(sc, 0); 2287 } 2288 2289 static void 2290 rt2860_scan_end(struct ieee80211com *ic) 2291 { 2292 struct rt2860_softc *sc = ic->ic_softc; 2293 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2294 2295 if (vap->iv_state == IEEE80211_S_RUN) { 2296 rt2860_enable_tsf_sync(sc); 2297 rt2860_set_gp_timer(sc, 500); 2298 } 2299 } 2300 2301 static void 2302 rt2860_set_channel(struct ieee80211com *ic) 2303 { 2304 struct rt2860_softc *sc = ic->ic_softc; 2305 2306 RAL_LOCK(sc); 2307 rt2860_switch_chan(sc, ic->ic_curchan); 2308 RAL_UNLOCK(sc); 2309 } 2310 2311 static void 2312 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2313 { 2314 uint32_t tmp; 2315 uint8_t agc; 2316 2317 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2318 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2319 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2320 rt2860_mcu_bbp_write(sc, 86, 0x00); 2321 2322 if (group == 0) { 2323 if (sc->ext_2ghz_lna) { 2324 rt2860_mcu_bbp_write(sc, 82, 0x62); 2325 rt2860_mcu_bbp_write(sc, 75, 0x46); 2326 } else { 2327 rt2860_mcu_bbp_write(sc, 82, 0x84); 2328 rt2860_mcu_bbp_write(sc, 75, 0x50); 2329 } 2330 } else { 2331 if (sc->ext_5ghz_lna) { 2332 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2333 rt2860_mcu_bbp_write(sc, 75, 0x46); 2334 } else { 2335 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2336 rt2860_mcu_bbp_write(sc, 75, 0x50); 2337 } 2338 } 2339 2340 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2341 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2342 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2343 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2344 2345 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2346 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2347 if (sc->nrxchains > 1) 2348 tmp |= RT2860_LNA_PE1_EN; 2349 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2350 tmp |= RT3593_LNA_PE2_EN; 2351 if (group == 0) { /* 2GHz */ 2352 tmp |= RT2860_PA_PE_G0_EN; 2353 if (sc->ntxchains > 1) 2354 tmp |= RT2860_PA_PE_G1_EN; 2355 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2356 tmp |= RT3593_PA_PE_G2_EN; 2357 } else { /* 5GHz */ 2358 tmp |= RT2860_PA_PE_A0_EN; 2359 if (sc->ntxchains > 1) 2360 tmp |= RT2860_PA_PE_A1_EN; 2361 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2362 tmp |= RT3593_PA_PE_A2_EN; 2363 } 2364 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2365 2366 if (sc->mac_ver == 0x3593) { 2367 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2368 if (sc->sc_flags & RT2860_PCIE) { 2369 tmp &= ~0x01010000; 2370 if (group == 0) 2371 tmp |= 0x00010000; 2372 } else { 2373 tmp &= ~0x00008080; 2374 if (group == 0) 2375 tmp |= 0x00000080; 2376 } 2377 tmp = (tmp & ~0x00001000) | 0x00000010; 2378 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2379 } 2380 2381 /* set initial AGC value */ 2382 if (group == 0) { /* 2GHz band */ 2383 if (sc->mac_ver >= 0x3071) 2384 agc = 0x1c + sc->lna[0] * 2; 2385 else 2386 agc = 0x2e + sc->lna[0]; 2387 } else { /* 5GHz band */ 2388 agc = 0x32 + (sc->lna[group] * 5) / 3; 2389 } 2390 rt2860_mcu_bbp_write(sc, 66, agc); 2391 2392 DELAY(1000); 2393 } 2394 2395 static void 2396 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2397 { 2398 const struct rfprog *rfprog = rt2860_rf2850; 2399 uint32_t r2, r3, r4; 2400 int8_t txpow1, txpow2; 2401 u_int i; 2402 2403 /* find the settings for this channel (we know it exists) */ 2404 for (i = 0; rfprog[i].chan != chan; i++); 2405 2406 r2 = rfprog[i].r2; 2407 if (sc->ntxchains == 1) 2408 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2409 if (sc->nrxchains == 1) 2410 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2411 else if (sc->nrxchains == 2) 2412 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2413 2414 /* use Tx power values from EEPROM */ 2415 txpow1 = sc->txpow1[i]; 2416 txpow2 = sc->txpow2[i]; 2417 if (chan > 14) { 2418 if (txpow1 >= 0) 2419 txpow1 = txpow1 << 1 | 1; 2420 else 2421 txpow1 = (7 + txpow1) << 1; 2422 if (txpow2 >= 0) 2423 txpow2 = txpow2 << 1 | 1; 2424 else 2425 txpow2 = (7 + txpow2) << 1; 2426 } 2427 r3 = rfprog[i].r3 | txpow1 << 7; 2428 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2429 2430 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2431 rt2860_rf_write(sc, RT2860_RF2, r2); 2432 rt2860_rf_write(sc, RT2860_RF3, r3); 2433 rt2860_rf_write(sc, RT2860_RF4, r4); 2434 2435 DELAY(200); 2436 2437 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2438 rt2860_rf_write(sc, RT2860_RF2, r2); 2439 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2440 rt2860_rf_write(sc, RT2860_RF4, r4); 2441 2442 DELAY(200); 2443 2444 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2445 rt2860_rf_write(sc, RT2860_RF2, r2); 2446 rt2860_rf_write(sc, RT2860_RF3, r3); 2447 rt2860_rf_write(sc, RT2860_RF4, r4); 2448 } 2449 2450 static void 2451 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2452 { 2453 int8_t txpow1, txpow2; 2454 uint8_t rf; 2455 int i; 2456 2457 /* RT3090 is 2GHz only */ 2458 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2459 2460 /* find the settings for this channel (we know it exists) */ 2461 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2462 2463 /* use Tx power values from EEPROM */ 2464 txpow1 = sc->txpow1[i]; 2465 txpow2 = sc->txpow2[i]; 2466 2467 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2468 rf = rt3090_rf_read(sc, 3); 2469 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2470 rt3090_rf_write(sc, 3, rf); 2471 rf = rt3090_rf_read(sc, 6); 2472 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2473 rt3090_rf_write(sc, 6, rf); 2474 2475 /* set Tx0 power */ 2476 rf = rt3090_rf_read(sc, 12); 2477 rf = (rf & ~0x1f) | txpow1; 2478 rt3090_rf_write(sc, 12, rf); 2479 2480 /* set Tx1 power */ 2481 rf = rt3090_rf_read(sc, 13); 2482 rf = (rf & ~0x1f) | txpow2; 2483 rt3090_rf_write(sc, 13, rf); 2484 2485 rf = rt3090_rf_read(sc, 1); 2486 rf &= ~0xfc; 2487 if (sc->ntxchains == 1) 2488 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2489 else if (sc->ntxchains == 2) 2490 rf |= RT3070_TX2_PD; 2491 if (sc->nrxchains == 1) 2492 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2493 else if (sc->nrxchains == 2) 2494 rf |= RT3070_RX2_PD; 2495 rt3090_rf_write(sc, 1, rf); 2496 2497 /* set RF offset */ 2498 rf = rt3090_rf_read(sc, 23); 2499 rf = (rf & ~0x7f) | sc->freq; 2500 rt3090_rf_write(sc, 23, rf); 2501 2502 /* program RF filter */ 2503 rf = rt3090_rf_read(sc, 24); /* Tx */ 2504 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2505 rt3090_rf_write(sc, 24, rf); 2506 rf = rt3090_rf_read(sc, 31); /* Rx */ 2507 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2508 rt3090_rf_write(sc, 31, rf); 2509 2510 /* enable RF tuning */ 2511 rf = rt3090_rf_read(sc, 7); 2512 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2513 } 2514 2515 static void 2516 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2517 { 2518 uint8_t h20mhz, rf, tmp; 2519 int8_t txpow1, txpow2; 2520 int i; 2521 2522 /* RT5390 is 2GHz only */ 2523 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2524 2525 /* find the settings for this channel (we know it exists) */ 2526 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2527 2528 /* use Tx power values from EEPROM */ 2529 txpow1 = sc->txpow1[i]; 2530 txpow2 = sc->txpow2[i]; 2531 2532 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2533 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2534 rf = rt3090_rf_read(sc, 11); 2535 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2536 rt3090_rf_write(sc, 11, rf); 2537 2538 rf = rt3090_rf_read(sc, 49); 2539 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2540 /* the valid range of the RF R49 is 0x00~0x27 */ 2541 if ((rf & 0x3f) > 0x27) 2542 rf = (rf & ~0x3f) | 0x27; 2543 rt3090_rf_write(sc, 49, rf); 2544 if (sc->mac_ver == 0x5392) { 2545 rf = rt3090_rf_read(sc, 50); 2546 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2547 /* the valid range of the RF R50 is 0x00~0x27 */ 2548 if ((rf & 0x3f) > 0x27) 2549 rf = (rf & ~0x3f) | 0x27; 2550 rt3090_rf_write(sc, 50, rf); 2551 } 2552 2553 rf = rt3090_rf_read(sc, 1); 2554 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2555 if (sc->mac_ver == 0x5392) 2556 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2557 rt3090_rf_write(sc, 1, rf); 2558 2559 rf = rt3090_rf_read(sc, 2); 2560 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2561 DELAY(1000); 2562 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2563 2564 rf = rt3090_rf_read(sc, 17); 2565 tmp = rf; 2566 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2567 rf = MIN(rf, 0x5f); 2568 if (tmp != rf) 2569 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2570 2571 if (sc->mac_ver == 0x5390) { 2572 if (chan <= 4) 2573 rf = 0x73; 2574 else if (chan >= 5 && chan <= 6) 2575 rf = 0x63; 2576 else if (chan >= 7 && chan <= 10) 2577 rf = 0x53; 2578 else 2579 rf = 43; 2580 rt3090_rf_write(sc, 55, rf); 2581 2582 if (chan == 1) 2583 rf = 0x0c; 2584 else if (chan == 2) 2585 rf = 0x0b; 2586 else if (chan == 3) 2587 rf = 0x0a; 2588 else if (chan >= 4 && chan <= 6) 2589 rf = 0x09; 2590 else if (chan >= 7 && chan <= 12) 2591 rf = 0x08; 2592 else if (chan == 13) 2593 rf = 0x07; 2594 else 2595 rf = 0x06; 2596 rt3090_rf_write(sc, 59, rf); 2597 } 2598 2599 /* Tx/Rx h20M */ 2600 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2601 rf = rt3090_rf_read(sc, 30); 2602 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2603 rt3090_rf_write(sc, 30, rf); 2604 2605 /* Rx BB filter VCM */ 2606 rf = rt3090_rf_read(sc, 30); 2607 rf = (rf & ~0x18) | 0x10; 2608 rt3090_rf_write(sc, 30, rf); 2609 2610 /* Initiate VCO calibration. */ 2611 rf = rt3090_rf_read(sc, 3); 2612 rf |= RT3593_VCOCAL; 2613 rt3090_rf_write(sc, 3, rf); 2614 } 2615 2616 static int 2617 rt3090_rf_init(struct rt2860_softc *sc) 2618 { 2619 uint32_t tmp; 2620 uint8_t rf, bbp; 2621 int i; 2622 2623 rf = rt3090_rf_read(sc, 30); 2624 /* toggle RF R30 bit 7 */ 2625 rt3090_rf_write(sc, 30, rf | 0x80); 2626 DELAY(1000); 2627 rt3090_rf_write(sc, 30, rf & ~0x80); 2628 2629 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2630 tmp &= ~0x1f000000; 2631 if (sc->patch_dac && sc->mac_rev < 0x0211) 2632 tmp |= 0x0d000000; /* 1.35V */ 2633 else 2634 tmp |= 0x01000000; /* 1.2V */ 2635 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2636 2637 /* patch LNA_PE_G1 */ 2638 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2639 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2640 2641 /* initialize RF registers to default value */ 2642 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2643 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2644 rt3090_def_rf[i].val); 2645 } 2646 2647 /* select 20MHz bandwidth */ 2648 rt3090_rf_write(sc, 31, 0x14); 2649 2650 rf = rt3090_rf_read(sc, 6); 2651 rt3090_rf_write(sc, 6, rf | 0x40); 2652 2653 if (sc->mac_ver != 0x3593) { 2654 /* calibrate filter for 20MHz bandwidth */ 2655 sc->rf24_20mhz = 0x1f; /* default value */ 2656 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2657 2658 /* select 40MHz bandwidth */ 2659 bbp = rt2860_mcu_bbp_read(sc, 4); 2660 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2661 rf = rt3090_rf_read(sc, 31); 2662 rt3090_rf_write(sc, 31, rf | 0x20); 2663 2664 /* calibrate filter for 40MHz bandwidth */ 2665 sc->rf24_40mhz = 0x2f; /* default value */ 2666 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2667 2668 /* go back to 20MHz bandwidth */ 2669 bbp = rt2860_mcu_bbp_read(sc, 4); 2670 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2671 } 2672 if (sc->mac_rev < 0x0211) 2673 rt3090_rf_write(sc, 27, 0x03); 2674 2675 tmp = RAL_READ(sc, RT3070_OPT_14); 2676 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2677 2678 if (sc->rf_rev == RT3070_RF_3020) 2679 rt3090_set_rx_antenna(sc, 0); 2680 2681 bbp = rt2860_mcu_bbp_read(sc, 138); 2682 if (sc->mac_ver == 0x3593) { 2683 if (sc->ntxchains == 1) 2684 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2685 else if (sc->ntxchains == 2) 2686 bbp |= 0x40; /* turn off DAC2 */ 2687 if (sc->nrxchains == 1) 2688 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2689 else if (sc->nrxchains == 2) 2690 bbp &= ~0x04; /* turn off ADC2 */ 2691 } else { 2692 if (sc->ntxchains == 1) 2693 bbp |= 0x20; /* turn off DAC1 */ 2694 if (sc->nrxchains == 1) 2695 bbp &= ~0x02; /* turn off ADC1 */ 2696 } 2697 rt2860_mcu_bbp_write(sc, 138, bbp); 2698 2699 rf = rt3090_rf_read(sc, 1); 2700 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2701 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2702 rt3090_rf_write(sc, 1, rf); 2703 2704 rf = rt3090_rf_read(sc, 15); 2705 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2706 2707 rf = rt3090_rf_read(sc, 17); 2708 rf &= ~RT3070_TX_LO1; 2709 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2710 rf |= 0x20; /* fix for long range Rx issue */ 2711 if (sc->txmixgain_2ghz >= 2) 2712 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2713 rt3090_rf_write(sc, 17, rf); 2714 2715 rf = rt3090_rf_read(sc, 20); 2716 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2717 2718 rf = rt3090_rf_read(sc, 21); 2719 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2720 2721 return (0); 2722 } 2723 2724 static void 2725 rt5390_rf_init(struct rt2860_softc *sc) 2726 { 2727 uint8_t rf, bbp; 2728 int i; 2729 2730 rf = rt3090_rf_read(sc, 2); 2731 /* Toggle RF R2 bit 7. */ 2732 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2733 DELAY(1000); 2734 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2735 2736 /* Initialize RF registers to default value. */ 2737 if (sc->mac_ver == 0x5392) { 2738 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2739 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2740 rt5392_def_rf[i].val); 2741 } 2742 } else { 2743 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2744 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2745 rt5390_def_rf[i].val); 2746 } 2747 } 2748 2749 sc->rf24_20mhz = 0x1f; 2750 sc->rf24_40mhz = 0x2f; 2751 2752 if (sc->mac_rev < 0x0211) 2753 rt3090_rf_write(sc, 27, 0x03); 2754 2755 /* Set led open drain enable. */ 2756 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2757 2758 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2759 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2760 2761 if (sc->mac_ver == 0x5390) 2762 rt3090_set_rx_antenna(sc, 0); 2763 2764 /* Patch RSSI inaccurate issue. */ 2765 rt2860_mcu_bbp_write(sc, 79, 0x13); 2766 rt2860_mcu_bbp_write(sc, 80, 0x05); 2767 rt2860_mcu_bbp_write(sc, 81, 0x33); 2768 2769 /* Enable DC filter. */ 2770 if (sc->mac_rev >= 0x0211) 2771 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2772 2773 bbp = rt2860_mcu_bbp_read(sc, 138); 2774 if (sc->ntxchains == 1) 2775 bbp |= 0x20; /* Turn off DAC1. */ 2776 if (sc->nrxchains == 1) 2777 bbp &= ~0x02; /* Turn off ADC1. */ 2778 rt2860_mcu_bbp_write(sc, 138, bbp); 2779 2780 /* Enable RX LO1 and LO2. */ 2781 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2782 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2783 2784 /* Avoid data lost and CRC error. */ 2785 rt2860_mcu_bbp_write(sc, 4, 2786 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2787 2788 rf = rt3090_rf_read(sc, 30); 2789 rf = (rf & ~0x18) | 0x10; 2790 rt3090_rf_write(sc, 30, rf); 2791 } 2792 2793 static void 2794 rt3090_rf_wakeup(struct rt2860_softc *sc) 2795 { 2796 uint32_t tmp; 2797 uint8_t rf; 2798 2799 if (sc->mac_ver == 0x3593) { 2800 /* enable VCO */ 2801 rf = rt3090_rf_read(sc, 1); 2802 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2803 2804 /* initiate VCO calibration */ 2805 rf = rt3090_rf_read(sc, 3); 2806 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2807 2808 /* enable VCO bias current control */ 2809 rf = rt3090_rf_read(sc, 6); 2810 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2811 2812 /* initiate res calibration */ 2813 rf = rt3090_rf_read(sc, 2); 2814 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2815 2816 /* set reference current control to 0.33 mA */ 2817 rf = rt3090_rf_read(sc, 22); 2818 rf &= ~RT3593_CP_IC_MASK; 2819 rf |= 1 << RT3593_CP_IC_SHIFT; 2820 rt3090_rf_write(sc, 22, rf); 2821 2822 /* enable RX CTB */ 2823 rf = rt3090_rf_read(sc, 46); 2824 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2825 2826 rf = rt3090_rf_read(sc, 20); 2827 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2828 rt3090_rf_write(sc, 20, rf); 2829 } else { 2830 /* enable RF block */ 2831 rf = rt3090_rf_read(sc, 1); 2832 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2833 2834 /* enable VCO bias current control */ 2835 rf = rt3090_rf_read(sc, 7); 2836 rt3090_rf_write(sc, 7, rf | 0x30); 2837 2838 rf = rt3090_rf_read(sc, 9); 2839 rt3090_rf_write(sc, 9, rf | 0x0e); 2840 2841 /* enable RX CTB */ 2842 rf = rt3090_rf_read(sc, 21); 2843 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2844 2845 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2846 rf = rt3090_rf_read(sc, 27); 2847 rf &= ~0x77; 2848 if (sc->mac_rev < 0x0211) 2849 rf |= 0x03; 2850 rt3090_rf_write(sc, 27, rf); 2851 } 2852 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2853 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2854 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2855 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2856 } 2857 } 2858 2859 static void 2860 rt5390_rf_wakeup(struct rt2860_softc *sc) 2861 { 2862 uint32_t tmp; 2863 uint8_t rf; 2864 2865 rf = rt3090_rf_read(sc, 1); 2866 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2867 RT3070_TX0_PD; 2868 if (sc->mac_ver == 0x5392) 2869 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2870 rt3090_rf_write(sc, 1, rf); 2871 2872 rf = rt3090_rf_read(sc, 6); 2873 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2874 if (sc->mac_ver == 0x5390) 2875 rf &= ~RT3593_VCO_IC; 2876 rt3090_rf_write(sc, 6, rf); 2877 2878 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2879 2880 rf = rt3090_rf_read(sc, 22); 2881 rf = (rf & ~0xe0) | 0x20; 2882 rt3090_rf_write(sc, 22, rf); 2883 2884 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2885 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2886 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2887 2888 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2889 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2890 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2891 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2892 } 2893 } 2894 2895 static int 2896 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2897 uint8_t *val) 2898 { 2899 uint8_t rf22, rf24; 2900 uint8_t bbp55_pb, bbp55_sb, delta; 2901 int ntries; 2902 2903 /* program filter */ 2904 rf24 = rt3090_rf_read(sc, 24); 2905 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2906 rt3090_rf_write(sc, 24, rf24); 2907 2908 /* enable baseband loopback mode */ 2909 rf22 = rt3090_rf_read(sc, 22); 2910 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2911 2912 /* set power and frequency of passband test tone */ 2913 rt2860_mcu_bbp_write(sc, 24, 0x00); 2914 for (ntries = 0; ntries < 100; ntries++) { 2915 /* transmit test tone */ 2916 rt2860_mcu_bbp_write(sc, 25, 0x90); 2917 DELAY(1000); 2918 /* read received power */ 2919 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2920 if (bbp55_pb != 0) 2921 break; 2922 } 2923 if (ntries == 100) 2924 return (ETIMEDOUT); 2925 2926 /* set power and frequency of stopband test tone */ 2927 rt2860_mcu_bbp_write(sc, 24, 0x06); 2928 for (ntries = 0; ntries < 100; ntries++) { 2929 /* transmit test tone */ 2930 rt2860_mcu_bbp_write(sc, 25, 0x90); 2931 DELAY(1000); 2932 /* read received power */ 2933 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2934 2935 delta = bbp55_pb - bbp55_sb; 2936 if (delta > target) 2937 break; 2938 2939 /* reprogram filter */ 2940 rf24++; 2941 rt3090_rf_write(sc, 24, rf24); 2942 } 2943 if (ntries < 100) { 2944 if (rf24 != init) 2945 rf24--; /* backtrack */ 2946 *val = rf24; 2947 rt3090_rf_write(sc, 24, rf24); 2948 } 2949 2950 /* restore initial state */ 2951 rt2860_mcu_bbp_write(sc, 24, 0x00); 2952 2953 /* disable baseband loopback mode */ 2954 rf22 = rt3090_rf_read(sc, 22); 2955 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2956 2957 return (0); 2958 } 2959 2960 static void 2961 rt3090_rf_setup(struct rt2860_softc *sc) 2962 { 2963 uint8_t bbp; 2964 int i; 2965 2966 if (sc->mac_rev >= 0x0211) { 2967 /* enable DC filter */ 2968 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2969 2970 /* improve power consumption */ 2971 bbp = rt2860_mcu_bbp_read(sc, 31); 2972 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2973 } 2974 2975 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2976 if (sc->mac_rev < 0x0211) { 2977 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2978 sc->patch_dac ? 0x2c : 0x0f); 2979 } else 2980 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2981 2982 /* initialize RF registers from ROM */ 2983 if (sc->mac_ver < 0x5390) { 2984 for (i = 0; i < 10; i++) { 2985 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2986 continue; 2987 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 2988 } 2989 } 2990 } 2991 2992 static void 2993 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 2994 { 2995 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 2996 which | (sc->leds & 0x7f), 0); 2997 } 2998 2999 /* 3000 * Hardware has a general-purpose programmable timer interrupt that can 3001 * periodically raise MAC_INT_4. 3002 */ 3003 static void 3004 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3005 { 3006 uint32_t tmp; 3007 3008 /* disable GP timer before reprogramming it */ 3009 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3010 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3011 3012 if (ms == 0) 3013 return; 3014 3015 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3016 ms *= 16; /* Unit: 64us */ 3017 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3018 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3019 3020 /* enable GP timer */ 3021 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3022 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3023 } 3024 3025 static void 3026 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3027 { 3028 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3029 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3030 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3031 bssid[4] | bssid[5] << 8); 3032 } 3033 3034 static void 3035 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3036 { 3037 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3038 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3039 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3040 addr[4] | addr[5] << 8 | 0xff << 16); 3041 } 3042 3043 static void 3044 rt2860_updateslot(struct ieee80211com *ic) 3045 { 3046 struct rt2860_softc *sc = ic->ic_softc; 3047 uint32_t tmp; 3048 3049 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3050 tmp &= ~0xff; 3051 tmp |= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 3052 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3053 } 3054 3055 static void 3056 rt2860_updateprot(struct rt2860_softc *sc) 3057 { 3058 struct ieee80211com *ic = &sc->sc_ic; 3059 uint32_t tmp; 3060 3061 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3062 /* setup protection frame rate (MCS code) */ 3063 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3064 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3065 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3066 3067 /* CCK frames don't require protection */ 3068 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3069 3070 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3071 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3072 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3073 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3074 tmp |= RT2860_PROT_CTRL_CTS; 3075 } 3076 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3077 } 3078 3079 static void 3080 rt2860_update_promisc(struct ieee80211com *ic) 3081 { 3082 struct rt2860_softc *sc = ic->ic_softc; 3083 uint32_t tmp; 3084 3085 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3086 tmp &= ~RT2860_DROP_NOT_MYBSS; 3087 if (ic->ic_promisc == 0) 3088 tmp |= RT2860_DROP_NOT_MYBSS; 3089 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3090 } 3091 3092 static int 3093 rt2860_updateedca(struct ieee80211com *ic) 3094 { 3095 struct rt2860_softc *sc = ic->ic_softc; 3096 const struct wmeParams *wmep; 3097 int aci; 3098 3099 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 3100 3101 /* update MAC TX configuration registers */ 3102 for (aci = 0; aci < WME_NUM_AC; aci++) { 3103 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3104 wmep[aci].wmep_logcwmax << 16 | 3105 wmep[aci].wmep_logcwmin << 12 | 3106 wmep[aci].wmep_aifsn << 8 | 3107 wmep[aci].wmep_txopLimit); 3108 } 3109 3110 /* update SCH/DMA registers too */ 3111 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3112 wmep[WME_AC_VO].wmep_aifsn << 12 | 3113 wmep[WME_AC_VI].wmep_aifsn << 8 | 3114 wmep[WME_AC_BK].wmep_aifsn << 4 | 3115 wmep[WME_AC_BE].wmep_aifsn); 3116 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3117 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3118 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3119 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3120 wmep[WME_AC_BE].wmep_logcwmin); 3121 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3122 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3123 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3124 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3125 wmep[WME_AC_BE].wmep_logcwmax); 3126 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3127 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3128 wmep[WME_AC_BE].wmep_txopLimit); 3129 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3130 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3131 wmep[WME_AC_VI].wmep_txopLimit); 3132 3133 return 0; 3134 } 3135 3136 #ifdef HW_CRYPTO 3137 static int 3138 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3139 struct ieee80211_key *k) 3140 { 3141 struct rt2860_softc *sc = ic->ic_softc; 3142 bus_size_t base; 3143 uint32_t attr; 3144 uint8_t mode, wcid, iv[8]; 3145 3146 /* defer setting of WEP keys until interface is brought up */ 3147 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3148 (IFF_UP | IFF_RUNNING)) 3149 return 0; 3150 3151 /* map net80211 cipher to RT2860 security mode */ 3152 switch (k->k_cipher) { 3153 case IEEE80211_CIPHER_WEP40: 3154 mode = RT2860_MODE_WEP40; 3155 break; 3156 case IEEE80211_CIPHER_WEP104: 3157 mode = RT2860_MODE_WEP104; 3158 break; 3159 case IEEE80211_CIPHER_TKIP: 3160 mode = RT2860_MODE_TKIP; 3161 break; 3162 case IEEE80211_CIPHER_CCMP: 3163 mode = RT2860_MODE_AES_CCMP; 3164 break; 3165 default: 3166 return EINVAL; 3167 } 3168 3169 if (k->k_flags & IEEE80211_KEY_GROUP) { 3170 wcid = 0; /* NB: update WCID0 for group keys */ 3171 base = RT2860_SKEY(0, k->k_id); 3172 } else { 3173 wcid = ((struct rt2860_node *)ni)->wcid; 3174 base = RT2860_PKEY(wcid); 3175 } 3176 3177 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3178 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3179 #ifndef IEEE80211_STA_ONLY 3180 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3181 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3182 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3183 } else 3184 #endif 3185 { 3186 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3187 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3188 } 3189 } else 3190 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3191 3192 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3193 (k->k_flags & IEEE80211_KEY_TX)) { 3194 /* set initial packet number in IV+EIV */ 3195 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3196 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3197 uint32_t val = arc4random(); 3198 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3199 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3200 val += 0x000100; 3201 iv[0] = val; 3202 iv[1] = val >> 8; 3203 iv[2] = val >> 16; 3204 iv[3] = k->k_id << 6; 3205 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3206 } else { 3207 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3208 iv[0] = k->k_tsc >> 8; 3209 iv[1] = (iv[0] | 0x20) & 0x7f; 3210 iv[2] = k->k_tsc; 3211 } else /* CCMP */ { 3212 iv[0] = k->k_tsc; 3213 iv[1] = k->k_tsc >> 8; 3214 iv[2] = 0; 3215 } 3216 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3217 iv[4] = k->k_tsc >> 16; 3218 iv[5] = k->k_tsc >> 24; 3219 iv[6] = k->k_tsc >> 32; 3220 iv[7] = k->k_tsc >> 40; 3221 } 3222 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3223 } 3224 3225 if (k->k_flags & IEEE80211_KEY_GROUP) { 3226 /* install group key */ 3227 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3228 attr &= ~(0xf << (k->k_id * 4)); 3229 attr |= mode << (k->k_id * 4); 3230 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3231 } else { 3232 /* install pairwise key */ 3233 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3234 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3235 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3236 } 3237 return 0; 3238 } 3239 3240 static void 3241 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3242 struct ieee80211_key *k) 3243 { 3244 struct rt2860_softc *sc = ic->ic_softc; 3245 uint32_t attr; 3246 uint8_t wcid; 3247 3248 if (k->k_flags & IEEE80211_KEY_GROUP) { 3249 /* remove group key */ 3250 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3251 attr &= ~(0xf << (k->k_id * 4)); 3252 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3253 3254 } else { 3255 /* remove pairwise key */ 3256 wcid = ((struct rt2860_node *)ni)->wcid; 3257 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3258 attr &= ~0xf; 3259 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3260 } 3261 } 3262 #endif 3263 3264 static int8_t 3265 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3266 { 3267 struct ieee80211com *ic = &sc->sc_ic; 3268 struct ieee80211_channel *c = ic->ic_curchan; 3269 int delta; 3270 3271 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3272 u_int chan = ieee80211_chan2ieee(ic, c); 3273 delta = sc->rssi_5ghz[rxchain]; 3274 3275 /* determine channel group */ 3276 if (chan <= 64) 3277 delta -= sc->lna[1]; 3278 else if (chan <= 128) 3279 delta -= sc->lna[2]; 3280 else 3281 delta -= sc->lna[3]; 3282 } else 3283 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3284 3285 return -12 - delta - rssi; 3286 } 3287 3288 /* 3289 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3290 * Used to adjust per-rate Tx power registers. 3291 */ 3292 static __inline uint32_t 3293 b4inc(uint32_t b32, int8_t delta) 3294 { 3295 int8_t i, b4; 3296 3297 for (i = 0; i < 8; i++) { 3298 b4 = b32 & 0xf; 3299 b4 += delta; 3300 if (b4 < 0) 3301 b4 = 0; 3302 else if (b4 > 0xf) 3303 b4 = 0xf; 3304 b32 = b32 >> 4 | b4 << 28; 3305 } 3306 return b32; 3307 } 3308 3309 static const char * 3310 rt2860_get_rf(uint8_t rev) 3311 { 3312 switch (rev) { 3313 case RT2860_RF_2820: return "RT2820"; 3314 case RT2860_RF_2850: return "RT2850"; 3315 case RT2860_RF_2720: return "RT2720"; 3316 case RT2860_RF_2750: return "RT2750"; 3317 case RT3070_RF_3020: return "RT3020"; 3318 case RT3070_RF_2020: return "RT2020"; 3319 case RT3070_RF_3021: return "RT3021"; 3320 case RT3070_RF_3022: return "RT3022"; 3321 case RT3070_RF_3052: return "RT3052"; 3322 case RT3070_RF_3320: return "RT3320"; 3323 case RT3070_RF_3053: return "RT3053"; 3324 case RT5390_RF_5390: return "RT5390"; 3325 default: return "unknown"; 3326 } 3327 } 3328 3329 static int 3330 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3331 { 3332 int8_t delta_2ghz, delta_5ghz; 3333 uint32_t tmp; 3334 uint16_t val; 3335 int ridx, ant, i; 3336 3337 /* check whether the ROM is eFUSE ROM or EEPROM */ 3338 sc->sc_srom_read = rt2860_eeprom_read_2; 3339 if (sc->mac_ver >= 0x3071) { 3340 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3341 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3342 if (tmp & RT3070_SEL_EFUSE) 3343 sc->sc_srom_read = rt3090_efuse_read_2; 3344 } 3345 3346 /* read EEPROM version */ 3347 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3348 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3349 3350 /* read MAC address */ 3351 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3352 macaddr[0] = val & 0xff; 3353 macaddr[1] = val >> 8; 3354 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3355 macaddr[2] = val & 0xff; 3356 macaddr[3] = val >> 8; 3357 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3358 macaddr[4] = val & 0xff; 3359 macaddr[5] = val >> 8; 3360 3361 /* read country code */ 3362 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3363 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3364 3365 /* read vendor BBP settings */ 3366 for (i = 0; i < 8; i++) { 3367 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3368 sc->bbp[i].val = val & 0xff; 3369 sc->bbp[i].reg = val >> 8; 3370 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3371 } 3372 if (sc->mac_ver >= 0x3071) { 3373 /* read vendor RF settings */ 3374 for (i = 0; i < 10; i++) { 3375 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3376 sc->rf[i].val = val & 0xff; 3377 sc->rf[i].reg = val >> 8; 3378 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3379 sc->rf[i].val)); 3380 } 3381 } 3382 3383 /* read RF frequency offset from EEPROM */ 3384 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3385 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3386 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3387 if ((val >> 8) != 0xff) { 3388 /* read LEDs operating mode */ 3389 sc->leds = val >> 8; 3390 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3391 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3392 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3393 } else { 3394 /* broken EEPROM, use default settings */ 3395 sc->leds = 0x01; 3396 sc->led[0] = 0x5555; 3397 sc->led[1] = 0x2221; 3398 sc->led[2] = 0xa9f8; 3399 } 3400 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3401 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3402 3403 /* read RF information */ 3404 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3405 if (val == 0xffff) { 3406 DPRINTF(("invalid EEPROM antenna info, using default\n")); 3407 if (sc->mac_ver >= 0x5390) { 3408 /* default to RF5390 */ 3409 sc->rf_rev = RT5390_RF_5390; 3410 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3411 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3412 } else if (sc->mac_ver == 0x3593) { 3413 /* default to RF3053 3T3R */ 3414 sc->rf_rev = RT3070_RF_3053; 3415 sc->ntxchains = 3; 3416 sc->nrxchains = 3; 3417 } else if (sc->mac_ver >= 0x3071) { 3418 /* default to RF3020 1T1R */ 3419 sc->rf_rev = RT3070_RF_3020; 3420 sc->ntxchains = 1; 3421 sc->nrxchains = 1; 3422 } else { 3423 /* default to RF2820 1T2R */ 3424 sc->rf_rev = RT2860_RF_2820; 3425 sc->ntxchains = 1; 3426 sc->nrxchains = 2; 3427 } 3428 } else { 3429 sc->rf_rev = (val >> 8) & 0xf; 3430 if (sc->mac_ver >= 0x5390) { 3431 sc->ntxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3432 sc->nrxchains = (sc->mac_ver == 0x5392) ? 2 : 1; 3433 } else { 3434 sc->ntxchains = (val >> 4) & 0xf; 3435 sc->nrxchains = val & 0xf; 3436 } 3437 } 3438 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3439 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3440 3441 /* check if RF supports automatic Tx access gain control */ 3442 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3443 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3444 /* check if driver should patch the DAC issue */ 3445 if ((val >> 8) != 0xff) 3446 sc->patch_dac = (val >> 15) & 1; 3447 if ((val & 0xff) != 0xff) { 3448 sc->ext_5ghz_lna = (val >> 3) & 1; 3449 sc->ext_2ghz_lna = (val >> 2) & 1; 3450 /* check if RF supports automatic Tx access gain control */ 3451 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */; 3452 /* check if we have a hardware radio switch */ 3453 sc->rfswitch = val & 1; 3454 } 3455 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3456 /* read PCIe power save level */ 3457 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3458 if ((val & 0xff) != 0xff) { 3459 sc->pslevel = val & 0x3; 3460 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3461 if ((val & 0xff80) != 0x9280) 3462 sc->pslevel = MIN(sc->pslevel, 1); 3463 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3464 } 3465 } 3466 3467 /* read power settings for 2GHz channels */ 3468 for (i = 0; i < 14; i += 2) { 3469 val = rt2860_srom_read(sc, 3470 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3471 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3472 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3473 3474 if (sc->mac_ver != 0x5390) { 3475 val = rt2860_srom_read(sc, 3476 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3477 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3478 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3479 } 3480 } 3481 /* fix broken Tx power entries */ 3482 for (i = 0; i < 14; i++) { 3483 if (sc->txpow1[i] < 0 || 3484 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3485 sc->txpow1[i] = 5; 3486 if (sc->mac_ver != 0x5390) { 3487 if (sc->txpow2[i] < 0 || 3488 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3489 sc->txpow2[i] = 5; 3490 } 3491 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3492 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3493 } 3494 /* read power settings for 5GHz channels */ 3495 for (i = 0; i < 40; i += 2) { 3496 val = rt2860_srom_read(sc, 3497 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3498 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3499 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3500 3501 val = rt2860_srom_read(sc, 3502 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3503 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3504 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3505 } 3506 /* fix broken Tx power entries */ 3507 for (i = 0; i < 40; i++) { 3508 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3509 sc->txpow1[14 + i] = 5; 3510 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3511 sc->txpow2[14 + i] = 5; 3512 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3513 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3514 sc->txpow2[14 + i])); 3515 } 3516 3517 /* read Tx power compensation for each Tx rate */ 3518 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3519 delta_2ghz = delta_5ghz = 0; 3520 if ((val & 0xff) != 0xff && (val & 0x80)) { 3521 delta_2ghz = val & 0xf; 3522 if (!(val & 0x40)) /* negative number */ 3523 delta_2ghz = -delta_2ghz; 3524 } 3525 val >>= 8; 3526 if ((val & 0xff) != 0xff && (val & 0x80)) { 3527 delta_5ghz = val & 0xf; 3528 if (!(val & 0x40)) /* negative number */ 3529 delta_5ghz = -delta_5ghz; 3530 } 3531 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3532 delta_2ghz, delta_5ghz)); 3533 3534 for (ridx = 0; ridx < 5; ridx++) { 3535 uint32_t reg; 3536 3537 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3538 reg = val; 3539 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3540 reg |= (uint32_t)val << 16; 3541 3542 sc->txpow20mhz[ridx] = reg; 3543 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3544 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3545 3546 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3547 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3548 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3549 } 3550 3551 /* read factory-calibrated samples for temperature compensation */ 3552 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3553 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3554 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3555 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3556 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3557 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3558 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3559 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3560 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3561 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3562 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3563 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3564 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3565 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3566 sc->step_2ghz = val >> 8; 3567 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3568 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3569 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3570 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3571 sc->tssi_2ghz[8], sc->step_2ghz)); 3572 /* check that ref value is correct, otherwise disable calibration */ 3573 if (sc->tssi_2ghz[4] == 0xff) 3574 sc->calib_2ghz = 0; 3575 3576 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3577 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3578 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3579 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3580 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3581 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3582 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3583 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3584 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3585 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3586 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3587 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3588 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3589 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3590 sc->step_5ghz = val >> 8; 3591 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3592 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3593 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3594 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3595 sc->tssi_5ghz[8], sc->step_5ghz)); 3596 /* check that ref value is correct, otherwise disable calibration */ 3597 if (sc->tssi_5ghz[4] == 0xff) 3598 sc->calib_5ghz = 0; 3599 3600 /* read RSSI offsets and LNA gains from EEPROM */ 3601 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3602 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3603 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3604 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3605 if (sc->mac_ver >= 0x3071) { 3606 /* 3607 * On RT3090 chips (limited to 2 Rx chains), this ROM 3608 * field contains the Tx mixer gain for the 2GHz band. 3609 */ 3610 if ((val & 0xff) != 0xff) 3611 sc->txmixgain_2ghz = val & 0x7; 3612 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3613 } else 3614 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3615 sc->lna[2] = val >> 8; /* channel group 2 */ 3616 3617 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3618 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3619 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3620 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3621 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3622 sc->lna[3] = val >> 8; /* channel group 3 */ 3623 3624 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3625 if (sc->mac_ver >= 0x3071) 3626 sc->lna[0] = RT3090_DEF_LNA; 3627 else /* channel group 0 */ 3628 sc->lna[0] = val & 0xff; 3629 sc->lna[1] = val >> 8; /* channel group 1 */ 3630 3631 /* fix broken 5GHz LNA entries */ 3632 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3633 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3634 sc->lna[2] = sc->lna[1]; 3635 } 3636 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3637 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3638 sc->lna[3] = sc->lna[1]; 3639 } 3640 3641 /* fix broken RSSI offset entries */ 3642 for (ant = 0; ant < 3; ant++) { 3643 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3644 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3645 ant + 1, sc->rssi_2ghz[ant])); 3646 sc->rssi_2ghz[ant] = 0; 3647 } 3648 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3649 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3650 ant + 1, sc->rssi_5ghz[ant])); 3651 sc->rssi_5ghz[ant] = 0; 3652 } 3653 } 3654 3655 return 0; 3656 } 3657 3658 static int 3659 rt2860_bbp_init(struct rt2860_softc *sc) 3660 { 3661 int i, ntries; 3662 3663 /* wait for BBP to wake up */ 3664 for (ntries = 0; ntries < 20; ntries++) { 3665 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3666 if (bbp0 != 0 && bbp0 != 0xff) 3667 break; 3668 } 3669 if (ntries == 20) { 3670 device_printf(sc->sc_dev, 3671 "timeout waiting for BBP to wake up\n"); 3672 return (ETIMEDOUT); 3673 } 3674 3675 /* initialize BBP registers to default values */ 3676 if (sc->mac_ver >= 0x5390) 3677 rt5390_bbp_init(sc); 3678 else { 3679 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3680 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3681 rt2860_def_bbp[i].val); 3682 } 3683 } 3684 3685 /* fix BBP84 for RT2860E */ 3686 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3687 rt2860_mcu_bbp_write(sc, 84, 0x19); 3688 3689 if (sc->mac_ver >= 0x3071) { 3690 rt2860_mcu_bbp_write(sc, 79, 0x13); 3691 rt2860_mcu_bbp_write(sc, 80, 0x05); 3692 rt2860_mcu_bbp_write(sc, 81, 0x33); 3693 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3694 rt2860_mcu_bbp_write(sc, 69, 0x16); 3695 rt2860_mcu_bbp_write(sc, 73, 0x12); 3696 } 3697 3698 return 0; 3699 } 3700 3701 static void 3702 rt5390_bbp_init(struct rt2860_softc *sc) 3703 { 3704 uint8_t bbp; 3705 int i; 3706 3707 /* Apply maximum likelihood detection for 2 stream case. */ 3708 if (sc->nrxchains > 1) { 3709 bbp = rt2860_mcu_bbp_read(sc, 105); 3710 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3711 } 3712 3713 /* Avoid data lost and CRC error. */ 3714 bbp = rt2860_mcu_bbp_read(sc, 4); 3715 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3716 3717 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3718 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3719 rt5390_def_bbp[i].val); 3720 } 3721 3722 if (sc->mac_ver == 0x5392) { 3723 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3724 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3725 rt2860_mcu_bbp_write(sc, 98, 0x12); 3726 rt2860_mcu_bbp_write(sc, 106, 0x05); 3727 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3728 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3729 } 3730 3731 bbp = rt2860_mcu_bbp_read(sc, 152); 3732 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3733 3734 /* Disable hardware antenna diversity. */ 3735 if (sc->mac_ver == 0x5390) 3736 rt2860_mcu_bbp_write(sc, 154, 0); 3737 } 3738 3739 static int 3740 rt2860_txrx_enable(struct rt2860_softc *sc) 3741 { 3742 struct ieee80211com *ic = &sc->sc_ic; 3743 uint32_t tmp; 3744 int ntries; 3745 3746 /* enable Tx/Rx DMA engine */ 3747 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3748 RAL_BARRIER_READ_WRITE(sc); 3749 for (ntries = 0; ntries < 200; ntries++) { 3750 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3751 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3752 break; 3753 DELAY(1000); 3754 } 3755 if (ntries == 200) { 3756 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3757 return ETIMEDOUT; 3758 } 3759 3760 DELAY(50); 3761 3762 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3763 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3764 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3765 3766 /* set Rx filter */ 3767 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3768 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3769 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3770 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3771 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3772 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3773 if (ic->ic_opmode == IEEE80211_M_STA) 3774 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3775 } 3776 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3777 3778 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3779 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3780 3781 return 0; 3782 } 3783 3784 static void 3785 rt2860_init(void *arg) 3786 { 3787 struct rt2860_softc *sc = arg; 3788 struct ieee80211com *ic = &sc->sc_ic; 3789 3790 RAL_LOCK(sc); 3791 rt2860_init_locked(sc); 3792 RAL_UNLOCK(sc); 3793 3794 if (sc->sc_flags & RT2860_RUNNNING) 3795 ieee80211_start_all(ic); 3796 } 3797 3798 static void 3799 rt2860_init_locked(struct rt2860_softc *sc) 3800 { 3801 struct ieee80211com *ic = &sc->sc_ic; 3802 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3803 uint32_t tmp; 3804 uint8_t bbp1, bbp3; 3805 int i, qid, ridx, ntries, error; 3806 3807 RAL_LOCK_ASSERT(sc); 3808 3809 if (sc->rfswitch) { 3810 /* hardware has a radio switch on GPIO pin 2 */ 3811 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3812 device_printf(sc->sc_dev, 3813 "radio is disabled by hardware switch\n"); 3814 #ifdef notyet 3815 rt2860_stop_locked(sc); 3816 return; 3817 #endif 3818 } 3819 } 3820 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3821 3822 /* disable DMA */ 3823 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3824 tmp &= 0xff0; 3825 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3826 3827 /* PBF hardware reset */ 3828 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3829 RAL_BARRIER_WRITE(sc); 3830 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3831 3832 if ((error = rt2860_load_microcode(sc)) != 0) { 3833 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3834 rt2860_stop_locked(sc); 3835 return; 3836 } 3837 3838 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3839 3840 /* init Tx power for all Tx rates (from EEPROM) */ 3841 for (ridx = 0; ridx < 5; ridx++) { 3842 if (sc->txpow20mhz[ridx] == 0xffffffff) 3843 continue; 3844 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3845 } 3846 3847 for (ntries = 0; ntries < 100; ntries++) { 3848 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3849 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3850 break; 3851 DELAY(1000); 3852 } 3853 if (ntries == 100) { 3854 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3855 rt2860_stop_locked(sc); 3856 return; 3857 } 3858 tmp &= 0xff0; 3859 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3860 3861 /* reset Rx ring and all 6 Tx rings */ 3862 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3863 3864 /* PBF hardware reset */ 3865 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3866 RAL_BARRIER_WRITE(sc); 3867 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3868 3869 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3870 3871 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3872 RAL_BARRIER_WRITE(sc); 3873 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3874 3875 for (i = 0; i < nitems(rt2860_def_mac); i++) 3876 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3877 if (sc->mac_ver >= 0x5390) 3878 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3879 else if (sc->mac_ver >= 0x3071) { 3880 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3881 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3882 4 << RT2860_DLY_PAPE_EN_SHIFT); 3883 } 3884 3885 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3886 sc->sc_flags |= RT2860_PCIE; 3887 /* PCIe has different clock cycle count than PCI */ 3888 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3889 tmp = (tmp & ~0xff) | 0x7d; 3890 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3891 } 3892 3893 /* wait while MAC is busy */ 3894 for (ntries = 0; ntries < 100; ntries++) { 3895 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3896 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3897 break; 3898 DELAY(1000); 3899 } 3900 if (ntries == 100) { 3901 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3902 rt2860_stop_locked(sc); 3903 return; 3904 } 3905 3906 /* clear Host to MCU mailbox */ 3907 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3908 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3909 3910 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3911 DELAY(1000); 3912 3913 if ((error = rt2860_bbp_init(sc)) != 0) { 3914 rt2860_stop_locked(sc); 3915 return; 3916 } 3917 3918 /* clear RX WCID search table */ 3919 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3920 /* clear pairwise key table */ 3921 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3922 /* clear IV/EIV table */ 3923 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3924 /* clear WCID attribute table */ 3925 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3926 /* clear shared key table */ 3927 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3928 /* clear shared key mode */ 3929 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3930 3931 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3932 for (qid = 0; qid < 6; qid++) { 3933 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3934 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3935 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3936 } 3937 3938 /* init Rx ring */ 3939 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3940 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3941 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3942 3943 /* setup maximum buffer sizes */ 3944 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3945 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3946 3947 for (ntries = 0; ntries < 100; ntries++) { 3948 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3949 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3950 break; 3951 DELAY(1000); 3952 } 3953 if (ntries == 100) { 3954 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3955 rt2860_stop_locked(sc); 3956 return; 3957 } 3958 tmp &= 0xff0; 3959 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3960 3961 /* disable interrupts mitigation */ 3962 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3963 3964 /* write vendor-specific BBP values (from EEPROM) */ 3965 for (i = 0; i < 8; i++) { 3966 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3967 continue; 3968 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3969 } 3970 3971 /* select Main antenna for 1T1R devices */ 3972 if (sc->rf_rev == RT3070_RF_2020 || 3973 sc->rf_rev == RT3070_RF_3020 || 3974 sc->rf_rev == RT3070_RF_3320 || 3975 sc->mac_ver == 0x5390) 3976 rt3090_set_rx_antenna(sc, 0); 3977 3978 /* send LEDs operating mode to microcontroller */ 3979 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3980 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3981 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3982 3983 if (sc->mac_ver >= 0x5390) 3984 rt5390_rf_init(sc); 3985 else if (sc->mac_ver >= 0x3071) { 3986 if ((error = rt3090_rf_init(sc)) != 0) { 3987 rt2860_stop_locked(sc); 3988 return; 3989 } 3990 } 3991 3992 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3993 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3994 3995 if (sc->mac_ver >= 0x5390) 3996 rt5390_rf_wakeup(sc); 3997 else if (sc->mac_ver >= 0x3071) 3998 rt3090_rf_wakeup(sc); 3999 4000 /* disable non-existing Rx chains */ 4001 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4002 bbp3 &= ~(1 << 3 | 1 << 4); 4003 if (sc->nrxchains == 2) 4004 bbp3 |= 1 << 3; 4005 else if (sc->nrxchains == 3) 4006 bbp3 |= 1 << 4; 4007 rt2860_mcu_bbp_write(sc, 3, bbp3); 4008 4009 /* disable non-existing Tx chains */ 4010 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4011 if (sc->ntxchains == 1) 4012 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4013 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4014 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4015 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4016 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4017 rt2860_mcu_bbp_write(sc, 1, bbp1); 4018 4019 if (sc->mac_ver >= 0x3071) 4020 rt3090_rf_setup(sc); 4021 4022 /* select default channel */ 4023 rt2860_switch_chan(sc, ic->ic_curchan); 4024 4025 /* reset RF from MCU */ 4026 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4027 4028 /* set RTS threshold */ 4029 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4030 tmp &= ~0xffff00; 4031 tmp |= IEEE80211_RTS_DEFAULT << 8; 4032 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4033 4034 /* setup initial protection mode */ 4035 rt2860_updateprot(sc); 4036 4037 /* turn radio LED on */ 4038 rt2860_set_leds(sc, RT2860_LED_RADIO); 4039 4040 /* enable Tx/Rx DMA engine */ 4041 if ((error = rt2860_txrx_enable(sc)) != 0) { 4042 rt2860_stop_locked(sc); 4043 return; 4044 } 4045 4046 /* clear pending interrupts */ 4047 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4048 /* enable interrupts */ 4049 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4050 4051 if (sc->sc_flags & RT2860_ADVANCED_PS) 4052 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4053 4054 sc->sc_flags |= RT2860_RUNNNING; 4055 4056 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4057 } 4058 4059 static void 4060 rt2860_stop(void *arg) 4061 { 4062 struct rt2860_softc *sc = arg; 4063 4064 RAL_LOCK(sc); 4065 rt2860_stop_locked(sc); 4066 RAL_UNLOCK(sc); 4067 } 4068 4069 static void 4070 rt2860_stop_locked(struct rt2860_softc *sc) 4071 { 4072 uint32_t tmp; 4073 int qid; 4074 4075 if (sc->sc_flags & RT2860_RUNNNING) 4076 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4077 4078 callout_stop(&sc->watchdog_ch); 4079 sc->sc_tx_timer = 0; 4080 sc->sc_flags &= ~RT2860_RUNNNING; 4081 4082 /* disable interrupts */ 4083 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4084 4085 /* disable GP timer */ 4086 rt2860_set_gp_timer(sc, 0); 4087 4088 /* disable Rx */ 4089 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4090 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4091 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4092 4093 /* reset adapter */ 4094 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4095 RAL_BARRIER_WRITE(sc); 4096 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4097 4098 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4099 sc->qfullmsk = 0; 4100 for (qid = 0; qid < 6; qid++) 4101 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4102 rt2860_reset_rx_ring(sc, &sc->rxq); 4103 } 4104 4105 int 4106 rt2860_load_microcode(struct rt2860_softc *sc) 4107 { 4108 const struct firmware *fp; 4109 int ntries, error; 4110 4111 RAL_LOCK_ASSERT(sc); 4112 4113 RAL_UNLOCK(sc); 4114 fp = firmware_get("rt2860fw"); 4115 RAL_LOCK(sc); 4116 if (fp == NULL) { 4117 device_printf(sc->sc_dev, 4118 "unable to receive rt2860fw firmware image\n"); 4119 return EINVAL; 4120 } 4121 4122 /* set "host program ram write selection" bit */ 4123 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4124 /* write microcode image */ 4125 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4126 /* kick microcontroller unit */ 4127 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4128 RAL_BARRIER_WRITE(sc); 4129 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4130 4131 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4132 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4133 4134 /* wait until microcontroller is ready */ 4135 RAL_BARRIER_READ_WRITE(sc); 4136 for (ntries = 0; ntries < 1000; ntries++) { 4137 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4138 break; 4139 DELAY(1000); 4140 } 4141 if (ntries == 1000) { 4142 device_printf(sc->sc_dev, 4143 "timeout waiting for MCU to initialize\n"); 4144 error = ETIMEDOUT; 4145 } else 4146 error = 0; 4147 4148 firmware_put(fp, FIRMWARE_UNLOAD); 4149 return error; 4150 } 4151 4152 /* 4153 * This function is called periodically to adjust Tx power based on 4154 * temperature variation. 4155 */ 4156 #ifdef NOT_YET 4157 static void 4158 rt2860_calib(struct rt2860_softc *sc) 4159 { 4160 struct ieee80211com *ic = &sc->sc_ic; 4161 const uint8_t *tssi; 4162 uint8_t step, bbp49; 4163 int8_t ridx, d; 4164 4165 /* read current temperature */ 4166 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4167 4168 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4169 tssi = &sc->tssi_2ghz[4]; 4170 step = sc->step_2ghz; 4171 } else { 4172 tssi = &sc->tssi_5ghz[4]; 4173 step = sc->step_5ghz; 4174 } 4175 4176 if (bbp49 < tssi[0]) { /* lower than reference */ 4177 /* use higher Tx power than default */ 4178 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4179 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4180 /* use lower Tx power than default */ 4181 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4182 } else { 4183 /* use default Tx power */ 4184 d = 0; 4185 } 4186 d *= step; 4187 4188 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4189 4190 /* write adjusted Tx power values for each Tx rate */ 4191 for (ridx = 0; ridx < 5; ridx++) { 4192 if (sc->txpow20mhz[ridx] == 0xffffffff) 4193 continue; 4194 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4195 b4inc(sc->txpow20mhz[ridx], d)); 4196 } 4197 } 4198 #endif 4199 4200 static void 4201 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4202 { 4203 uint32_t tmp; 4204 4205 if (aux) { 4206 if (sc->mac_ver == 0x5390) { 4207 rt2860_mcu_bbp_write(sc, 152, 4208 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4209 } else { 4210 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4211 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4212 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4213 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4214 } 4215 } else { 4216 if (sc->mac_ver == 0x5390) { 4217 rt2860_mcu_bbp_write(sc, 152, 4218 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4219 } else { 4220 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4221 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4222 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4223 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4224 } 4225 } 4226 } 4227 4228 static void 4229 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4230 { 4231 struct ieee80211com *ic = &sc->sc_ic; 4232 u_int chan, group; 4233 4234 chan = ieee80211_chan2ieee(ic, c); 4235 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4236 return; 4237 4238 if (sc->mac_ver >= 0x5390) 4239 rt5390_set_chan(sc, chan); 4240 else if (sc->mac_ver >= 0x3071) 4241 rt3090_set_chan(sc, chan); 4242 else 4243 rt2860_set_chan(sc, chan); 4244 4245 /* determine channel group */ 4246 if (chan <= 14) 4247 group = 0; 4248 else if (chan <= 64) 4249 group = 1; 4250 else if (chan <= 128) 4251 group = 2; 4252 else 4253 group = 3; 4254 4255 /* XXX necessary only when group has changed! */ 4256 if (sc->mac_ver < 0x5390) 4257 rt2860_select_chan_group(sc, group); 4258 4259 DELAY(1000); 4260 } 4261 4262 static int 4263 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4264 { 4265 struct ieee80211com *ic = vap->iv_ic; 4266 struct rt2860_txwi txwi; 4267 struct mbuf *m; 4268 int ridx; 4269 4270 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4271 return ENOBUFS; 4272 4273 memset(&txwi, 0, sizeof txwi); 4274 txwi.wcid = 0xff; 4275 txwi.len = htole16(m->m_pkthdr.len); 4276 /* send beacons at the lowest available rate */ 4277 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4278 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4279 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4280 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4281 txwi.phy |= htole16(RT2860_PHY_OFDM); 4282 txwi.txop = RT2860_TX_TXOP_HT; 4283 txwi.flags = RT2860_TX_TS; 4284 txwi.xflags = RT2860_TX_NSEQ; 4285 4286 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4287 (uint8_t *)&txwi, sizeof txwi); 4288 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4289 mtod(m, uint8_t *), m->m_pkthdr.len); 4290 4291 m_freem(m); 4292 4293 return 0; 4294 } 4295 4296 static void 4297 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4298 { 4299 struct ieee80211com *ic = &sc->sc_ic; 4300 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4301 uint32_t tmp; 4302 4303 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4304 4305 tmp &= ~0x1fffff; 4306 tmp |= vap->iv_bss->ni_intval * 16; 4307 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4308 if (vap->iv_opmode == IEEE80211_M_STA) { 4309 /* 4310 * Local TSF is always updated with remote TSF on beacon 4311 * reception. 4312 */ 4313 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4314 } 4315 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4316 vap->iv_opmode == IEEE80211_M_MBSS) { 4317 tmp |= RT2860_BCN_TX_EN; 4318 /* 4319 * Local TSF is updated with remote TSF on beacon reception 4320 * only if the remote TSF is greater than local TSF. 4321 */ 4322 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4323 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4324 tmp |= RT2860_BCN_TX_EN; 4325 /* SYNC with nobody */ 4326 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4327 } 4328 4329 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4330 } 4331