1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 /*- 22 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 23 * http://www.ralinktech.com/ 24 */ 25 26 #include <sys/param.h> 27 #include <sys/sysctl.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/firmware.h> 40 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_radiotap.h> 56 #include <net80211/ieee80211_regdomain.h> 57 #include <net80211/ieee80211_ratectl.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_ether.h> 64 65 #include <dev/ral/rt2860reg.h> 66 #include <dev/ral/rt2860var.h> 67 68 #define RAL_DEBUG 69 #ifdef RAL_DEBUG 70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n, x) 75 #endif 76 77 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 78 const char [IFNAMSIZ], int, enum ieee80211_opmode, 79 int, const uint8_t [IEEE80211_ADDR_LEN], 80 const uint8_t [IEEE80211_ADDR_LEN]); 81 static void rt2860_vap_delete(struct ieee80211vap *); 82 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 83 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 84 struct rt2860_tx_ring *); 85 static void rt2860_reset_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_free_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 90 static void rt2860_free_tx_pool(struct rt2860_softc *); 91 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 92 struct rt2860_rx_ring *); 93 static void rt2860_reset_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_free_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_updatestats(struct rt2860_softc *); 98 static void rt2860_newassoc(struct ieee80211_node *, int); 99 static void rt2860_node_free(struct ieee80211_node *); 100 #ifdef IEEE80211_HT 101 static int rt2860_ampdu_rx_start(struct ieee80211com *, 102 struct ieee80211_node *, uint8_t); 103 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 #endif 106 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 107 int); 108 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 109 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 110 static void rt2860_intr_coherent(struct rt2860_softc *); 111 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 112 static void rt2860_tx_intr(struct rt2860_softc *, int); 113 static void rt2860_rx_intr(struct rt2860_softc *); 114 static void rt2860_tbtt_intr(struct rt2860_softc *); 115 static void rt2860_gp_intr(struct rt2860_softc *); 116 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 117 struct ieee80211_node *); 118 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 119 const struct ieee80211_bpf_params *); 120 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 121 struct ieee80211_node *, 122 const struct ieee80211_bpf_params *params); 123 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 124 static void rt2860_start(struct rt2860_softc *); 125 static void rt2860_watchdog(void *); 126 static void rt2860_parent(struct ieee80211com *); 127 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 128 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 129 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 130 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 131 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 132 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 133 static void rt2860_enable_mrr(struct rt2860_softc *); 134 static void rt2860_set_txpreamble(struct rt2860_softc *); 135 static void rt2860_set_basicrates(struct rt2860_softc *, 136 const struct ieee80211_rateset *); 137 static void rt2860_scan_start(struct ieee80211com *); 138 static void rt2860_scan_end(struct ieee80211com *); 139 static void rt2860_getradiocaps(struct ieee80211com *, int, int *, 140 struct ieee80211_channel[]); 141 static void rt2860_set_channel(struct ieee80211com *); 142 static void rt2860_select_chan_group(struct rt2860_softc *, int); 143 static void rt2860_set_chan(struct rt2860_softc *, u_int); 144 static void rt3090_set_chan(struct rt2860_softc *, u_int); 145 static void rt5390_set_chan(struct rt2860_softc *, u_int); 146 static int rt3090_rf_init(struct rt2860_softc *); 147 static void rt5390_rf_init(struct rt2860_softc *); 148 static void rt3090_rf_wakeup(struct rt2860_softc *); 149 static void rt5390_rf_wakeup(struct rt2860_softc *); 150 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 151 uint8_t *); 152 static void rt3090_rf_setup(struct rt2860_softc *); 153 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 154 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 155 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 156 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 157 static void rt2860_update_promisc(struct ieee80211com *); 158 static void rt2860_updateslot(struct ieee80211com *); 159 static void rt2860_updateprot(struct rt2860_softc *); 160 static int rt2860_updateedca(struct ieee80211com *); 161 #ifdef HW_CRYPTO 162 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 163 struct ieee80211_key *); 164 static void rt2860_delete_key(struct ieee80211com *, 165 struct ieee80211_node *, struct ieee80211_key *); 166 #endif 167 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 168 static const char *rt2860_get_rf(uint16_t); 169 static int rt2860_read_eeprom(struct rt2860_softc *, 170 uint8_t macaddr[IEEE80211_ADDR_LEN]); 171 static int rt2860_bbp_init(struct rt2860_softc *); 172 static void rt5390_bbp_init(struct rt2860_softc *); 173 static int rt2860_txrx_enable(struct rt2860_softc *); 174 static void rt2860_init(void *); 175 static void rt2860_init_locked(struct rt2860_softc *); 176 static void rt2860_stop(void *); 177 static void rt2860_stop_locked(struct rt2860_softc *); 178 static int rt2860_load_microcode(struct rt2860_softc *); 179 #ifdef NOT_YET 180 static void rt2860_calib(struct rt2860_softc *); 181 #endif 182 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 183 static void rt2860_switch_chan(struct rt2860_softc *, 184 struct ieee80211_channel *); 185 static int rt2860_setup_beacon(struct rt2860_softc *, 186 struct ieee80211vap *); 187 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 188 189 static const struct { 190 uint32_t reg; 191 uint32_t val; 192 } rt2860_def_mac[] = { 193 RT2860_DEF_MAC 194 }; 195 196 static const struct { 197 uint8_t reg; 198 uint8_t val; 199 } rt2860_def_bbp[] = { 200 RT2860_DEF_BBP 201 }, rt5390_def_bbp[] = { 202 RT5390_DEF_BBP 203 }; 204 205 static const struct rfprog { 206 uint8_t chan; 207 uint32_t r1, r2, r3, r4; 208 } rt2860_rf2850[] = { 209 RT2860_RF2850 210 }; 211 212 struct { 213 uint8_t n, r, k; 214 } rt3090_freqs[] = { 215 RT3070_RF3052 216 }; 217 218 static const struct { 219 uint8_t reg; 220 uint8_t val; 221 } rt3090_def_rf[] = { 222 RT3070_DEF_RF 223 }, rt5390_def_rf[] = { 224 RT5390_DEF_RF 225 }, rt5392_def_rf[] = { 226 RT5392_DEF_RF 227 }; 228 229 static const uint8_t rt2860_chan_5ghz[] = 230 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 231 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 232 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 }; 233 234 int 235 rt2860_attach(device_t dev, int id) 236 { 237 struct rt2860_softc *sc = device_get_softc(dev); 238 struct ieee80211com *ic = &sc->sc_ic; 239 uint32_t tmp; 240 int error, ntries, qid; 241 242 sc->sc_dev = dev; 243 sc->sc_debug = 0; 244 245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 246 MTX_DEF | MTX_RECURSE); 247 248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 249 mbufq_init(&sc->sc_snd, ifqmaxlen); 250 251 /* wait for NIC to initialize */ 252 for (ntries = 0; ntries < 100; ntries++) { 253 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 254 if (tmp != 0 && tmp != 0xffffffff) 255 break; 256 DELAY(10); 257 } 258 if (ntries == 100) { 259 device_printf(sc->sc_dev, 260 "timeout waiting for NIC to initialize\n"); 261 error = EIO; 262 goto fail1; 263 } 264 sc->mac_ver = tmp >> 16; 265 sc->mac_rev = tmp & 0xffff; 266 267 if (sc->mac_ver != 0x2860 && 268 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 269 sc->sc_flags |= RT2860_ADVANCED_PS; 270 271 /* retrieve RF rev. no and various other things from EEPROM */ 272 rt2860_read_eeprom(sc, ic->ic_macaddr); 273 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 274 "RF %s (MIMO %dT%dR), address %6D\n", 275 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 276 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 277 278 /* 279 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 280 */ 281 for (qid = 0; qid < 6; qid++) { 282 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 283 device_printf(sc->sc_dev, 284 "could not allocate Tx ring %d\n", qid); 285 goto fail2; 286 } 287 } 288 289 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 290 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 291 goto fail2; 292 } 293 294 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 295 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 296 goto fail3; 297 } 298 299 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 300 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 301 WME_AC_VO : 5; 302 303 ic->ic_softc = sc; 304 ic->ic_name = device_get_nameunit(dev); 305 ic->ic_opmode = IEEE80211_M_STA; 306 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 307 308 /* set device capabilities */ 309 ic->ic_caps = 310 IEEE80211_C_STA /* station mode */ 311 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 312 | IEEE80211_C_HOSTAP /* hostap mode */ 313 | IEEE80211_C_MONITOR /* monitor mode */ 314 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 315 | IEEE80211_C_WDS /* 4-address traffic works */ 316 | IEEE80211_C_MBSS /* mesh point link mode */ 317 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 318 | IEEE80211_C_SHSLOT /* short slot time supported */ 319 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 320 #if 0 321 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 322 #endif 323 | IEEE80211_C_WME /* 802.11e */ 324 ; 325 326 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 327 ic->ic_channels); 328 329 ieee80211_ifattach(ic); 330 331 ic->ic_wme.wme_update = rt2860_updateedca; 332 ic->ic_scan_start = rt2860_scan_start; 333 ic->ic_scan_end = rt2860_scan_end; 334 ic->ic_getradiocaps = rt2860_getradiocaps; 335 ic->ic_set_channel = rt2860_set_channel; 336 ic->ic_updateslot = rt2860_updateslot; 337 ic->ic_update_promisc = rt2860_update_promisc; 338 ic->ic_raw_xmit = rt2860_raw_xmit; 339 sc->sc_node_free = ic->ic_node_free; 340 ic->ic_node_free = rt2860_node_free; 341 ic->ic_newassoc = rt2860_newassoc; 342 ic->ic_transmit = rt2860_transmit; 343 ic->ic_parent = rt2860_parent; 344 ic->ic_vap_create = rt2860_vap_create; 345 ic->ic_vap_delete = rt2860_vap_delete; 346 347 ieee80211_radiotap_attach(ic, 348 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 349 RT2860_TX_RADIOTAP_PRESENT, 350 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 351 RT2860_RX_RADIOTAP_PRESENT); 352 353 #ifdef RAL_DEBUG 354 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 355 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 356 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 357 #endif 358 if (bootverbose) 359 ieee80211_announce(ic); 360 361 return 0; 362 363 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 364 fail2: while (--qid >= 0) 365 rt2860_free_tx_ring(sc, &sc->txq[qid]); 366 fail1: mtx_destroy(&sc->sc_mtx); 367 return error; 368 } 369 370 int 371 rt2860_detach(void *xsc) 372 { 373 struct rt2860_softc *sc = xsc; 374 struct ieee80211com *ic = &sc->sc_ic; 375 int qid; 376 377 RAL_LOCK(sc); 378 rt2860_stop_locked(sc); 379 RAL_UNLOCK(sc); 380 381 ieee80211_ifdetach(ic); 382 mbufq_drain(&sc->sc_snd); 383 for (qid = 0; qid < 6; qid++) 384 rt2860_free_tx_ring(sc, &sc->txq[qid]); 385 rt2860_free_rx_ring(sc, &sc->rxq); 386 rt2860_free_tx_pool(sc); 387 388 mtx_destroy(&sc->sc_mtx); 389 390 return 0; 391 } 392 393 void 394 rt2860_shutdown(void *xsc) 395 { 396 struct rt2860_softc *sc = xsc; 397 398 rt2860_stop(sc); 399 } 400 401 void 402 rt2860_suspend(void *xsc) 403 { 404 struct rt2860_softc *sc = xsc; 405 406 rt2860_stop(sc); 407 } 408 409 void 410 rt2860_resume(void *xsc) 411 { 412 struct rt2860_softc *sc = xsc; 413 414 if (sc->sc_ic.ic_nrunning > 0) 415 rt2860_init(sc); 416 } 417 418 static struct ieee80211vap * 419 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 420 enum ieee80211_opmode opmode, int flags, 421 const uint8_t bssid[IEEE80211_ADDR_LEN], 422 const uint8_t mac[IEEE80211_ADDR_LEN]) 423 { 424 struct rt2860_softc *sc = ic->ic_softc; 425 struct rt2860_vap *rvp; 426 struct ieee80211vap *vap; 427 428 switch (opmode) { 429 case IEEE80211_M_STA: 430 case IEEE80211_M_IBSS: 431 case IEEE80211_M_AHDEMO: 432 case IEEE80211_M_MONITOR: 433 case IEEE80211_M_HOSTAP: 434 case IEEE80211_M_MBSS: 435 /* XXXRP: TBD */ 436 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 437 device_printf(sc->sc_dev, "only 1 vap supported\n"); 438 return NULL; 439 } 440 if (opmode == IEEE80211_M_STA) 441 flags |= IEEE80211_CLONE_NOBEACONS; 442 break; 443 case IEEE80211_M_WDS: 444 if (TAILQ_EMPTY(&ic->ic_vaps) || 445 ic->ic_opmode != IEEE80211_M_HOSTAP) { 446 device_printf(sc->sc_dev, 447 "wds only supported in ap mode\n"); 448 return NULL; 449 } 450 /* 451 * Silently remove any request for a unique 452 * bssid; WDS vap's always share the local 453 * mac address. 454 */ 455 flags &= ~IEEE80211_CLONE_BSSID; 456 break; 457 default: 458 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 459 return NULL; 460 } 461 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 462 vap = &rvp->ral_vap; 463 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 464 465 /* override state transition machine */ 466 rvp->ral_newstate = vap->iv_newstate; 467 vap->iv_newstate = rt2860_newstate; 468 #if 0 469 vap->iv_update_beacon = rt2860_beacon_update; 470 #endif 471 472 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 473 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 474 475 ieee80211_ratectl_init(vap); 476 /* complete setup */ 477 ieee80211_vap_attach(vap, ieee80211_media_change, 478 ieee80211_media_status, mac); 479 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 480 ic->ic_opmode = opmode; 481 return vap; 482 } 483 484 static void 485 rt2860_vap_delete(struct ieee80211vap *vap) 486 { 487 struct rt2860_vap *rvp = RT2860_VAP(vap); 488 489 ieee80211_ratectl_deinit(vap); 490 ieee80211_vap_detach(vap); 491 free(rvp, M_80211_VAP); 492 } 493 494 static void 495 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 496 { 497 if (error != 0) 498 return; 499 500 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 501 502 *(bus_addr_t *)arg = segs[0].ds_addr; 503 } 504 505 static int 506 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 507 { 508 int size, error; 509 510 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 511 512 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 513 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 514 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 517 goto fail; 518 } 519 520 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 521 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 522 if (error != 0) { 523 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 524 goto fail; 525 } 526 527 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 528 size, rt2860_dma_map_addr, &ring->paddr, 0); 529 if (error != 0) { 530 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 531 goto fail; 532 } 533 534 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 535 536 return 0; 537 538 fail: rt2860_free_tx_ring(sc, ring); 539 return error; 540 } 541 542 void 543 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 544 { 545 struct rt2860_tx_data *data; 546 int i; 547 548 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 549 if ((data = ring->data[i]) == NULL) 550 continue; /* nothing mapped in this slot */ 551 552 if (data->m != NULL) { 553 bus_dmamap_sync(sc->txwi_dmat, data->map, 554 BUS_DMASYNC_POSTWRITE); 555 bus_dmamap_unload(sc->txwi_dmat, data->map); 556 m_freem(data->m); 557 data->m = NULL; 558 } 559 if (data->ni != NULL) { 560 ieee80211_free_node(data->ni); 561 data->ni = NULL; 562 } 563 564 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 565 ring->data[i] = NULL; 566 } 567 568 ring->queued = 0; 569 ring->cur = ring->next = 0; 570 } 571 572 void 573 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 574 { 575 struct rt2860_tx_data *data; 576 int i; 577 578 if (ring->txd != NULL) { 579 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 580 BUS_DMASYNC_POSTWRITE); 581 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 582 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 583 } 584 if (ring->desc_dmat != NULL) 585 bus_dma_tag_destroy(ring->desc_dmat); 586 587 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 588 if ((data = ring->data[i]) == NULL) 589 continue; /* nothing mapped in this slot */ 590 591 if (data->m != NULL) { 592 bus_dmamap_sync(sc->txwi_dmat, data->map, 593 BUS_DMASYNC_POSTWRITE); 594 bus_dmamap_unload(sc->txwi_dmat, data->map); 595 m_freem(data->m); 596 } 597 if (data->ni != NULL) 598 ieee80211_free_node(data->ni); 599 600 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 601 } 602 } 603 604 /* 605 * Allocate a pool of TX Wireless Information blocks. 606 */ 607 int 608 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 609 { 610 caddr_t vaddr; 611 bus_addr_t paddr; 612 int i, size, error; 613 614 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 615 616 /* init data_pool early in case of failure.. */ 617 SLIST_INIT(&sc->data_pool); 618 619 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 620 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 621 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 622 if (error != 0) { 623 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 624 goto fail; 625 } 626 627 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 628 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 629 if (error != 0) { 630 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 631 goto fail; 632 } 633 634 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 635 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 636 if (error != 0) { 637 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 638 goto fail; 639 } 640 641 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 642 643 vaddr = sc->txwi_vaddr; 644 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 645 struct rt2860_tx_data *data = &sc->data[i]; 646 647 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 648 if (error != 0) { 649 device_printf(sc->sc_dev, "could not create DMA map\n"); 650 goto fail; 651 } 652 data->txwi = (struct rt2860_txwi *)vaddr; 653 data->paddr = paddr; 654 vaddr += RT2860_TXWI_DMASZ; 655 paddr += RT2860_TXWI_DMASZ; 656 657 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 658 } 659 660 return 0; 661 662 fail: rt2860_free_tx_pool(sc); 663 return error; 664 } 665 666 void 667 rt2860_free_tx_pool(struct rt2860_softc *sc) 668 { 669 if (sc->txwi_vaddr != NULL) { 670 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 671 BUS_DMASYNC_POSTWRITE); 672 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 673 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 674 } 675 if (sc->txwi_dmat != NULL) 676 bus_dma_tag_destroy(sc->txwi_dmat); 677 678 while (!SLIST_EMPTY(&sc->data_pool)) { 679 struct rt2860_tx_data *data; 680 data = SLIST_FIRST(&sc->data_pool); 681 bus_dmamap_destroy(sc->txwi_dmat, data->map); 682 SLIST_REMOVE_HEAD(&sc->data_pool, next); 683 } 684 } 685 686 int 687 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 688 { 689 bus_addr_t physaddr; 690 int i, size, error; 691 692 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 693 694 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 695 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 696 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 697 if (error != 0) { 698 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 699 goto fail; 700 } 701 702 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 703 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 704 if (error != 0) { 705 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 706 goto fail; 707 } 708 709 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 710 size, rt2860_dma_map_addr, &ring->paddr, 0); 711 if (error != 0) { 712 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 713 goto fail; 714 } 715 716 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 717 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 718 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 719 if (error != 0) { 720 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 721 goto fail; 722 } 723 724 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 725 struct rt2860_rx_data *data = &ring->data[i]; 726 struct rt2860_rxd *rxd = &ring->rxd[i]; 727 728 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 729 if (error != 0) { 730 device_printf(sc->sc_dev, "could not create DMA map\n"); 731 goto fail; 732 } 733 734 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 735 if (data->m == NULL) { 736 device_printf(sc->sc_dev, 737 "could not allocate rx mbuf\n"); 738 error = ENOMEM; 739 goto fail; 740 } 741 742 error = bus_dmamap_load(ring->data_dmat, data->map, 743 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 744 &physaddr, 0); 745 if (error != 0) { 746 device_printf(sc->sc_dev, 747 "could not load rx buf DMA map"); 748 goto fail; 749 } 750 751 rxd->sdp0 = htole32(physaddr); 752 rxd->sdl0 = htole16(MCLBYTES); 753 } 754 755 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 756 757 return 0; 758 759 fail: rt2860_free_rx_ring(sc, ring); 760 return error; 761 } 762 763 void 764 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 765 { 766 int i; 767 768 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 769 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 770 771 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 772 773 ring->cur = 0; 774 } 775 776 void 777 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 778 { 779 int i; 780 781 if (ring->rxd != NULL) { 782 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 783 BUS_DMASYNC_POSTWRITE); 784 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 785 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 786 } 787 if (ring->desc_dmat != NULL) 788 bus_dma_tag_destroy(ring->desc_dmat); 789 790 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 791 struct rt2860_rx_data *data = &ring->data[i]; 792 793 if (data->m != NULL) { 794 bus_dmamap_sync(ring->data_dmat, data->map, 795 BUS_DMASYNC_POSTREAD); 796 bus_dmamap_unload(ring->data_dmat, data->map); 797 m_freem(data->m); 798 } 799 if (data->map != NULL) 800 bus_dmamap_destroy(ring->data_dmat, data->map); 801 } 802 if (ring->data_dmat != NULL) 803 bus_dma_tag_destroy(ring->data_dmat); 804 } 805 806 static void 807 rt2860_updatestats(struct rt2860_softc *sc) 808 { 809 struct ieee80211com *ic = &sc->sc_ic; 810 811 /* 812 * In IBSS or HostAP modes (when the hardware sends beacons), the 813 * MAC can run into a livelock and start sending CTS-to-self frames 814 * like crazy if protection is enabled. Fortunately, we can detect 815 * when such a situation occurs and reset the MAC. 816 */ 817 if (ic->ic_curmode != IEEE80211_M_STA) { 818 /* check if we're in a livelock situation.. */ 819 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 820 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 821 /* ..and reset MAC/BBP for a while.. */ 822 DPRINTF(("CTS-to-self livelock detected\n")); 823 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 824 RAL_BARRIER_WRITE(sc); 825 DELAY(1); 826 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 827 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 828 } 829 } 830 } 831 832 static void 833 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 834 { 835 struct ieee80211com *ic = ni->ni_ic; 836 struct rt2860_softc *sc = ic->ic_softc; 837 uint8_t wcid; 838 839 wcid = IEEE80211_AID(ni->ni_associd); 840 if (isnew && ni->ni_associd != 0) { 841 sc->wcid2ni[wcid] = ni; 842 843 /* init WCID table entry */ 844 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 845 ni->ni_macaddr, IEEE80211_ADDR_LEN); 846 } 847 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 848 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 849 } 850 851 static void 852 rt2860_node_free(struct ieee80211_node *ni) 853 { 854 struct ieee80211com *ic = ni->ni_ic; 855 struct rt2860_softc *sc = ic->ic_softc; 856 uint8_t wcid; 857 858 if (ni->ni_associd != 0) { 859 wcid = IEEE80211_AID(ni->ni_associd); 860 861 /* clear Rx WCID search table entry */ 862 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 863 } 864 sc->sc_node_free(ni); 865 } 866 867 #ifdef IEEE80211_HT 868 static int 869 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 870 uint8_t tid) 871 { 872 struct rt2860_softc *sc = ic->ic_softc; 873 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 874 uint32_t tmp; 875 876 /* update BA session mask */ 877 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 878 tmp |= (1 << tid) << 16; 879 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 880 return 0; 881 } 882 883 static void 884 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 885 uint8_t tid) 886 { 887 struct rt2860_softc *sc = ic->ic_softc; 888 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 889 uint32_t tmp; 890 891 /* update BA session mask */ 892 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 893 tmp &= ~((1 << tid) << 16); 894 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 895 } 896 #endif 897 898 static int 899 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 900 { 901 struct rt2860_vap *rvp = RT2860_VAP(vap); 902 struct ieee80211com *ic = vap->iv_ic; 903 struct rt2860_softc *sc = ic->ic_softc; 904 uint32_t tmp; 905 int error; 906 907 if (vap->iv_state == IEEE80211_S_RUN) { 908 /* turn link LED off */ 909 rt2860_set_leds(sc, RT2860_LED_RADIO); 910 } 911 912 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 913 /* abort TSF synchronization */ 914 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 915 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 916 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 917 RT2860_TBTT_TIMER_EN)); 918 } 919 920 rt2860_set_gp_timer(sc, 0); 921 922 error = rvp->ral_newstate(vap, nstate, arg); 923 if (error != 0) 924 return (error); 925 926 if (nstate == IEEE80211_S_RUN) { 927 struct ieee80211_node *ni = vap->iv_bss; 928 929 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 930 rt2860_enable_mrr(sc); 931 rt2860_set_txpreamble(sc); 932 rt2860_set_basicrates(sc, &ni->ni_rates); 933 rt2860_set_bssid(sc, ni->ni_bssid); 934 } 935 936 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 937 vap->iv_opmode == IEEE80211_M_IBSS || 938 vap->iv_opmode == IEEE80211_M_MBSS) { 939 error = rt2860_setup_beacon(sc, vap); 940 if (error != 0) 941 return error; 942 } 943 944 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 945 rt2860_enable_tsf_sync(sc); 946 rt2860_set_gp_timer(sc, 500); 947 } 948 949 /* turn link LED on */ 950 rt2860_set_leds(sc, RT2860_LED_RADIO | 951 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 952 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 953 } 954 return error; 955 } 956 957 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 958 static uint16_t 959 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 960 { 961 uint32_t tmp; 962 uint16_t reg; 963 int ntries; 964 965 addr *= 2; 966 /*- 967 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 968 * DATA0: F E D C 969 * DATA1: B A 9 8 970 * DATA2: 7 6 5 4 971 * DATA3: 3 2 1 0 972 */ 973 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 974 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 975 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 976 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 977 for (ntries = 0; ntries < 500; ntries++) { 978 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 979 if (!(tmp & RT3070_EFSROM_KICK)) 980 break; 981 DELAY(2); 982 } 983 if (ntries == 500) 984 return 0xffff; 985 986 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 987 return 0xffff; /* address not found */ 988 989 /* determine to which 32-bit register our 16-bit word belongs */ 990 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 991 tmp = RAL_READ(sc, reg); 992 993 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 994 } 995 996 /* 997 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 998 * 93C66 or 93C86). 999 */ 1000 static uint16_t 1001 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1002 { 1003 uint32_t tmp; 1004 uint16_t val; 1005 int n; 1006 1007 /* clock C once before the first command */ 1008 RT2860_EEPROM_CTL(sc, 0); 1009 1010 RT2860_EEPROM_CTL(sc, RT2860_S); 1011 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1012 RT2860_EEPROM_CTL(sc, RT2860_S); 1013 1014 /* write start bit (1) */ 1015 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1016 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1017 1018 /* write READ opcode (10) */ 1019 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1020 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1021 RT2860_EEPROM_CTL(sc, RT2860_S); 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1023 1024 /* write address (A5-A0 or A7-A0) */ 1025 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1026 for (; n >= 0; n--) { 1027 RT2860_EEPROM_CTL(sc, RT2860_S | 1028 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1029 RT2860_EEPROM_CTL(sc, RT2860_S | 1030 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1031 } 1032 1033 RT2860_EEPROM_CTL(sc, RT2860_S); 1034 1035 /* read data Q15-Q0 */ 1036 val = 0; 1037 for (n = 15; n >= 0; n--) { 1038 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1039 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1040 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1041 RT2860_EEPROM_CTL(sc, RT2860_S); 1042 } 1043 1044 RT2860_EEPROM_CTL(sc, 0); 1045 1046 /* clear Chip Select and clock C */ 1047 RT2860_EEPROM_CTL(sc, RT2860_S); 1048 RT2860_EEPROM_CTL(sc, 0); 1049 RT2860_EEPROM_CTL(sc, RT2860_C); 1050 1051 return val; 1052 } 1053 1054 static __inline uint16_t 1055 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1056 { 1057 /* either eFUSE ROM or EEPROM */ 1058 return sc->sc_srom_read(sc, addr); 1059 } 1060 1061 static void 1062 rt2860_intr_coherent(struct rt2860_softc *sc) 1063 { 1064 uint32_t tmp; 1065 1066 /* DMA finds data coherent event when checking the DDONE bit */ 1067 1068 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1069 1070 /* restart DMA engine */ 1071 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1072 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1073 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1074 1075 (void)rt2860_txrx_enable(sc); 1076 } 1077 1078 static void 1079 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1080 { 1081 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 1082 struct ieee80211_node *ni; 1083 uint32_t stat; 1084 uint8_t wcid, mcs, pid; 1085 1086 /* drain Tx status FIFO (maxsize = 16) */ 1087 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 1088 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1089 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1090 1091 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1092 if (wcid > RT2860_WCID_MAX) 1093 continue; 1094 ni = sc->wcid2ni[wcid]; 1095 1096 /* if no ACK was requested, no feedback is available */ 1097 if (!(stat & RT2860_TXQ_ACKREQ) || ni == NULL) 1098 continue; 1099 1100 /* update per-STA AMRR stats */ 1101 if (stat & RT2860_TXQ_OK) { 1102 /* 1103 * Check if there were retries, ie if the Tx success 1104 * rate is different from the requested rate. Note 1105 * that it works only because we do not allow rate 1106 * fallback from OFDM to CCK. 1107 */ 1108 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1109 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1110 if (mcs + 1 != pid) 1111 txs->long_retries = 1; 1112 else 1113 txs->long_retries = 0; 1114 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 1115 ieee80211_ratectl_tx_complete(ni, txs); 1116 } else { 1117 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 1118 txs->long_retries = 1; /* XXX */ 1119 ieee80211_ratectl_tx_complete(ni, txs); 1120 if_inc_counter(ni->ni_vap->iv_ifp, 1121 IFCOUNTER_OERRORS, 1); 1122 } 1123 } 1124 } 1125 1126 static void 1127 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1128 { 1129 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1130 uint32_t hw; 1131 1132 rt2860_drain_stats_fifo(sc); 1133 1134 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1135 while (ring->next != hw) { 1136 struct rt2860_tx_data *data = ring->data[ring->next]; 1137 1138 if (data != NULL) { 1139 bus_dmamap_sync(sc->txwi_dmat, data->map, 1140 BUS_DMASYNC_POSTWRITE); 1141 bus_dmamap_unload(sc->txwi_dmat, data->map); 1142 ieee80211_tx_complete(data->ni, data->m, 0); 1143 data->ni = NULL; 1144 data->m = NULL; 1145 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1146 ring->data[ring->next] = NULL; 1147 } 1148 ring->queued--; 1149 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1150 } 1151 1152 sc->sc_tx_timer = 0; 1153 if (ring->queued < RT2860_TX_RING_COUNT) 1154 sc->qfullmsk &= ~(1 << qid); 1155 rt2860_start(sc); 1156 } 1157 1158 /* 1159 * Return the Rx chain with the highest RSSI for a given frame. 1160 */ 1161 static __inline uint8_t 1162 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1163 { 1164 uint8_t rxchain = 0; 1165 1166 if (sc->nrxchains > 1) { 1167 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1168 rxchain = 1; 1169 if (sc->nrxchains > 2) 1170 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1171 rxchain = 2; 1172 } 1173 return rxchain; 1174 } 1175 1176 static void 1177 rt2860_rx_intr(struct rt2860_softc *sc) 1178 { 1179 struct epoch_tracker et; 1180 struct rt2860_rx_radiotap_header *tap; 1181 struct ieee80211com *ic = &sc->sc_ic; 1182 struct ieee80211_frame *wh; 1183 struct ieee80211_node *ni; 1184 struct mbuf *m, *m1; 1185 bus_addr_t physaddr; 1186 uint32_t hw; 1187 uint16_t phy; 1188 uint8_t ant; 1189 int8_t rssi, nf; 1190 int error; 1191 1192 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1193 while (sc->rxq.cur != hw) { 1194 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1195 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1196 struct rt2860_rxwi *rxwi; 1197 1198 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1199 BUS_DMASYNC_POSTREAD); 1200 1201 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1202 DPRINTF(("RXD DDONE bit not set!\n")); 1203 break; /* should not happen */ 1204 } 1205 1206 if (__predict_false(rxd->flags & 1207 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1208 counter_u64_add(ic->ic_ierrors, 1); 1209 goto skip; 1210 } 1211 1212 #ifdef HW_CRYPTO 1213 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1214 /* report MIC failures to net80211 for TKIP */ 1215 ic->ic_stats.is_rx_locmicfail++; 1216 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1217 counter_u64_add(ic->ic_ierrors, 1); 1218 goto skip; 1219 } 1220 #endif 1221 1222 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1223 if (__predict_false(m1 == NULL)) { 1224 counter_u64_add(ic->ic_ierrors, 1); 1225 goto skip; 1226 } 1227 1228 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1229 BUS_DMASYNC_POSTREAD); 1230 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1231 1232 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1233 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1234 &physaddr, 0); 1235 if (__predict_false(error != 0)) { 1236 m_freem(m1); 1237 1238 /* try to reload the old mbuf */ 1239 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1240 mtod(data->m, void *), MCLBYTES, 1241 rt2860_dma_map_addr, &physaddr, 0); 1242 if (__predict_false(error != 0)) { 1243 panic("%s: could not load old rx mbuf", 1244 device_get_name(sc->sc_dev)); 1245 } 1246 /* physical address may have changed */ 1247 rxd->sdp0 = htole32(physaddr); 1248 counter_u64_add(ic->ic_ierrors, 1); 1249 goto skip; 1250 } 1251 1252 /* 1253 * New mbuf successfully loaded, update Rx ring and continue 1254 * processing. 1255 */ 1256 m = data->m; 1257 data->m = m1; 1258 rxd->sdp0 = htole32(physaddr); 1259 1260 rxwi = mtod(m, struct rt2860_rxwi *); 1261 1262 /* finalize mbuf */ 1263 m->m_data = (caddr_t)(rxwi + 1); 1264 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1265 1266 wh = mtod(m, struct ieee80211_frame *); 1267 #ifdef HW_CRYPTO 1268 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1269 /* frame is decrypted by hardware */ 1270 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1271 } 1272 #endif 1273 1274 /* HW may insert 2 padding bytes after 802.11 header */ 1275 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1276 u_int hdrlen = ieee80211_hdrsize(wh); 1277 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1278 m->m_data += 2; 1279 wh = mtod(m, struct ieee80211_frame *); 1280 } 1281 1282 ant = rt2860_maxrssi_chain(sc, rxwi); 1283 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1284 nf = RT2860_NOISE_FLOOR; 1285 1286 if (ieee80211_radiotap_active(ic)) { 1287 tap = &sc->sc_rxtap; 1288 tap->wr_flags = 0; 1289 tap->wr_antenna = ant; 1290 tap->wr_antsignal = nf + rssi; 1291 tap->wr_antnoise = nf; 1292 /* in case it can't be found below */ 1293 tap->wr_rate = 2; 1294 phy = le16toh(rxwi->phy); 1295 switch (phy & RT2860_PHY_MODE) { 1296 case RT2860_PHY_CCK: 1297 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1298 case 0: tap->wr_rate = 2; break; 1299 case 1: tap->wr_rate = 4; break; 1300 case 2: tap->wr_rate = 11; break; 1301 case 3: tap->wr_rate = 22; break; 1302 } 1303 if (phy & RT2860_PHY_SHPRE) 1304 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1305 break; 1306 case RT2860_PHY_OFDM: 1307 switch (phy & RT2860_PHY_MCS) { 1308 case 0: tap->wr_rate = 12; break; 1309 case 1: tap->wr_rate = 18; break; 1310 case 2: tap->wr_rate = 24; break; 1311 case 3: tap->wr_rate = 36; break; 1312 case 4: tap->wr_rate = 48; break; 1313 case 5: tap->wr_rate = 72; break; 1314 case 6: tap->wr_rate = 96; break; 1315 case 7: tap->wr_rate = 108; break; 1316 } 1317 break; 1318 } 1319 } 1320 1321 RAL_UNLOCK(sc); 1322 wh = mtod(m, struct ieee80211_frame *); 1323 1324 /* send the frame to the 802.11 layer */ 1325 ni = ieee80211_find_rxnode(ic, 1326 (struct ieee80211_frame_min *)wh); 1327 NET_EPOCH_ENTER(et); 1328 if (ni != NULL) { 1329 (void)ieee80211_input(ni, m, rssi - nf, nf); 1330 ieee80211_free_node(ni); 1331 } else 1332 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1333 NET_EPOCH_EXIT(et); 1334 1335 RAL_LOCK(sc); 1336 1337 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1338 1339 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1340 BUS_DMASYNC_PREWRITE); 1341 1342 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1343 } 1344 1345 /* tell HW what we have processed */ 1346 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1347 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1348 } 1349 1350 static void 1351 rt2860_tbtt_intr(struct rt2860_softc *sc) 1352 { 1353 #if 0 1354 struct ieee80211com *ic = &sc->sc_ic; 1355 1356 #ifndef IEEE80211_STA_ONLY 1357 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1358 /* one less beacon until next DTIM */ 1359 if (ic->ic_dtim_count == 0) 1360 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1361 else 1362 ic->ic_dtim_count--; 1363 1364 /* update dynamic parts of beacon */ 1365 rt2860_setup_beacon(sc); 1366 1367 /* flush buffered multicast frames */ 1368 if (ic->ic_dtim_count == 0) 1369 ieee80211_notify_dtim(ic); 1370 } 1371 #endif 1372 /* check if protection mode has changed */ 1373 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1374 rt2860_updateprot(sc); 1375 sc->sc_ic_flags = ic->ic_flags; 1376 } 1377 #endif 1378 } 1379 1380 static void 1381 rt2860_gp_intr(struct rt2860_softc *sc) 1382 { 1383 struct ieee80211com *ic = &sc->sc_ic; 1384 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1385 1386 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1387 1388 if (vap->iv_state == IEEE80211_S_RUN) 1389 rt2860_updatestats(sc); 1390 } 1391 1392 void 1393 rt2860_intr(void *arg) 1394 { 1395 struct rt2860_softc *sc = arg; 1396 uint32_t r; 1397 1398 RAL_LOCK(sc); 1399 1400 r = RAL_READ(sc, RT2860_INT_STATUS); 1401 if (__predict_false(r == 0xffffffff)) { 1402 RAL_UNLOCK(sc); 1403 return; /* device likely went away */ 1404 } 1405 if (r == 0) { 1406 RAL_UNLOCK(sc); 1407 return; /* not for us */ 1408 } 1409 1410 /* acknowledge interrupts */ 1411 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1412 1413 if (r & RT2860_TX_RX_COHERENT) 1414 rt2860_intr_coherent(sc); 1415 1416 if (r & RT2860_MAC_INT_2) /* TX status */ 1417 rt2860_drain_stats_fifo(sc); 1418 1419 if (r & RT2860_TX_DONE_INT5) 1420 rt2860_tx_intr(sc, 5); 1421 1422 if (r & RT2860_RX_DONE_INT) 1423 rt2860_rx_intr(sc); 1424 1425 if (r & RT2860_TX_DONE_INT4) 1426 rt2860_tx_intr(sc, 4); 1427 1428 if (r & RT2860_TX_DONE_INT3) 1429 rt2860_tx_intr(sc, 3); 1430 1431 if (r & RT2860_TX_DONE_INT2) 1432 rt2860_tx_intr(sc, 2); 1433 1434 if (r & RT2860_TX_DONE_INT1) 1435 rt2860_tx_intr(sc, 1); 1436 1437 if (r & RT2860_TX_DONE_INT0) 1438 rt2860_tx_intr(sc, 0); 1439 1440 if (r & RT2860_MAC_INT_0) /* TBTT */ 1441 rt2860_tbtt_intr(sc); 1442 1443 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1444 /* TBD wakeup */; 1445 1446 if (r & RT2860_MAC_INT_4) /* GP timer */ 1447 rt2860_gp_intr(sc); 1448 1449 RAL_UNLOCK(sc); 1450 } 1451 1452 static int 1453 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1454 { 1455 struct ieee80211com *ic = &sc->sc_ic; 1456 struct ieee80211vap *vap = ni->ni_vap; 1457 struct rt2860_tx_ring *ring; 1458 struct rt2860_tx_data *data; 1459 struct rt2860_txd *txd; 1460 struct rt2860_txwi *txwi; 1461 struct ieee80211_frame *wh; 1462 const struct ieee80211_txparam *tp = ni->ni_txparms; 1463 struct ieee80211_key *k; 1464 struct mbuf *m1; 1465 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1466 bus_dma_segment_t *seg; 1467 u_int hdrlen; 1468 uint16_t qos, dur; 1469 uint8_t type, qsel, mcs, pid, qid; 1470 int i, nsegs, ntxds, pad, rate, ridx, error; 1471 1472 /* the data pool contains at least one element, pick the first */ 1473 data = SLIST_FIRST(&sc->data_pool); 1474 1475 wh = mtod(m, struct ieee80211_frame *); 1476 1477 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1478 k = ieee80211_crypto_encap(ni, m); 1479 if (k == NULL) { 1480 m_freem(m); 1481 return ENOBUFS; 1482 } 1483 1484 /* packet header may have moved, reset our local pointer */ 1485 wh = mtod(m, struct ieee80211_frame *); 1486 } 1487 1488 hdrlen = ieee80211_anyhdrsize(wh); 1489 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1490 1491 if (m->m_flags & M_EAPOL) { 1492 rate = tp->mgmtrate; 1493 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1494 rate = tp->mcastrate; 1495 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1496 rate = tp->ucastrate; 1497 } else { 1498 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1499 rate = ni->ni_txrate; 1500 } 1501 rate &= IEEE80211_RATE_VAL; 1502 1503 qid = M_WME_GETAC(m); 1504 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1505 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1506 } else { 1507 qos = 0; 1508 } 1509 ring = &sc->txq[qid]; 1510 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1511 1512 /* get MCS code from rate index */ 1513 mcs = rt2860_rates[ridx].mcs; 1514 1515 /* setup TX Wireless Information */ 1516 txwi = data->txwi; 1517 txwi->flags = 0; 1518 /* let HW generate seq numbers for non-QoS frames */ 1519 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1520 if (type == IEEE80211_FC0_TYPE_DATA) 1521 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1522 else 1523 txwi->wcid = 0xff; 1524 txwi->len = htole16(m->m_pkthdr.len); 1525 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1526 txwi->phy = htole16(RT2860_PHY_CCK); 1527 if (ridx != RT2860_RIDX_CCK1 && 1528 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1529 mcs |= RT2860_PHY_SHPRE; 1530 } else 1531 txwi->phy = htole16(RT2860_PHY_OFDM); 1532 txwi->phy |= htole16(mcs); 1533 1534 /* 1535 * We store the MCS code into the driver-private PacketID field. 1536 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1537 * that we know at which initial rate the frame was transmitted. 1538 * We add 1 to the MCS code because setting the PacketID field to 1539 * 0 means that we don't want feedback in TX_STAT_FIFO. 1540 */ 1541 pid = (mcs + 1) & 0xf; 1542 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1543 1544 /* check if RTS/CTS or CTS-to-self protection is required */ 1545 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1546 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1547 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1548 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1549 txwi->txop = RT2860_TX_TXOP_HT; 1550 else 1551 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1552 1553 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1554 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1555 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1556 txwi->xflags |= RT2860_TX_ACK; 1557 1558 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1559 dur = rt2860_rates[ridx].sp_ack_dur; 1560 else 1561 dur = rt2860_rates[ridx].lp_ack_dur; 1562 *(uint16_t *)wh->i_dur = htole16(dur); 1563 } 1564 /* ask MAC to insert timestamp into probe responses */ 1565 if ((wh->i_fc[0] & 1566 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1567 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1568 /* NOTE: beacons do not pass through tx_data() */ 1569 txwi->flags |= RT2860_TX_TS; 1570 1571 if (ieee80211_radiotap_active_vap(vap)) { 1572 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1573 1574 tap->wt_flags = 0; 1575 tap->wt_rate = rate; 1576 if (mcs & RT2860_PHY_SHPRE) 1577 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1578 1579 ieee80211_radiotap_tx(vap, m); 1580 } 1581 1582 pad = (hdrlen + 3) & ~3; 1583 1584 /* copy and trim 802.11 header */ 1585 memcpy(txwi + 1, wh, hdrlen); 1586 m_adj(m, hdrlen); 1587 1588 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1589 &nsegs, 0); 1590 if (__predict_false(error != 0 && error != EFBIG)) { 1591 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1592 error); 1593 m_freem(m); 1594 return error; 1595 } 1596 if (__predict_true(error == 0)) { 1597 /* determine how many TXDs are required */ 1598 ntxds = 1 + (nsegs / 2); 1599 1600 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1601 /* not enough free TXDs, force mbuf defrag */ 1602 bus_dmamap_unload(sc->txwi_dmat, data->map); 1603 error = EFBIG; 1604 } 1605 } 1606 if (__predict_false(error != 0)) { 1607 m1 = m_defrag(m, M_NOWAIT); 1608 if (m1 == NULL) { 1609 device_printf(sc->sc_dev, 1610 "could not defragment mbuf\n"); 1611 m_freem(m); 1612 return ENOBUFS; 1613 } 1614 m = m1; 1615 1616 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1617 segs, &nsegs, 0); 1618 if (__predict_false(error != 0)) { 1619 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1620 error); 1621 m_freem(m); 1622 return error; 1623 } 1624 1625 /* determine how many TXDs are now required */ 1626 ntxds = 1 + (nsegs / 2); 1627 1628 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1629 /* this is a hopeless case, drop the mbuf! */ 1630 bus_dmamap_unload(sc->txwi_dmat, data->map); 1631 m_freem(m); 1632 return ENOBUFS; 1633 } 1634 } 1635 1636 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1637 1638 /* first segment is TXWI + 802.11 header */ 1639 txd = &ring->txd[ring->cur]; 1640 txd->sdp0 = htole32(data->paddr); 1641 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1642 txd->flags = qsel; 1643 1644 /* setup payload segments */ 1645 seg = &segs[0]; 1646 for (i = nsegs; i >= 2; i -= 2) { 1647 txd->sdp1 = htole32(seg->ds_addr); 1648 txd->sdl1 = htole16(seg->ds_len); 1649 seg++; 1650 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1651 /* grab a new Tx descriptor */ 1652 txd = &ring->txd[ring->cur]; 1653 txd->sdp0 = htole32(seg->ds_addr); 1654 txd->sdl0 = htole16(seg->ds_len); 1655 txd->flags = qsel; 1656 seg++; 1657 } 1658 /* finalize last segment */ 1659 if (i > 0) { 1660 txd->sdp1 = htole32(seg->ds_addr); 1661 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1662 } else { 1663 txd->sdl0 |= htole16(RT2860_TX_LS0); 1664 txd->sdl1 = 0; 1665 } 1666 1667 /* remove from the free pool and link it into the SW Tx slot */ 1668 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1669 data->m = m; 1670 data->ni = ni; 1671 ring->data[ring->cur] = data; 1672 1673 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1674 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1675 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1676 1677 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1678 qid, txwi->wcid, nsegs, ridx)); 1679 1680 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1681 ring->queued += ntxds; 1682 if (ring->queued >= RT2860_TX_RING_COUNT) 1683 sc->qfullmsk |= 1 << qid; 1684 1685 /* kick Tx */ 1686 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1687 1688 return 0; 1689 } 1690 1691 static int 1692 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1693 const struct ieee80211_bpf_params *params) 1694 { 1695 struct ieee80211com *ic = ni->ni_ic; 1696 struct rt2860_softc *sc = ic->ic_softc; 1697 int error; 1698 1699 RAL_LOCK(sc); 1700 1701 /* prevent management frames from being sent if we're not ready */ 1702 if (!(sc->sc_flags & RT2860_RUNNING)) { 1703 RAL_UNLOCK(sc); 1704 m_freem(m); 1705 return ENETDOWN; 1706 } 1707 if (params == NULL) { 1708 /* 1709 * Legacy path; interpret frame contents to decide 1710 * precisely how to send the frame. 1711 */ 1712 error = rt2860_tx(sc, m, ni); 1713 } else { 1714 /* 1715 * Caller supplied explicit parameters to use in 1716 * sending the frame. 1717 */ 1718 error = rt2860_tx_raw(sc, m, ni, params); 1719 } 1720 sc->sc_tx_timer = 5; 1721 RAL_UNLOCK(sc); 1722 return error; 1723 } 1724 1725 static int 1726 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1727 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1728 { 1729 struct ieee80211com *ic = &sc->sc_ic; 1730 struct ieee80211vap *vap = ni->ni_vap; 1731 struct rt2860_tx_ring *ring; 1732 struct rt2860_tx_data *data; 1733 struct rt2860_txd *txd; 1734 struct rt2860_txwi *txwi; 1735 struct ieee80211_frame *wh; 1736 struct mbuf *m1; 1737 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1738 bus_dma_segment_t *seg; 1739 u_int hdrlen; 1740 uint16_t dur; 1741 uint8_t qsel, mcs, pid, qid; 1742 int i, nsegs, ntxds, pad, rate, ridx, error; 1743 1744 /* the data pool contains at least one element, pick the first */ 1745 data = SLIST_FIRST(&sc->data_pool); 1746 1747 wh = mtod(m, struct ieee80211_frame *); 1748 hdrlen = ieee80211_hdrsize(wh); 1749 1750 /* Choose a TX rate index. */ 1751 rate = params->ibp_rate0; 1752 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1753 rate & IEEE80211_RATE_VAL); 1754 if (ridx == (uint8_t)-1) { 1755 /* XXX fall back to mcast/mgmt rate? */ 1756 m_freem(m); 1757 return EINVAL; 1758 } 1759 1760 qid = params->ibp_pri & 3; 1761 ring = &sc->txq[qid]; 1762 1763 /* get MCS code from rate index */ 1764 mcs = rt2860_rates[ridx].mcs; 1765 1766 /* setup TX Wireless Information */ 1767 txwi = data->txwi; 1768 txwi->flags = 0; 1769 /* let HW generate seq numbers for non-QoS frames */ 1770 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1771 txwi->wcid = 0xff; 1772 txwi->len = htole16(m->m_pkthdr.len); 1773 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1774 txwi->phy = htole16(RT2860_PHY_CCK); 1775 if (ridx != RT2860_RIDX_CCK1 && 1776 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1777 mcs |= RT2860_PHY_SHPRE; 1778 } else 1779 txwi->phy = htole16(RT2860_PHY_OFDM); 1780 txwi->phy |= htole16(mcs); 1781 1782 /* 1783 * We store the MCS code into the driver-private PacketID field. 1784 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1785 * that we know at which initial rate the frame was transmitted. 1786 * We add 1 to the MCS code because setting the PacketID field to 1787 * 0 means that we don't want feedback in TX_STAT_FIFO. 1788 */ 1789 pid = (mcs + 1) & 0xf; 1790 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1791 1792 /* check if RTS/CTS or CTS-to-self protection is required */ 1793 if (params->ibp_flags & IEEE80211_BPF_RTS || 1794 params->ibp_flags & IEEE80211_BPF_CTS) 1795 txwi->txop = RT2860_TX_TXOP_HT; 1796 else 1797 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1798 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1799 txwi->xflags |= RT2860_TX_ACK; 1800 1801 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1802 dur = rt2860_rates[ridx].sp_ack_dur; 1803 else 1804 dur = rt2860_rates[ridx].lp_ack_dur; 1805 *(uint16_t *)wh->i_dur = htole16(dur); 1806 } 1807 /* ask MAC to insert timestamp into probe responses */ 1808 if ((wh->i_fc[0] & 1809 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1810 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1811 /* NOTE: beacons do not pass through tx_data() */ 1812 txwi->flags |= RT2860_TX_TS; 1813 1814 if (ieee80211_radiotap_active_vap(vap)) { 1815 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1816 1817 tap->wt_flags = 0; 1818 tap->wt_rate = rate; 1819 if (mcs & RT2860_PHY_SHPRE) 1820 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1821 1822 ieee80211_radiotap_tx(vap, m); 1823 } 1824 1825 pad = (hdrlen + 3) & ~3; 1826 1827 /* copy and trim 802.11 header */ 1828 memcpy(txwi + 1, wh, hdrlen); 1829 m_adj(m, hdrlen); 1830 1831 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1832 &nsegs, 0); 1833 if (__predict_false(error != 0 && error != EFBIG)) { 1834 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1835 error); 1836 m_freem(m); 1837 return error; 1838 } 1839 if (__predict_true(error == 0)) { 1840 /* determine how many TXDs are required */ 1841 ntxds = 1 + (nsegs / 2); 1842 1843 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1844 /* not enough free TXDs, force mbuf defrag */ 1845 bus_dmamap_unload(sc->txwi_dmat, data->map); 1846 error = EFBIG; 1847 } 1848 } 1849 if (__predict_false(error != 0)) { 1850 m1 = m_defrag(m, M_NOWAIT); 1851 if (m1 == NULL) { 1852 device_printf(sc->sc_dev, 1853 "could not defragment mbuf\n"); 1854 m_freem(m); 1855 return ENOBUFS; 1856 } 1857 m = m1; 1858 1859 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1860 segs, &nsegs, 0); 1861 if (__predict_false(error != 0)) { 1862 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1863 error); 1864 m_freem(m); 1865 return error; 1866 } 1867 1868 /* determine how many TXDs are now required */ 1869 ntxds = 1 + (nsegs / 2); 1870 1871 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1872 /* this is a hopeless case, drop the mbuf! */ 1873 bus_dmamap_unload(sc->txwi_dmat, data->map); 1874 m_freem(m); 1875 return ENOBUFS; 1876 } 1877 } 1878 1879 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1880 1881 /* first segment is TXWI + 802.11 header */ 1882 txd = &ring->txd[ring->cur]; 1883 txd->sdp0 = htole32(data->paddr); 1884 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1885 txd->flags = qsel; 1886 1887 /* setup payload segments */ 1888 seg = &segs[0]; 1889 for (i = nsegs; i >= 2; i -= 2) { 1890 txd->sdp1 = htole32(seg->ds_addr); 1891 txd->sdl1 = htole16(seg->ds_len); 1892 seg++; 1893 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1894 /* grab a new Tx descriptor */ 1895 txd = &ring->txd[ring->cur]; 1896 txd->sdp0 = htole32(seg->ds_addr); 1897 txd->sdl0 = htole16(seg->ds_len); 1898 txd->flags = qsel; 1899 seg++; 1900 } 1901 /* finalize last segment */ 1902 if (i > 0) { 1903 txd->sdp1 = htole32(seg->ds_addr); 1904 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1905 } else { 1906 txd->sdl0 |= htole16(RT2860_TX_LS0); 1907 txd->sdl1 = 0; 1908 } 1909 1910 /* remove from the free pool and link it into the SW Tx slot */ 1911 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1912 data->m = m; 1913 data->ni = ni; 1914 ring->data[ring->cur] = data; 1915 1916 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1917 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1918 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1919 1920 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1921 qid, txwi->wcid, nsegs, ridx)); 1922 1923 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1924 ring->queued += ntxds; 1925 if (ring->queued >= RT2860_TX_RING_COUNT) 1926 sc->qfullmsk |= 1 << qid; 1927 1928 /* kick Tx */ 1929 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1930 1931 return 0; 1932 } 1933 1934 static int 1935 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1936 { 1937 struct rt2860_softc *sc = ic->ic_softc; 1938 int error; 1939 1940 RAL_LOCK(sc); 1941 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 1942 RAL_UNLOCK(sc); 1943 return (ENXIO); 1944 } 1945 error = mbufq_enqueue(&sc->sc_snd, m); 1946 if (error) { 1947 RAL_UNLOCK(sc); 1948 return (error); 1949 } 1950 rt2860_start(sc); 1951 RAL_UNLOCK(sc); 1952 1953 return (0); 1954 } 1955 1956 static void 1957 rt2860_start(struct rt2860_softc *sc) 1958 { 1959 struct ieee80211_node *ni; 1960 struct mbuf *m; 1961 1962 RAL_LOCK_ASSERT(sc); 1963 1964 if ((sc->sc_flags & RT2860_RUNNING) == 0) 1965 return; 1966 1967 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1968 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1969 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1970 if (rt2860_tx(sc, m, ni) != 0) { 1971 if_inc_counter(ni->ni_vap->iv_ifp, 1972 IFCOUNTER_OERRORS, 1); 1973 ieee80211_free_node(ni); 1974 continue; 1975 } 1976 sc->sc_tx_timer = 5; 1977 } 1978 } 1979 1980 static void 1981 rt2860_watchdog(void *arg) 1982 { 1983 struct rt2860_softc *sc = arg; 1984 1985 RAL_LOCK_ASSERT(sc); 1986 1987 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 1988 1989 if (sc->sc_invalid) /* card ejected */ 1990 return; 1991 1992 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1993 device_printf(sc->sc_dev, "device timeout\n"); 1994 rt2860_stop_locked(sc); 1995 rt2860_init_locked(sc); 1996 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1997 return; 1998 } 1999 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 2000 } 2001 2002 static void 2003 rt2860_parent(struct ieee80211com *ic) 2004 { 2005 struct rt2860_softc *sc = ic->ic_softc; 2006 int startall = 0; 2007 2008 RAL_LOCK(sc); 2009 if (ic->ic_nrunning> 0) { 2010 if (!(sc->sc_flags & RT2860_RUNNING)) { 2011 rt2860_init_locked(sc); 2012 startall = 1; 2013 } else 2014 rt2860_update_promisc(ic); 2015 } else if (sc->sc_flags & RT2860_RUNNING) 2016 rt2860_stop_locked(sc); 2017 RAL_UNLOCK(sc); 2018 if (startall) 2019 ieee80211_start_all(ic); 2020 } 2021 2022 /* 2023 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2024 * We access the BBP through the 8051 microcontroller unit which means that 2025 * the microcode must be loaded first. 2026 */ 2027 void 2028 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2029 { 2030 int ntries; 2031 2032 for (ntries = 0; ntries < 100; ntries++) { 2033 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2034 break; 2035 DELAY(1); 2036 } 2037 if (ntries == 100) { 2038 device_printf(sc->sc_dev, 2039 "could not write to BBP through MCU\n"); 2040 return; 2041 } 2042 2043 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2044 RT2860_BBP_CSR_KICK | reg << 8 | val); 2045 RAL_BARRIER_WRITE(sc); 2046 2047 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2048 DELAY(1000); 2049 } 2050 2051 uint8_t 2052 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2053 { 2054 uint32_t val; 2055 int ntries; 2056 2057 for (ntries = 0; ntries < 100; ntries++) { 2058 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2059 break; 2060 DELAY(1); 2061 } 2062 if (ntries == 100) { 2063 device_printf(sc->sc_dev, 2064 "could not read from BBP through MCU\n"); 2065 return 0; 2066 } 2067 2068 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2069 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2070 RAL_BARRIER_WRITE(sc); 2071 2072 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2073 DELAY(1000); 2074 2075 for (ntries = 0; ntries < 100; ntries++) { 2076 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2077 if (!(val & RT2860_BBP_CSR_KICK)) 2078 return val & 0xff; 2079 DELAY(1); 2080 } 2081 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2082 2083 return 0; 2084 } 2085 2086 /* 2087 * Write to one of the 4 programmable 24-bit RF registers. 2088 */ 2089 static void 2090 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2091 { 2092 uint32_t tmp; 2093 int ntries; 2094 2095 for (ntries = 0; ntries < 100; ntries++) { 2096 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2097 break; 2098 DELAY(1); 2099 } 2100 if (ntries == 100) { 2101 device_printf(sc->sc_dev, "could not write to RF\n"); 2102 return; 2103 } 2104 2105 /* RF registers are 24-bit on the RT2860 */ 2106 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2107 (val & 0x3fffff) << 2 | (reg & 3); 2108 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2109 } 2110 2111 static uint8_t 2112 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2113 { 2114 uint32_t tmp; 2115 int ntries; 2116 2117 for (ntries = 0; ntries < 100; ntries++) { 2118 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2119 break; 2120 DELAY(1); 2121 } 2122 if (ntries == 100) { 2123 device_printf(sc->sc_dev, "could not read RF register\n"); 2124 return 0xff; 2125 } 2126 tmp = RT3070_RF_KICK | reg << 8; 2127 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2128 2129 for (ntries = 0; ntries < 100; ntries++) { 2130 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2131 if (!(tmp & RT3070_RF_KICK)) 2132 break; 2133 DELAY(1); 2134 } 2135 if (ntries == 100) { 2136 device_printf(sc->sc_dev, "could not read RF register\n"); 2137 return 0xff; 2138 } 2139 return tmp & 0xff; 2140 } 2141 2142 void 2143 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2144 { 2145 uint32_t tmp; 2146 int ntries; 2147 2148 for (ntries = 0; ntries < 10; ntries++) { 2149 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2150 break; 2151 DELAY(10); 2152 } 2153 if (ntries == 10) { 2154 device_printf(sc->sc_dev, "could not write to RF\n"); 2155 return; 2156 } 2157 2158 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2159 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2160 } 2161 2162 /* 2163 * Send a command to the 8051 microcontroller unit. 2164 */ 2165 int 2166 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2167 { 2168 int slot, ntries; 2169 uint32_t tmp; 2170 uint8_t cid; 2171 2172 for (ntries = 0; ntries < 100; ntries++) { 2173 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2174 break; 2175 DELAY(2); 2176 } 2177 if (ntries == 100) 2178 return EIO; 2179 2180 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2181 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2182 RAL_BARRIER_WRITE(sc); 2183 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2184 2185 if (!wait) 2186 return 0; 2187 /* wait for the command to complete */ 2188 for (ntries = 0; ntries < 200; ntries++) { 2189 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2190 /* find the command slot */ 2191 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2192 if ((tmp & 0xff) == cid) 2193 break; 2194 if (slot < 4) 2195 break; 2196 DELAY(100); 2197 } 2198 if (ntries == 200) { 2199 /* clear command and status */ 2200 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2201 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2202 return ETIMEDOUT; 2203 } 2204 /* get command status (1 means success) */ 2205 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2206 tmp = (tmp >> (slot * 8)) & 0xff; 2207 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2208 cmd, slot, tmp)); 2209 /* clear command and status */ 2210 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2211 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2212 return (tmp == 1) ? 0 : EIO; 2213 } 2214 2215 static void 2216 rt2860_enable_mrr(struct rt2860_softc *sc) 2217 { 2218 #define CCK(mcs) (mcs) 2219 #define OFDM(mcs) (1U << 3 | (mcs)) 2220 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2221 OFDM(6) << 28 | /* 54->48 */ 2222 OFDM(5) << 24 | /* 48->36 */ 2223 OFDM(4) << 20 | /* 36->24 */ 2224 OFDM(3) << 16 | /* 24->18 */ 2225 OFDM(2) << 12 | /* 18->12 */ 2226 OFDM(1) << 8 | /* 12-> 9 */ 2227 OFDM(0) << 4 | /* 9-> 6 */ 2228 OFDM(0)); /* 6-> 6 */ 2229 2230 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2231 CCK(2) << 12 | /* 11->5.5 */ 2232 CCK(1) << 8 | /* 5.5-> 2 */ 2233 CCK(0) << 4 | /* 2-> 1 */ 2234 CCK(0)); /* 1-> 1 */ 2235 #undef OFDM 2236 #undef CCK 2237 } 2238 2239 static void 2240 rt2860_set_txpreamble(struct rt2860_softc *sc) 2241 { 2242 struct ieee80211com *ic = &sc->sc_ic; 2243 uint32_t tmp; 2244 2245 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2246 tmp &= ~RT2860_CCK_SHORT_EN; 2247 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2248 tmp |= RT2860_CCK_SHORT_EN; 2249 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2250 } 2251 2252 void 2253 rt2860_set_basicrates(struct rt2860_softc *sc, 2254 const struct ieee80211_rateset *rs) 2255 { 2256 struct ieee80211com *ic = &sc->sc_ic; 2257 uint32_t mask = 0; 2258 uint8_t rate; 2259 int i; 2260 2261 for (i = 0; i < rs->rs_nrates; i++) { 2262 rate = rs->rs_rates[i]; 2263 2264 if (!(rate & IEEE80211_RATE_BASIC)) 2265 continue; 2266 2267 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2268 IEEE80211_RV(rate)); 2269 } 2270 2271 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2272 } 2273 2274 static void 2275 rt2860_scan_start(struct ieee80211com *ic) 2276 { 2277 struct rt2860_softc *sc = ic->ic_softc; 2278 uint32_t tmp; 2279 2280 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2281 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2282 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2283 RT2860_TBTT_TIMER_EN)); 2284 rt2860_set_gp_timer(sc, 0); 2285 } 2286 2287 static void 2288 rt2860_scan_end(struct ieee80211com *ic) 2289 { 2290 struct rt2860_softc *sc = ic->ic_softc; 2291 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2292 2293 if (vap->iv_state == IEEE80211_S_RUN) { 2294 rt2860_enable_tsf_sync(sc); 2295 rt2860_set_gp_timer(sc, 500); 2296 } 2297 } 2298 2299 static void 2300 rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, 2301 struct ieee80211_channel chans[]) 2302 { 2303 struct rt2860_softc *sc = ic->ic_softc; 2304 uint8_t bands[IEEE80211_MODE_BYTES]; 2305 2306 memset(bands, 0, sizeof(bands)); 2307 setbit(bands, IEEE80211_MODE_11B); 2308 setbit(bands, IEEE80211_MODE_11G); 2309 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2310 2311 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 2312 setbit(bands, IEEE80211_MODE_11A); 2313 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2314 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0); 2315 } 2316 } 2317 2318 static void 2319 rt2860_set_channel(struct ieee80211com *ic) 2320 { 2321 struct rt2860_softc *sc = ic->ic_softc; 2322 2323 RAL_LOCK(sc); 2324 rt2860_switch_chan(sc, ic->ic_curchan); 2325 RAL_UNLOCK(sc); 2326 } 2327 2328 static void 2329 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2330 { 2331 uint32_t tmp; 2332 uint8_t agc; 2333 2334 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2335 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2336 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2337 rt2860_mcu_bbp_write(sc, 86, 0x00); 2338 2339 if (group == 0) { 2340 if (sc->ext_2ghz_lna) { 2341 rt2860_mcu_bbp_write(sc, 82, 0x62); 2342 rt2860_mcu_bbp_write(sc, 75, 0x46); 2343 } else { 2344 rt2860_mcu_bbp_write(sc, 82, 0x84); 2345 rt2860_mcu_bbp_write(sc, 75, 0x50); 2346 } 2347 } else { 2348 if (sc->ext_5ghz_lna) { 2349 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2350 rt2860_mcu_bbp_write(sc, 75, 0x46); 2351 } else { 2352 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2353 rt2860_mcu_bbp_write(sc, 75, 0x50); 2354 } 2355 } 2356 2357 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2358 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2359 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2360 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2361 2362 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2363 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2364 if (sc->nrxchains > 1) 2365 tmp |= RT2860_LNA_PE1_EN; 2366 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2367 tmp |= RT3593_LNA_PE2_EN; 2368 if (group == 0) { /* 2GHz */ 2369 tmp |= RT2860_PA_PE_G0_EN; 2370 if (sc->ntxchains > 1) 2371 tmp |= RT2860_PA_PE_G1_EN; 2372 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2373 tmp |= RT3593_PA_PE_G2_EN; 2374 } else { /* 5GHz */ 2375 tmp |= RT2860_PA_PE_A0_EN; 2376 if (sc->ntxchains > 1) 2377 tmp |= RT2860_PA_PE_A1_EN; 2378 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2379 tmp |= RT3593_PA_PE_A2_EN; 2380 } 2381 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2382 2383 if (sc->mac_ver == 0x3593) { 2384 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2385 if (sc->sc_flags & RT2860_PCIE) { 2386 tmp &= ~0x01010000; 2387 if (group == 0) 2388 tmp |= 0x00010000; 2389 } else { 2390 tmp &= ~0x00008080; 2391 if (group == 0) 2392 tmp |= 0x00000080; 2393 } 2394 tmp = (tmp & ~0x00001000) | 0x00000010; 2395 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2396 } 2397 2398 /* set initial AGC value */ 2399 if (group == 0) { /* 2GHz band */ 2400 if (sc->mac_ver >= 0x3071) 2401 agc = 0x1c + sc->lna[0] * 2; 2402 else 2403 agc = 0x2e + sc->lna[0]; 2404 } else { /* 5GHz band */ 2405 agc = 0x32 + (sc->lna[group] * 5) / 3; 2406 } 2407 rt2860_mcu_bbp_write(sc, 66, agc); 2408 2409 DELAY(1000); 2410 } 2411 2412 static void 2413 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2414 { 2415 const struct rfprog *rfprog = rt2860_rf2850; 2416 uint32_t r2, r3, r4; 2417 int8_t txpow1, txpow2; 2418 u_int i; 2419 2420 /* find the settings for this channel (we know it exists) */ 2421 for (i = 0; rfprog[i].chan != chan; i++); 2422 2423 r2 = rfprog[i].r2; 2424 if (sc->ntxchains == 1) 2425 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2426 if (sc->nrxchains == 1) 2427 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2428 else if (sc->nrxchains == 2) 2429 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2430 2431 /* use Tx power values from EEPROM */ 2432 txpow1 = sc->txpow1[i]; 2433 txpow2 = sc->txpow2[i]; 2434 if (chan > 14) { 2435 if (txpow1 >= 0) 2436 txpow1 = txpow1 << 1 | 1; 2437 else 2438 txpow1 = (7 + txpow1) << 1; 2439 if (txpow2 >= 0) 2440 txpow2 = txpow2 << 1 | 1; 2441 else 2442 txpow2 = (7 + txpow2) << 1; 2443 } 2444 r3 = rfprog[i].r3 | txpow1 << 7; 2445 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2446 2447 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2448 rt2860_rf_write(sc, RT2860_RF2, r2); 2449 rt2860_rf_write(sc, RT2860_RF3, r3); 2450 rt2860_rf_write(sc, RT2860_RF4, r4); 2451 2452 DELAY(200); 2453 2454 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2455 rt2860_rf_write(sc, RT2860_RF2, r2); 2456 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2457 rt2860_rf_write(sc, RT2860_RF4, r4); 2458 2459 DELAY(200); 2460 2461 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2462 rt2860_rf_write(sc, RT2860_RF2, r2); 2463 rt2860_rf_write(sc, RT2860_RF3, r3); 2464 rt2860_rf_write(sc, RT2860_RF4, r4); 2465 } 2466 2467 static void 2468 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2469 { 2470 int8_t txpow1, txpow2; 2471 uint8_t rf; 2472 int i; 2473 2474 /* RT3090 is 2GHz only */ 2475 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2476 2477 /* find the settings for this channel (we know it exists) */ 2478 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2479 2480 /* use Tx power values from EEPROM */ 2481 txpow1 = sc->txpow1[i]; 2482 txpow2 = sc->txpow2[i]; 2483 2484 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2485 rf = rt3090_rf_read(sc, 3); 2486 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2487 rt3090_rf_write(sc, 3, rf); 2488 rf = rt3090_rf_read(sc, 6); 2489 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2490 rt3090_rf_write(sc, 6, rf); 2491 2492 /* set Tx0 power */ 2493 rf = rt3090_rf_read(sc, 12); 2494 rf = (rf & ~0x1f) | txpow1; 2495 rt3090_rf_write(sc, 12, rf); 2496 2497 /* set Tx1 power */ 2498 rf = rt3090_rf_read(sc, 13); 2499 rf = (rf & ~0x1f) | txpow2; 2500 rt3090_rf_write(sc, 13, rf); 2501 2502 rf = rt3090_rf_read(sc, 1); 2503 rf &= ~0xfc; 2504 if (sc->ntxchains == 1) 2505 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2506 else if (sc->ntxchains == 2) 2507 rf |= RT3070_TX2_PD; 2508 if (sc->nrxchains == 1) 2509 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2510 else if (sc->nrxchains == 2) 2511 rf |= RT3070_RX2_PD; 2512 rt3090_rf_write(sc, 1, rf); 2513 2514 /* set RF offset */ 2515 rf = rt3090_rf_read(sc, 23); 2516 rf = (rf & ~0x7f) | sc->freq; 2517 rt3090_rf_write(sc, 23, rf); 2518 2519 /* program RF filter */ 2520 rf = rt3090_rf_read(sc, 24); /* Tx */ 2521 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2522 rt3090_rf_write(sc, 24, rf); 2523 rf = rt3090_rf_read(sc, 31); /* Rx */ 2524 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2525 rt3090_rf_write(sc, 31, rf); 2526 2527 /* enable RF tuning */ 2528 rf = rt3090_rf_read(sc, 7); 2529 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2530 } 2531 2532 static void 2533 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2534 { 2535 uint8_t h20mhz, rf, tmp; 2536 int8_t txpow1, txpow2; 2537 int i; 2538 2539 /* RT5390 is 2GHz only */ 2540 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2541 2542 /* find the settings for this channel (we know it exists) */ 2543 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2544 2545 /* use Tx power values from EEPROM */ 2546 txpow1 = sc->txpow1[i]; 2547 txpow2 = sc->txpow2[i]; 2548 2549 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2550 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2551 rf = rt3090_rf_read(sc, 11); 2552 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2553 rt3090_rf_write(sc, 11, rf); 2554 2555 rf = rt3090_rf_read(sc, 49); 2556 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2557 /* the valid range of the RF R49 is 0x00~0x27 */ 2558 if ((rf & 0x3f) > 0x27) 2559 rf = (rf & ~0x3f) | 0x27; 2560 rt3090_rf_write(sc, 49, rf); 2561 if (sc->mac_ver == 0x5392) { 2562 rf = rt3090_rf_read(sc, 50); 2563 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2564 /* the valid range of the RF R50 is 0x00~0x27 */ 2565 if ((rf & 0x3f) > 0x27) 2566 rf = (rf & ~0x3f) | 0x27; 2567 rt3090_rf_write(sc, 50, rf); 2568 } 2569 2570 rf = rt3090_rf_read(sc, 1); 2571 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2572 if (sc->mac_ver == 0x5392) 2573 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2574 rt3090_rf_write(sc, 1, rf); 2575 2576 rf = rt3090_rf_read(sc, 2); 2577 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2578 DELAY(1000); 2579 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2580 2581 rf = rt3090_rf_read(sc, 17); 2582 tmp = rf; 2583 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2584 rf = MIN(rf, 0x5f); 2585 if (tmp != rf) 2586 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2587 2588 if (sc->mac_ver == 0x5390) { 2589 if (chan <= 4) 2590 rf = 0x73; 2591 else if (chan >= 5 && chan <= 6) 2592 rf = 0x63; 2593 else if (chan >= 7 && chan <= 10) 2594 rf = 0x53; 2595 else 2596 rf = 43; 2597 rt3090_rf_write(sc, 55, rf); 2598 2599 if (chan == 1) 2600 rf = 0x0c; 2601 else if (chan == 2) 2602 rf = 0x0b; 2603 else if (chan == 3) 2604 rf = 0x0a; 2605 else if (chan >= 4 && chan <= 6) 2606 rf = 0x09; 2607 else if (chan >= 7 && chan <= 12) 2608 rf = 0x08; 2609 else if (chan == 13) 2610 rf = 0x07; 2611 else 2612 rf = 0x06; 2613 rt3090_rf_write(sc, 59, rf); 2614 } 2615 2616 /* Tx/Rx h20M */ 2617 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2618 rf = rt3090_rf_read(sc, 30); 2619 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2620 rt3090_rf_write(sc, 30, rf); 2621 2622 /* Rx BB filter VCM */ 2623 rf = rt3090_rf_read(sc, 30); 2624 rf = (rf & ~0x18) | 0x10; 2625 rt3090_rf_write(sc, 30, rf); 2626 2627 /* Initiate VCO calibration. */ 2628 rf = rt3090_rf_read(sc, 3); 2629 rf |= RT3593_VCOCAL; 2630 rt3090_rf_write(sc, 3, rf); 2631 } 2632 2633 static int 2634 rt3090_rf_init(struct rt2860_softc *sc) 2635 { 2636 uint32_t tmp; 2637 uint8_t rf, bbp; 2638 int i; 2639 2640 rf = rt3090_rf_read(sc, 30); 2641 /* toggle RF R30 bit 7 */ 2642 rt3090_rf_write(sc, 30, rf | 0x80); 2643 DELAY(1000); 2644 rt3090_rf_write(sc, 30, rf & ~0x80); 2645 2646 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2647 tmp &= ~0x1f000000; 2648 if (sc->patch_dac && sc->mac_rev < 0x0211) 2649 tmp |= 0x0d000000; /* 1.35V */ 2650 else 2651 tmp |= 0x01000000; /* 1.2V */ 2652 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2653 2654 /* patch LNA_PE_G1 */ 2655 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2656 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2657 2658 /* initialize RF registers to default value */ 2659 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2660 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2661 rt3090_def_rf[i].val); 2662 } 2663 2664 /* select 20MHz bandwidth */ 2665 rt3090_rf_write(sc, 31, 0x14); 2666 2667 rf = rt3090_rf_read(sc, 6); 2668 rt3090_rf_write(sc, 6, rf | 0x40); 2669 2670 if (sc->mac_ver != 0x3593) { 2671 /* calibrate filter for 20MHz bandwidth */ 2672 sc->rf24_20mhz = 0x1f; /* default value */ 2673 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2674 2675 /* select 40MHz bandwidth */ 2676 bbp = rt2860_mcu_bbp_read(sc, 4); 2677 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2678 rf = rt3090_rf_read(sc, 31); 2679 rt3090_rf_write(sc, 31, rf | 0x20); 2680 2681 /* calibrate filter for 40MHz bandwidth */ 2682 sc->rf24_40mhz = 0x2f; /* default value */ 2683 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2684 2685 /* go back to 20MHz bandwidth */ 2686 bbp = rt2860_mcu_bbp_read(sc, 4); 2687 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2688 } 2689 if (sc->mac_rev < 0x0211) 2690 rt3090_rf_write(sc, 27, 0x03); 2691 2692 tmp = RAL_READ(sc, RT3070_OPT_14); 2693 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2694 2695 if (sc->rf_rev == RT3070_RF_3020) 2696 rt3090_set_rx_antenna(sc, 0); 2697 2698 bbp = rt2860_mcu_bbp_read(sc, 138); 2699 if (sc->mac_ver == 0x3593) { 2700 if (sc->ntxchains == 1) 2701 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2702 else if (sc->ntxchains == 2) 2703 bbp |= 0x40; /* turn off DAC2 */ 2704 if (sc->nrxchains == 1) 2705 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2706 else if (sc->nrxchains == 2) 2707 bbp &= ~0x04; /* turn off ADC2 */ 2708 } else { 2709 if (sc->ntxchains == 1) 2710 bbp |= 0x20; /* turn off DAC1 */ 2711 if (sc->nrxchains == 1) 2712 bbp &= ~0x02; /* turn off ADC1 */ 2713 } 2714 rt2860_mcu_bbp_write(sc, 138, bbp); 2715 2716 rf = rt3090_rf_read(sc, 1); 2717 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2718 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2719 rt3090_rf_write(sc, 1, rf); 2720 2721 rf = rt3090_rf_read(sc, 15); 2722 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2723 2724 rf = rt3090_rf_read(sc, 17); 2725 rf &= ~RT3070_TX_LO1; 2726 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2727 rf |= 0x20; /* fix for long range Rx issue */ 2728 if (sc->txmixgain_2ghz >= 2) 2729 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2730 rt3090_rf_write(sc, 17, rf); 2731 2732 rf = rt3090_rf_read(sc, 20); 2733 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2734 2735 rf = rt3090_rf_read(sc, 21); 2736 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2737 2738 return (0); 2739 } 2740 2741 static void 2742 rt5390_rf_init(struct rt2860_softc *sc) 2743 { 2744 uint8_t rf, bbp; 2745 int i; 2746 2747 rf = rt3090_rf_read(sc, 2); 2748 /* Toggle RF R2 bit 7. */ 2749 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2750 DELAY(1000); 2751 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2752 2753 /* Initialize RF registers to default value. */ 2754 if (sc->mac_ver == 0x5392) { 2755 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2756 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2757 rt5392_def_rf[i].val); 2758 } 2759 } else { 2760 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2761 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2762 rt5390_def_rf[i].val); 2763 } 2764 } 2765 2766 sc->rf24_20mhz = 0x1f; 2767 sc->rf24_40mhz = 0x2f; 2768 2769 if (sc->mac_rev < 0x0211) 2770 rt3090_rf_write(sc, 27, 0x03); 2771 2772 /* Set led open drain enable. */ 2773 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2774 2775 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2776 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2777 2778 if (sc->mac_ver == 0x5390) 2779 rt3090_set_rx_antenna(sc, 0); 2780 2781 /* Patch RSSI inaccurate issue. */ 2782 rt2860_mcu_bbp_write(sc, 79, 0x13); 2783 rt2860_mcu_bbp_write(sc, 80, 0x05); 2784 rt2860_mcu_bbp_write(sc, 81, 0x33); 2785 2786 /* Enable DC filter. */ 2787 if (sc->mac_rev >= 0x0211) 2788 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2789 2790 bbp = rt2860_mcu_bbp_read(sc, 138); 2791 if (sc->ntxchains == 1) 2792 bbp |= 0x20; /* Turn off DAC1. */ 2793 if (sc->nrxchains == 1) 2794 bbp &= ~0x02; /* Turn off ADC1. */ 2795 rt2860_mcu_bbp_write(sc, 138, bbp); 2796 2797 /* Enable RX LO1 and LO2. */ 2798 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2799 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2800 2801 /* Avoid data lost and CRC error. */ 2802 rt2860_mcu_bbp_write(sc, 4, 2803 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2804 2805 rf = rt3090_rf_read(sc, 30); 2806 rf = (rf & ~0x18) | 0x10; 2807 rt3090_rf_write(sc, 30, rf); 2808 } 2809 2810 static void 2811 rt3090_rf_wakeup(struct rt2860_softc *sc) 2812 { 2813 uint32_t tmp; 2814 uint8_t rf; 2815 2816 if (sc->mac_ver == 0x3593) { 2817 /* enable VCO */ 2818 rf = rt3090_rf_read(sc, 1); 2819 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2820 2821 /* initiate VCO calibration */ 2822 rf = rt3090_rf_read(sc, 3); 2823 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2824 2825 /* enable VCO bias current control */ 2826 rf = rt3090_rf_read(sc, 6); 2827 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2828 2829 /* initiate res calibration */ 2830 rf = rt3090_rf_read(sc, 2); 2831 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2832 2833 /* set reference current control to 0.33 mA */ 2834 rf = rt3090_rf_read(sc, 22); 2835 rf &= ~RT3593_CP_IC_MASK; 2836 rf |= 1 << RT3593_CP_IC_SHIFT; 2837 rt3090_rf_write(sc, 22, rf); 2838 2839 /* enable RX CTB */ 2840 rf = rt3090_rf_read(sc, 46); 2841 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2842 2843 rf = rt3090_rf_read(sc, 20); 2844 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2845 rt3090_rf_write(sc, 20, rf); 2846 } else { 2847 /* enable RF block */ 2848 rf = rt3090_rf_read(sc, 1); 2849 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2850 2851 /* enable VCO bias current control */ 2852 rf = rt3090_rf_read(sc, 7); 2853 rt3090_rf_write(sc, 7, rf | 0x30); 2854 2855 rf = rt3090_rf_read(sc, 9); 2856 rt3090_rf_write(sc, 9, rf | 0x0e); 2857 2858 /* enable RX CTB */ 2859 rf = rt3090_rf_read(sc, 21); 2860 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2861 2862 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2863 rf = rt3090_rf_read(sc, 27); 2864 rf &= ~0x77; 2865 if (sc->mac_rev < 0x0211) 2866 rf |= 0x03; 2867 rt3090_rf_write(sc, 27, rf); 2868 } 2869 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2870 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2871 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2872 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2873 } 2874 } 2875 2876 static void 2877 rt5390_rf_wakeup(struct rt2860_softc *sc) 2878 { 2879 uint32_t tmp; 2880 uint8_t rf; 2881 2882 rf = rt3090_rf_read(sc, 1); 2883 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2884 RT3070_TX0_PD; 2885 if (sc->mac_ver == 0x5392) 2886 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2887 rt3090_rf_write(sc, 1, rf); 2888 2889 rf = rt3090_rf_read(sc, 6); 2890 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2891 if (sc->mac_ver == 0x5390) 2892 rf &= ~RT3593_VCO_IC; 2893 rt3090_rf_write(sc, 6, rf); 2894 2895 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2896 2897 rf = rt3090_rf_read(sc, 22); 2898 rf = (rf & ~0xe0) | 0x20; 2899 rt3090_rf_write(sc, 22, rf); 2900 2901 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2902 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2903 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2904 2905 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2906 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2907 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2908 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2909 } 2910 } 2911 2912 static int 2913 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2914 uint8_t *val) 2915 { 2916 uint8_t rf22, rf24; 2917 uint8_t bbp55_pb, bbp55_sb, delta; 2918 int ntries; 2919 2920 /* program filter */ 2921 rf24 = rt3090_rf_read(sc, 24); 2922 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2923 rt3090_rf_write(sc, 24, rf24); 2924 2925 /* enable baseband loopback mode */ 2926 rf22 = rt3090_rf_read(sc, 22); 2927 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2928 2929 /* set power and frequency of passband test tone */ 2930 rt2860_mcu_bbp_write(sc, 24, 0x00); 2931 for (ntries = 0; ntries < 100; ntries++) { 2932 /* transmit test tone */ 2933 rt2860_mcu_bbp_write(sc, 25, 0x90); 2934 DELAY(1000); 2935 /* read received power */ 2936 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2937 if (bbp55_pb != 0) 2938 break; 2939 } 2940 if (ntries == 100) 2941 return (ETIMEDOUT); 2942 2943 /* set power and frequency of stopband test tone */ 2944 rt2860_mcu_bbp_write(sc, 24, 0x06); 2945 for (ntries = 0; ntries < 100; ntries++) { 2946 /* transmit test tone */ 2947 rt2860_mcu_bbp_write(sc, 25, 0x90); 2948 DELAY(1000); 2949 /* read received power */ 2950 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2951 2952 delta = bbp55_pb - bbp55_sb; 2953 if (delta > target) 2954 break; 2955 2956 /* reprogram filter */ 2957 rf24++; 2958 rt3090_rf_write(sc, 24, rf24); 2959 } 2960 if (ntries < 100) { 2961 if (rf24 != init) 2962 rf24--; /* backtrack */ 2963 *val = rf24; 2964 rt3090_rf_write(sc, 24, rf24); 2965 } 2966 2967 /* restore initial state */ 2968 rt2860_mcu_bbp_write(sc, 24, 0x00); 2969 2970 /* disable baseband loopback mode */ 2971 rf22 = rt3090_rf_read(sc, 22); 2972 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2973 2974 return (0); 2975 } 2976 2977 static void 2978 rt3090_rf_setup(struct rt2860_softc *sc) 2979 { 2980 uint8_t bbp; 2981 int i; 2982 2983 if (sc->mac_rev >= 0x0211) { 2984 /* enable DC filter */ 2985 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2986 2987 /* improve power consumption */ 2988 bbp = rt2860_mcu_bbp_read(sc, 31); 2989 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2990 } 2991 2992 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2993 if (sc->mac_rev < 0x0211) { 2994 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2995 sc->patch_dac ? 0x2c : 0x0f); 2996 } else 2997 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2998 2999 /* initialize RF registers from ROM */ 3000 if (sc->mac_ver < 0x5390) { 3001 for (i = 0; i < 10; i++) { 3002 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 3003 continue; 3004 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3005 } 3006 } 3007 } 3008 3009 static void 3010 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3011 { 3012 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3013 which | (sc->leds & 0x7f), 0); 3014 } 3015 3016 /* 3017 * Hardware has a general-purpose programmable timer interrupt that can 3018 * periodically raise MAC_INT_4. 3019 */ 3020 static void 3021 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3022 { 3023 uint32_t tmp; 3024 3025 /* disable GP timer before reprogramming it */ 3026 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3027 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3028 3029 if (ms == 0) 3030 return; 3031 3032 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3033 ms *= 16; /* Unit: 64us */ 3034 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3035 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3036 3037 /* enable GP timer */ 3038 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3039 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3040 } 3041 3042 static void 3043 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3044 { 3045 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3046 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3047 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3048 bssid[4] | bssid[5] << 8); 3049 } 3050 3051 static void 3052 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3053 { 3054 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3055 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3056 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3057 addr[4] | addr[5] << 8 | 0xff << 16); 3058 } 3059 3060 static void 3061 rt2860_updateslot(struct ieee80211com *ic) 3062 { 3063 struct rt2860_softc *sc = ic->ic_softc; 3064 uint32_t tmp; 3065 3066 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3067 tmp &= ~0xff; 3068 tmp |= IEEE80211_GET_SLOTTIME(ic); 3069 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3070 } 3071 3072 static void 3073 rt2860_updateprot(struct rt2860_softc *sc) 3074 { 3075 struct ieee80211com *ic = &sc->sc_ic; 3076 uint32_t tmp; 3077 3078 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3079 /* setup protection frame rate (MCS code) */ 3080 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3081 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3082 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3083 3084 /* CCK frames don't require protection */ 3085 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3086 3087 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3088 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3089 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3090 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3091 tmp |= RT2860_PROT_CTRL_CTS; 3092 } 3093 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3094 } 3095 3096 static void 3097 rt2860_update_promisc(struct ieee80211com *ic) 3098 { 3099 struct rt2860_softc *sc = ic->ic_softc; 3100 uint32_t tmp; 3101 3102 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3103 tmp &= ~RT2860_DROP_NOT_MYBSS; 3104 if (ic->ic_promisc == 0) 3105 tmp |= RT2860_DROP_NOT_MYBSS; 3106 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3107 } 3108 3109 static int 3110 rt2860_updateedca(struct ieee80211com *ic) 3111 { 3112 struct rt2860_softc *sc = ic->ic_softc; 3113 struct chanAccParams chp; 3114 const struct wmeParams *wmep; 3115 int aci; 3116 3117 ieee80211_wme_ic_getparams(ic, &chp); 3118 3119 wmep = chp.cap_wmeParams; 3120 3121 /* update MAC TX configuration registers */ 3122 for (aci = 0; aci < WME_NUM_AC; aci++) { 3123 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3124 wmep[aci].wmep_logcwmax << 16 | 3125 wmep[aci].wmep_logcwmin << 12 | 3126 wmep[aci].wmep_aifsn << 8 | 3127 wmep[aci].wmep_txopLimit); 3128 } 3129 3130 /* update SCH/DMA registers too */ 3131 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3132 wmep[WME_AC_VO].wmep_aifsn << 12 | 3133 wmep[WME_AC_VI].wmep_aifsn << 8 | 3134 wmep[WME_AC_BK].wmep_aifsn << 4 | 3135 wmep[WME_AC_BE].wmep_aifsn); 3136 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3137 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3138 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3139 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3140 wmep[WME_AC_BE].wmep_logcwmin); 3141 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3142 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3143 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3144 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3145 wmep[WME_AC_BE].wmep_logcwmax); 3146 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3147 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3148 wmep[WME_AC_BE].wmep_txopLimit); 3149 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3150 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3151 wmep[WME_AC_VI].wmep_txopLimit); 3152 3153 return 0; 3154 } 3155 3156 #ifdef HW_CRYPTO 3157 static int 3158 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3159 struct ieee80211_key *k) 3160 { 3161 struct rt2860_softc *sc = ic->ic_softc; 3162 bus_size_t base; 3163 uint32_t attr; 3164 uint8_t mode, wcid, iv[8]; 3165 3166 /* defer setting of WEP keys until interface is brought up */ 3167 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3168 (IFF_UP | IFF_RUNNING)) 3169 return 0; 3170 3171 /* map net80211 cipher to RT2860 security mode */ 3172 switch (k->k_cipher) { 3173 case IEEE80211_CIPHER_WEP40: 3174 mode = RT2860_MODE_WEP40; 3175 break; 3176 case IEEE80211_CIPHER_WEP104: 3177 mode = RT2860_MODE_WEP104; 3178 break; 3179 case IEEE80211_CIPHER_TKIP: 3180 mode = RT2860_MODE_TKIP; 3181 break; 3182 case IEEE80211_CIPHER_CCMP: 3183 mode = RT2860_MODE_AES_CCMP; 3184 break; 3185 default: 3186 return EINVAL; 3187 } 3188 3189 if (k->k_flags & IEEE80211_KEY_GROUP) { 3190 wcid = 0; /* NB: update WCID0 for group keys */ 3191 base = RT2860_SKEY(0, k->k_id); 3192 } else { 3193 wcid = ((struct rt2860_node *)ni)->wcid; 3194 base = RT2860_PKEY(wcid); 3195 } 3196 3197 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3198 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3199 #ifndef IEEE80211_STA_ONLY 3200 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3201 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3202 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3203 } else 3204 #endif 3205 { 3206 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3207 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3208 } 3209 } else 3210 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3211 3212 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3213 (k->k_flags & IEEE80211_KEY_TX)) { 3214 /* set initial packet number in IV+EIV */ 3215 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3216 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3217 uint32_t val = arc4random(); 3218 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3219 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3220 val += 0x000100; 3221 iv[0] = val; 3222 iv[1] = val >> 8; 3223 iv[2] = val >> 16; 3224 iv[3] = k->k_id << 6; 3225 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3226 } else { 3227 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3228 iv[0] = k->k_tsc >> 8; 3229 iv[1] = (iv[0] | 0x20) & 0x7f; 3230 iv[2] = k->k_tsc; 3231 } else /* CCMP */ { 3232 iv[0] = k->k_tsc; 3233 iv[1] = k->k_tsc >> 8; 3234 iv[2] = 0; 3235 } 3236 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3237 iv[4] = k->k_tsc >> 16; 3238 iv[5] = k->k_tsc >> 24; 3239 iv[6] = k->k_tsc >> 32; 3240 iv[7] = k->k_tsc >> 40; 3241 } 3242 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3243 } 3244 3245 if (k->k_flags & IEEE80211_KEY_GROUP) { 3246 /* install group key */ 3247 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3248 attr &= ~(0xf << (k->k_id * 4)); 3249 attr |= mode << (k->k_id * 4); 3250 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3251 } else { 3252 /* install pairwise key */ 3253 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3254 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3255 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3256 } 3257 return 0; 3258 } 3259 3260 static void 3261 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3262 struct ieee80211_key *k) 3263 { 3264 struct rt2860_softc *sc = ic->ic_softc; 3265 uint32_t attr; 3266 uint8_t wcid; 3267 3268 if (k->k_flags & IEEE80211_KEY_GROUP) { 3269 /* remove group key */ 3270 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3271 attr &= ~(0xf << (k->k_id * 4)); 3272 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3273 3274 } else { 3275 /* remove pairwise key */ 3276 wcid = ((struct rt2860_node *)ni)->wcid; 3277 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3278 attr &= ~0xf; 3279 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3280 } 3281 } 3282 #endif 3283 3284 static int8_t 3285 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3286 { 3287 struct ieee80211com *ic = &sc->sc_ic; 3288 struct ieee80211_channel *c = ic->ic_curchan; 3289 int delta; 3290 3291 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3292 u_int chan = ieee80211_chan2ieee(ic, c); 3293 delta = sc->rssi_5ghz[rxchain]; 3294 3295 /* determine channel group */ 3296 if (chan <= 64) 3297 delta -= sc->lna[1]; 3298 else if (chan <= 128) 3299 delta -= sc->lna[2]; 3300 else 3301 delta -= sc->lna[3]; 3302 } else 3303 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3304 3305 return -12 - delta - rssi; 3306 } 3307 3308 /* 3309 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3310 * Used to adjust per-rate Tx power registers. 3311 */ 3312 static __inline uint32_t 3313 b4inc(uint32_t b32, int8_t delta) 3314 { 3315 int8_t i, b4; 3316 3317 for (i = 0; i < 8; i++) { 3318 b4 = b32 & 0xf; 3319 b4 += delta; 3320 if (b4 < 0) 3321 b4 = 0; 3322 else if (b4 > 0xf) 3323 b4 = 0xf; 3324 b32 = b32 >> 4 | (uint32_t)b4 << 28; 3325 } 3326 return b32; 3327 } 3328 3329 static const char * 3330 rt2860_get_rf(uint16_t rev) 3331 { 3332 switch (rev) { 3333 case RT2860_RF_2820: return "RT2820"; 3334 case RT2860_RF_2850: return "RT2850"; 3335 case RT2860_RF_2720: return "RT2720"; 3336 case RT2860_RF_2750: return "RT2750"; 3337 case RT3070_RF_3020: return "RT3020"; 3338 case RT3070_RF_2020: return "RT2020"; 3339 case RT3070_RF_3021: return "RT3021"; 3340 case RT3070_RF_3022: return "RT3022"; 3341 case RT3070_RF_3052: return "RT3052"; 3342 case RT3070_RF_3320: return "RT3320"; 3343 case RT3070_RF_3053: return "RT3053"; 3344 case RT5390_RF_5360: return "RT5360"; 3345 case RT5390_RF_5390: return "RT5390"; 3346 default: return "unknown"; 3347 } 3348 } 3349 3350 static int 3351 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3352 { 3353 int8_t delta_2ghz, delta_5ghz; 3354 uint32_t tmp; 3355 uint16_t val; 3356 int ridx, ant, i; 3357 3358 /* check whether the ROM is eFUSE ROM or EEPROM */ 3359 sc->sc_srom_read = rt2860_eeprom_read_2; 3360 if (sc->mac_ver >= 0x3071) { 3361 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3362 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3363 if (tmp & RT3070_SEL_EFUSE) 3364 sc->sc_srom_read = rt3090_efuse_read_2; 3365 } 3366 3367 #ifdef RAL_DEBUG 3368 /* read EEPROM version */ 3369 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3370 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3371 #endif 3372 3373 /* read MAC address */ 3374 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3375 macaddr[0] = val & 0xff; 3376 macaddr[1] = val >> 8; 3377 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3378 macaddr[2] = val & 0xff; 3379 macaddr[3] = val >> 8; 3380 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3381 macaddr[4] = val & 0xff; 3382 macaddr[5] = val >> 8; 3383 3384 #ifdef RAL_DEBUG 3385 /* read country code */ 3386 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3387 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3388 #endif 3389 3390 /* read vendor BBP settings */ 3391 for (i = 0; i < 8; i++) { 3392 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3393 sc->bbp[i].val = val & 0xff; 3394 sc->bbp[i].reg = val >> 8; 3395 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3396 } 3397 if (sc->mac_ver >= 0x3071) { 3398 /* read vendor RF settings */ 3399 for (i = 0; i < 10; i++) { 3400 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3401 sc->rf[i].val = val & 0xff; 3402 sc->rf[i].reg = val >> 8; 3403 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3404 sc->rf[i].val)); 3405 } 3406 } 3407 3408 /* read RF frequency offset from EEPROM */ 3409 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3410 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3411 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3412 if ((val >> 8) != 0xff) { 3413 /* read LEDs operating mode */ 3414 sc->leds = val >> 8; 3415 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3416 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3417 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3418 } else { 3419 /* broken EEPROM, use default settings */ 3420 sc->leds = 0x01; 3421 sc->led[0] = 0x5555; 3422 sc->led[1] = 0x2221; 3423 sc->led[2] = 0xa9f8; 3424 } 3425 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3426 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3427 3428 /* read RF information */ 3429 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3430 if (sc->mac_ver >= 0x5390) 3431 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3432 else 3433 sc->rf_rev = (val >> 8) & 0xf; 3434 sc->ntxchains = (val >> 4) & 0xf; 3435 sc->nrxchains = val & 0xf; 3436 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3437 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3438 3439 /* check if RF supports automatic Tx access gain control */ 3440 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3441 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3442 /* check if driver should patch the DAC issue */ 3443 if ((val >> 8) != 0xff) 3444 sc->patch_dac = (val >> 15) & 1; 3445 if ((val & 0xff) != 0xff) { 3446 sc->ext_5ghz_lna = (val >> 3) & 1; 3447 sc->ext_2ghz_lna = (val >> 2) & 1; 3448 /* check if RF supports automatic Tx access gain control */ 3449 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3450 /* check if we have a hardware radio switch */ 3451 sc->rfswitch = val & 1; 3452 } 3453 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3454 /* read PCIe power save level */ 3455 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3456 if ((val & 0xff) != 0xff) { 3457 sc->pslevel = val & 0x3; 3458 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3459 if ((val & 0xff80) != 0x9280) 3460 sc->pslevel = MIN(sc->pslevel, 1); 3461 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3462 } 3463 } 3464 3465 /* read power settings for 2GHz channels */ 3466 for (i = 0; i < 14; i += 2) { 3467 val = rt2860_srom_read(sc, 3468 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3469 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3470 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3471 3472 if (sc->mac_ver != 0x5390) { 3473 val = rt2860_srom_read(sc, 3474 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3475 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3476 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3477 } 3478 } 3479 /* fix broken Tx power entries */ 3480 for (i = 0; i < 14; i++) { 3481 if (sc->txpow1[i] < 0 || 3482 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3483 sc->txpow1[i] = 5; 3484 if (sc->mac_ver != 0x5390) { 3485 if (sc->txpow2[i] < 0 || 3486 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3487 sc->txpow2[i] = 5; 3488 } 3489 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3490 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3491 } 3492 /* read power settings for 5GHz channels */ 3493 for (i = 0; i < 40; i += 2) { 3494 val = rt2860_srom_read(sc, 3495 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3496 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3497 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3498 3499 val = rt2860_srom_read(sc, 3500 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3501 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3502 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3503 } 3504 /* fix broken Tx power entries */ 3505 for (i = 0; i < 40; i++) { 3506 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3507 sc->txpow1[14 + i] = 5; 3508 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3509 sc->txpow2[14 + i] = 5; 3510 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3511 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3512 sc->txpow2[14 + i])); 3513 } 3514 3515 /* read Tx power compensation for each Tx rate */ 3516 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3517 delta_2ghz = delta_5ghz = 0; 3518 if ((val & 0xff) != 0xff && (val & 0x80)) { 3519 delta_2ghz = val & 0xf; 3520 if (!(val & 0x40)) /* negative number */ 3521 delta_2ghz = -delta_2ghz; 3522 } 3523 val >>= 8; 3524 if ((val & 0xff) != 0xff && (val & 0x80)) { 3525 delta_5ghz = val & 0xf; 3526 if (!(val & 0x40)) /* negative number */ 3527 delta_5ghz = -delta_5ghz; 3528 } 3529 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3530 delta_2ghz, delta_5ghz)); 3531 3532 for (ridx = 0; ridx < 5; ridx++) { 3533 uint32_t reg; 3534 3535 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3536 reg = val; 3537 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3538 reg |= (uint32_t)val << 16; 3539 3540 sc->txpow20mhz[ridx] = reg; 3541 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3542 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3543 3544 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3545 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3546 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3547 } 3548 3549 /* read factory-calibrated samples for temperature compensation */ 3550 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3551 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3552 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3553 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3554 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3555 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3556 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3557 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3558 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3559 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3560 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3561 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3562 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3563 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3564 sc->step_2ghz = val >> 8; 3565 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3566 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3567 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3568 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3569 sc->tssi_2ghz[8], sc->step_2ghz)); 3570 /* check that ref value is correct, otherwise disable calibration */ 3571 if (sc->tssi_2ghz[4] == 0xff) 3572 sc->calib_2ghz = 0; 3573 3574 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3575 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3576 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3577 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3578 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3579 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3580 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3581 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3582 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3583 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3584 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3585 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3586 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3587 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3588 sc->step_5ghz = val >> 8; 3589 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3590 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3591 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3592 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3593 sc->tssi_5ghz[8], sc->step_5ghz)); 3594 /* check that ref value is correct, otherwise disable calibration */ 3595 if (sc->tssi_5ghz[4] == 0xff) 3596 sc->calib_5ghz = 0; 3597 3598 /* read RSSI offsets and LNA gains from EEPROM */ 3599 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3600 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3601 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3602 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3603 if (sc->mac_ver >= 0x3071) { 3604 /* 3605 * On RT3090 chips (limited to 2 Rx chains), this ROM 3606 * field contains the Tx mixer gain for the 2GHz band. 3607 */ 3608 if ((val & 0xff) != 0xff) 3609 sc->txmixgain_2ghz = val & 0x7; 3610 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3611 } else 3612 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3613 sc->lna[2] = val >> 8; /* channel group 2 */ 3614 3615 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3616 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3617 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3618 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3619 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3620 sc->lna[3] = val >> 8; /* channel group 3 */ 3621 3622 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3623 if (sc->mac_ver >= 0x3071) 3624 sc->lna[0] = RT3090_DEF_LNA; 3625 else /* channel group 0 */ 3626 sc->lna[0] = val & 0xff; 3627 sc->lna[1] = val >> 8; /* channel group 1 */ 3628 3629 /* fix broken 5GHz LNA entries */ 3630 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3631 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3632 sc->lna[2] = sc->lna[1]; 3633 } 3634 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3635 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3636 sc->lna[3] = sc->lna[1]; 3637 } 3638 3639 /* fix broken RSSI offset entries */ 3640 for (ant = 0; ant < 3; ant++) { 3641 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3642 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3643 ant + 1, sc->rssi_2ghz[ant])); 3644 sc->rssi_2ghz[ant] = 0; 3645 } 3646 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3647 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3648 ant + 1, sc->rssi_5ghz[ant])); 3649 sc->rssi_5ghz[ant] = 0; 3650 } 3651 } 3652 3653 return 0; 3654 } 3655 3656 static int 3657 rt2860_bbp_init(struct rt2860_softc *sc) 3658 { 3659 int i, ntries; 3660 3661 /* wait for BBP to wake up */ 3662 for (ntries = 0; ntries < 20; ntries++) { 3663 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3664 if (bbp0 != 0 && bbp0 != 0xff) 3665 break; 3666 } 3667 if (ntries == 20) { 3668 device_printf(sc->sc_dev, 3669 "timeout waiting for BBP to wake up\n"); 3670 return (ETIMEDOUT); 3671 } 3672 3673 /* initialize BBP registers to default values */ 3674 if (sc->mac_ver >= 0x5390) 3675 rt5390_bbp_init(sc); 3676 else { 3677 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3678 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3679 rt2860_def_bbp[i].val); 3680 } 3681 } 3682 3683 /* fix BBP84 for RT2860E */ 3684 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3685 rt2860_mcu_bbp_write(sc, 84, 0x19); 3686 3687 if (sc->mac_ver >= 0x3071) { 3688 rt2860_mcu_bbp_write(sc, 79, 0x13); 3689 rt2860_mcu_bbp_write(sc, 80, 0x05); 3690 rt2860_mcu_bbp_write(sc, 81, 0x33); 3691 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3692 rt2860_mcu_bbp_write(sc, 69, 0x16); 3693 rt2860_mcu_bbp_write(sc, 73, 0x12); 3694 } 3695 3696 return 0; 3697 } 3698 3699 static void 3700 rt5390_bbp_init(struct rt2860_softc *sc) 3701 { 3702 uint8_t bbp; 3703 int i; 3704 3705 /* Apply maximum likelihood detection for 2 stream case. */ 3706 if (sc->nrxchains > 1) { 3707 bbp = rt2860_mcu_bbp_read(sc, 105); 3708 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3709 } 3710 3711 /* Avoid data lost and CRC error. */ 3712 bbp = rt2860_mcu_bbp_read(sc, 4); 3713 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3714 3715 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3716 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3717 rt5390_def_bbp[i].val); 3718 } 3719 3720 if (sc->mac_ver == 0x5392) { 3721 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3722 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3723 rt2860_mcu_bbp_write(sc, 98, 0x12); 3724 rt2860_mcu_bbp_write(sc, 106, 0x05); 3725 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3726 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3727 } 3728 3729 bbp = rt2860_mcu_bbp_read(sc, 152); 3730 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3731 3732 /* Disable hardware antenna diversity. */ 3733 if (sc->mac_ver == 0x5390) 3734 rt2860_mcu_bbp_write(sc, 154, 0); 3735 } 3736 3737 static int 3738 rt2860_txrx_enable(struct rt2860_softc *sc) 3739 { 3740 struct ieee80211com *ic = &sc->sc_ic; 3741 uint32_t tmp; 3742 int ntries; 3743 3744 /* enable Tx/Rx DMA engine */ 3745 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3746 RAL_BARRIER_READ_WRITE(sc); 3747 for (ntries = 0; ntries < 200; ntries++) { 3748 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3749 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3750 break; 3751 DELAY(1000); 3752 } 3753 if (ntries == 200) { 3754 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3755 return ETIMEDOUT; 3756 } 3757 3758 DELAY(50); 3759 3760 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3761 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3762 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3763 3764 /* set Rx filter */ 3765 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3766 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3767 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3768 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3769 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3770 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3771 if (ic->ic_opmode == IEEE80211_M_STA) 3772 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3773 } 3774 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3775 3776 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3777 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3778 3779 return 0; 3780 } 3781 3782 static void 3783 rt2860_init(void *arg) 3784 { 3785 struct rt2860_softc *sc = arg; 3786 struct ieee80211com *ic = &sc->sc_ic; 3787 3788 RAL_LOCK(sc); 3789 rt2860_init_locked(sc); 3790 RAL_UNLOCK(sc); 3791 3792 if (sc->sc_flags & RT2860_RUNNING) 3793 ieee80211_start_all(ic); 3794 } 3795 3796 static void 3797 rt2860_init_locked(struct rt2860_softc *sc) 3798 { 3799 struct ieee80211com *ic = &sc->sc_ic; 3800 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3801 uint32_t tmp; 3802 uint8_t bbp1, bbp3; 3803 int i, qid, ridx, ntries, error; 3804 3805 RAL_LOCK_ASSERT(sc); 3806 3807 if (sc->rfswitch) { 3808 /* hardware has a radio switch on GPIO pin 2 */ 3809 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3810 device_printf(sc->sc_dev, 3811 "radio is disabled by hardware switch\n"); 3812 #ifdef notyet 3813 rt2860_stop_locked(sc); 3814 return; 3815 #endif 3816 } 3817 } 3818 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3819 3820 /* disable DMA */ 3821 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3822 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3823 RT2860_TX_DMA_EN); 3824 tmp |= RT2860_TX_WB_DDONE; 3825 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3826 3827 /* reset DMA indexes */ 3828 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3829 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3830 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3831 3832 /* PBF hardware reset */ 3833 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3834 RAL_BARRIER_WRITE(sc); 3835 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3836 3837 if ((error = rt2860_load_microcode(sc)) != 0) { 3838 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3839 rt2860_stop_locked(sc); 3840 return; 3841 } 3842 3843 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3844 3845 /* init Tx power for all Tx rates (from EEPROM) */ 3846 for (ridx = 0; ridx < 5; ridx++) { 3847 if (sc->txpow20mhz[ridx] == 0xffffffff) 3848 continue; 3849 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3850 } 3851 3852 for (ntries = 0; ntries < 100; ntries++) { 3853 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3854 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3855 break; 3856 DELAY(1000); 3857 } 3858 if (ntries == 100) { 3859 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3860 rt2860_stop_locked(sc); 3861 return; 3862 } 3863 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3864 RT2860_TX_DMA_EN); 3865 tmp |= RT2860_TX_WB_DDONE; 3866 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3867 3868 /* reset Rx ring and all 6 Tx rings */ 3869 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3870 3871 /* PBF hardware reset */ 3872 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3873 RAL_BARRIER_WRITE(sc); 3874 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3875 3876 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3877 3878 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3879 RAL_BARRIER_WRITE(sc); 3880 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3881 3882 for (i = 0; i < nitems(rt2860_def_mac); i++) 3883 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3884 if (sc->mac_ver >= 0x5390) 3885 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3886 else if (sc->mac_ver >= 0x3071) { 3887 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3888 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3889 4 << RT2860_DLY_PAPE_EN_SHIFT); 3890 } 3891 3892 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3893 sc->sc_flags |= RT2860_PCIE; 3894 /* PCIe has different clock cycle count than PCI */ 3895 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3896 tmp = (tmp & ~0xff) | 0x7d; 3897 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3898 } 3899 3900 /* wait while MAC is busy */ 3901 for (ntries = 0; ntries < 100; ntries++) { 3902 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3903 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3904 break; 3905 DELAY(1000); 3906 } 3907 if (ntries == 100) { 3908 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3909 rt2860_stop_locked(sc); 3910 return; 3911 } 3912 3913 /* clear Host to MCU mailbox */ 3914 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3915 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3916 3917 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3918 DELAY(1000); 3919 3920 if ((error = rt2860_bbp_init(sc)) != 0) { 3921 rt2860_stop_locked(sc); 3922 return; 3923 } 3924 3925 /* clear RX WCID search table */ 3926 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3927 /* clear pairwise key table */ 3928 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3929 /* clear IV/EIV table */ 3930 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3931 /* clear WCID attribute table */ 3932 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3933 /* clear shared key table */ 3934 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3935 /* clear shared key mode */ 3936 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3937 3938 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3939 for (qid = 0; qid < 6; qid++) { 3940 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3941 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3942 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3943 } 3944 3945 /* init Rx ring */ 3946 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3947 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3948 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3949 3950 /* setup maximum buffer sizes */ 3951 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3952 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3953 3954 for (ntries = 0; ntries < 100; ntries++) { 3955 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3956 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3957 break; 3958 DELAY(1000); 3959 } 3960 if (ntries == 100) { 3961 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3962 rt2860_stop_locked(sc); 3963 return; 3964 } 3965 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3966 RT2860_TX_DMA_EN); 3967 tmp |= RT2860_TX_WB_DDONE; 3968 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3969 3970 /* disable interrupts mitigation */ 3971 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3972 3973 /* write vendor-specific BBP values (from EEPROM) */ 3974 for (i = 0; i < 8; i++) { 3975 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3976 continue; 3977 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3978 } 3979 3980 /* select Main antenna for 1T1R devices */ 3981 if (sc->rf_rev == RT3070_RF_2020 || 3982 sc->rf_rev == RT3070_RF_3020 || 3983 sc->rf_rev == RT3070_RF_3320 || 3984 sc->mac_ver == 0x5390) 3985 rt3090_set_rx_antenna(sc, 0); 3986 3987 /* send LEDs operating mode to microcontroller */ 3988 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3989 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3990 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3991 3992 if (sc->mac_ver >= 0x5390) 3993 rt5390_rf_init(sc); 3994 else if (sc->mac_ver >= 0x3071) { 3995 if ((error = rt3090_rf_init(sc)) != 0) { 3996 rt2860_stop_locked(sc); 3997 return; 3998 } 3999 } 4000 4001 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 4002 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 4003 4004 if (sc->mac_ver >= 0x5390) 4005 rt5390_rf_wakeup(sc); 4006 else if (sc->mac_ver >= 0x3071) 4007 rt3090_rf_wakeup(sc); 4008 4009 /* disable non-existing Rx chains */ 4010 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4011 bbp3 &= ~(1 << 3 | 1 << 4); 4012 if (sc->nrxchains == 2) 4013 bbp3 |= 1 << 3; 4014 else if (sc->nrxchains == 3) 4015 bbp3 |= 1 << 4; 4016 rt2860_mcu_bbp_write(sc, 3, bbp3); 4017 4018 /* disable non-existing Tx chains */ 4019 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4020 if (sc->ntxchains == 1) 4021 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4022 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4023 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4024 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4025 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4026 rt2860_mcu_bbp_write(sc, 1, bbp1); 4027 4028 if (sc->mac_ver >= 0x3071) 4029 rt3090_rf_setup(sc); 4030 4031 /* select default channel */ 4032 rt2860_switch_chan(sc, ic->ic_curchan); 4033 4034 /* reset RF from MCU */ 4035 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4036 4037 /* set RTS threshold */ 4038 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4039 tmp &= ~0xffff00; 4040 tmp |= IEEE80211_RTS_DEFAULT << 8; 4041 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4042 4043 /* setup initial protection mode */ 4044 rt2860_updateprot(sc); 4045 4046 /* turn radio LED on */ 4047 rt2860_set_leds(sc, RT2860_LED_RADIO); 4048 4049 /* enable Tx/Rx DMA engine */ 4050 if ((error = rt2860_txrx_enable(sc)) != 0) { 4051 rt2860_stop_locked(sc); 4052 return; 4053 } 4054 4055 /* clear pending interrupts */ 4056 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4057 /* enable interrupts */ 4058 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4059 4060 if (sc->sc_flags & RT2860_ADVANCED_PS) 4061 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4062 4063 sc->sc_flags |= RT2860_RUNNING; 4064 4065 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4066 } 4067 4068 static void 4069 rt2860_stop(void *arg) 4070 { 4071 struct rt2860_softc *sc = arg; 4072 4073 RAL_LOCK(sc); 4074 rt2860_stop_locked(sc); 4075 RAL_UNLOCK(sc); 4076 } 4077 4078 static void 4079 rt2860_stop_locked(struct rt2860_softc *sc) 4080 { 4081 uint32_t tmp; 4082 int qid; 4083 4084 if (sc->sc_flags & RT2860_RUNNING) 4085 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4086 4087 callout_stop(&sc->watchdog_ch); 4088 sc->sc_tx_timer = 0; 4089 sc->sc_flags &= ~RT2860_RUNNING; 4090 4091 /* disable interrupts */ 4092 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4093 4094 /* disable GP timer */ 4095 rt2860_set_gp_timer(sc, 0); 4096 4097 /* disable Rx */ 4098 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4099 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4100 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4101 4102 /* reset adapter */ 4103 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4104 RAL_BARRIER_WRITE(sc); 4105 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4106 4107 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4108 sc->qfullmsk = 0; 4109 for (qid = 0; qid < 6; qid++) 4110 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4111 rt2860_reset_rx_ring(sc, &sc->rxq); 4112 } 4113 4114 int 4115 rt2860_load_microcode(struct rt2860_softc *sc) 4116 { 4117 const struct firmware *fp; 4118 int ntries, error; 4119 4120 RAL_LOCK_ASSERT(sc); 4121 4122 RAL_UNLOCK(sc); 4123 fp = firmware_get("rt2860fw"); 4124 RAL_LOCK(sc); 4125 if (fp == NULL) { 4126 device_printf(sc->sc_dev, 4127 "unable to receive rt2860fw firmware image\n"); 4128 return EINVAL; 4129 } 4130 4131 /* set "host program ram write selection" bit */ 4132 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4133 /* write microcode image */ 4134 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4135 /* kick microcontroller unit */ 4136 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4137 RAL_BARRIER_WRITE(sc); 4138 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4139 4140 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4141 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4142 4143 /* wait until microcontroller is ready */ 4144 RAL_BARRIER_READ_WRITE(sc); 4145 for (ntries = 0; ntries < 1000; ntries++) { 4146 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4147 break; 4148 DELAY(1000); 4149 } 4150 if (ntries == 1000) { 4151 device_printf(sc->sc_dev, 4152 "timeout waiting for MCU to initialize\n"); 4153 error = ETIMEDOUT; 4154 } else 4155 error = 0; 4156 4157 firmware_put(fp, FIRMWARE_UNLOAD); 4158 return error; 4159 } 4160 4161 /* 4162 * This function is called periodically to adjust Tx power based on 4163 * temperature variation. 4164 */ 4165 #ifdef NOT_YET 4166 static void 4167 rt2860_calib(struct rt2860_softc *sc) 4168 { 4169 struct ieee80211com *ic = &sc->sc_ic; 4170 const uint8_t *tssi; 4171 uint8_t step, bbp49; 4172 int8_t ridx, d; 4173 4174 /* read current temperature */ 4175 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4176 4177 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4178 tssi = &sc->tssi_2ghz[4]; 4179 step = sc->step_2ghz; 4180 } else { 4181 tssi = &sc->tssi_5ghz[4]; 4182 step = sc->step_5ghz; 4183 } 4184 4185 if (bbp49 < tssi[0]) { /* lower than reference */ 4186 /* use higher Tx power than default */ 4187 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4188 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4189 /* use lower Tx power than default */ 4190 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4191 } else { 4192 /* use default Tx power */ 4193 d = 0; 4194 } 4195 d *= step; 4196 4197 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4198 4199 /* write adjusted Tx power values for each Tx rate */ 4200 for (ridx = 0; ridx < 5; ridx++) { 4201 if (sc->txpow20mhz[ridx] == 0xffffffff) 4202 continue; 4203 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4204 b4inc(sc->txpow20mhz[ridx], d)); 4205 } 4206 } 4207 #endif 4208 4209 static void 4210 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4211 { 4212 uint32_t tmp; 4213 4214 if (aux) { 4215 if (sc->mac_ver == 0x5390) { 4216 rt2860_mcu_bbp_write(sc, 152, 4217 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4218 } else { 4219 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4220 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4221 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4222 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4223 } 4224 } else { 4225 if (sc->mac_ver == 0x5390) { 4226 rt2860_mcu_bbp_write(sc, 152, 4227 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4228 } else { 4229 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4230 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4231 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4232 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4233 } 4234 } 4235 } 4236 4237 static void 4238 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4239 { 4240 struct ieee80211com *ic = &sc->sc_ic; 4241 u_int chan, group; 4242 4243 chan = ieee80211_chan2ieee(ic, c); 4244 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4245 return; 4246 4247 if (sc->mac_ver >= 0x5390) 4248 rt5390_set_chan(sc, chan); 4249 else if (sc->mac_ver >= 0x3071) 4250 rt3090_set_chan(sc, chan); 4251 else 4252 rt2860_set_chan(sc, chan); 4253 4254 /* determine channel group */ 4255 if (chan <= 14) 4256 group = 0; 4257 else if (chan <= 64) 4258 group = 1; 4259 else if (chan <= 128) 4260 group = 2; 4261 else 4262 group = 3; 4263 4264 /* XXX necessary only when group has changed! */ 4265 if (sc->mac_ver < 0x5390) 4266 rt2860_select_chan_group(sc, group); 4267 4268 DELAY(1000); 4269 } 4270 4271 static int 4272 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4273 { 4274 struct ieee80211com *ic = vap->iv_ic; 4275 struct rt2860_txwi txwi; 4276 struct mbuf *m; 4277 int ridx; 4278 4279 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4280 return ENOBUFS; 4281 4282 memset(&txwi, 0, sizeof txwi); 4283 txwi.wcid = 0xff; 4284 txwi.len = htole16(m->m_pkthdr.len); 4285 /* send beacons at the lowest available rate */ 4286 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4287 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4288 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4289 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4290 txwi.phy |= htole16(RT2860_PHY_OFDM); 4291 txwi.txop = RT2860_TX_TXOP_HT; 4292 txwi.flags = RT2860_TX_TS; 4293 txwi.xflags = RT2860_TX_NSEQ; 4294 4295 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4296 (uint8_t *)&txwi, sizeof txwi); 4297 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4298 mtod(m, uint8_t *), m->m_pkthdr.len); 4299 4300 m_freem(m); 4301 4302 return 0; 4303 } 4304 4305 static void 4306 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4307 { 4308 struct ieee80211com *ic = &sc->sc_ic; 4309 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4310 uint32_t tmp; 4311 4312 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4313 4314 tmp &= ~0x1fffff; 4315 tmp |= vap->iv_bss->ni_intval * 16; 4316 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4317 if (vap->iv_opmode == IEEE80211_M_STA) { 4318 /* 4319 * Local TSF is always updated with remote TSF on beacon 4320 * reception. 4321 */ 4322 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4323 } 4324 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4325 vap->iv_opmode == IEEE80211_M_MBSS) { 4326 tmp |= RT2860_BCN_TX_EN; 4327 /* 4328 * Local TSF is updated with remote TSF on beacon reception 4329 * only if the remote TSF is greater than local TSF. 4330 */ 4331 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4332 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4333 tmp |= RT2860_BCN_TX_EN; 4334 /* SYNC with nobody */ 4335 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4336 } 4337 4338 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4339 } 4340