1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 /*- 22 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 23 * http://www.ralinktech.com/ 24 */ 25 26 #include <sys/param.h> 27 #include <sys/sysctl.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/firmware.h> 40 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_radiotap.h> 56 #include <net80211/ieee80211_regdomain.h> 57 #include <net80211/ieee80211_ratectl.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_ether.h> 64 65 #include <dev/ral/rt2860reg.h> 66 #include <dev/ral/rt2860var.h> 67 68 #define RAL_DEBUG 69 #ifdef RAL_DEBUG 70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n, x) 75 #endif 76 77 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 78 const char [IFNAMSIZ], int, enum ieee80211_opmode, 79 int, const uint8_t [IEEE80211_ADDR_LEN], 80 const uint8_t [IEEE80211_ADDR_LEN]); 81 static void rt2860_vap_delete(struct ieee80211vap *); 82 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 83 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 84 struct rt2860_tx_ring *); 85 static void rt2860_reset_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_free_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 90 static void rt2860_free_tx_pool(struct rt2860_softc *); 91 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 92 struct rt2860_rx_ring *); 93 static void rt2860_reset_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_free_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_updatestats(struct rt2860_softc *); 98 static void rt2860_newassoc(struct ieee80211_node *, int); 99 static void rt2860_node_free(struct ieee80211_node *); 100 #ifdef IEEE80211_HT 101 static int rt2860_ampdu_rx_start(struct ieee80211com *, 102 struct ieee80211_node *, uint8_t); 103 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 #endif 106 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 107 int); 108 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 109 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 110 static void rt2860_intr_coherent(struct rt2860_softc *); 111 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 112 static void rt2860_tx_intr(struct rt2860_softc *, int); 113 static void rt2860_rx_intr(struct rt2860_softc *); 114 static void rt2860_tbtt_intr(struct rt2860_softc *); 115 static void rt2860_gp_intr(struct rt2860_softc *); 116 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 117 struct ieee80211_node *); 118 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 119 const struct ieee80211_bpf_params *); 120 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 121 struct ieee80211_node *, 122 const struct ieee80211_bpf_params *params); 123 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 124 static void rt2860_start(struct rt2860_softc *); 125 static void rt2860_watchdog(void *); 126 static void rt2860_parent(struct ieee80211com *); 127 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 128 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 129 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 130 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 131 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 132 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 133 static void rt2860_enable_mrr(struct rt2860_softc *); 134 static void rt2860_set_txpreamble(struct rt2860_softc *); 135 static void rt2860_set_basicrates(struct rt2860_softc *, 136 const struct ieee80211_rateset *); 137 static void rt2860_scan_start(struct ieee80211com *); 138 static void rt2860_scan_end(struct ieee80211com *); 139 static void rt2860_getradiocaps(struct ieee80211com *, int, int *, 140 struct ieee80211_channel[]); 141 static void rt2860_set_channel(struct ieee80211com *); 142 static void rt2860_select_chan_group(struct rt2860_softc *, int); 143 static void rt2860_set_chan(struct rt2860_softc *, u_int); 144 static void rt3090_set_chan(struct rt2860_softc *, u_int); 145 static void rt5390_set_chan(struct rt2860_softc *, u_int); 146 static int rt3090_rf_init(struct rt2860_softc *); 147 static void rt5390_rf_init(struct rt2860_softc *); 148 static void rt3090_rf_wakeup(struct rt2860_softc *); 149 static void rt5390_rf_wakeup(struct rt2860_softc *); 150 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 151 uint8_t *); 152 static void rt3090_rf_setup(struct rt2860_softc *); 153 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 154 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 155 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 156 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 157 static void rt2860_update_promisc(struct ieee80211com *); 158 static void rt2860_updateslot(struct ieee80211com *); 159 static void rt2860_updateprot(struct rt2860_softc *); 160 static int rt2860_updateedca(struct ieee80211com *); 161 #ifdef HW_CRYPTO 162 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 163 struct ieee80211_key *); 164 static void rt2860_delete_key(struct ieee80211com *, 165 struct ieee80211_node *, struct ieee80211_key *); 166 #endif 167 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 168 static const char *rt2860_get_rf(uint16_t); 169 static int rt2860_read_eeprom(struct rt2860_softc *, 170 uint8_t macaddr[IEEE80211_ADDR_LEN]); 171 static int rt2860_bbp_init(struct rt2860_softc *); 172 static void rt5390_bbp_init(struct rt2860_softc *); 173 static int rt2860_txrx_enable(struct rt2860_softc *); 174 static void rt2860_init(void *); 175 static void rt2860_init_locked(struct rt2860_softc *); 176 static void rt2860_stop(void *); 177 static void rt2860_stop_locked(struct rt2860_softc *); 178 static int rt2860_load_microcode(struct rt2860_softc *); 179 #ifdef NOT_YET 180 static void rt2860_calib(struct rt2860_softc *); 181 #endif 182 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 183 static void rt2860_switch_chan(struct rt2860_softc *, 184 struct ieee80211_channel *); 185 static int rt2860_setup_beacon(struct rt2860_softc *, 186 struct ieee80211vap *); 187 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 188 189 static const struct { 190 uint32_t reg; 191 uint32_t val; 192 } rt2860_def_mac[] = { 193 RT2860_DEF_MAC 194 }; 195 196 static const struct { 197 uint8_t reg; 198 uint8_t val; 199 } rt2860_def_bbp[] = { 200 RT2860_DEF_BBP 201 }, rt5390_def_bbp[] = { 202 RT5390_DEF_BBP 203 }; 204 205 static const struct rfprog { 206 uint8_t chan; 207 uint32_t r1, r2, r3, r4; 208 } rt2860_rf2850[] = { 209 RT2860_RF2850 210 }; 211 212 struct { 213 uint8_t n, r, k; 214 } rt3090_freqs[] = { 215 RT3070_RF3052 216 }; 217 218 static const struct { 219 uint8_t reg; 220 uint8_t val; 221 } rt3090_def_rf[] = { 222 RT3070_DEF_RF 223 }, rt5390_def_rf[] = { 224 RT5390_DEF_RF 225 }, rt5392_def_rf[] = { 226 RT5392_DEF_RF 227 }; 228 229 static const uint8_t rt2860_chan_5ghz[] = 230 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 231 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 232 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 }; 233 234 int 235 rt2860_attach(device_t dev, int id) 236 { 237 struct rt2860_softc *sc = device_get_softc(dev); 238 struct ieee80211com *ic = &sc->sc_ic; 239 uint32_t tmp; 240 int error, ntries, qid; 241 242 sc->sc_dev = dev; 243 sc->sc_debug = 0; 244 245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 246 MTX_DEF | MTX_RECURSE); 247 248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 249 mbufq_init(&sc->sc_snd, ifqmaxlen); 250 251 /* wait for NIC to initialize */ 252 for (ntries = 0; ntries < 100; ntries++) { 253 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 254 if (tmp != 0 && tmp != 0xffffffff) 255 break; 256 DELAY(10); 257 } 258 if (ntries == 100) { 259 device_printf(sc->sc_dev, 260 "timeout waiting for NIC to initialize\n"); 261 error = EIO; 262 goto fail1; 263 } 264 sc->mac_ver = tmp >> 16; 265 sc->mac_rev = tmp & 0xffff; 266 267 if (sc->mac_ver != 0x2860 && 268 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 269 sc->sc_flags |= RT2860_ADVANCED_PS; 270 271 /* retrieve RF rev. no and various other things from EEPROM */ 272 rt2860_read_eeprom(sc, ic->ic_macaddr); 273 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 274 "RF %s (MIMO %dT%dR), address %6D\n", 275 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 276 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 277 278 /* 279 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 280 */ 281 for (qid = 0; qid < 6; qid++) { 282 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 283 device_printf(sc->sc_dev, 284 "could not allocate Tx ring %d\n", qid); 285 goto fail2; 286 } 287 } 288 289 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 290 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 291 goto fail2; 292 } 293 294 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 295 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 296 goto fail3; 297 } 298 299 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 300 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 301 WME_AC_VO : 5; 302 303 ic->ic_softc = sc; 304 ic->ic_name = device_get_nameunit(dev); 305 ic->ic_opmode = IEEE80211_M_STA; 306 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 307 308 /* set device capabilities */ 309 ic->ic_caps = 310 IEEE80211_C_STA /* station mode */ 311 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 312 | IEEE80211_C_HOSTAP /* hostap mode */ 313 | IEEE80211_C_MONITOR /* monitor mode */ 314 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 315 | IEEE80211_C_WDS /* 4-address traffic works */ 316 | IEEE80211_C_MBSS /* mesh point link mode */ 317 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 318 | IEEE80211_C_SHSLOT /* short slot time supported */ 319 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 320 #if 0 321 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 322 #endif 323 | IEEE80211_C_WME /* 802.11e */ 324 ; 325 326 ic->ic_flags_ext |= IEEE80211_FEXT_SEQNO_OFFLOAD; 327 328 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 329 ic->ic_channels); 330 331 ieee80211_ifattach(ic); 332 333 ic->ic_wme.wme_update = rt2860_updateedca; 334 ic->ic_scan_start = rt2860_scan_start; 335 ic->ic_scan_end = rt2860_scan_end; 336 ic->ic_getradiocaps = rt2860_getradiocaps; 337 ic->ic_set_channel = rt2860_set_channel; 338 ic->ic_updateslot = rt2860_updateslot; 339 ic->ic_update_promisc = rt2860_update_promisc; 340 ic->ic_raw_xmit = rt2860_raw_xmit; 341 sc->sc_node_free = ic->ic_node_free; 342 ic->ic_node_free = rt2860_node_free; 343 ic->ic_newassoc = rt2860_newassoc; 344 ic->ic_transmit = rt2860_transmit; 345 ic->ic_parent = rt2860_parent; 346 ic->ic_vap_create = rt2860_vap_create; 347 ic->ic_vap_delete = rt2860_vap_delete; 348 349 ieee80211_radiotap_attach(ic, 350 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 351 RT2860_TX_RADIOTAP_PRESENT, 352 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 353 RT2860_RX_RADIOTAP_PRESENT); 354 355 #ifdef RAL_DEBUG 356 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 357 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 358 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 359 #endif 360 if (bootverbose) 361 ieee80211_announce(ic); 362 363 return 0; 364 365 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 366 fail2: while (--qid >= 0) 367 rt2860_free_tx_ring(sc, &sc->txq[qid]); 368 fail1: mtx_destroy(&sc->sc_mtx); 369 return error; 370 } 371 372 int 373 rt2860_detach(void *xsc) 374 { 375 struct rt2860_softc *sc = xsc; 376 struct ieee80211com *ic = &sc->sc_ic; 377 int qid; 378 379 RAL_LOCK(sc); 380 rt2860_stop_locked(sc); 381 RAL_UNLOCK(sc); 382 383 ieee80211_ifdetach(ic); 384 mbufq_drain(&sc->sc_snd); 385 for (qid = 0; qid < 6; qid++) 386 rt2860_free_tx_ring(sc, &sc->txq[qid]); 387 rt2860_free_rx_ring(sc, &sc->rxq); 388 rt2860_free_tx_pool(sc); 389 390 mtx_destroy(&sc->sc_mtx); 391 392 return 0; 393 } 394 395 void 396 rt2860_shutdown(void *xsc) 397 { 398 struct rt2860_softc *sc = xsc; 399 400 rt2860_stop(sc); 401 } 402 403 void 404 rt2860_suspend(void *xsc) 405 { 406 struct rt2860_softc *sc = xsc; 407 408 rt2860_stop(sc); 409 } 410 411 void 412 rt2860_resume(void *xsc) 413 { 414 struct rt2860_softc *sc = xsc; 415 416 if (sc->sc_ic.ic_nrunning > 0) 417 rt2860_init(sc); 418 } 419 420 static struct ieee80211vap * 421 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 422 enum ieee80211_opmode opmode, int flags, 423 const uint8_t bssid[IEEE80211_ADDR_LEN], 424 const uint8_t mac[IEEE80211_ADDR_LEN]) 425 { 426 struct rt2860_softc *sc = ic->ic_softc; 427 struct rt2860_vap *rvp; 428 struct ieee80211vap *vap; 429 430 switch (opmode) { 431 case IEEE80211_M_STA: 432 case IEEE80211_M_IBSS: 433 case IEEE80211_M_AHDEMO: 434 case IEEE80211_M_MONITOR: 435 case IEEE80211_M_HOSTAP: 436 case IEEE80211_M_MBSS: 437 /* XXXRP: TBD */ 438 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 439 device_printf(sc->sc_dev, "only 1 vap supported\n"); 440 return NULL; 441 } 442 if (opmode == IEEE80211_M_STA) 443 flags |= IEEE80211_CLONE_NOBEACONS; 444 break; 445 case IEEE80211_M_WDS: 446 if (TAILQ_EMPTY(&ic->ic_vaps) || 447 ic->ic_opmode != IEEE80211_M_HOSTAP) { 448 device_printf(sc->sc_dev, 449 "wds only supported in ap mode\n"); 450 return NULL; 451 } 452 /* 453 * Silently remove any request for a unique 454 * bssid; WDS vap's always share the local 455 * mac address. 456 */ 457 flags &= ~IEEE80211_CLONE_BSSID; 458 break; 459 default: 460 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 461 return NULL; 462 } 463 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 464 vap = &rvp->ral_vap; 465 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 466 467 /* override state transition machine */ 468 rvp->ral_newstate = vap->iv_newstate; 469 vap->iv_newstate = rt2860_newstate; 470 #if 0 471 vap->iv_update_beacon = rt2860_beacon_update; 472 #endif 473 474 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 475 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 476 477 ieee80211_ratectl_init(vap); 478 /* complete setup */ 479 ieee80211_vap_attach(vap, ieee80211_media_change, 480 ieee80211_media_status, mac); 481 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 482 ic->ic_opmode = opmode; 483 return vap; 484 } 485 486 static void 487 rt2860_vap_delete(struct ieee80211vap *vap) 488 { 489 struct rt2860_vap *rvp = RT2860_VAP(vap); 490 491 ieee80211_ratectl_deinit(vap); 492 ieee80211_vap_detach(vap); 493 free(rvp, M_80211_VAP); 494 } 495 496 static void 497 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 498 { 499 if (error != 0) 500 return; 501 502 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 503 504 *(bus_addr_t *)arg = segs[0].ds_addr; 505 } 506 507 static int 508 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 509 { 510 int size, error; 511 512 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 513 514 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 515 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 516 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 517 if (error != 0) { 518 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 519 goto fail; 520 } 521 522 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 523 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 524 if (error != 0) { 525 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 526 goto fail; 527 } 528 529 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 530 size, rt2860_dma_map_addr, &ring->paddr, 0); 531 if (error != 0) { 532 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 533 goto fail; 534 } 535 536 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 537 538 return 0; 539 540 fail: rt2860_free_tx_ring(sc, ring); 541 return error; 542 } 543 544 void 545 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 546 { 547 struct rt2860_tx_data *data; 548 int i; 549 550 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 551 if ((data = ring->data[i]) == NULL) 552 continue; /* nothing mapped in this slot */ 553 554 if (data->m != NULL) { 555 bus_dmamap_sync(sc->txwi_dmat, data->map, 556 BUS_DMASYNC_POSTWRITE); 557 bus_dmamap_unload(sc->txwi_dmat, data->map); 558 m_freem(data->m); 559 data->m = NULL; 560 } 561 if (data->ni != NULL) { 562 ieee80211_free_node(data->ni); 563 data->ni = NULL; 564 } 565 566 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 567 ring->data[i] = NULL; 568 } 569 570 ring->queued = 0; 571 ring->cur = ring->next = 0; 572 } 573 574 void 575 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 576 { 577 struct rt2860_tx_data *data; 578 int i; 579 580 if (ring->txd != NULL) { 581 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 582 BUS_DMASYNC_POSTWRITE); 583 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 584 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 585 } 586 if (ring->desc_dmat != NULL) 587 bus_dma_tag_destroy(ring->desc_dmat); 588 589 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 590 if ((data = ring->data[i]) == NULL) 591 continue; /* nothing mapped in this slot */ 592 593 if (data->m != NULL) { 594 bus_dmamap_sync(sc->txwi_dmat, data->map, 595 BUS_DMASYNC_POSTWRITE); 596 bus_dmamap_unload(sc->txwi_dmat, data->map); 597 m_freem(data->m); 598 } 599 if (data->ni != NULL) 600 ieee80211_free_node(data->ni); 601 602 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 603 } 604 } 605 606 /* 607 * Allocate a pool of TX Wireless Information blocks. 608 */ 609 int 610 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 611 { 612 caddr_t vaddr; 613 bus_addr_t paddr; 614 int i, size, error; 615 616 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 617 618 /* init data_pool early in case of failure.. */ 619 SLIST_INIT(&sc->data_pool); 620 621 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 622 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 623 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 624 if (error != 0) { 625 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 626 goto fail; 627 } 628 629 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 630 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 631 if (error != 0) { 632 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 633 goto fail; 634 } 635 636 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 637 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 638 if (error != 0) { 639 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 640 goto fail; 641 } 642 643 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 644 645 vaddr = sc->txwi_vaddr; 646 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 647 struct rt2860_tx_data *data = &sc->data[i]; 648 649 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 650 if (error != 0) { 651 device_printf(sc->sc_dev, "could not create DMA map\n"); 652 goto fail; 653 } 654 data->txwi = (struct rt2860_txwi *)vaddr; 655 data->paddr = paddr; 656 vaddr += RT2860_TXWI_DMASZ; 657 paddr += RT2860_TXWI_DMASZ; 658 659 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 660 } 661 662 return 0; 663 664 fail: rt2860_free_tx_pool(sc); 665 return error; 666 } 667 668 void 669 rt2860_free_tx_pool(struct rt2860_softc *sc) 670 { 671 if (sc->txwi_vaddr != NULL) { 672 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 673 BUS_DMASYNC_POSTWRITE); 674 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 675 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 676 } 677 if (sc->txwi_dmat != NULL) 678 bus_dma_tag_destroy(sc->txwi_dmat); 679 680 while (!SLIST_EMPTY(&sc->data_pool)) { 681 struct rt2860_tx_data *data; 682 data = SLIST_FIRST(&sc->data_pool); 683 bus_dmamap_destroy(sc->txwi_dmat, data->map); 684 SLIST_REMOVE_HEAD(&sc->data_pool, next); 685 } 686 } 687 688 int 689 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 690 { 691 bus_addr_t physaddr; 692 int i, size, error; 693 694 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 695 696 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 697 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 698 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 699 if (error != 0) { 700 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 701 goto fail; 702 } 703 704 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 705 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 706 if (error != 0) { 707 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 708 goto fail; 709 } 710 711 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 712 size, rt2860_dma_map_addr, &ring->paddr, 0); 713 if (error != 0) { 714 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 715 goto fail; 716 } 717 718 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 719 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 720 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 721 if (error != 0) { 722 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 723 goto fail; 724 } 725 726 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 727 struct rt2860_rx_data *data = &ring->data[i]; 728 struct rt2860_rxd *rxd = &ring->rxd[i]; 729 730 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 731 if (error != 0) { 732 device_printf(sc->sc_dev, "could not create DMA map\n"); 733 goto fail; 734 } 735 736 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 737 if (data->m == NULL) { 738 device_printf(sc->sc_dev, 739 "could not allocate rx mbuf\n"); 740 error = ENOMEM; 741 goto fail; 742 } 743 744 error = bus_dmamap_load(ring->data_dmat, data->map, 745 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 746 &physaddr, 0); 747 if (error != 0) { 748 device_printf(sc->sc_dev, 749 "could not load rx buf DMA map"); 750 goto fail; 751 } 752 753 rxd->sdp0 = htole32(physaddr); 754 rxd->sdl0 = htole16(MCLBYTES); 755 } 756 757 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 758 759 return 0; 760 761 fail: rt2860_free_rx_ring(sc, ring); 762 return error; 763 } 764 765 void 766 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 767 { 768 int i; 769 770 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 771 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 772 773 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 774 775 ring->cur = 0; 776 } 777 778 void 779 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 780 { 781 int i; 782 783 if (ring->rxd != NULL) { 784 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 785 BUS_DMASYNC_POSTWRITE); 786 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 787 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 788 } 789 if (ring->desc_dmat != NULL) 790 bus_dma_tag_destroy(ring->desc_dmat); 791 792 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 793 struct rt2860_rx_data *data = &ring->data[i]; 794 795 if (data->m != NULL) { 796 bus_dmamap_sync(ring->data_dmat, data->map, 797 BUS_DMASYNC_POSTREAD); 798 bus_dmamap_unload(ring->data_dmat, data->map); 799 m_freem(data->m); 800 } 801 if (data->map != NULL) 802 bus_dmamap_destroy(ring->data_dmat, data->map); 803 } 804 if (ring->data_dmat != NULL) 805 bus_dma_tag_destroy(ring->data_dmat); 806 } 807 808 static void 809 rt2860_updatestats(struct rt2860_softc *sc) 810 { 811 struct ieee80211com *ic = &sc->sc_ic; 812 813 /* 814 * In IBSS or HostAP modes (when the hardware sends beacons), the 815 * MAC can run into a livelock and start sending CTS-to-self frames 816 * like crazy if protection is enabled. Fortunately, we can detect 817 * when such a situation occurs and reset the MAC. 818 */ 819 if (ic->ic_curmode != IEEE80211_M_STA) { 820 /* check if we're in a livelock situation.. */ 821 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 822 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 823 /* ..and reset MAC/BBP for a while.. */ 824 DPRINTF(("CTS-to-self livelock detected\n")); 825 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 826 RAL_BARRIER_WRITE(sc); 827 DELAY(1); 828 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 829 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 830 } 831 } 832 } 833 834 static void 835 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 836 { 837 struct ieee80211com *ic = ni->ni_ic; 838 struct rt2860_softc *sc = ic->ic_softc; 839 uint8_t wcid; 840 841 wcid = IEEE80211_AID(ni->ni_associd); 842 if (isnew && ni->ni_associd != 0) { 843 sc->wcid2ni[wcid] = ni; 844 845 /* init WCID table entry */ 846 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 847 ni->ni_macaddr, IEEE80211_ADDR_LEN); 848 } 849 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 850 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 851 } 852 853 static void 854 rt2860_node_free(struct ieee80211_node *ni) 855 { 856 struct ieee80211com *ic = ni->ni_ic; 857 struct rt2860_softc *sc = ic->ic_softc; 858 uint8_t wcid; 859 860 if (ni->ni_associd != 0) { 861 wcid = IEEE80211_AID(ni->ni_associd); 862 863 /* clear Rx WCID search table entry */ 864 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 865 } 866 sc->sc_node_free(ni); 867 } 868 869 #ifdef IEEE80211_HT 870 static int 871 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 872 uint8_t tid) 873 { 874 struct rt2860_softc *sc = ic->ic_softc; 875 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 876 uint32_t tmp; 877 878 /* update BA session mask */ 879 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 880 tmp |= (1 << tid) << 16; 881 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 882 return 0; 883 } 884 885 static void 886 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 887 uint8_t tid) 888 { 889 struct rt2860_softc *sc = ic->ic_softc; 890 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 891 uint32_t tmp; 892 893 /* update BA session mask */ 894 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 895 tmp &= ~((1 << tid) << 16); 896 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 897 } 898 #endif 899 900 static int 901 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 902 { 903 struct rt2860_vap *rvp = RT2860_VAP(vap); 904 struct ieee80211com *ic = vap->iv_ic; 905 struct rt2860_softc *sc = ic->ic_softc; 906 uint32_t tmp; 907 int error; 908 909 if (vap->iv_state == IEEE80211_S_RUN) { 910 /* turn link LED off */ 911 rt2860_set_leds(sc, RT2860_LED_RADIO); 912 } 913 914 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 915 /* abort TSF synchronization */ 916 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 917 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 918 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 919 RT2860_TBTT_TIMER_EN)); 920 } 921 922 rt2860_set_gp_timer(sc, 0); 923 924 error = rvp->ral_newstate(vap, nstate, arg); 925 if (error != 0) 926 return (error); 927 928 if (nstate == IEEE80211_S_RUN) { 929 struct ieee80211_node *ni = vap->iv_bss; 930 931 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 932 rt2860_enable_mrr(sc); 933 rt2860_set_txpreamble(sc); 934 rt2860_set_basicrates(sc, &ni->ni_rates); 935 rt2860_set_bssid(sc, ni->ni_bssid); 936 } 937 938 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 939 vap->iv_opmode == IEEE80211_M_IBSS || 940 vap->iv_opmode == IEEE80211_M_MBSS) { 941 error = rt2860_setup_beacon(sc, vap); 942 if (error != 0) 943 return error; 944 } 945 946 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 947 rt2860_enable_tsf_sync(sc); 948 rt2860_set_gp_timer(sc, 500); 949 } 950 951 /* turn link LED on */ 952 rt2860_set_leds(sc, RT2860_LED_RADIO | 953 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 954 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 955 } 956 return error; 957 } 958 959 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 960 static uint16_t 961 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 962 { 963 uint32_t tmp; 964 uint16_t reg; 965 int ntries; 966 967 addr *= 2; 968 /*- 969 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 970 * DATA0: F E D C 971 * DATA1: B A 9 8 972 * DATA2: 7 6 5 4 973 * DATA3: 3 2 1 0 974 */ 975 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 976 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 977 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 978 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 979 for (ntries = 0; ntries < 500; ntries++) { 980 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 981 if (!(tmp & RT3070_EFSROM_KICK)) 982 break; 983 DELAY(2); 984 } 985 if (ntries == 500) 986 return 0xffff; 987 988 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 989 return 0xffff; /* address not found */ 990 991 /* determine to which 32-bit register our 16-bit word belongs */ 992 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 993 tmp = RAL_READ(sc, reg); 994 995 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 996 } 997 998 /* 999 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 1000 * 93C66 or 93C86). 1001 */ 1002 static uint16_t 1003 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1004 { 1005 uint32_t tmp; 1006 uint16_t val; 1007 int n; 1008 1009 /* clock C once before the first command */ 1010 RT2860_EEPROM_CTL(sc, 0); 1011 1012 RT2860_EEPROM_CTL(sc, RT2860_S); 1013 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1014 RT2860_EEPROM_CTL(sc, RT2860_S); 1015 1016 /* write start bit (1) */ 1017 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1018 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1019 1020 /* write READ opcode (10) */ 1021 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1023 RT2860_EEPROM_CTL(sc, RT2860_S); 1024 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1025 1026 /* write address (A5-A0 or A7-A0) */ 1027 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1028 for (; n >= 0; n--) { 1029 RT2860_EEPROM_CTL(sc, RT2860_S | 1030 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1031 RT2860_EEPROM_CTL(sc, RT2860_S | 1032 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1033 } 1034 1035 RT2860_EEPROM_CTL(sc, RT2860_S); 1036 1037 /* read data Q15-Q0 */ 1038 val = 0; 1039 for (n = 15; n >= 0; n--) { 1040 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1041 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1042 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1043 RT2860_EEPROM_CTL(sc, RT2860_S); 1044 } 1045 1046 RT2860_EEPROM_CTL(sc, 0); 1047 1048 /* clear Chip Select and clock C */ 1049 RT2860_EEPROM_CTL(sc, RT2860_S); 1050 RT2860_EEPROM_CTL(sc, 0); 1051 RT2860_EEPROM_CTL(sc, RT2860_C); 1052 1053 return val; 1054 } 1055 1056 static __inline uint16_t 1057 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1058 { 1059 /* either eFUSE ROM or EEPROM */ 1060 return sc->sc_srom_read(sc, addr); 1061 } 1062 1063 static void 1064 rt2860_intr_coherent(struct rt2860_softc *sc) 1065 { 1066 uint32_t tmp; 1067 1068 /* DMA finds data coherent event when checking the DDONE bit */ 1069 1070 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1071 1072 /* restart DMA engine */ 1073 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1074 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1075 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1076 1077 (void)rt2860_txrx_enable(sc); 1078 } 1079 1080 static void 1081 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1082 { 1083 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 1084 struct ieee80211_node *ni; 1085 uint32_t stat; 1086 uint8_t wcid, mcs, pid; 1087 1088 /* drain Tx status FIFO (maxsize = 16) */ 1089 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 1090 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1091 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1092 1093 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1094 if (wcid > RT2860_WCID_MAX) 1095 continue; 1096 ni = sc->wcid2ni[wcid]; 1097 1098 /* if no ACK was requested, no feedback is available */ 1099 if (!(stat & RT2860_TXQ_ACKREQ) || ni == NULL) 1100 continue; 1101 1102 /* update per-STA AMRR stats */ 1103 if (stat & RT2860_TXQ_OK) { 1104 /* 1105 * Check if there were retries, ie if the Tx success 1106 * rate is different from the requested rate. Note 1107 * that it works only because we do not allow rate 1108 * fallback from OFDM to CCK. 1109 */ 1110 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1111 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1112 if (mcs + 1 != pid) 1113 txs->long_retries = 1; 1114 else 1115 txs->long_retries = 0; 1116 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 1117 ieee80211_ratectl_tx_complete(ni, txs); 1118 } else { 1119 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 1120 txs->long_retries = 1; /* XXX */ 1121 ieee80211_ratectl_tx_complete(ni, txs); 1122 if_inc_counter(ni->ni_vap->iv_ifp, 1123 IFCOUNTER_OERRORS, 1); 1124 } 1125 } 1126 } 1127 1128 static void 1129 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1130 { 1131 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1132 uint32_t hw; 1133 1134 rt2860_drain_stats_fifo(sc); 1135 1136 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1137 while (ring->next != hw) { 1138 struct rt2860_tx_data *data = ring->data[ring->next]; 1139 1140 if (data != NULL) { 1141 bus_dmamap_sync(sc->txwi_dmat, data->map, 1142 BUS_DMASYNC_POSTWRITE); 1143 bus_dmamap_unload(sc->txwi_dmat, data->map); 1144 ieee80211_tx_complete(data->ni, data->m, 0); 1145 data->ni = NULL; 1146 data->m = NULL; 1147 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1148 ring->data[ring->next] = NULL; 1149 } 1150 ring->queued--; 1151 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1152 } 1153 1154 sc->sc_tx_timer = 0; 1155 if (ring->queued < RT2860_TX_RING_COUNT) 1156 sc->qfullmsk &= ~(1 << qid); 1157 rt2860_start(sc); 1158 } 1159 1160 /* 1161 * Return the Rx chain with the highest RSSI for a given frame. 1162 */ 1163 static __inline uint8_t 1164 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1165 { 1166 uint8_t rxchain = 0; 1167 1168 if (sc->nrxchains > 1) { 1169 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1170 rxchain = 1; 1171 if (sc->nrxchains > 2) 1172 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1173 rxchain = 2; 1174 } 1175 return rxchain; 1176 } 1177 1178 static void 1179 rt2860_rx_intr(struct rt2860_softc *sc) 1180 { 1181 struct rt2860_rx_radiotap_header *tap; 1182 struct ieee80211com *ic = &sc->sc_ic; 1183 struct ieee80211_frame *wh; 1184 struct ieee80211_node *ni; 1185 struct mbuf *m, *m1; 1186 bus_addr_t physaddr; 1187 uint32_t hw; 1188 uint16_t phy; 1189 uint8_t ant; 1190 int8_t rssi, nf; 1191 int error; 1192 1193 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1194 while (sc->rxq.cur != hw) { 1195 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1196 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1197 struct rt2860_rxwi *rxwi; 1198 1199 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1200 BUS_DMASYNC_POSTREAD); 1201 1202 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1203 DPRINTF(("RXD DDONE bit not set!\n")); 1204 break; /* should not happen */ 1205 } 1206 1207 if (__predict_false(rxd->flags & 1208 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1209 counter_u64_add(ic->ic_ierrors, 1); 1210 goto skip; 1211 } 1212 1213 #ifdef HW_CRYPTO 1214 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1215 /* report MIC failures to net80211 for TKIP */ 1216 ic->ic_stats.is_rx_locmicfail++; 1217 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1218 counter_u64_add(ic->ic_ierrors, 1); 1219 goto skip; 1220 } 1221 #endif 1222 1223 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1224 if (__predict_false(m1 == NULL)) { 1225 counter_u64_add(ic->ic_ierrors, 1); 1226 goto skip; 1227 } 1228 1229 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1230 BUS_DMASYNC_POSTREAD); 1231 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1232 1233 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1234 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1235 &physaddr, 0); 1236 if (__predict_false(error != 0)) { 1237 m_freem(m1); 1238 1239 /* try to reload the old mbuf */ 1240 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1241 mtod(data->m, void *), MCLBYTES, 1242 rt2860_dma_map_addr, &physaddr, 0); 1243 if (__predict_false(error != 0)) { 1244 panic("%s: could not load old rx mbuf", 1245 device_get_name(sc->sc_dev)); 1246 } 1247 /* physical address may have changed */ 1248 rxd->sdp0 = htole32(physaddr); 1249 counter_u64_add(ic->ic_ierrors, 1); 1250 goto skip; 1251 } 1252 1253 /* 1254 * New mbuf successfully loaded, update Rx ring and continue 1255 * processing. 1256 */ 1257 m = data->m; 1258 data->m = m1; 1259 rxd->sdp0 = htole32(physaddr); 1260 1261 rxwi = mtod(m, struct rt2860_rxwi *); 1262 1263 /* finalize mbuf */ 1264 m->m_data = (caddr_t)(rxwi + 1); 1265 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1266 1267 wh = mtod(m, struct ieee80211_frame *); 1268 #ifdef HW_CRYPTO 1269 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1270 /* frame is decrypted by hardware */ 1271 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1272 } 1273 #endif 1274 1275 /* HW may insert 2 padding bytes after 802.11 header */ 1276 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1277 u_int hdrlen = ieee80211_hdrsize(wh); 1278 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1279 m->m_data += 2; 1280 wh = mtod(m, struct ieee80211_frame *); 1281 } 1282 1283 ant = rt2860_maxrssi_chain(sc, rxwi); 1284 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1285 nf = RT2860_NOISE_FLOOR; 1286 1287 if (ieee80211_radiotap_active(ic)) { 1288 tap = &sc->sc_rxtap; 1289 tap->wr_flags = 0; 1290 tap->wr_antenna = ant; 1291 tap->wr_antsignal = nf + rssi; 1292 tap->wr_antnoise = nf; 1293 /* in case it can't be found below */ 1294 tap->wr_rate = 2; 1295 phy = le16toh(rxwi->phy); 1296 switch (phy & RT2860_PHY_MODE) { 1297 case RT2860_PHY_CCK: 1298 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1299 case 0: tap->wr_rate = 2; break; 1300 case 1: tap->wr_rate = 4; break; 1301 case 2: tap->wr_rate = 11; break; 1302 case 3: tap->wr_rate = 22; break; 1303 } 1304 if (phy & RT2860_PHY_SHPRE) 1305 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1306 break; 1307 case RT2860_PHY_OFDM: 1308 switch (phy & RT2860_PHY_MCS) { 1309 case 0: tap->wr_rate = 12; break; 1310 case 1: tap->wr_rate = 18; break; 1311 case 2: tap->wr_rate = 24; break; 1312 case 3: tap->wr_rate = 36; break; 1313 case 4: tap->wr_rate = 48; break; 1314 case 5: tap->wr_rate = 72; break; 1315 case 6: tap->wr_rate = 96; break; 1316 case 7: tap->wr_rate = 108; break; 1317 } 1318 break; 1319 } 1320 } 1321 1322 RAL_UNLOCK(sc); 1323 wh = mtod(m, struct ieee80211_frame *); 1324 1325 /* send the frame to the 802.11 layer */ 1326 ni = ieee80211_find_rxnode(ic, 1327 (struct ieee80211_frame_min *)wh); 1328 if (ni != NULL) { 1329 (void)ieee80211_input(ni, m, rssi - nf, nf); 1330 ieee80211_free_node(ni); 1331 } else 1332 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1333 1334 RAL_LOCK(sc); 1335 1336 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1337 1338 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1339 BUS_DMASYNC_PREWRITE); 1340 1341 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1342 } 1343 1344 /* tell HW what we have processed */ 1345 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1346 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1347 } 1348 1349 static void 1350 rt2860_tbtt_intr(struct rt2860_softc *sc) 1351 { 1352 #if 0 1353 struct ieee80211com *ic = &sc->sc_ic; 1354 1355 #ifndef IEEE80211_STA_ONLY 1356 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1357 /* one less beacon until next DTIM */ 1358 if (ic->ic_dtim_count == 0) 1359 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1360 else 1361 ic->ic_dtim_count--; 1362 1363 /* update dynamic parts of beacon */ 1364 rt2860_setup_beacon(sc); 1365 1366 /* flush buffered multicast frames */ 1367 if (ic->ic_dtim_count == 0) 1368 ieee80211_notify_dtim(ic); 1369 } 1370 #endif 1371 /* check if protection mode has changed */ 1372 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1373 rt2860_updateprot(sc); 1374 sc->sc_ic_flags = ic->ic_flags; 1375 } 1376 #endif 1377 } 1378 1379 static void 1380 rt2860_gp_intr(struct rt2860_softc *sc) 1381 { 1382 struct ieee80211com *ic = &sc->sc_ic; 1383 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1384 1385 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1386 1387 if (vap->iv_state == IEEE80211_S_RUN) 1388 rt2860_updatestats(sc); 1389 } 1390 1391 void 1392 rt2860_intr(void *arg) 1393 { 1394 struct rt2860_softc *sc = arg; 1395 uint32_t r; 1396 1397 RAL_LOCK(sc); 1398 1399 r = RAL_READ(sc, RT2860_INT_STATUS); 1400 if (__predict_false(r == 0xffffffff)) { 1401 RAL_UNLOCK(sc); 1402 return; /* device likely went away */ 1403 } 1404 if (r == 0) { 1405 RAL_UNLOCK(sc); 1406 return; /* not for us */ 1407 } 1408 1409 /* acknowledge interrupts */ 1410 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1411 1412 if (r & RT2860_TX_RX_COHERENT) 1413 rt2860_intr_coherent(sc); 1414 1415 if (r & RT2860_MAC_INT_2) /* TX status */ 1416 rt2860_drain_stats_fifo(sc); 1417 1418 if (r & RT2860_TX_DONE_INT5) 1419 rt2860_tx_intr(sc, 5); 1420 1421 if (r & RT2860_RX_DONE_INT) 1422 rt2860_rx_intr(sc); 1423 1424 if (r & RT2860_TX_DONE_INT4) 1425 rt2860_tx_intr(sc, 4); 1426 1427 if (r & RT2860_TX_DONE_INT3) 1428 rt2860_tx_intr(sc, 3); 1429 1430 if (r & RT2860_TX_DONE_INT2) 1431 rt2860_tx_intr(sc, 2); 1432 1433 if (r & RT2860_TX_DONE_INT1) 1434 rt2860_tx_intr(sc, 1); 1435 1436 if (r & RT2860_TX_DONE_INT0) 1437 rt2860_tx_intr(sc, 0); 1438 1439 if (r & RT2860_MAC_INT_0) /* TBTT */ 1440 rt2860_tbtt_intr(sc); 1441 1442 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1443 /* TBD wakeup */; 1444 1445 if (r & RT2860_MAC_INT_4) /* GP timer */ 1446 rt2860_gp_intr(sc); 1447 1448 RAL_UNLOCK(sc); 1449 } 1450 1451 static int 1452 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1453 { 1454 struct ieee80211com *ic = &sc->sc_ic; 1455 struct ieee80211vap *vap = ni->ni_vap; 1456 struct rt2860_tx_ring *ring; 1457 struct rt2860_tx_data *data; 1458 struct rt2860_txd *txd; 1459 struct rt2860_txwi *txwi; 1460 struct ieee80211_frame *wh; 1461 const struct ieee80211_txparam *tp = ni->ni_txparms; 1462 struct ieee80211_key *k; 1463 struct mbuf *m1; 1464 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1465 bus_dma_segment_t *seg; 1466 u_int hdrlen; 1467 uint16_t qos, dur; 1468 uint8_t type, qsel, mcs, pid, qid; 1469 int i, nsegs, ntxds, pad, rate, ridx, error; 1470 1471 /* the data pool contains at least one element, pick the first */ 1472 data = SLIST_FIRST(&sc->data_pool); 1473 1474 wh = mtod(m, struct ieee80211_frame *); 1475 1476 ieee80211_output_seqno_assign(ni, -1, m); 1477 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1478 k = ieee80211_crypto_encap(ni, m); 1479 if (k == NULL) { 1480 m_freem(m); 1481 return ENOBUFS; 1482 } 1483 1484 /* packet header may have moved, reset our local pointer */ 1485 wh = mtod(m, struct ieee80211_frame *); 1486 } 1487 1488 hdrlen = ieee80211_anyhdrsize(wh); 1489 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1490 1491 if (m->m_flags & M_EAPOL) { 1492 rate = tp->mgmtrate; 1493 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1494 rate = tp->mcastrate; 1495 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1496 rate = tp->ucastrate; 1497 } else { 1498 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1499 rate = ieee80211_node_get_txrate_dot11rate(ni); 1500 } 1501 rate &= IEEE80211_RATE_VAL; 1502 1503 qid = M_WME_GETAC(m); 1504 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1505 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1506 } else { 1507 qos = 0; 1508 } 1509 ring = &sc->txq[qid]; 1510 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1511 1512 /* get MCS code from rate index */ 1513 mcs = rt2860_rates[ridx].mcs; 1514 1515 /* setup TX Wireless Information */ 1516 txwi = data->txwi; 1517 txwi->flags = 0; 1518 /* let HW generate seq numbers for non-QoS frames */ 1519 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1520 if (type == IEEE80211_FC0_TYPE_DATA) 1521 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1522 else 1523 txwi->wcid = 0xff; 1524 txwi->len = htole16(m->m_pkthdr.len); 1525 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1526 txwi->phy = htole16(RT2860_PHY_CCK); 1527 if (ridx != RT2860_RIDX_CCK1 && 1528 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1529 mcs |= RT2860_PHY_SHPRE; 1530 } else 1531 txwi->phy = htole16(RT2860_PHY_OFDM); 1532 txwi->phy |= htole16(mcs); 1533 1534 /* 1535 * We store the MCS code into the driver-private PacketID field. 1536 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1537 * that we know at which initial rate the frame was transmitted. 1538 * We add 1 to the MCS code because setting the PacketID field to 1539 * 0 means that we don't want feedback in TX_STAT_FIFO. 1540 */ 1541 pid = (mcs + 1) & 0xf; 1542 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1543 1544 /* check if RTS/CTS or CTS-to-self protection is required */ 1545 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1546 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1547 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1548 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1549 txwi->txop = RT2860_TX_TXOP_HT; 1550 else 1551 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1552 1553 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1554 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1555 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1556 txwi->xflags |= RT2860_TX_ACK; 1557 1558 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1559 dur = rt2860_rates[ridx].sp_ack_dur; 1560 else 1561 dur = rt2860_rates[ridx].lp_ack_dur; 1562 *(uint16_t *)wh->i_dur = htole16(dur); 1563 } 1564 /* ask MAC to insert timestamp into probe responses */ 1565 if (IEEE80211_IS_MGMT_PROBE_RESP(wh)) 1566 /* NOTE: beacons do not pass through tx_data() */ 1567 txwi->flags |= RT2860_TX_TS; 1568 1569 if (ieee80211_radiotap_active_vap(vap)) { 1570 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1571 1572 tap->wt_flags = 0; 1573 tap->wt_rate = rate; 1574 if (mcs & RT2860_PHY_SHPRE) 1575 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1576 1577 ieee80211_radiotap_tx(vap, m); 1578 } 1579 1580 pad = (hdrlen + 3) & ~3; 1581 1582 /* copy and trim 802.11 header */ 1583 memcpy(txwi + 1, wh, hdrlen); 1584 m_adj(m, hdrlen); 1585 1586 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1587 &nsegs, 0); 1588 if (__predict_false(error != 0 && error != EFBIG)) { 1589 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1590 error); 1591 m_freem(m); 1592 return error; 1593 } 1594 if (__predict_true(error == 0)) { 1595 /* determine how many TXDs are required */ 1596 ntxds = 1 + (nsegs / 2); 1597 1598 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1599 /* not enough free TXDs, force mbuf defrag */ 1600 bus_dmamap_unload(sc->txwi_dmat, data->map); 1601 error = EFBIG; 1602 } 1603 } 1604 if (__predict_false(error != 0)) { 1605 m1 = m_defrag(m, M_NOWAIT); 1606 if (m1 == NULL) { 1607 device_printf(sc->sc_dev, 1608 "could not defragment mbuf\n"); 1609 m_freem(m); 1610 return ENOBUFS; 1611 } 1612 m = m1; 1613 1614 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1615 segs, &nsegs, 0); 1616 if (__predict_false(error != 0)) { 1617 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1618 error); 1619 m_freem(m); 1620 return error; 1621 } 1622 1623 /* determine how many TXDs are now required */ 1624 ntxds = 1 + (nsegs / 2); 1625 1626 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1627 /* this is a hopeless case, drop the mbuf! */ 1628 bus_dmamap_unload(sc->txwi_dmat, data->map); 1629 m_freem(m); 1630 return ENOBUFS; 1631 } 1632 } 1633 1634 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1635 1636 /* first segment is TXWI + 802.11 header */ 1637 txd = &ring->txd[ring->cur]; 1638 txd->sdp0 = htole32(data->paddr); 1639 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1640 txd->flags = qsel; 1641 1642 /* setup payload segments */ 1643 seg = &segs[0]; 1644 for (i = nsegs; i >= 2; i -= 2) { 1645 txd->sdp1 = htole32(seg->ds_addr); 1646 txd->sdl1 = htole16(seg->ds_len); 1647 seg++; 1648 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1649 /* grab a new Tx descriptor */ 1650 txd = &ring->txd[ring->cur]; 1651 txd->sdp0 = htole32(seg->ds_addr); 1652 txd->sdl0 = htole16(seg->ds_len); 1653 txd->flags = qsel; 1654 seg++; 1655 } 1656 /* finalize last segment */ 1657 if (i > 0) { 1658 txd->sdp1 = htole32(seg->ds_addr); 1659 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1660 } else { 1661 txd->sdl0 |= htole16(RT2860_TX_LS0); 1662 txd->sdl1 = 0; 1663 } 1664 1665 /* remove from the free pool and link it into the SW Tx slot */ 1666 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1667 data->m = m; 1668 data->ni = ni; 1669 ring->data[ring->cur] = data; 1670 1671 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1672 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1673 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1674 1675 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1676 qid, txwi->wcid, nsegs, ridx)); 1677 1678 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1679 ring->queued += ntxds; 1680 if (ring->queued >= RT2860_TX_RING_COUNT) 1681 sc->qfullmsk |= 1 << qid; 1682 1683 /* kick Tx */ 1684 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1685 1686 return 0; 1687 } 1688 1689 static int 1690 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1691 const struct ieee80211_bpf_params *params) 1692 { 1693 struct ieee80211com *ic = ni->ni_ic; 1694 struct rt2860_softc *sc = ic->ic_softc; 1695 int error; 1696 1697 RAL_LOCK(sc); 1698 1699 /* prevent management frames from being sent if we're not ready */ 1700 if (!(sc->sc_flags & RT2860_RUNNING)) { 1701 RAL_UNLOCK(sc); 1702 m_freem(m); 1703 return ENETDOWN; 1704 } 1705 if (params == NULL) { 1706 /* 1707 * Legacy path; interpret frame contents to decide 1708 * precisely how to send the frame. 1709 */ 1710 error = rt2860_tx(sc, m, ni); 1711 } else { 1712 /* 1713 * Caller supplied explicit parameters to use in 1714 * sending the frame. 1715 */ 1716 error = rt2860_tx_raw(sc, m, ni, params); 1717 } 1718 sc->sc_tx_timer = 5; 1719 RAL_UNLOCK(sc); 1720 return error; 1721 } 1722 1723 static int 1724 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1725 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1726 { 1727 struct ieee80211com *ic = &sc->sc_ic; 1728 struct ieee80211vap *vap = ni->ni_vap; 1729 struct rt2860_tx_ring *ring; 1730 struct rt2860_tx_data *data; 1731 struct rt2860_txd *txd; 1732 struct rt2860_txwi *txwi; 1733 struct ieee80211_frame *wh; 1734 struct mbuf *m1; 1735 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1736 bus_dma_segment_t *seg; 1737 u_int hdrlen; 1738 uint16_t dur; 1739 uint8_t qsel, mcs, pid, qid; 1740 int i, nsegs, ntxds, pad, rate, ridx, error; 1741 1742 /* the data pool contains at least one element, pick the first */ 1743 data = SLIST_FIRST(&sc->data_pool); 1744 1745 wh = mtod(m, struct ieee80211_frame *); 1746 hdrlen = ieee80211_hdrsize(wh); 1747 1748 /* Choose a TX rate index. */ 1749 rate = params->ibp_rate0; 1750 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1751 rate & IEEE80211_RATE_VAL); 1752 if (ridx == (uint8_t)-1) { 1753 /* XXX fall back to mcast/mgmt rate? */ 1754 m_freem(m); 1755 return EINVAL; 1756 } 1757 1758 qid = params->ibp_pri & 3; 1759 ring = &sc->txq[qid]; 1760 1761 /* get MCS code from rate index */ 1762 mcs = rt2860_rates[ridx].mcs; 1763 1764 /* setup TX Wireless Information */ 1765 txwi = data->txwi; 1766 txwi->flags = 0; 1767 /* let HW generate seq numbers for non-QoS frames */ 1768 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1769 txwi->wcid = 0xff; 1770 txwi->len = htole16(m->m_pkthdr.len); 1771 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1772 txwi->phy = htole16(RT2860_PHY_CCK); 1773 if (ridx != RT2860_RIDX_CCK1 && 1774 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1775 mcs |= RT2860_PHY_SHPRE; 1776 } else 1777 txwi->phy = htole16(RT2860_PHY_OFDM); 1778 txwi->phy |= htole16(mcs); 1779 1780 /* 1781 * We store the MCS code into the driver-private PacketID field. 1782 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1783 * that we know at which initial rate the frame was transmitted. 1784 * We add 1 to the MCS code because setting the PacketID field to 1785 * 0 means that we don't want feedback in TX_STAT_FIFO. 1786 */ 1787 pid = (mcs + 1) & 0xf; 1788 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1789 1790 /* check if RTS/CTS or CTS-to-self protection is required */ 1791 if (params->ibp_flags & IEEE80211_BPF_RTS || 1792 params->ibp_flags & IEEE80211_BPF_CTS) 1793 txwi->txop = RT2860_TX_TXOP_HT; 1794 else 1795 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1796 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1797 txwi->xflags |= RT2860_TX_ACK; 1798 1799 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1800 dur = rt2860_rates[ridx].sp_ack_dur; 1801 else 1802 dur = rt2860_rates[ridx].lp_ack_dur; 1803 *(uint16_t *)wh->i_dur = htole16(dur); 1804 } 1805 /* ask MAC to insert timestamp into probe responses */ 1806 if (IEEE80211_IS_MGMT_PROBE_RESP(wh)) 1807 /* NOTE: beacons do not pass through tx_data() */ 1808 txwi->flags |= RT2860_TX_TS; 1809 1810 if (ieee80211_radiotap_active_vap(vap)) { 1811 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1812 1813 tap->wt_flags = 0; 1814 tap->wt_rate = rate; 1815 if (mcs & RT2860_PHY_SHPRE) 1816 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1817 1818 ieee80211_radiotap_tx(vap, m); 1819 } 1820 1821 pad = (hdrlen + 3) & ~3; 1822 1823 /* copy and trim 802.11 header */ 1824 memcpy(txwi + 1, wh, hdrlen); 1825 m_adj(m, hdrlen); 1826 1827 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1828 &nsegs, 0); 1829 if (__predict_false(error != 0 && error != EFBIG)) { 1830 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1831 error); 1832 m_freem(m); 1833 return error; 1834 } 1835 if (__predict_true(error == 0)) { 1836 /* determine how many TXDs are required */ 1837 ntxds = 1 + (nsegs / 2); 1838 1839 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1840 /* not enough free TXDs, force mbuf defrag */ 1841 bus_dmamap_unload(sc->txwi_dmat, data->map); 1842 error = EFBIG; 1843 } 1844 } 1845 if (__predict_false(error != 0)) { 1846 m1 = m_defrag(m, M_NOWAIT); 1847 if (m1 == NULL) { 1848 device_printf(sc->sc_dev, 1849 "could not defragment mbuf\n"); 1850 m_freem(m); 1851 return ENOBUFS; 1852 } 1853 m = m1; 1854 1855 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1856 segs, &nsegs, 0); 1857 if (__predict_false(error != 0)) { 1858 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1859 error); 1860 m_freem(m); 1861 return error; 1862 } 1863 1864 /* determine how many TXDs are now required */ 1865 ntxds = 1 + (nsegs / 2); 1866 1867 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1868 /* this is a hopeless case, drop the mbuf! */ 1869 bus_dmamap_unload(sc->txwi_dmat, data->map); 1870 m_freem(m); 1871 return ENOBUFS; 1872 } 1873 } 1874 1875 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1876 1877 /* first segment is TXWI + 802.11 header */ 1878 txd = &ring->txd[ring->cur]; 1879 txd->sdp0 = htole32(data->paddr); 1880 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1881 txd->flags = qsel; 1882 1883 /* setup payload segments */ 1884 seg = &segs[0]; 1885 for (i = nsegs; i >= 2; i -= 2) { 1886 txd->sdp1 = htole32(seg->ds_addr); 1887 txd->sdl1 = htole16(seg->ds_len); 1888 seg++; 1889 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1890 /* grab a new Tx descriptor */ 1891 txd = &ring->txd[ring->cur]; 1892 txd->sdp0 = htole32(seg->ds_addr); 1893 txd->sdl0 = htole16(seg->ds_len); 1894 txd->flags = qsel; 1895 seg++; 1896 } 1897 /* finalize last segment */ 1898 if (i > 0) { 1899 txd->sdp1 = htole32(seg->ds_addr); 1900 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1901 } else { 1902 txd->sdl0 |= htole16(RT2860_TX_LS0); 1903 txd->sdl1 = 0; 1904 } 1905 1906 /* remove from the free pool and link it into the SW Tx slot */ 1907 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1908 data->m = m; 1909 data->ni = ni; 1910 ring->data[ring->cur] = data; 1911 1912 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1913 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1914 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1915 1916 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1917 qid, txwi->wcid, nsegs, ridx)); 1918 1919 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1920 ring->queued += ntxds; 1921 if (ring->queued >= RT2860_TX_RING_COUNT) 1922 sc->qfullmsk |= 1 << qid; 1923 1924 /* kick Tx */ 1925 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1926 1927 return 0; 1928 } 1929 1930 static int 1931 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1932 { 1933 struct rt2860_softc *sc = ic->ic_softc; 1934 int error; 1935 1936 RAL_LOCK(sc); 1937 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 1938 RAL_UNLOCK(sc); 1939 return (ENXIO); 1940 } 1941 error = mbufq_enqueue(&sc->sc_snd, m); 1942 if (error) { 1943 RAL_UNLOCK(sc); 1944 return (error); 1945 } 1946 rt2860_start(sc); 1947 RAL_UNLOCK(sc); 1948 1949 return (0); 1950 } 1951 1952 static void 1953 rt2860_start(struct rt2860_softc *sc) 1954 { 1955 struct ieee80211_node *ni; 1956 struct mbuf *m; 1957 1958 RAL_LOCK_ASSERT(sc); 1959 1960 if ((sc->sc_flags & RT2860_RUNNING) == 0) 1961 return; 1962 1963 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1964 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1965 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1966 if (rt2860_tx(sc, m, ni) != 0) { 1967 if_inc_counter(ni->ni_vap->iv_ifp, 1968 IFCOUNTER_OERRORS, 1); 1969 ieee80211_free_node(ni); 1970 continue; 1971 } 1972 sc->sc_tx_timer = 5; 1973 } 1974 } 1975 1976 static void 1977 rt2860_watchdog(void *arg) 1978 { 1979 struct rt2860_softc *sc = arg; 1980 1981 RAL_LOCK_ASSERT(sc); 1982 1983 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 1984 1985 if (sc->sc_invalid) /* card ejected */ 1986 return; 1987 1988 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1989 device_printf(sc->sc_dev, "device timeout\n"); 1990 rt2860_stop_locked(sc); 1991 rt2860_init_locked(sc); 1992 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1993 return; 1994 } 1995 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 1996 } 1997 1998 static void 1999 rt2860_parent(struct ieee80211com *ic) 2000 { 2001 struct rt2860_softc *sc = ic->ic_softc; 2002 int startall = 0; 2003 2004 RAL_LOCK(sc); 2005 if (ic->ic_nrunning> 0) { 2006 if (!(sc->sc_flags & RT2860_RUNNING)) { 2007 rt2860_init_locked(sc); 2008 startall = 1; 2009 } else 2010 rt2860_update_promisc(ic); 2011 } else if (sc->sc_flags & RT2860_RUNNING) 2012 rt2860_stop_locked(sc); 2013 RAL_UNLOCK(sc); 2014 if (startall) 2015 ieee80211_start_all(ic); 2016 } 2017 2018 /* 2019 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2020 * We access the BBP through the 8051 microcontroller unit which means that 2021 * the microcode must be loaded first. 2022 */ 2023 void 2024 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2025 { 2026 int ntries; 2027 2028 for (ntries = 0; ntries < 100; ntries++) { 2029 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2030 break; 2031 DELAY(1); 2032 } 2033 if (ntries == 100) { 2034 device_printf(sc->sc_dev, 2035 "could not write to BBP through MCU\n"); 2036 return; 2037 } 2038 2039 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2040 RT2860_BBP_CSR_KICK | reg << 8 | val); 2041 RAL_BARRIER_WRITE(sc); 2042 2043 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2044 DELAY(1000); 2045 } 2046 2047 uint8_t 2048 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2049 { 2050 uint32_t val; 2051 int ntries; 2052 2053 for (ntries = 0; ntries < 100; ntries++) { 2054 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2055 break; 2056 DELAY(1); 2057 } 2058 if (ntries == 100) { 2059 device_printf(sc->sc_dev, 2060 "could not read from BBP through MCU\n"); 2061 return 0; 2062 } 2063 2064 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2065 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2066 RAL_BARRIER_WRITE(sc); 2067 2068 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2069 DELAY(1000); 2070 2071 for (ntries = 0; ntries < 100; ntries++) { 2072 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2073 if (!(val & RT2860_BBP_CSR_KICK)) 2074 return val & 0xff; 2075 DELAY(1); 2076 } 2077 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2078 2079 return 0; 2080 } 2081 2082 /* 2083 * Write to one of the 4 programmable 24-bit RF registers. 2084 */ 2085 static void 2086 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2087 { 2088 uint32_t tmp; 2089 int ntries; 2090 2091 for (ntries = 0; ntries < 100; ntries++) { 2092 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2093 break; 2094 DELAY(1); 2095 } 2096 if (ntries == 100) { 2097 device_printf(sc->sc_dev, "could not write to RF\n"); 2098 return; 2099 } 2100 2101 /* RF registers are 24-bit on the RT2860 */ 2102 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2103 (val & 0x3fffff) << 2 | (reg & 3); 2104 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2105 } 2106 2107 static uint8_t 2108 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2109 { 2110 uint32_t tmp; 2111 int ntries; 2112 2113 for (ntries = 0; ntries < 100; ntries++) { 2114 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2115 break; 2116 DELAY(1); 2117 } 2118 if (ntries == 100) { 2119 device_printf(sc->sc_dev, "could not read RF register\n"); 2120 return 0xff; 2121 } 2122 tmp = RT3070_RF_KICK | reg << 8; 2123 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2124 2125 for (ntries = 0; ntries < 100; ntries++) { 2126 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2127 if (!(tmp & RT3070_RF_KICK)) 2128 break; 2129 DELAY(1); 2130 } 2131 if (ntries == 100) { 2132 device_printf(sc->sc_dev, "could not read RF register\n"); 2133 return 0xff; 2134 } 2135 return tmp & 0xff; 2136 } 2137 2138 void 2139 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2140 { 2141 uint32_t tmp; 2142 int ntries; 2143 2144 for (ntries = 0; ntries < 10; ntries++) { 2145 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2146 break; 2147 DELAY(10); 2148 } 2149 if (ntries == 10) { 2150 device_printf(sc->sc_dev, "could not write to RF\n"); 2151 return; 2152 } 2153 2154 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2155 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2156 } 2157 2158 /* 2159 * Send a command to the 8051 microcontroller unit. 2160 */ 2161 int 2162 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2163 { 2164 int slot, ntries; 2165 uint32_t tmp; 2166 uint8_t cid; 2167 2168 for (ntries = 0; ntries < 100; ntries++) { 2169 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2170 break; 2171 DELAY(2); 2172 } 2173 if (ntries == 100) 2174 return EIO; 2175 2176 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2177 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2178 RAL_BARRIER_WRITE(sc); 2179 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2180 2181 if (!wait) 2182 return 0; 2183 /* wait for the command to complete */ 2184 for (ntries = 0; ntries < 200; ntries++) { 2185 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2186 /* find the command slot */ 2187 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2188 if ((tmp & 0xff) == cid) 2189 break; 2190 if (slot < 4) 2191 break; 2192 DELAY(100); 2193 } 2194 if (ntries == 200) { 2195 /* clear command and status */ 2196 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2197 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2198 return ETIMEDOUT; 2199 } 2200 /* get command status (1 means success) */ 2201 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2202 tmp = (tmp >> (slot * 8)) & 0xff; 2203 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2204 cmd, slot, tmp)); 2205 /* clear command and status */ 2206 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2207 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2208 return (tmp == 1) ? 0 : EIO; 2209 } 2210 2211 static void 2212 rt2860_enable_mrr(struct rt2860_softc *sc) 2213 { 2214 #define CCK(mcs) (mcs) 2215 #define OFDM(mcs) (1U << 3 | (mcs)) 2216 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2217 OFDM(6) << 28 | /* 54->48 */ 2218 OFDM(5) << 24 | /* 48->36 */ 2219 OFDM(4) << 20 | /* 36->24 */ 2220 OFDM(3) << 16 | /* 24->18 */ 2221 OFDM(2) << 12 | /* 18->12 */ 2222 OFDM(1) << 8 | /* 12-> 9 */ 2223 OFDM(0) << 4 | /* 9-> 6 */ 2224 OFDM(0)); /* 6-> 6 */ 2225 2226 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2227 CCK(2) << 12 | /* 11->5.5 */ 2228 CCK(1) << 8 | /* 5.5-> 2 */ 2229 CCK(0) << 4 | /* 2-> 1 */ 2230 CCK(0)); /* 1-> 1 */ 2231 #undef OFDM 2232 #undef CCK 2233 } 2234 2235 static void 2236 rt2860_set_txpreamble(struct rt2860_softc *sc) 2237 { 2238 struct ieee80211com *ic = &sc->sc_ic; 2239 uint32_t tmp; 2240 2241 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2242 tmp &= ~RT2860_CCK_SHORT_EN; 2243 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2244 tmp |= RT2860_CCK_SHORT_EN; 2245 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2246 } 2247 2248 void 2249 rt2860_set_basicrates(struct rt2860_softc *sc, 2250 const struct ieee80211_rateset *rs) 2251 { 2252 struct ieee80211com *ic = &sc->sc_ic; 2253 uint32_t mask = 0; 2254 uint8_t rate; 2255 int i; 2256 2257 for (i = 0; i < rs->rs_nrates; i++) { 2258 rate = rs->rs_rates[i]; 2259 2260 if (!(rate & IEEE80211_RATE_BASIC)) 2261 continue; 2262 2263 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2264 IEEE80211_RV(rate)); 2265 } 2266 2267 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2268 } 2269 2270 static void 2271 rt2860_scan_start(struct ieee80211com *ic) 2272 { 2273 struct rt2860_softc *sc = ic->ic_softc; 2274 uint32_t tmp; 2275 2276 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2277 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2278 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2279 RT2860_TBTT_TIMER_EN)); 2280 rt2860_set_gp_timer(sc, 0); 2281 } 2282 2283 static void 2284 rt2860_scan_end(struct ieee80211com *ic) 2285 { 2286 struct rt2860_softc *sc = ic->ic_softc; 2287 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2288 2289 if (vap->iv_state == IEEE80211_S_RUN) { 2290 rt2860_enable_tsf_sync(sc); 2291 rt2860_set_gp_timer(sc, 500); 2292 } 2293 } 2294 2295 static void 2296 rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, 2297 struct ieee80211_channel chans[]) 2298 { 2299 struct rt2860_softc *sc = ic->ic_softc; 2300 uint8_t bands[IEEE80211_MODE_BYTES]; 2301 2302 memset(bands, 0, sizeof(bands)); 2303 setbit(bands, IEEE80211_MODE_11B); 2304 setbit(bands, IEEE80211_MODE_11G); 2305 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2306 2307 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 2308 setbit(bands, IEEE80211_MODE_11A); 2309 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2310 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0); 2311 } 2312 } 2313 2314 static void 2315 rt2860_set_channel(struct ieee80211com *ic) 2316 { 2317 struct rt2860_softc *sc = ic->ic_softc; 2318 2319 RAL_LOCK(sc); 2320 rt2860_switch_chan(sc, ic->ic_curchan); 2321 RAL_UNLOCK(sc); 2322 } 2323 2324 static void 2325 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2326 { 2327 uint32_t tmp; 2328 uint8_t agc; 2329 2330 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2331 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2332 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2333 rt2860_mcu_bbp_write(sc, 86, 0x00); 2334 2335 if (group == 0) { 2336 if (sc->ext_2ghz_lna) { 2337 rt2860_mcu_bbp_write(sc, 82, 0x62); 2338 rt2860_mcu_bbp_write(sc, 75, 0x46); 2339 } else { 2340 rt2860_mcu_bbp_write(sc, 82, 0x84); 2341 rt2860_mcu_bbp_write(sc, 75, 0x50); 2342 } 2343 } else { 2344 if (sc->ext_5ghz_lna) { 2345 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2346 rt2860_mcu_bbp_write(sc, 75, 0x46); 2347 } else { 2348 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2349 rt2860_mcu_bbp_write(sc, 75, 0x50); 2350 } 2351 } 2352 2353 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2354 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2355 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2356 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2357 2358 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2359 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2360 if (sc->nrxchains > 1) 2361 tmp |= RT2860_LNA_PE1_EN; 2362 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2363 tmp |= RT3593_LNA_PE2_EN; 2364 if (group == 0) { /* 2GHz */ 2365 tmp |= RT2860_PA_PE_G0_EN; 2366 if (sc->ntxchains > 1) 2367 tmp |= RT2860_PA_PE_G1_EN; 2368 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2369 tmp |= RT3593_PA_PE_G2_EN; 2370 } else { /* 5GHz */ 2371 tmp |= RT2860_PA_PE_A0_EN; 2372 if (sc->ntxchains > 1) 2373 tmp |= RT2860_PA_PE_A1_EN; 2374 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2375 tmp |= RT3593_PA_PE_A2_EN; 2376 } 2377 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2378 2379 if (sc->mac_ver == 0x3593) { 2380 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2381 if (sc->sc_flags & RT2860_PCIE) { 2382 tmp &= ~0x01010000; 2383 if (group == 0) 2384 tmp |= 0x00010000; 2385 } else { 2386 tmp &= ~0x00008080; 2387 if (group == 0) 2388 tmp |= 0x00000080; 2389 } 2390 tmp = (tmp & ~0x00001000) | 0x00000010; 2391 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2392 } 2393 2394 /* set initial AGC value */ 2395 if (group == 0) { /* 2GHz band */ 2396 if (sc->mac_ver >= 0x3071) 2397 agc = 0x1c + sc->lna[0] * 2; 2398 else 2399 agc = 0x2e + sc->lna[0]; 2400 } else { /* 5GHz band */ 2401 agc = 0x32 + (sc->lna[group] * 5) / 3; 2402 } 2403 rt2860_mcu_bbp_write(sc, 66, agc); 2404 2405 DELAY(1000); 2406 } 2407 2408 static void 2409 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2410 { 2411 const struct rfprog *rfprog = rt2860_rf2850; 2412 uint32_t r2, r3, r4; 2413 int8_t txpow1, txpow2; 2414 u_int i; 2415 2416 /* find the settings for this channel (we know it exists) */ 2417 for (i = 0; rfprog[i].chan != chan; i++); 2418 2419 r2 = rfprog[i].r2; 2420 if (sc->ntxchains == 1) 2421 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2422 if (sc->nrxchains == 1) 2423 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2424 else if (sc->nrxchains == 2) 2425 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2426 2427 /* use Tx power values from EEPROM */ 2428 txpow1 = sc->txpow1[i]; 2429 txpow2 = sc->txpow2[i]; 2430 if (chan > 14) { 2431 if (txpow1 >= 0) 2432 txpow1 = txpow1 << 1 | 1; 2433 else 2434 txpow1 = (7 + txpow1) << 1; 2435 if (txpow2 >= 0) 2436 txpow2 = txpow2 << 1 | 1; 2437 else 2438 txpow2 = (7 + txpow2) << 1; 2439 } 2440 r3 = rfprog[i].r3 | txpow1 << 7; 2441 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2442 2443 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2444 rt2860_rf_write(sc, RT2860_RF2, r2); 2445 rt2860_rf_write(sc, RT2860_RF3, r3); 2446 rt2860_rf_write(sc, RT2860_RF4, r4); 2447 2448 DELAY(200); 2449 2450 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2451 rt2860_rf_write(sc, RT2860_RF2, r2); 2452 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2453 rt2860_rf_write(sc, RT2860_RF4, r4); 2454 2455 DELAY(200); 2456 2457 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2458 rt2860_rf_write(sc, RT2860_RF2, r2); 2459 rt2860_rf_write(sc, RT2860_RF3, r3); 2460 rt2860_rf_write(sc, RT2860_RF4, r4); 2461 } 2462 2463 static void 2464 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2465 { 2466 int8_t txpow1, txpow2; 2467 uint8_t rf; 2468 int i; 2469 2470 /* RT3090 is 2GHz only */ 2471 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2472 2473 /* find the settings for this channel (we know it exists) */ 2474 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2475 2476 /* use Tx power values from EEPROM */ 2477 txpow1 = sc->txpow1[i]; 2478 txpow2 = sc->txpow2[i]; 2479 2480 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2481 rf = rt3090_rf_read(sc, 3); 2482 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2483 rt3090_rf_write(sc, 3, rf); 2484 rf = rt3090_rf_read(sc, 6); 2485 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2486 rt3090_rf_write(sc, 6, rf); 2487 2488 /* set Tx0 power */ 2489 rf = rt3090_rf_read(sc, 12); 2490 rf = (rf & ~0x1f) | txpow1; 2491 rt3090_rf_write(sc, 12, rf); 2492 2493 /* set Tx1 power */ 2494 rf = rt3090_rf_read(sc, 13); 2495 rf = (rf & ~0x1f) | txpow2; 2496 rt3090_rf_write(sc, 13, rf); 2497 2498 rf = rt3090_rf_read(sc, 1); 2499 rf &= ~0xfc; 2500 if (sc->ntxchains == 1) 2501 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2502 else if (sc->ntxchains == 2) 2503 rf |= RT3070_TX2_PD; 2504 if (sc->nrxchains == 1) 2505 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2506 else if (sc->nrxchains == 2) 2507 rf |= RT3070_RX2_PD; 2508 rt3090_rf_write(sc, 1, rf); 2509 2510 /* set RF offset */ 2511 rf = rt3090_rf_read(sc, 23); 2512 rf = (rf & ~0x7f) | sc->freq; 2513 rt3090_rf_write(sc, 23, rf); 2514 2515 /* program RF filter */ 2516 rf = rt3090_rf_read(sc, 24); /* Tx */ 2517 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2518 rt3090_rf_write(sc, 24, rf); 2519 rf = rt3090_rf_read(sc, 31); /* Rx */ 2520 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2521 rt3090_rf_write(sc, 31, rf); 2522 2523 /* enable RF tuning */ 2524 rf = rt3090_rf_read(sc, 7); 2525 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2526 } 2527 2528 static void 2529 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2530 { 2531 uint8_t h20mhz, rf, tmp; 2532 int8_t txpow1, txpow2; 2533 int i; 2534 2535 /* RT5390 is 2GHz only */ 2536 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2537 2538 /* find the settings for this channel (we know it exists) */ 2539 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2540 2541 /* use Tx power values from EEPROM */ 2542 txpow1 = sc->txpow1[i]; 2543 txpow2 = sc->txpow2[i]; 2544 2545 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2546 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2547 rf = rt3090_rf_read(sc, 11); 2548 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2549 rt3090_rf_write(sc, 11, rf); 2550 2551 rf = rt3090_rf_read(sc, 49); 2552 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2553 /* the valid range of the RF R49 is 0x00~0x27 */ 2554 if ((rf & 0x3f) > 0x27) 2555 rf = (rf & ~0x3f) | 0x27; 2556 rt3090_rf_write(sc, 49, rf); 2557 if (sc->mac_ver == 0x5392) { 2558 rf = rt3090_rf_read(sc, 50); 2559 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2560 /* the valid range of the RF R50 is 0x00~0x27 */ 2561 if ((rf & 0x3f) > 0x27) 2562 rf = (rf & ~0x3f) | 0x27; 2563 rt3090_rf_write(sc, 50, rf); 2564 } 2565 2566 rf = rt3090_rf_read(sc, 1); 2567 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2568 if (sc->mac_ver == 0x5392) 2569 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2570 rt3090_rf_write(sc, 1, rf); 2571 2572 rf = rt3090_rf_read(sc, 2); 2573 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2574 DELAY(1000); 2575 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2576 2577 rf = rt3090_rf_read(sc, 17); 2578 tmp = rf; 2579 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2580 rf = MIN(rf, 0x5f); 2581 if (tmp != rf) 2582 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2583 2584 if (sc->mac_ver == 0x5390) { 2585 if (chan <= 4) 2586 rf = 0x73; 2587 else if (chan >= 5 && chan <= 6) 2588 rf = 0x63; 2589 else if (chan >= 7 && chan <= 10) 2590 rf = 0x53; 2591 else 2592 rf = 43; 2593 rt3090_rf_write(sc, 55, rf); 2594 2595 if (chan == 1) 2596 rf = 0x0c; 2597 else if (chan == 2) 2598 rf = 0x0b; 2599 else if (chan == 3) 2600 rf = 0x0a; 2601 else if (chan >= 4 && chan <= 6) 2602 rf = 0x09; 2603 else if (chan >= 7 && chan <= 12) 2604 rf = 0x08; 2605 else if (chan == 13) 2606 rf = 0x07; 2607 else 2608 rf = 0x06; 2609 rt3090_rf_write(sc, 59, rf); 2610 } 2611 2612 /* Tx/Rx h20M */ 2613 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2614 rf = rt3090_rf_read(sc, 30); 2615 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2616 rt3090_rf_write(sc, 30, rf); 2617 2618 /* Rx BB filter VCM */ 2619 rf = rt3090_rf_read(sc, 30); 2620 rf = (rf & ~0x18) | 0x10; 2621 rt3090_rf_write(sc, 30, rf); 2622 2623 /* Initiate VCO calibration. */ 2624 rf = rt3090_rf_read(sc, 3); 2625 rf |= RT3593_VCOCAL; 2626 rt3090_rf_write(sc, 3, rf); 2627 } 2628 2629 static int 2630 rt3090_rf_init(struct rt2860_softc *sc) 2631 { 2632 uint32_t tmp; 2633 uint8_t rf, bbp; 2634 int i; 2635 2636 rf = rt3090_rf_read(sc, 30); 2637 /* toggle RF R30 bit 7 */ 2638 rt3090_rf_write(sc, 30, rf | 0x80); 2639 DELAY(1000); 2640 rt3090_rf_write(sc, 30, rf & ~0x80); 2641 2642 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2643 tmp &= ~0x1f000000; 2644 if (sc->patch_dac && sc->mac_rev < 0x0211) 2645 tmp |= 0x0d000000; /* 1.35V */ 2646 else 2647 tmp |= 0x01000000; /* 1.2V */ 2648 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2649 2650 /* patch LNA_PE_G1 */ 2651 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2652 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2653 2654 /* initialize RF registers to default value */ 2655 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2656 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2657 rt3090_def_rf[i].val); 2658 } 2659 2660 /* select 20MHz bandwidth */ 2661 rt3090_rf_write(sc, 31, 0x14); 2662 2663 rf = rt3090_rf_read(sc, 6); 2664 rt3090_rf_write(sc, 6, rf | 0x40); 2665 2666 if (sc->mac_ver != 0x3593) { 2667 /* calibrate filter for 20MHz bandwidth */ 2668 sc->rf24_20mhz = 0x1f; /* default value */ 2669 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2670 2671 /* select 40MHz bandwidth */ 2672 bbp = rt2860_mcu_bbp_read(sc, 4); 2673 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2674 rf = rt3090_rf_read(sc, 31); 2675 rt3090_rf_write(sc, 31, rf | 0x20); 2676 2677 /* calibrate filter for 40MHz bandwidth */ 2678 sc->rf24_40mhz = 0x2f; /* default value */ 2679 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2680 2681 /* go back to 20MHz bandwidth */ 2682 bbp = rt2860_mcu_bbp_read(sc, 4); 2683 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2684 } 2685 if (sc->mac_rev < 0x0211) 2686 rt3090_rf_write(sc, 27, 0x03); 2687 2688 tmp = RAL_READ(sc, RT3070_OPT_14); 2689 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2690 2691 if (sc->rf_rev == RT3070_RF_3020) 2692 rt3090_set_rx_antenna(sc, 0); 2693 2694 bbp = rt2860_mcu_bbp_read(sc, 138); 2695 if (sc->mac_ver == 0x3593) { 2696 if (sc->ntxchains == 1) 2697 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2698 else if (sc->ntxchains == 2) 2699 bbp |= 0x40; /* turn off DAC2 */ 2700 if (sc->nrxchains == 1) 2701 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2702 else if (sc->nrxchains == 2) 2703 bbp &= ~0x04; /* turn off ADC2 */ 2704 } else { 2705 if (sc->ntxchains == 1) 2706 bbp |= 0x20; /* turn off DAC1 */ 2707 if (sc->nrxchains == 1) 2708 bbp &= ~0x02; /* turn off ADC1 */ 2709 } 2710 rt2860_mcu_bbp_write(sc, 138, bbp); 2711 2712 rf = rt3090_rf_read(sc, 1); 2713 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2714 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2715 rt3090_rf_write(sc, 1, rf); 2716 2717 rf = rt3090_rf_read(sc, 15); 2718 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2719 2720 rf = rt3090_rf_read(sc, 17); 2721 rf &= ~RT3070_TX_LO1; 2722 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2723 rf |= 0x20; /* fix for long range Rx issue */ 2724 if (sc->txmixgain_2ghz >= 2) 2725 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2726 rt3090_rf_write(sc, 17, rf); 2727 2728 rf = rt3090_rf_read(sc, 20); 2729 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2730 2731 rf = rt3090_rf_read(sc, 21); 2732 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2733 2734 return (0); 2735 } 2736 2737 static void 2738 rt5390_rf_init(struct rt2860_softc *sc) 2739 { 2740 uint8_t rf, bbp; 2741 int i; 2742 2743 rf = rt3090_rf_read(sc, 2); 2744 /* Toggle RF R2 bit 7. */ 2745 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2746 DELAY(1000); 2747 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2748 2749 /* Initialize RF registers to default value. */ 2750 if (sc->mac_ver == 0x5392) { 2751 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2752 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2753 rt5392_def_rf[i].val); 2754 } 2755 } else { 2756 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2757 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2758 rt5390_def_rf[i].val); 2759 } 2760 } 2761 2762 sc->rf24_20mhz = 0x1f; 2763 sc->rf24_40mhz = 0x2f; 2764 2765 if (sc->mac_rev < 0x0211) 2766 rt3090_rf_write(sc, 27, 0x03); 2767 2768 /* Set led open drain enable. */ 2769 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2770 2771 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2772 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2773 2774 if (sc->mac_ver == 0x5390) 2775 rt3090_set_rx_antenna(sc, 0); 2776 2777 /* Patch RSSI inaccurate issue. */ 2778 rt2860_mcu_bbp_write(sc, 79, 0x13); 2779 rt2860_mcu_bbp_write(sc, 80, 0x05); 2780 rt2860_mcu_bbp_write(sc, 81, 0x33); 2781 2782 /* Enable DC filter. */ 2783 if (sc->mac_rev >= 0x0211) 2784 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2785 2786 bbp = rt2860_mcu_bbp_read(sc, 138); 2787 if (sc->ntxchains == 1) 2788 bbp |= 0x20; /* Turn off DAC1. */ 2789 if (sc->nrxchains == 1) 2790 bbp &= ~0x02; /* Turn off ADC1. */ 2791 rt2860_mcu_bbp_write(sc, 138, bbp); 2792 2793 /* Enable RX LO1 and LO2. */ 2794 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2795 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2796 2797 /* Avoid data lost and CRC error. */ 2798 rt2860_mcu_bbp_write(sc, 4, 2799 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2800 2801 rf = rt3090_rf_read(sc, 30); 2802 rf = (rf & ~0x18) | 0x10; 2803 rt3090_rf_write(sc, 30, rf); 2804 } 2805 2806 static void 2807 rt3090_rf_wakeup(struct rt2860_softc *sc) 2808 { 2809 uint32_t tmp; 2810 uint8_t rf; 2811 2812 if (sc->mac_ver == 0x3593) { 2813 /* enable VCO */ 2814 rf = rt3090_rf_read(sc, 1); 2815 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2816 2817 /* initiate VCO calibration */ 2818 rf = rt3090_rf_read(sc, 3); 2819 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2820 2821 /* enable VCO bias current control */ 2822 rf = rt3090_rf_read(sc, 6); 2823 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2824 2825 /* initiate res calibration */ 2826 rf = rt3090_rf_read(sc, 2); 2827 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2828 2829 /* set reference current control to 0.33 mA */ 2830 rf = rt3090_rf_read(sc, 22); 2831 rf &= ~RT3593_CP_IC_MASK; 2832 rf |= 1 << RT3593_CP_IC_SHIFT; 2833 rt3090_rf_write(sc, 22, rf); 2834 2835 /* enable RX CTB */ 2836 rf = rt3090_rf_read(sc, 46); 2837 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2838 2839 rf = rt3090_rf_read(sc, 20); 2840 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2841 rt3090_rf_write(sc, 20, rf); 2842 } else { 2843 /* enable RF block */ 2844 rf = rt3090_rf_read(sc, 1); 2845 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2846 2847 /* enable VCO bias current control */ 2848 rf = rt3090_rf_read(sc, 7); 2849 rt3090_rf_write(sc, 7, rf | 0x30); 2850 2851 rf = rt3090_rf_read(sc, 9); 2852 rt3090_rf_write(sc, 9, rf | 0x0e); 2853 2854 /* enable RX CTB */ 2855 rf = rt3090_rf_read(sc, 21); 2856 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2857 2858 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2859 rf = rt3090_rf_read(sc, 27); 2860 rf &= ~0x77; 2861 if (sc->mac_rev < 0x0211) 2862 rf |= 0x03; 2863 rt3090_rf_write(sc, 27, rf); 2864 } 2865 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2866 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2867 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2868 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2869 } 2870 } 2871 2872 static void 2873 rt5390_rf_wakeup(struct rt2860_softc *sc) 2874 { 2875 uint32_t tmp; 2876 uint8_t rf; 2877 2878 rf = rt3090_rf_read(sc, 1); 2879 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2880 RT3070_TX0_PD; 2881 if (sc->mac_ver == 0x5392) 2882 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2883 rt3090_rf_write(sc, 1, rf); 2884 2885 rf = rt3090_rf_read(sc, 6); 2886 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2887 if (sc->mac_ver == 0x5390) 2888 rf &= ~RT3593_VCO_IC; 2889 rt3090_rf_write(sc, 6, rf); 2890 2891 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2892 2893 rf = rt3090_rf_read(sc, 22); 2894 rf = (rf & ~0xe0) | 0x20; 2895 rt3090_rf_write(sc, 22, rf); 2896 2897 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2898 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2899 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2900 2901 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2902 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2903 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2904 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2905 } 2906 } 2907 2908 static int 2909 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2910 uint8_t *val) 2911 { 2912 uint8_t rf22, rf24; 2913 uint8_t bbp55_pb, bbp55_sb, delta; 2914 int ntries; 2915 2916 /* program filter */ 2917 rf24 = rt3090_rf_read(sc, 24); 2918 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2919 rt3090_rf_write(sc, 24, rf24); 2920 2921 /* enable baseband loopback mode */ 2922 rf22 = rt3090_rf_read(sc, 22); 2923 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2924 2925 /* set power and frequency of passband test tone */ 2926 rt2860_mcu_bbp_write(sc, 24, 0x00); 2927 for (ntries = 0; ntries < 100; ntries++) { 2928 /* transmit test tone */ 2929 rt2860_mcu_bbp_write(sc, 25, 0x90); 2930 DELAY(1000); 2931 /* read received power */ 2932 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2933 if (bbp55_pb != 0) 2934 break; 2935 } 2936 if (ntries == 100) 2937 return (ETIMEDOUT); 2938 2939 /* set power and frequency of stopband test tone */ 2940 rt2860_mcu_bbp_write(sc, 24, 0x06); 2941 for (ntries = 0; ntries < 100; ntries++) { 2942 /* transmit test tone */ 2943 rt2860_mcu_bbp_write(sc, 25, 0x90); 2944 DELAY(1000); 2945 /* read received power */ 2946 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2947 2948 delta = bbp55_pb - bbp55_sb; 2949 if (delta > target) 2950 break; 2951 2952 /* reprogram filter */ 2953 rf24++; 2954 rt3090_rf_write(sc, 24, rf24); 2955 } 2956 if (ntries < 100) { 2957 if (rf24 != init) 2958 rf24--; /* backtrack */ 2959 *val = rf24; 2960 rt3090_rf_write(sc, 24, rf24); 2961 } 2962 2963 /* restore initial state */ 2964 rt2860_mcu_bbp_write(sc, 24, 0x00); 2965 2966 /* disable baseband loopback mode */ 2967 rf22 = rt3090_rf_read(sc, 22); 2968 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2969 2970 return (0); 2971 } 2972 2973 static void 2974 rt3090_rf_setup(struct rt2860_softc *sc) 2975 { 2976 uint8_t bbp; 2977 int i; 2978 2979 if (sc->mac_rev >= 0x0211) { 2980 /* enable DC filter */ 2981 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2982 2983 /* improve power consumption */ 2984 bbp = rt2860_mcu_bbp_read(sc, 31); 2985 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2986 } 2987 2988 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2989 if (sc->mac_rev < 0x0211) { 2990 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2991 sc->patch_dac ? 0x2c : 0x0f); 2992 } else 2993 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2994 2995 /* initialize RF registers from ROM */ 2996 if (sc->mac_ver < 0x5390) { 2997 for (i = 0; i < 10; i++) { 2998 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 2999 continue; 3000 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3001 } 3002 } 3003 } 3004 3005 static void 3006 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3007 { 3008 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3009 which | (sc->leds & 0x7f), 0); 3010 } 3011 3012 /* 3013 * Hardware has a general-purpose programmable timer interrupt that can 3014 * periodically raise MAC_INT_4. 3015 */ 3016 static void 3017 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3018 { 3019 uint32_t tmp; 3020 3021 /* disable GP timer before reprogramming it */ 3022 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3023 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3024 3025 if (ms == 0) 3026 return; 3027 3028 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3029 ms *= 16; /* Unit: 64us */ 3030 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3031 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3032 3033 /* enable GP timer */ 3034 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3035 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3036 } 3037 3038 static void 3039 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3040 { 3041 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3042 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3043 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3044 bssid[4] | bssid[5] << 8); 3045 } 3046 3047 static void 3048 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3049 { 3050 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3051 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3052 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3053 addr[4] | addr[5] << 8 | 0xff << 16); 3054 } 3055 3056 static void 3057 rt2860_updateslot(struct ieee80211com *ic) 3058 { 3059 struct rt2860_softc *sc = ic->ic_softc; 3060 uint32_t tmp; 3061 3062 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3063 tmp &= ~0xff; 3064 tmp |= IEEE80211_GET_SLOTTIME(ic); 3065 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3066 } 3067 3068 static void 3069 rt2860_updateprot(struct rt2860_softc *sc) 3070 { 3071 struct ieee80211com *ic = &sc->sc_ic; 3072 uint32_t tmp; 3073 3074 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3075 /* setup protection frame rate (MCS code) */ 3076 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3077 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3078 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3079 3080 /* CCK frames don't require protection */ 3081 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3082 3083 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3084 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3085 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3086 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3087 tmp |= RT2860_PROT_CTRL_CTS; 3088 } 3089 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3090 } 3091 3092 static void 3093 rt2860_update_promisc(struct ieee80211com *ic) 3094 { 3095 struct rt2860_softc *sc = ic->ic_softc; 3096 uint32_t tmp; 3097 3098 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3099 tmp &= ~RT2860_DROP_NOT_MYBSS; 3100 if (ic->ic_promisc == 0) 3101 tmp |= RT2860_DROP_NOT_MYBSS; 3102 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3103 } 3104 3105 static int 3106 rt2860_updateedca(struct ieee80211com *ic) 3107 { 3108 struct rt2860_softc *sc = ic->ic_softc; 3109 struct chanAccParams chp; 3110 const struct wmeParams *wmep; 3111 int aci; 3112 3113 ieee80211_wme_ic_getparams(ic, &chp); 3114 3115 wmep = chp.cap_wmeParams; 3116 3117 /* update MAC TX configuration registers */ 3118 for (aci = 0; aci < WME_NUM_AC; aci++) { 3119 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3120 wmep[aci].wmep_logcwmax << 16 | 3121 wmep[aci].wmep_logcwmin << 12 | 3122 wmep[aci].wmep_aifsn << 8 | 3123 wmep[aci].wmep_txopLimit); 3124 } 3125 3126 /* update SCH/DMA registers too */ 3127 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3128 wmep[WME_AC_VO].wmep_aifsn << 12 | 3129 wmep[WME_AC_VI].wmep_aifsn << 8 | 3130 wmep[WME_AC_BK].wmep_aifsn << 4 | 3131 wmep[WME_AC_BE].wmep_aifsn); 3132 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3133 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3134 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3135 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3136 wmep[WME_AC_BE].wmep_logcwmin); 3137 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3138 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3139 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3140 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3141 wmep[WME_AC_BE].wmep_logcwmax); 3142 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3143 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3144 wmep[WME_AC_BE].wmep_txopLimit); 3145 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3146 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3147 wmep[WME_AC_VI].wmep_txopLimit); 3148 3149 return 0; 3150 } 3151 3152 #ifdef HW_CRYPTO 3153 static int 3154 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3155 struct ieee80211_key *k) 3156 { 3157 struct rt2860_softc *sc = ic->ic_softc; 3158 bus_size_t base; 3159 uint32_t attr; 3160 uint8_t mode, wcid, iv[8]; 3161 3162 /* defer setting of WEP keys until interface is brought up */ 3163 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3164 (IFF_UP | IFF_RUNNING)) 3165 return 0; 3166 3167 /* map net80211 cipher to RT2860 security mode */ 3168 switch (k->k_cipher) { 3169 case IEEE80211_CIPHER_WEP40: 3170 mode = RT2860_MODE_WEP40; 3171 break; 3172 case IEEE80211_CIPHER_WEP104: 3173 mode = RT2860_MODE_WEP104; 3174 break; 3175 case IEEE80211_CIPHER_TKIP: 3176 mode = RT2860_MODE_TKIP; 3177 break; 3178 case IEEE80211_CIPHER_CCMP: 3179 mode = RT2860_MODE_AES_CCMP; 3180 break; 3181 default: 3182 return EINVAL; 3183 } 3184 3185 if (k->k_flags & IEEE80211_KEY_GROUP) { 3186 wcid = 0; /* NB: update WCID0 for group keys */ 3187 base = RT2860_SKEY(0, k->k_id); 3188 } else { 3189 wcid = ((struct rt2860_node *)ni)->wcid; 3190 base = RT2860_PKEY(wcid); 3191 } 3192 3193 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3194 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3195 #ifndef IEEE80211_STA_ONLY 3196 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3197 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3198 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3199 } else 3200 #endif 3201 { 3202 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3203 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3204 } 3205 } else 3206 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3207 3208 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3209 (k->k_flags & IEEE80211_KEY_TX)) { 3210 /* set initial packet number in IV+EIV */ 3211 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3212 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3213 uint32_t val = arc4random(); 3214 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3215 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3216 val += 0x000100; 3217 iv[0] = val; 3218 iv[1] = val >> 8; 3219 iv[2] = val >> 16; 3220 iv[3] = k->k_id << 6; 3221 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3222 } else { 3223 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3224 iv[0] = k->k_tsc >> 8; 3225 iv[1] = (iv[0] | 0x20) & 0x7f; 3226 iv[2] = k->k_tsc; 3227 } else /* CCMP */ { 3228 iv[0] = k->k_tsc; 3229 iv[1] = k->k_tsc >> 8; 3230 iv[2] = 0; 3231 } 3232 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3233 iv[4] = k->k_tsc >> 16; 3234 iv[5] = k->k_tsc >> 24; 3235 iv[6] = k->k_tsc >> 32; 3236 iv[7] = k->k_tsc >> 40; 3237 } 3238 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3239 } 3240 3241 if (k->k_flags & IEEE80211_KEY_GROUP) { 3242 /* install group key */ 3243 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3244 attr &= ~(0xf << (k->k_id * 4)); 3245 attr |= mode << (k->k_id * 4); 3246 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3247 } else { 3248 /* install pairwise key */ 3249 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3250 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3251 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3252 } 3253 return 0; 3254 } 3255 3256 static void 3257 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3258 struct ieee80211_key *k) 3259 { 3260 struct rt2860_softc *sc = ic->ic_softc; 3261 uint32_t attr; 3262 uint8_t wcid; 3263 3264 if (k->k_flags & IEEE80211_KEY_GROUP) { 3265 /* remove group key */ 3266 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3267 attr &= ~(0xf << (k->k_id * 4)); 3268 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3269 3270 } else { 3271 /* remove pairwise key */ 3272 wcid = ((struct rt2860_node *)ni)->wcid; 3273 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3274 attr &= ~0xf; 3275 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3276 } 3277 } 3278 #endif 3279 3280 static int8_t 3281 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3282 { 3283 struct ieee80211com *ic = &sc->sc_ic; 3284 struct ieee80211_channel *c = ic->ic_curchan; 3285 int delta; 3286 3287 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3288 u_int chan = ieee80211_chan2ieee(ic, c); 3289 delta = sc->rssi_5ghz[rxchain]; 3290 3291 /* determine channel group */ 3292 if (chan <= 64) 3293 delta -= sc->lna[1]; 3294 else if (chan <= 128) 3295 delta -= sc->lna[2]; 3296 else 3297 delta -= sc->lna[3]; 3298 } else 3299 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3300 3301 return -12 - delta - rssi; 3302 } 3303 3304 /* 3305 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3306 * Used to adjust per-rate Tx power registers. 3307 */ 3308 static __inline uint32_t 3309 b4inc(uint32_t b32, int8_t delta) 3310 { 3311 int8_t i, b4; 3312 3313 for (i = 0; i < 8; i++) { 3314 b4 = b32 & 0xf; 3315 b4 += delta; 3316 if (b4 < 0) 3317 b4 = 0; 3318 else if (b4 > 0xf) 3319 b4 = 0xf; 3320 b32 = b32 >> 4 | (uint32_t)b4 << 28; 3321 } 3322 return b32; 3323 } 3324 3325 static const char * 3326 rt2860_get_rf(uint16_t rev) 3327 { 3328 switch (rev) { 3329 case RT2860_RF_2820: return "RT2820"; 3330 case RT2860_RF_2850: return "RT2850"; 3331 case RT2860_RF_2720: return "RT2720"; 3332 case RT2860_RF_2750: return "RT2750"; 3333 case RT3070_RF_3020: return "RT3020"; 3334 case RT3070_RF_2020: return "RT2020"; 3335 case RT3070_RF_3021: return "RT3021"; 3336 case RT3070_RF_3022: return "RT3022"; 3337 case RT3070_RF_3052: return "RT3052"; 3338 case RT3070_RF_3320: return "RT3320"; 3339 case RT3070_RF_3053: return "RT3053"; 3340 case RT5390_RF_5360: return "RT5360"; 3341 case RT5390_RF_5390: return "RT5390"; 3342 default: return "unknown"; 3343 } 3344 } 3345 3346 static int 3347 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3348 { 3349 int8_t delta_2ghz, delta_5ghz; 3350 uint32_t tmp; 3351 uint16_t val; 3352 int ridx, ant, i; 3353 3354 /* check whether the ROM is eFUSE ROM or EEPROM */ 3355 sc->sc_srom_read = rt2860_eeprom_read_2; 3356 if (sc->mac_ver >= 0x3071) { 3357 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3358 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3359 if (tmp & RT3070_SEL_EFUSE) 3360 sc->sc_srom_read = rt3090_efuse_read_2; 3361 } 3362 3363 #ifdef RAL_DEBUG 3364 /* read EEPROM version */ 3365 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3366 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3367 #endif 3368 3369 /* read MAC address */ 3370 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3371 macaddr[0] = val & 0xff; 3372 macaddr[1] = val >> 8; 3373 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3374 macaddr[2] = val & 0xff; 3375 macaddr[3] = val >> 8; 3376 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3377 macaddr[4] = val & 0xff; 3378 macaddr[5] = val >> 8; 3379 3380 #ifdef RAL_DEBUG 3381 /* read country code */ 3382 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3383 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3384 #endif 3385 3386 /* read vendor BBP settings */ 3387 for (i = 0; i < 8; i++) { 3388 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3389 sc->bbp[i].val = val & 0xff; 3390 sc->bbp[i].reg = val >> 8; 3391 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3392 } 3393 if (sc->mac_ver >= 0x3071) { 3394 /* read vendor RF settings */ 3395 for (i = 0; i < 10; i++) { 3396 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3397 sc->rf[i].val = val & 0xff; 3398 sc->rf[i].reg = val >> 8; 3399 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3400 sc->rf[i].val)); 3401 } 3402 } 3403 3404 /* read RF frequency offset from EEPROM */ 3405 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3406 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3407 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3408 if ((val >> 8) != 0xff) { 3409 /* read LEDs operating mode */ 3410 sc->leds = val >> 8; 3411 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3412 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3413 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3414 } else { 3415 /* broken EEPROM, use default settings */ 3416 sc->leds = 0x01; 3417 sc->led[0] = 0x5555; 3418 sc->led[1] = 0x2221; 3419 sc->led[2] = 0xa9f8; 3420 } 3421 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3422 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3423 3424 /* read RF information */ 3425 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3426 if (sc->mac_ver >= 0x5390) 3427 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3428 else 3429 sc->rf_rev = (val >> 8) & 0xf; 3430 sc->ntxchains = (val >> 4) & 0xf; 3431 sc->nrxchains = val & 0xf; 3432 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3433 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3434 3435 /* check if RF supports automatic Tx access gain control */ 3436 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3437 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3438 /* check if driver should patch the DAC issue */ 3439 if ((val >> 8) != 0xff) 3440 sc->patch_dac = (val >> 15) & 1; 3441 if ((val & 0xff) != 0xff) { 3442 sc->ext_5ghz_lna = (val >> 3) & 1; 3443 sc->ext_2ghz_lna = (val >> 2) & 1; 3444 /* check if RF supports automatic Tx access gain control */ 3445 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3446 /* check if we have a hardware radio switch */ 3447 sc->rfswitch = val & 1; 3448 } 3449 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3450 /* read PCIe power save level */ 3451 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3452 if ((val & 0xff) != 0xff) { 3453 sc->pslevel = val & 0x3; 3454 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3455 if ((val & 0xff80) != 0x9280) 3456 sc->pslevel = MIN(sc->pslevel, 1); 3457 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3458 } 3459 } 3460 3461 /* read power settings for 2GHz channels */ 3462 for (i = 0; i < 14; i += 2) { 3463 val = rt2860_srom_read(sc, 3464 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3465 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3466 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3467 3468 if (sc->mac_ver != 0x5390) { 3469 val = rt2860_srom_read(sc, 3470 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3471 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3472 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3473 } 3474 } 3475 /* fix broken Tx power entries */ 3476 for (i = 0; i < 14; i++) { 3477 if (sc->txpow1[i] < 0 || 3478 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3479 sc->txpow1[i] = 5; 3480 if (sc->mac_ver != 0x5390) { 3481 if (sc->txpow2[i] < 0 || 3482 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3483 sc->txpow2[i] = 5; 3484 } 3485 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3486 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3487 } 3488 /* read power settings for 5GHz channels */ 3489 for (i = 0; i < 40; i += 2) { 3490 val = rt2860_srom_read(sc, 3491 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3492 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3493 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3494 3495 val = rt2860_srom_read(sc, 3496 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3497 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3498 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3499 } 3500 /* fix broken Tx power entries */ 3501 for (i = 0; i < 40; i++) { 3502 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3503 sc->txpow1[14 + i] = 5; 3504 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3505 sc->txpow2[14 + i] = 5; 3506 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3507 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3508 sc->txpow2[14 + i])); 3509 } 3510 3511 /* read Tx power compensation for each Tx rate */ 3512 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3513 delta_2ghz = delta_5ghz = 0; 3514 if ((val & 0xff) != 0xff && (val & 0x80)) { 3515 delta_2ghz = val & 0xf; 3516 if (!(val & 0x40)) /* negative number */ 3517 delta_2ghz = -delta_2ghz; 3518 } 3519 val >>= 8; 3520 if ((val & 0xff) != 0xff && (val & 0x80)) { 3521 delta_5ghz = val & 0xf; 3522 if (!(val & 0x40)) /* negative number */ 3523 delta_5ghz = -delta_5ghz; 3524 } 3525 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3526 delta_2ghz, delta_5ghz)); 3527 3528 for (ridx = 0; ridx < 5; ridx++) { 3529 uint32_t reg; 3530 3531 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3532 reg = val; 3533 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3534 reg |= (uint32_t)val << 16; 3535 3536 sc->txpow20mhz[ridx] = reg; 3537 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3538 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3539 3540 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3541 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3542 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3543 } 3544 3545 /* read factory-calibrated samples for temperature compensation */ 3546 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3547 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3548 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3549 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3550 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3551 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3552 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3553 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3554 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3555 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3556 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3557 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3558 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3559 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3560 sc->step_2ghz = val >> 8; 3561 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3562 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3563 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3564 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3565 sc->tssi_2ghz[8], sc->step_2ghz)); 3566 /* check that ref value is correct, otherwise disable calibration */ 3567 if (sc->tssi_2ghz[4] == 0xff) 3568 sc->calib_2ghz = 0; 3569 3570 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3571 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3572 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3573 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3574 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3575 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3576 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3577 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3578 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3579 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3580 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3581 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3582 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3583 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3584 sc->step_5ghz = val >> 8; 3585 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3586 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3587 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3588 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3589 sc->tssi_5ghz[8], sc->step_5ghz)); 3590 /* check that ref value is correct, otherwise disable calibration */ 3591 if (sc->tssi_5ghz[4] == 0xff) 3592 sc->calib_5ghz = 0; 3593 3594 /* read RSSI offsets and LNA gains from EEPROM */ 3595 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3596 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3597 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3598 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3599 if (sc->mac_ver >= 0x3071) { 3600 /* 3601 * On RT3090 chips (limited to 2 Rx chains), this ROM 3602 * field contains the Tx mixer gain for the 2GHz band. 3603 */ 3604 if ((val & 0xff) != 0xff) 3605 sc->txmixgain_2ghz = val & 0x7; 3606 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3607 } else 3608 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3609 sc->lna[2] = val >> 8; /* channel group 2 */ 3610 3611 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3612 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3613 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3614 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3615 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3616 sc->lna[3] = val >> 8; /* channel group 3 */ 3617 3618 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3619 if (sc->mac_ver >= 0x3071) 3620 sc->lna[0] = RT3090_DEF_LNA; 3621 else /* channel group 0 */ 3622 sc->lna[0] = val & 0xff; 3623 sc->lna[1] = val >> 8; /* channel group 1 */ 3624 3625 /* fix broken 5GHz LNA entries */ 3626 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3627 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3628 sc->lna[2] = sc->lna[1]; 3629 } 3630 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3631 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3632 sc->lna[3] = sc->lna[1]; 3633 } 3634 3635 /* fix broken RSSI offset entries */ 3636 for (ant = 0; ant < 3; ant++) { 3637 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3638 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3639 ant + 1, sc->rssi_2ghz[ant])); 3640 sc->rssi_2ghz[ant] = 0; 3641 } 3642 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3643 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3644 ant + 1, sc->rssi_5ghz[ant])); 3645 sc->rssi_5ghz[ant] = 0; 3646 } 3647 } 3648 3649 return 0; 3650 } 3651 3652 static int 3653 rt2860_bbp_init(struct rt2860_softc *sc) 3654 { 3655 int i, ntries; 3656 3657 /* wait for BBP to wake up */ 3658 for (ntries = 0; ntries < 20; ntries++) { 3659 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3660 if (bbp0 != 0 && bbp0 != 0xff) 3661 break; 3662 } 3663 if (ntries == 20) { 3664 device_printf(sc->sc_dev, 3665 "timeout waiting for BBP to wake up\n"); 3666 return (ETIMEDOUT); 3667 } 3668 3669 /* initialize BBP registers to default values */ 3670 if (sc->mac_ver >= 0x5390) 3671 rt5390_bbp_init(sc); 3672 else { 3673 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3674 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3675 rt2860_def_bbp[i].val); 3676 } 3677 } 3678 3679 /* fix BBP84 for RT2860E */ 3680 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3681 rt2860_mcu_bbp_write(sc, 84, 0x19); 3682 3683 if (sc->mac_ver >= 0x3071) { 3684 rt2860_mcu_bbp_write(sc, 79, 0x13); 3685 rt2860_mcu_bbp_write(sc, 80, 0x05); 3686 rt2860_mcu_bbp_write(sc, 81, 0x33); 3687 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3688 rt2860_mcu_bbp_write(sc, 69, 0x16); 3689 rt2860_mcu_bbp_write(sc, 73, 0x12); 3690 } 3691 3692 return 0; 3693 } 3694 3695 static void 3696 rt5390_bbp_init(struct rt2860_softc *sc) 3697 { 3698 uint8_t bbp; 3699 int i; 3700 3701 /* Apply maximum likelihood detection for 2 stream case. */ 3702 if (sc->nrxchains > 1) { 3703 bbp = rt2860_mcu_bbp_read(sc, 105); 3704 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3705 } 3706 3707 /* Avoid data lost and CRC error. */ 3708 bbp = rt2860_mcu_bbp_read(sc, 4); 3709 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3710 3711 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3712 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3713 rt5390_def_bbp[i].val); 3714 } 3715 3716 if (sc->mac_ver == 0x5392) { 3717 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3718 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3719 rt2860_mcu_bbp_write(sc, 98, 0x12); 3720 rt2860_mcu_bbp_write(sc, 106, 0x05); 3721 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3722 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3723 } 3724 3725 bbp = rt2860_mcu_bbp_read(sc, 152); 3726 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3727 3728 /* Disable hardware antenna diversity. */ 3729 if (sc->mac_ver == 0x5390) 3730 rt2860_mcu_bbp_write(sc, 154, 0); 3731 } 3732 3733 static int 3734 rt2860_txrx_enable(struct rt2860_softc *sc) 3735 { 3736 struct ieee80211com *ic = &sc->sc_ic; 3737 uint32_t tmp; 3738 int ntries; 3739 3740 /* enable Tx/Rx DMA engine */ 3741 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3742 RAL_BARRIER_READ_WRITE(sc); 3743 for (ntries = 0; ntries < 200; ntries++) { 3744 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3745 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3746 break; 3747 DELAY(1000); 3748 } 3749 if (ntries == 200) { 3750 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3751 return ETIMEDOUT; 3752 } 3753 3754 DELAY(50); 3755 3756 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3757 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3758 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3759 3760 /* set Rx filter */ 3761 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3762 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3763 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3764 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3765 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3766 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3767 if (ic->ic_opmode == IEEE80211_M_STA) 3768 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3769 } 3770 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3771 3772 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3773 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3774 3775 return 0; 3776 } 3777 3778 static void 3779 rt2860_init(void *arg) 3780 { 3781 struct rt2860_softc *sc = arg; 3782 struct ieee80211com *ic = &sc->sc_ic; 3783 3784 RAL_LOCK(sc); 3785 rt2860_init_locked(sc); 3786 RAL_UNLOCK(sc); 3787 3788 if (sc->sc_flags & RT2860_RUNNING) 3789 ieee80211_start_all(ic); 3790 } 3791 3792 static void 3793 rt2860_init_locked(struct rt2860_softc *sc) 3794 { 3795 struct ieee80211com *ic = &sc->sc_ic; 3796 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3797 uint32_t tmp; 3798 uint8_t bbp1, bbp3; 3799 int i, qid, ridx, ntries, error; 3800 3801 RAL_LOCK_ASSERT(sc); 3802 3803 if (sc->rfswitch) { 3804 /* hardware has a radio switch on GPIO pin 2 */ 3805 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3806 device_printf(sc->sc_dev, 3807 "radio is disabled by hardware switch\n"); 3808 #ifdef notyet 3809 rt2860_stop_locked(sc); 3810 return; 3811 #endif 3812 } 3813 } 3814 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3815 3816 /* disable DMA */ 3817 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3818 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3819 RT2860_TX_DMA_EN); 3820 tmp |= RT2860_TX_WB_DDONE; 3821 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3822 3823 /* reset DMA indexes */ 3824 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3825 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3826 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3827 3828 /* PBF hardware reset */ 3829 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3830 RAL_BARRIER_WRITE(sc); 3831 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3832 3833 if ((error = rt2860_load_microcode(sc)) != 0) { 3834 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3835 rt2860_stop_locked(sc); 3836 return; 3837 } 3838 3839 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3840 3841 /* init Tx power for all Tx rates (from EEPROM) */ 3842 for (ridx = 0; ridx < 5; ridx++) { 3843 if (sc->txpow20mhz[ridx] == 0xffffffff) 3844 continue; 3845 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3846 } 3847 3848 for (ntries = 0; ntries < 100; ntries++) { 3849 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3850 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3851 break; 3852 DELAY(1000); 3853 } 3854 if (ntries == 100) { 3855 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3856 rt2860_stop_locked(sc); 3857 return; 3858 } 3859 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3860 RT2860_TX_DMA_EN); 3861 tmp |= RT2860_TX_WB_DDONE; 3862 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3863 3864 /* reset Rx ring and all 6 Tx rings */ 3865 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3866 3867 /* PBF hardware reset */ 3868 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3869 RAL_BARRIER_WRITE(sc); 3870 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3871 3872 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3873 3874 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3875 RAL_BARRIER_WRITE(sc); 3876 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3877 3878 for (i = 0; i < nitems(rt2860_def_mac); i++) 3879 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3880 if (sc->mac_ver >= 0x5390) 3881 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3882 else if (sc->mac_ver >= 0x3071) { 3883 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3884 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3885 4 << RT2860_DLY_PAPE_EN_SHIFT); 3886 } 3887 3888 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3889 sc->sc_flags |= RT2860_PCIE; 3890 /* PCIe has different clock cycle count than PCI */ 3891 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3892 tmp = (tmp & ~0xff) | 0x7d; 3893 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3894 } 3895 3896 /* wait while MAC is busy */ 3897 for (ntries = 0; ntries < 100; ntries++) { 3898 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3899 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3900 break; 3901 DELAY(1000); 3902 } 3903 if (ntries == 100) { 3904 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3905 rt2860_stop_locked(sc); 3906 return; 3907 } 3908 3909 /* clear Host to MCU mailbox */ 3910 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3911 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3912 3913 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3914 DELAY(1000); 3915 3916 if ((error = rt2860_bbp_init(sc)) != 0) { 3917 rt2860_stop_locked(sc); 3918 return; 3919 } 3920 3921 /* clear RX WCID search table */ 3922 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3923 /* clear pairwise key table */ 3924 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3925 /* clear IV/EIV table */ 3926 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3927 /* clear WCID attribute table */ 3928 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3929 /* clear shared key table */ 3930 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3931 /* clear shared key mode */ 3932 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3933 3934 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3935 for (qid = 0; qid < 6; qid++) { 3936 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3937 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3938 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3939 } 3940 3941 /* init Rx ring */ 3942 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3943 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3944 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3945 3946 /* setup maximum buffer sizes */ 3947 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3948 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3949 3950 for (ntries = 0; ntries < 100; ntries++) { 3951 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3952 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3953 break; 3954 DELAY(1000); 3955 } 3956 if (ntries == 100) { 3957 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3958 rt2860_stop_locked(sc); 3959 return; 3960 } 3961 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3962 RT2860_TX_DMA_EN); 3963 tmp |= RT2860_TX_WB_DDONE; 3964 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3965 3966 /* disable interrupts mitigation */ 3967 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3968 3969 /* write vendor-specific BBP values (from EEPROM) */ 3970 for (i = 0; i < 8; i++) { 3971 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3972 continue; 3973 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3974 } 3975 3976 /* select Main antenna for 1T1R devices */ 3977 if (sc->rf_rev == RT3070_RF_2020 || 3978 sc->rf_rev == RT3070_RF_3020 || 3979 sc->rf_rev == RT3070_RF_3320 || 3980 sc->mac_ver == 0x5390) 3981 rt3090_set_rx_antenna(sc, 0); 3982 3983 /* send LEDs operating mode to microcontroller */ 3984 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3985 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3986 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3987 3988 if (sc->mac_ver >= 0x5390) 3989 rt5390_rf_init(sc); 3990 else if (sc->mac_ver >= 0x3071) { 3991 if ((error = rt3090_rf_init(sc)) != 0) { 3992 rt2860_stop_locked(sc); 3993 return; 3994 } 3995 } 3996 3997 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3998 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 3999 4000 if (sc->mac_ver >= 0x5390) 4001 rt5390_rf_wakeup(sc); 4002 else if (sc->mac_ver >= 0x3071) 4003 rt3090_rf_wakeup(sc); 4004 4005 /* disable non-existing Rx chains */ 4006 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4007 bbp3 &= ~(1 << 3 | 1 << 4); 4008 if (sc->nrxchains == 2) 4009 bbp3 |= 1 << 3; 4010 else if (sc->nrxchains == 3) 4011 bbp3 |= 1 << 4; 4012 rt2860_mcu_bbp_write(sc, 3, bbp3); 4013 4014 /* disable non-existing Tx chains */ 4015 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4016 if (sc->ntxchains == 1) 4017 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4018 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4019 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4020 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4021 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4022 rt2860_mcu_bbp_write(sc, 1, bbp1); 4023 4024 if (sc->mac_ver >= 0x3071) 4025 rt3090_rf_setup(sc); 4026 4027 /* select default channel */ 4028 rt2860_switch_chan(sc, ic->ic_curchan); 4029 4030 /* reset RF from MCU */ 4031 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4032 4033 /* set RTS threshold */ 4034 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4035 tmp &= ~0xffff00; 4036 tmp |= IEEE80211_RTS_DEFAULT << 8; 4037 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4038 4039 /* setup initial protection mode */ 4040 rt2860_updateprot(sc); 4041 4042 /* turn radio LED on */ 4043 rt2860_set_leds(sc, RT2860_LED_RADIO); 4044 4045 /* enable Tx/Rx DMA engine */ 4046 if ((error = rt2860_txrx_enable(sc)) != 0) { 4047 rt2860_stop_locked(sc); 4048 return; 4049 } 4050 4051 /* clear pending interrupts */ 4052 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4053 /* enable interrupts */ 4054 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4055 4056 if (sc->sc_flags & RT2860_ADVANCED_PS) 4057 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4058 4059 sc->sc_flags |= RT2860_RUNNING; 4060 4061 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4062 } 4063 4064 static void 4065 rt2860_stop(void *arg) 4066 { 4067 struct rt2860_softc *sc = arg; 4068 4069 RAL_LOCK(sc); 4070 rt2860_stop_locked(sc); 4071 RAL_UNLOCK(sc); 4072 } 4073 4074 static void 4075 rt2860_stop_locked(struct rt2860_softc *sc) 4076 { 4077 uint32_t tmp; 4078 int qid; 4079 4080 if (sc->sc_flags & RT2860_RUNNING) 4081 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4082 4083 callout_stop(&sc->watchdog_ch); 4084 sc->sc_tx_timer = 0; 4085 sc->sc_flags &= ~RT2860_RUNNING; 4086 4087 /* disable interrupts */ 4088 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4089 4090 /* disable GP timer */ 4091 rt2860_set_gp_timer(sc, 0); 4092 4093 /* disable Rx */ 4094 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4095 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4096 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4097 4098 /* reset adapter */ 4099 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4100 RAL_BARRIER_WRITE(sc); 4101 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4102 4103 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4104 sc->qfullmsk = 0; 4105 for (qid = 0; qid < 6; qid++) 4106 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4107 rt2860_reset_rx_ring(sc, &sc->rxq); 4108 } 4109 4110 int 4111 rt2860_load_microcode(struct rt2860_softc *sc) 4112 { 4113 const struct firmware *fp; 4114 int ntries, error; 4115 4116 RAL_LOCK_ASSERT(sc); 4117 4118 RAL_UNLOCK(sc); 4119 fp = firmware_get("rt2860fw"); 4120 RAL_LOCK(sc); 4121 if (fp == NULL) { 4122 device_printf(sc->sc_dev, 4123 "unable to receive rt2860fw firmware image\n"); 4124 return EINVAL; 4125 } 4126 4127 /* set "host program ram write selection" bit */ 4128 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4129 /* write microcode image */ 4130 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4131 /* kick microcontroller unit */ 4132 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4133 RAL_BARRIER_WRITE(sc); 4134 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4135 4136 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4137 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4138 4139 /* wait until microcontroller is ready */ 4140 RAL_BARRIER_READ_WRITE(sc); 4141 for (ntries = 0; ntries < 1000; ntries++) { 4142 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4143 break; 4144 DELAY(1000); 4145 } 4146 if (ntries == 1000) { 4147 device_printf(sc->sc_dev, 4148 "timeout waiting for MCU to initialize\n"); 4149 error = ETIMEDOUT; 4150 } else 4151 error = 0; 4152 4153 firmware_put(fp, FIRMWARE_UNLOAD); 4154 return error; 4155 } 4156 4157 /* 4158 * This function is called periodically to adjust Tx power based on 4159 * temperature variation. 4160 */ 4161 #ifdef NOT_YET 4162 static void 4163 rt2860_calib(struct rt2860_softc *sc) 4164 { 4165 struct ieee80211com *ic = &sc->sc_ic; 4166 const uint8_t *tssi; 4167 uint8_t step, bbp49; 4168 int8_t ridx, d; 4169 4170 /* read current temperature */ 4171 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4172 4173 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4174 tssi = &sc->tssi_2ghz[4]; 4175 step = sc->step_2ghz; 4176 } else { 4177 tssi = &sc->tssi_5ghz[4]; 4178 step = sc->step_5ghz; 4179 } 4180 4181 if (bbp49 < tssi[0]) { /* lower than reference */ 4182 /* use higher Tx power than default */ 4183 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4184 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4185 /* use lower Tx power than default */ 4186 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4187 } else { 4188 /* use default Tx power */ 4189 d = 0; 4190 } 4191 d *= step; 4192 4193 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4194 4195 /* write adjusted Tx power values for each Tx rate */ 4196 for (ridx = 0; ridx < 5; ridx++) { 4197 if (sc->txpow20mhz[ridx] == 0xffffffff) 4198 continue; 4199 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4200 b4inc(sc->txpow20mhz[ridx], d)); 4201 } 4202 } 4203 #endif 4204 4205 static void 4206 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4207 { 4208 uint32_t tmp; 4209 4210 if (aux) { 4211 if (sc->mac_ver == 0x5390) { 4212 rt2860_mcu_bbp_write(sc, 152, 4213 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4214 } else { 4215 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4216 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4217 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4218 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4219 } 4220 } else { 4221 if (sc->mac_ver == 0x5390) { 4222 rt2860_mcu_bbp_write(sc, 152, 4223 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4224 } else { 4225 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4226 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4227 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4228 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4229 } 4230 } 4231 } 4232 4233 static void 4234 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4235 { 4236 struct ieee80211com *ic = &sc->sc_ic; 4237 u_int chan, group; 4238 4239 chan = ieee80211_chan2ieee(ic, c); 4240 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4241 return; 4242 4243 if (sc->mac_ver >= 0x5390) 4244 rt5390_set_chan(sc, chan); 4245 else if (sc->mac_ver >= 0x3071) 4246 rt3090_set_chan(sc, chan); 4247 else 4248 rt2860_set_chan(sc, chan); 4249 4250 /* determine channel group */ 4251 if (chan <= 14) 4252 group = 0; 4253 else if (chan <= 64) 4254 group = 1; 4255 else if (chan <= 128) 4256 group = 2; 4257 else 4258 group = 3; 4259 4260 /* XXX necessary only when group has changed! */ 4261 if (sc->mac_ver < 0x5390) 4262 rt2860_select_chan_group(sc, group); 4263 4264 DELAY(1000); 4265 } 4266 4267 static int 4268 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4269 { 4270 struct ieee80211com *ic = vap->iv_ic; 4271 struct rt2860_txwi txwi; 4272 struct mbuf *m; 4273 int ridx; 4274 4275 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4276 return ENOBUFS; 4277 4278 memset(&txwi, 0, sizeof txwi); 4279 txwi.wcid = 0xff; 4280 txwi.len = htole16(m->m_pkthdr.len); 4281 /* send beacons at the lowest available rate */ 4282 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4283 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4284 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4285 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4286 txwi.phy |= htole16(RT2860_PHY_OFDM); 4287 txwi.txop = RT2860_TX_TXOP_HT; 4288 txwi.flags = RT2860_TX_TS; 4289 txwi.xflags = RT2860_TX_NSEQ; 4290 4291 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4292 (uint8_t *)&txwi, sizeof txwi); 4293 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4294 mtod(m, uint8_t *), m->m_pkthdr.len); 4295 4296 m_freem(m); 4297 4298 return 0; 4299 } 4300 4301 static void 4302 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4303 { 4304 struct ieee80211com *ic = &sc->sc_ic; 4305 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4306 uint32_t tmp; 4307 4308 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4309 4310 tmp &= ~0x1fffff; 4311 tmp |= vap->iv_bss->ni_intval * 16; 4312 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4313 if (vap->iv_opmode == IEEE80211_M_STA) { 4314 /* 4315 * Local TSF is always updated with remote TSF on beacon 4316 * reception. 4317 */ 4318 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4319 } 4320 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4321 vap->iv_opmode == IEEE80211_M_MBSS) { 4322 tmp |= RT2860_BCN_TX_EN; 4323 /* 4324 * Local TSF is updated with remote TSF on beacon reception 4325 * only if the remote TSF is greater than local TSF. 4326 */ 4327 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4328 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4329 tmp |= RT2860_BCN_TX_EN; 4330 /* SYNC with nobody */ 4331 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4332 } 4333 4334 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4335 } 4336