1 /*- 2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860.c,v 1.65 2010/10/23 14:24:54 damien Exp $ 18 */ 19 20 #include <sys/cdefs.h> 21 /*- 22 * Ralink Technology RT2860/RT3090/RT3390/RT3562/RT5390/RT5392 chipset driver 23 * http://www.ralinktech.com/ 24 */ 25 26 #include <sys/param.h> 27 #include <sys/sysctl.h> 28 #include <sys/sockio.h> 29 #include <sys/mbuf.h> 30 #include <sys/kernel.h> 31 #include <sys/socket.h> 32 #include <sys/systm.h> 33 #include <sys/malloc.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/firmware.h> 40 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <sys/rman.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_radiotap.h> 56 #include <net80211/ieee80211_regdomain.h> 57 #include <net80211/ieee80211_ratectl.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/in_var.h> 62 #include <netinet/ip.h> 63 #include <netinet/if_ether.h> 64 65 #include <dev/ral/rt2860reg.h> 66 #include <dev/ral/rt2860var.h> 67 68 #define RAL_DEBUG 69 #ifdef RAL_DEBUG 70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 72 #else 73 #define DPRINTF(x) 74 #define DPRINTFN(n, x) 75 #endif 76 77 static struct ieee80211vap *rt2860_vap_create(struct ieee80211com *, 78 const char [IFNAMSIZ], int, enum ieee80211_opmode, 79 int, const uint8_t [IEEE80211_ADDR_LEN], 80 const uint8_t [IEEE80211_ADDR_LEN]); 81 static void rt2860_vap_delete(struct ieee80211vap *); 82 static void rt2860_dma_map_addr(void *, bus_dma_segment_t *, int, int); 83 static int rt2860_alloc_tx_ring(struct rt2860_softc *, 84 struct rt2860_tx_ring *); 85 static void rt2860_reset_tx_ring(struct rt2860_softc *, 86 struct rt2860_tx_ring *); 87 static void rt2860_free_tx_ring(struct rt2860_softc *, 88 struct rt2860_tx_ring *); 89 static int rt2860_alloc_tx_pool(struct rt2860_softc *); 90 static void rt2860_free_tx_pool(struct rt2860_softc *); 91 static int rt2860_alloc_rx_ring(struct rt2860_softc *, 92 struct rt2860_rx_ring *); 93 static void rt2860_reset_rx_ring(struct rt2860_softc *, 94 struct rt2860_rx_ring *); 95 static void rt2860_free_rx_ring(struct rt2860_softc *, 96 struct rt2860_rx_ring *); 97 static void rt2860_updatestats(struct rt2860_softc *); 98 static void rt2860_newassoc(struct ieee80211_node *, int); 99 static void rt2860_node_free(struct ieee80211_node *); 100 #ifdef IEEE80211_HT 101 static int rt2860_ampdu_rx_start(struct ieee80211com *, 102 struct ieee80211_node *, uint8_t); 103 static void rt2860_ampdu_rx_stop(struct ieee80211com *, 104 struct ieee80211_node *, uint8_t); 105 #endif 106 static int rt2860_newstate(struct ieee80211vap *, enum ieee80211_state, 107 int); 108 static uint16_t rt3090_efuse_read_2(struct rt2860_softc *, uint16_t); 109 static uint16_t rt2860_eeprom_read_2(struct rt2860_softc *, uint16_t); 110 static void rt2860_intr_coherent(struct rt2860_softc *); 111 static void rt2860_drain_stats_fifo(struct rt2860_softc *); 112 static void rt2860_tx_intr(struct rt2860_softc *, int); 113 static void rt2860_rx_intr(struct rt2860_softc *); 114 static void rt2860_tbtt_intr(struct rt2860_softc *); 115 static void rt2860_gp_intr(struct rt2860_softc *); 116 static int rt2860_tx(struct rt2860_softc *, struct mbuf *, 117 struct ieee80211_node *); 118 static int rt2860_raw_xmit(struct ieee80211_node *, struct mbuf *, 119 const struct ieee80211_bpf_params *); 120 static int rt2860_tx_raw(struct rt2860_softc *, struct mbuf *, 121 struct ieee80211_node *, 122 const struct ieee80211_bpf_params *params); 123 static int rt2860_transmit(struct ieee80211com *, struct mbuf *); 124 static void rt2860_start(struct rt2860_softc *); 125 static void rt2860_watchdog(void *); 126 static void rt2860_parent(struct ieee80211com *); 127 static void rt2860_mcu_bbp_write(struct rt2860_softc *, uint8_t, uint8_t); 128 static uint8_t rt2860_mcu_bbp_read(struct rt2860_softc *, uint8_t); 129 static void rt2860_rf_write(struct rt2860_softc *, uint8_t, uint32_t); 130 static uint8_t rt3090_rf_read(struct rt2860_softc *, uint8_t); 131 static void rt3090_rf_write(struct rt2860_softc *, uint8_t, uint8_t); 132 static int rt2860_mcu_cmd(struct rt2860_softc *, uint8_t, uint16_t, int); 133 static void rt2860_enable_mrr(struct rt2860_softc *); 134 static void rt2860_set_txpreamble(struct rt2860_softc *); 135 static void rt2860_set_basicrates(struct rt2860_softc *, 136 const struct ieee80211_rateset *); 137 static void rt2860_scan_start(struct ieee80211com *); 138 static void rt2860_scan_end(struct ieee80211com *); 139 static void rt2860_getradiocaps(struct ieee80211com *, int, int *, 140 struct ieee80211_channel[]); 141 static void rt2860_set_channel(struct ieee80211com *); 142 static void rt2860_select_chan_group(struct rt2860_softc *, int); 143 static void rt2860_set_chan(struct rt2860_softc *, u_int); 144 static void rt3090_set_chan(struct rt2860_softc *, u_int); 145 static void rt5390_set_chan(struct rt2860_softc *, u_int); 146 static int rt3090_rf_init(struct rt2860_softc *); 147 static void rt5390_rf_init(struct rt2860_softc *); 148 static void rt3090_rf_wakeup(struct rt2860_softc *); 149 static void rt5390_rf_wakeup(struct rt2860_softc *); 150 static int rt3090_filter_calib(struct rt2860_softc *, uint8_t, uint8_t, 151 uint8_t *); 152 static void rt3090_rf_setup(struct rt2860_softc *); 153 static void rt2860_set_leds(struct rt2860_softc *, uint16_t); 154 static void rt2860_set_gp_timer(struct rt2860_softc *, int); 155 static void rt2860_set_bssid(struct rt2860_softc *, const uint8_t *); 156 static void rt2860_set_macaddr(struct rt2860_softc *, const uint8_t *); 157 static void rt2860_update_promisc(struct ieee80211com *); 158 static void rt2860_updateslot(struct ieee80211com *); 159 static void rt2860_updateprot(struct rt2860_softc *); 160 static int rt2860_updateedca(struct ieee80211com *); 161 #ifdef HW_CRYPTO 162 static int rt2860_set_key(struct ieee80211com *, struct ieee80211_node *, 163 struct ieee80211_key *); 164 static void rt2860_delete_key(struct ieee80211com *, 165 struct ieee80211_node *, struct ieee80211_key *); 166 #endif 167 static int8_t rt2860_rssi2dbm(struct rt2860_softc *, uint8_t, uint8_t); 168 static const char *rt2860_get_rf(uint16_t); 169 static int rt2860_read_eeprom(struct rt2860_softc *, 170 uint8_t macaddr[IEEE80211_ADDR_LEN]); 171 static int rt2860_bbp_init(struct rt2860_softc *); 172 static void rt5390_bbp_init(struct rt2860_softc *); 173 static int rt2860_txrx_enable(struct rt2860_softc *); 174 static void rt2860_init(void *); 175 static void rt2860_init_locked(struct rt2860_softc *); 176 static void rt2860_stop(void *); 177 static void rt2860_stop_locked(struct rt2860_softc *); 178 static int rt2860_load_microcode(struct rt2860_softc *); 179 #ifdef NOT_YET 180 static void rt2860_calib(struct rt2860_softc *); 181 #endif 182 static void rt3090_set_rx_antenna(struct rt2860_softc *, int); 183 static void rt2860_switch_chan(struct rt2860_softc *, 184 struct ieee80211_channel *); 185 static int rt2860_setup_beacon(struct rt2860_softc *, 186 struct ieee80211vap *); 187 static void rt2860_enable_tsf_sync(struct rt2860_softc *); 188 189 static const struct { 190 uint32_t reg; 191 uint32_t val; 192 } rt2860_def_mac[] = { 193 RT2860_DEF_MAC 194 }; 195 196 static const struct { 197 uint8_t reg; 198 uint8_t val; 199 } rt2860_def_bbp[] = { 200 RT2860_DEF_BBP 201 }, rt5390_def_bbp[] = { 202 RT5390_DEF_BBP 203 }; 204 205 static const struct rfprog { 206 uint8_t chan; 207 uint32_t r1, r2, r3, r4; 208 } rt2860_rf2850[] = { 209 RT2860_RF2850 210 }; 211 212 struct { 213 uint8_t n, r, k; 214 } rt3090_freqs[] = { 215 RT3070_RF3052 216 }; 217 218 static const struct { 219 uint8_t reg; 220 uint8_t val; 221 } rt3090_def_rf[] = { 222 RT3070_DEF_RF 223 }, rt5390_def_rf[] = { 224 RT5390_DEF_RF 225 }, rt5392_def_rf[] = { 226 RT5392_DEF_RF 227 }; 228 229 static const uint8_t rt2860_chan_5ghz[] = 230 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 231 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 232 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173 }; 233 234 int 235 rt2860_attach(device_t dev, int id) 236 { 237 struct rt2860_softc *sc = device_get_softc(dev); 238 struct ieee80211com *ic = &sc->sc_ic; 239 uint32_t tmp; 240 int error, ntries, qid; 241 242 sc->sc_dev = dev; 243 sc->sc_debug = 0; 244 245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 246 MTX_DEF | MTX_RECURSE); 247 248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 249 mbufq_init(&sc->sc_snd, ifqmaxlen); 250 251 /* wait for NIC to initialize */ 252 for (ntries = 0; ntries < 100; ntries++) { 253 tmp = RAL_READ(sc, RT2860_ASIC_VER_ID); 254 if (tmp != 0 && tmp != 0xffffffff) 255 break; 256 DELAY(10); 257 } 258 if (ntries == 100) { 259 device_printf(sc->sc_dev, 260 "timeout waiting for NIC to initialize\n"); 261 error = EIO; 262 goto fail1; 263 } 264 sc->mac_ver = tmp >> 16; 265 sc->mac_rev = tmp & 0xffff; 266 267 if (sc->mac_ver != 0x2860 && 268 (id == 0x0681 || id == 0x0781 || id == 0x1059)) 269 sc->sc_flags |= RT2860_ADVANCED_PS; 270 271 /* retrieve RF rev. no and various other things from EEPROM */ 272 rt2860_read_eeprom(sc, ic->ic_macaddr); 273 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " 274 "RF %s (MIMO %dT%dR), address %6D\n", 275 sc->mac_ver, sc->mac_rev, rt2860_get_rf(sc->rf_rev), 276 sc->ntxchains, sc->nrxchains, ic->ic_macaddr, ":"); 277 278 /* 279 * Allocate Tx (4 EDCAs + HCCA + Mgt) and Rx rings. 280 */ 281 for (qid = 0; qid < 6; qid++) { 282 if ((error = rt2860_alloc_tx_ring(sc, &sc->txq[qid])) != 0) { 283 device_printf(sc->sc_dev, 284 "could not allocate Tx ring %d\n", qid); 285 goto fail2; 286 } 287 } 288 289 if ((error = rt2860_alloc_rx_ring(sc, &sc->rxq)) != 0) { 290 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 291 goto fail2; 292 } 293 294 if ((error = rt2860_alloc_tx_pool(sc)) != 0) { 295 device_printf(sc->sc_dev, "could not allocate Tx pool\n"); 296 goto fail3; 297 } 298 299 /* mgmt ring is broken on RT2860C, use EDCA AC VO ring instead */ 300 sc->mgtqid = (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) ? 301 WME_AC_VO : 5; 302 303 ic->ic_softc = sc; 304 ic->ic_name = device_get_nameunit(dev); 305 ic->ic_opmode = IEEE80211_M_STA; 306 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 307 308 /* set device capabilities */ 309 ic->ic_caps = 310 IEEE80211_C_STA /* station mode */ 311 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 312 | IEEE80211_C_HOSTAP /* hostap mode */ 313 | IEEE80211_C_MONITOR /* monitor mode */ 314 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 315 | IEEE80211_C_WDS /* 4-address traffic works */ 316 | IEEE80211_C_MBSS /* mesh point link mode */ 317 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 318 | IEEE80211_C_SHSLOT /* short slot time supported */ 319 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 320 #if 0 321 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 322 #endif 323 | IEEE80211_C_WME /* 802.11e */ 324 ; 325 326 rt2860_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 327 ic->ic_channels); 328 329 ieee80211_ifattach(ic); 330 331 ic->ic_wme.wme_update = rt2860_updateedca; 332 ic->ic_scan_start = rt2860_scan_start; 333 ic->ic_scan_end = rt2860_scan_end; 334 ic->ic_getradiocaps = rt2860_getradiocaps; 335 ic->ic_set_channel = rt2860_set_channel; 336 ic->ic_updateslot = rt2860_updateslot; 337 ic->ic_update_promisc = rt2860_update_promisc; 338 ic->ic_raw_xmit = rt2860_raw_xmit; 339 sc->sc_node_free = ic->ic_node_free; 340 ic->ic_node_free = rt2860_node_free; 341 ic->ic_newassoc = rt2860_newassoc; 342 ic->ic_transmit = rt2860_transmit; 343 ic->ic_parent = rt2860_parent; 344 ic->ic_vap_create = rt2860_vap_create; 345 ic->ic_vap_delete = rt2860_vap_delete; 346 347 ieee80211_radiotap_attach(ic, 348 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 349 RT2860_TX_RADIOTAP_PRESENT, 350 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 351 RT2860_RX_RADIOTAP_PRESENT); 352 353 #ifdef RAL_DEBUG 354 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 355 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 356 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 357 #endif 358 if (bootverbose) 359 ieee80211_announce(ic); 360 361 return 0; 362 363 fail3: rt2860_free_rx_ring(sc, &sc->rxq); 364 fail2: while (--qid >= 0) 365 rt2860_free_tx_ring(sc, &sc->txq[qid]); 366 fail1: mtx_destroy(&sc->sc_mtx); 367 return error; 368 } 369 370 int 371 rt2860_detach(void *xsc) 372 { 373 struct rt2860_softc *sc = xsc; 374 struct ieee80211com *ic = &sc->sc_ic; 375 int qid; 376 377 RAL_LOCK(sc); 378 rt2860_stop_locked(sc); 379 RAL_UNLOCK(sc); 380 381 ieee80211_ifdetach(ic); 382 mbufq_drain(&sc->sc_snd); 383 for (qid = 0; qid < 6; qid++) 384 rt2860_free_tx_ring(sc, &sc->txq[qid]); 385 rt2860_free_rx_ring(sc, &sc->rxq); 386 rt2860_free_tx_pool(sc); 387 388 mtx_destroy(&sc->sc_mtx); 389 390 return 0; 391 } 392 393 void 394 rt2860_shutdown(void *xsc) 395 { 396 struct rt2860_softc *sc = xsc; 397 398 rt2860_stop(sc); 399 } 400 401 void 402 rt2860_suspend(void *xsc) 403 { 404 struct rt2860_softc *sc = xsc; 405 406 rt2860_stop(sc); 407 } 408 409 void 410 rt2860_resume(void *xsc) 411 { 412 struct rt2860_softc *sc = xsc; 413 414 if (sc->sc_ic.ic_nrunning > 0) 415 rt2860_init(sc); 416 } 417 418 static struct ieee80211vap * 419 rt2860_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 420 enum ieee80211_opmode opmode, int flags, 421 const uint8_t bssid[IEEE80211_ADDR_LEN], 422 const uint8_t mac[IEEE80211_ADDR_LEN]) 423 { 424 struct rt2860_softc *sc = ic->ic_softc; 425 struct rt2860_vap *rvp; 426 struct ieee80211vap *vap; 427 428 switch (opmode) { 429 case IEEE80211_M_STA: 430 case IEEE80211_M_IBSS: 431 case IEEE80211_M_AHDEMO: 432 case IEEE80211_M_MONITOR: 433 case IEEE80211_M_HOSTAP: 434 case IEEE80211_M_MBSS: 435 /* XXXRP: TBD */ 436 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 437 device_printf(sc->sc_dev, "only 1 vap supported\n"); 438 return NULL; 439 } 440 if (opmode == IEEE80211_M_STA) 441 flags |= IEEE80211_CLONE_NOBEACONS; 442 break; 443 case IEEE80211_M_WDS: 444 if (TAILQ_EMPTY(&ic->ic_vaps) || 445 ic->ic_opmode != IEEE80211_M_HOSTAP) { 446 device_printf(sc->sc_dev, 447 "wds only supported in ap mode\n"); 448 return NULL; 449 } 450 /* 451 * Silently remove any request for a unique 452 * bssid; WDS vap's always share the local 453 * mac address. 454 */ 455 flags &= ~IEEE80211_CLONE_BSSID; 456 break; 457 default: 458 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 459 return NULL; 460 } 461 rvp = malloc(sizeof(struct rt2860_vap), M_80211_VAP, M_WAITOK | M_ZERO); 462 vap = &rvp->ral_vap; 463 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 464 465 /* override state transition machine */ 466 rvp->ral_newstate = vap->iv_newstate; 467 vap->iv_newstate = rt2860_newstate; 468 #if 0 469 vap->iv_update_beacon = rt2860_beacon_update; 470 #endif 471 472 /* HW supports up to 255 STAs (0-254) in HostAP and IBSS modes */ 473 vap->iv_max_aid = min(IEEE80211_AID_MAX, RT2860_WCID_MAX); 474 475 ieee80211_ratectl_init(vap); 476 /* complete setup */ 477 ieee80211_vap_attach(vap, ieee80211_media_change, 478 ieee80211_media_status, mac); 479 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 480 ic->ic_opmode = opmode; 481 return vap; 482 } 483 484 static void 485 rt2860_vap_delete(struct ieee80211vap *vap) 486 { 487 struct rt2860_vap *rvp = RT2860_VAP(vap); 488 489 ieee80211_ratectl_deinit(vap); 490 ieee80211_vap_detach(vap); 491 free(rvp, M_80211_VAP); 492 } 493 494 static void 495 rt2860_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 496 { 497 if (error != 0) 498 return; 499 500 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 501 502 *(bus_addr_t *)arg = segs[0].ds_addr; 503 } 504 505 static int 506 rt2860_alloc_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 507 { 508 int size, error; 509 510 size = RT2860_TX_RING_COUNT * sizeof (struct rt2860_txd); 511 512 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 513 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 514 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 517 goto fail; 518 } 519 520 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->txd, 521 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 522 if (error != 0) { 523 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 524 goto fail; 525 } 526 527 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->txd, 528 size, rt2860_dma_map_addr, &ring->paddr, 0); 529 if (error != 0) { 530 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 531 goto fail; 532 } 533 534 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 535 536 return 0; 537 538 fail: rt2860_free_tx_ring(sc, ring); 539 return error; 540 } 541 542 void 543 rt2860_reset_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 544 { 545 struct rt2860_tx_data *data; 546 int i; 547 548 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 549 if ((data = ring->data[i]) == NULL) 550 continue; /* nothing mapped in this slot */ 551 552 if (data->m != NULL) { 553 bus_dmamap_sync(sc->txwi_dmat, data->map, 554 BUS_DMASYNC_POSTWRITE); 555 bus_dmamap_unload(sc->txwi_dmat, data->map); 556 m_freem(data->m); 557 data->m = NULL; 558 } 559 if (data->ni != NULL) { 560 ieee80211_free_node(data->ni); 561 data->ni = NULL; 562 } 563 564 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 565 ring->data[i] = NULL; 566 } 567 568 ring->queued = 0; 569 ring->cur = ring->next = 0; 570 } 571 572 void 573 rt2860_free_tx_ring(struct rt2860_softc *sc, struct rt2860_tx_ring *ring) 574 { 575 struct rt2860_tx_data *data; 576 int i; 577 578 if (ring->txd != NULL) { 579 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 580 BUS_DMASYNC_POSTWRITE); 581 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 582 bus_dmamem_free(ring->desc_dmat, ring->txd, ring->desc_map); 583 } 584 if (ring->desc_dmat != NULL) 585 bus_dma_tag_destroy(ring->desc_dmat); 586 587 for (i = 0; i < RT2860_TX_RING_COUNT; i++) { 588 if ((data = ring->data[i]) == NULL) 589 continue; /* nothing mapped in this slot */ 590 591 if (data->m != NULL) { 592 bus_dmamap_sync(sc->txwi_dmat, data->map, 593 BUS_DMASYNC_POSTWRITE); 594 bus_dmamap_unload(sc->txwi_dmat, data->map); 595 m_freem(data->m); 596 } 597 if (data->ni != NULL) 598 ieee80211_free_node(data->ni); 599 600 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 601 } 602 } 603 604 /* 605 * Allocate a pool of TX Wireless Information blocks. 606 */ 607 int 608 rt2860_alloc_tx_pool(struct rt2860_softc *sc) 609 { 610 caddr_t vaddr; 611 bus_addr_t paddr; 612 int i, size, error; 613 614 size = RT2860_TX_POOL_COUNT * RT2860_TXWI_DMASZ; 615 616 /* init data_pool early in case of failure.. */ 617 SLIST_INIT(&sc->data_pool); 618 619 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 620 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 621 size, 1, size, 0, NULL, NULL, &sc->txwi_dmat); 622 if (error != 0) { 623 device_printf(sc->sc_dev, "could not create txwi DMA tag\n"); 624 goto fail; 625 } 626 627 error = bus_dmamem_alloc(sc->txwi_dmat, (void **)&sc->txwi_vaddr, 628 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->txwi_map); 629 if (error != 0) { 630 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 631 goto fail; 632 } 633 634 error = bus_dmamap_load(sc->txwi_dmat, sc->txwi_map, 635 sc->txwi_vaddr, size, rt2860_dma_map_addr, &paddr, 0); 636 if (error != 0) { 637 device_printf(sc->sc_dev, "could not load txwi DMA map\n"); 638 goto fail; 639 } 640 641 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 642 643 vaddr = sc->txwi_vaddr; 644 for (i = 0; i < RT2860_TX_POOL_COUNT; i++) { 645 struct rt2860_tx_data *data = &sc->data[i]; 646 647 error = bus_dmamap_create(sc->txwi_dmat, 0, &data->map); 648 if (error != 0) { 649 device_printf(sc->sc_dev, "could not create DMA map\n"); 650 goto fail; 651 } 652 data->txwi = (struct rt2860_txwi *)vaddr; 653 data->paddr = paddr; 654 vaddr += RT2860_TXWI_DMASZ; 655 paddr += RT2860_TXWI_DMASZ; 656 657 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 658 } 659 660 return 0; 661 662 fail: rt2860_free_tx_pool(sc); 663 return error; 664 } 665 666 void 667 rt2860_free_tx_pool(struct rt2860_softc *sc) 668 { 669 if (sc->txwi_vaddr != NULL) { 670 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, 671 BUS_DMASYNC_POSTWRITE); 672 bus_dmamap_unload(sc->txwi_dmat, sc->txwi_map); 673 bus_dmamem_free(sc->txwi_dmat, sc->txwi_vaddr, sc->txwi_map); 674 } 675 if (sc->txwi_dmat != NULL) 676 bus_dma_tag_destroy(sc->txwi_dmat); 677 678 while (!SLIST_EMPTY(&sc->data_pool)) { 679 struct rt2860_tx_data *data; 680 data = SLIST_FIRST(&sc->data_pool); 681 bus_dmamap_destroy(sc->txwi_dmat, data->map); 682 SLIST_REMOVE_HEAD(&sc->data_pool, next); 683 } 684 } 685 686 int 687 rt2860_alloc_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 688 { 689 bus_addr_t physaddr; 690 int i, size, error; 691 692 size = RT2860_RX_RING_COUNT * sizeof (struct rt2860_rxd); 693 694 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 16, 0, 695 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 696 size, 1, size, 0, NULL, NULL, &ring->desc_dmat); 697 if (error != 0) { 698 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 699 goto fail; 700 } 701 702 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->rxd, 703 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 704 if (error != 0) { 705 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 706 goto fail; 707 } 708 709 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->rxd, 710 size, rt2860_dma_map_addr, &ring->paddr, 0); 711 if (error != 0) { 712 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 713 goto fail; 714 } 715 716 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 717 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 718 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 719 if (error != 0) { 720 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 721 goto fail; 722 } 723 724 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 725 struct rt2860_rx_data *data = &ring->data[i]; 726 struct rt2860_rxd *rxd = &ring->rxd[i]; 727 728 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 729 if (error != 0) { 730 device_printf(sc->sc_dev, "could not create DMA map\n"); 731 goto fail; 732 } 733 734 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 735 if (data->m == NULL) { 736 device_printf(sc->sc_dev, 737 "could not allocate rx mbuf\n"); 738 error = ENOMEM; 739 goto fail; 740 } 741 742 error = bus_dmamap_load(ring->data_dmat, data->map, 743 mtod(data->m, void *), MCLBYTES, rt2860_dma_map_addr, 744 &physaddr, 0); 745 if (error != 0) { 746 device_printf(sc->sc_dev, 747 "could not load rx buf DMA map"); 748 goto fail; 749 } 750 751 rxd->sdp0 = htole32(physaddr); 752 rxd->sdl0 = htole16(MCLBYTES); 753 } 754 755 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 756 757 return 0; 758 759 fail: rt2860_free_rx_ring(sc, ring); 760 return error; 761 } 762 763 void 764 rt2860_reset_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 765 { 766 int i; 767 768 for (i = 0; i < RT2860_RX_RING_COUNT; i++) 769 ring->rxd[i].sdl0 &= ~htole16(RT2860_RX_DDONE); 770 771 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 772 773 ring->cur = 0; 774 } 775 776 void 777 rt2860_free_rx_ring(struct rt2860_softc *sc, struct rt2860_rx_ring *ring) 778 { 779 int i; 780 781 if (ring->rxd != NULL) { 782 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 783 BUS_DMASYNC_POSTWRITE); 784 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 785 bus_dmamem_free(ring->desc_dmat, ring->rxd, ring->desc_map); 786 } 787 if (ring->desc_dmat != NULL) 788 bus_dma_tag_destroy(ring->desc_dmat); 789 790 for (i = 0; i < RT2860_RX_RING_COUNT; i++) { 791 struct rt2860_rx_data *data = &ring->data[i]; 792 793 if (data->m != NULL) { 794 bus_dmamap_sync(ring->data_dmat, data->map, 795 BUS_DMASYNC_POSTREAD); 796 bus_dmamap_unload(ring->data_dmat, data->map); 797 m_freem(data->m); 798 } 799 if (data->map != NULL) 800 bus_dmamap_destroy(ring->data_dmat, data->map); 801 } 802 if (ring->data_dmat != NULL) 803 bus_dma_tag_destroy(ring->data_dmat); 804 } 805 806 static void 807 rt2860_updatestats(struct rt2860_softc *sc) 808 { 809 struct ieee80211com *ic = &sc->sc_ic; 810 811 /* 812 * In IBSS or HostAP modes (when the hardware sends beacons), the 813 * MAC can run into a livelock and start sending CTS-to-self frames 814 * like crazy if protection is enabled. Fortunately, we can detect 815 * when such a situation occurs and reset the MAC. 816 */ 817 if (ic->ic_curmode != IEEE80211_M_STA) { 818 /* check if we're in a livelock situation.. */ 819 uint32_t tmp = RAL_READ(sc, RT2860_DEBUG); 820 if ((tmp & (1 << 29)) && (tmp & (1 << 7 | 1 << 5))) { 821 /* ..and reset MAC/BBP for a while.. */ 822 DPRINTF(("CTS-to-self livelock detected\n")); 823 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_SRST); 824 RAL_BARRIER_WRITE(sc); 825 DELAY(1); 826 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 827 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 828 } 829 } 830 } 831 832 static void 833 rt2860_newassoc(struct ieee80211_node *ni, int isnew) 834 { 835 struct ieee80211com *ic = ni->ni_ic; 836 struct rt2860_softc *sc = ic->ic_softc; 837 uint8_t wcid; 838 839 wcid = IEEE80211_AID(ni->ni_associd); 840 if (isnew && ni->ni_associd != 0) { 841 sc->wcid2ni[wcid] = ni; 842 843 /* init WCID table entry */ 844 RAL_WRITE_REGION_1(sc, RT2860_WCID_ENTRY(wcid), 845 ni->ni_macaddr, IEEE80211_ADDR_LEN); 846 } 847 DPRINTF(("new assoc isnew=%d addr=%s WCID=%d\n", 848 isnew, ether_sprintf(ni->ni_macaddr), wcid)); 849 } 850 851 static void 852 rt2860_node_free(struct ieee80211_node *ni) 853 { 854 struct ieee80211com *ic = ni->ni_ic; 855 struct rt2860_softc *sc = ic->ic_softc; 856 uint8_t wcid; 857 858 if (ni->ni_associd != 0) { 859 wcid = IEEE80211_AID(ni->ni_associd); 860 861 /* clear Rx WCID search table entry */ 862 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(wcid), 0, 2); 863 } 864 sc->sc_node_free(ni); 865 } 866 867 #ifdef IEEE80211_HT 868 static int 869 rt2860_ampdu_rx_start(struct ieee80211com *ic, struct ieee80211_node *ni, 870 uint8_t tid) 871 { 872 struct rt2860_softc *sc = ic->ic_softc; 873 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 874 uint32_t tmp; 875 876 /* update BA session mask */ 877 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 878 tmp |= (1 << tid) << 16; 879 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 880 return 0; 881 } 882 883 static void 884 rt2860_ampdu_rx_stop(struct ieee80211com *ic, struct ieee80211_node *ni, 885 uint8_t tid) 886 { 887 struct rt2860_softc *sc = ic->ic_softc; 888 uint8_t wcid = ((struct rt2860_node *)ni)->wcid; 889 uint32_t tmp; 890 891 /* update BA session mask */ 892 tmp = RAL_READ(sc, RT2860_WCID_ENTRY(wcid) + 4); 893 tmp &= ~((1 << tid) << 16); 894 RAL_WRITE(sc, RT2860_WCID_ENTRY(wcid) + 4, tmp); 895 } 896 #endif 897 898 static int 899 rt2860_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 900 { 901 struct rt2860_vap *rvp = RT2860_VAP(vap); 902 struct ieee80211com *ic = vap->iv_ic; 903 struct rt2860_softc *sc = ic->ic_softc; 904 uint32_t tmp; 905 int error; 906 907 if (vap->iv_state == IEEE80211_S_RUN) { 908 /* turn link LED off */ 909 rt2860_set_leds(sc, RT2860_LED_RADIO); 910 } 911 912 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 913 /* abort TSF synchronization */ 914 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 915 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 916 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 917 RT2860_TBTT_TIMER_EN)); 918 } 919 920 rt2860_set_gp_timer(sc, 0); 921 922 error = rvp->ral_newstate(vap, nstate, arg); 923 if (error != 0) 924 return (error); 925 926 if (nstate == IEEE80211_S_RUN) { 927 struct ieee80211_node *ni = vap->iv_bss; 928 929 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 930 rt2860_enable_mrr(sc); 931 rt2860_set_txpreamble(sc); 932 rt2860_set_basicrates(sc, &ni->ni_rates); 933 rt2860_set_bssid(sc, ni->ni_bssid); 934 } 935 936 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 937 vap->iv_opmode == IEEE80211_M_IBSS || 938 vap->iv_opmode == IEEE80211_M_MBSS) { 939 error = rt2860_setup_beacon(sc, vap); 940 if (error != 0) 941 return error; 942 } 943 944 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 945 rt2860_enable_tsf_sync(sc); 946 rt2860_set_gp_timer(sc, 500); 947 } 948 949 /* turn link LED on */ 950 rt2860_set_leds(sc, RT2860_LED_RADIO | 951 (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan) ? 952 RT2860_LED_LINK_2GHZ : RT2860_LED_LINK_5GHZ)); 953 } 954 return error; 955 } 956 957 /* Read 16-bit from eFUSE ROM (>=RT3071 only.) */ 958 static uint16_t 959 rt3090_efuse_read_2(struct rt2860_softc *sc, uint16_t addr) 960 { 961 uint32_t tmp; 962 uint16_t reg; 963 int ntries; 964 965 addr *= 2; 966 /*- 967 * Read one 16-byte block into registers EFUSE_DATA[0-3]: 968 * DATA0: F E D C 969 * DATA1: B A 9 8 970 * DATA2: 7 6 5 4 971 * DATA3: 3 2 1 0 972 */ 973 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 974 tmp &= ~(RT3070_EFSROM_MODE_MASK | RT3070_EFSROM_AIN_MASK); 975 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT | RT3070_EFSROM_KICK; 976 RAL_WRITE(sc, RT3070_EFUSE_CTRL, tmp); 977 for (ntries = 0; ntries < 500; ntries++) { 978 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 979 if (!(tmp & RT3070_EFSROM_KICK)) 980 break; 981 DELAY(2); 982 } 983 if (ntries == 500) 984 return 0xffff; 985 986 if ((tmp & RT3070_EFUSE_AOUT_MASK) == RT3070_EFUSE_AOUT_MASK) 987 return 0xffff; /* address not found */ 988 989 /* determine to which 32-bit register our 16-bit word belongs */ 990 reg = RT3070_EFUSE_DATA3 - (addr & 0xc); 991 tmp = RAL_READ(sc, reg); 992 993 return (addr & 2) ? tmp >> 16 : tmp & 0xffff; 994 } 995 996 /* 997 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46, 998 * 93C66 or 93C86). 999 */ 1000 static uint16_t 1001 rt2860_eeprom_read_2(struct rt2860_softc *sc, uint16_t addr) 1002 { 1003 uint32_t tmp; 1004 uint16_t val; 1005 int n; 1006 1007 /* clock C once before the first command */ 1008 RT2860_EEPROM_CTL(sc, 0); 1009 1010 RT2860_EEPROM_CTL(sc, RT2860_S); 1011 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1012 RT2860_EEPROM_CTL(sc, RT2860_S); 1013 1014 /* write start bit (1) */ 1015 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1016 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1017 1018 /* write READ opcode (10) */ 1019 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D); 1020 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_D | RT2860_C); 1021 RT2860_EEPROM_CTL(sc, RT2860_S); 1022 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1023 1024 /* write address (A5-A0 or A7-A0) */ 1025 n = ((RAL_READ(sc, RT2860_PCI_EECTRL) & 0x30) == 0) ? 5 : 7; 1026 for (; n >= 0; n--) { 1027 RT2860_EEPROM_CTL(sc, RT2860_S | 1028 (((addr >> n) & 1) << RT2860_SHIFT_D)); 1029 RT2860_EEPROM_CTL(sc, RT2860_S | 1030 (((addr >> n) & 1) << RT2860_SHIFT_D) | RT2860_C); 1031 } 1032 1033 RT2860_EEPROM_CTL(sc, RT2860_S); 1034 1035 /* read data Q15-Q0 */ 1036 val = 0; 1037 for (n = 15; n >= 0; n--) { 1038 RT2860_EEPROM_CTL(sc, RT2860_S | RT2860_C); 1039 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 1040 val |= ((tmp & RT2860_Q) >> RT2860_SHIFT_Q) << n; 1041 RT2860_EEPROM_CTL(sc, RT2860_S); 1042 } 1043 1044 RT2860_EEPROM_CTL(sc, 0); 1045 1046 /* clear Chip Select and clock C */ 1047 RT2860_EEPROM_CTL(sc, RT2860_S); 1048 RT2860_EEPROM_CTL(sc, 0); 1049 RT2860_EEPROM_CTL(sc, RT2860_C); 1050 1051 return val; 1052 } 1053 1054 static __inline uint16_t 1055 rt2860_srom_read(struct rt2860_softc *sc, uint8_t addr) 1056 { 1057 /* either eFUSE ROM or EEPROM */ 1058 return sc->sc_srom_read(sc, addr); 1059 } 1060 1061 static void 1062 rt2860_intr_coherent(struct rt2860_softc *sc) 1063 { 1064 uint32_t tmp; 1065 1066 /* DMA finds data coherent event when checking the DDONE bit */ 1067 1068 DPRINTF(("Tx/Rx Coherent interrupt\n")); 1069 1070 /* restart DMA engine */ 1071 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 1072 tmp &= ~(RT2860_TX_WB_DDONE | RT2860_RX_DMA_EN | RT2860_TX_DMA_EN); 1073 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 1074 1075 (void)rt2860_txrx_enable(sc); 1076 } 1077 1078 static void 1079 rt2860_drain_stats_fifo(struct rt2860_softc *sc) 1080 { 1081 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 1082 struct ieee80211_node *ni; 1083 uint32_t stat; 1084 uint8_t wcid, mcs, pid; 1085 1086 /* drain Tx status FIFO (maxsize = 16) */ 1087 txs->flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 1088 while ((stat = RAL_READ(sc, RT2860_TX_STAT_FIFO)) & RT2860_TXQ_VLD) { 1089 DPRINTFN(4, ("tx stat 0x%08x\n", stat)); 1090 1091 wcid = (stat >> RT2860_TXQ_WCID_SHIFT) & 0xff; 1092 if (wcid > RT2860_WCID_MAX) 1093 continue; 1094 ni = sc->wcid2ni[wcid]; 1095 1096 /* if no ACK was requested, no feedback is available */ 1097 if (!(stat & RT2860_TXQ_ACKREQ) || ni == NULL) 1098 continue; 1099 1100 /* update per-STA AMRR stats */ 1101 if (stat & RT2860_TXQ_OK) { 1102 /* 1103 * Check if there were retries, ie if the Tx success 1104 * rate is different from the requested rate. Note 1105 * that it works only because we do not allow rate 1106 * fallback from OFDM to CCK. 1107 */ 1108 mcs = (stat >> RT2860_TXQ_MCS_SHIFT) & 0x7f; 1109 pid = (stat >> RT2860_TXQ_PID_SHIFT) & 0xf; 1110 if (mcs + 1 != pid) 1111 txs->long_retries = 1; 1112 else 1113 txs->long_retries = 0; 1114 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 1115 ieee80211_ratectl_tx_complete(ni, txs); 1116 } else { 1117 txs->status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 1118 txs->long_retries = 1; /* XXX */ 1119 ieee80211_ratectl_tx_complete(ni, txs); 1120 if_inc_counter(ni->ni_vap->iv_ifp, 1121 IFCOUNTER_OERRORS, 1); 1122 } 1123 } 1124 } 1125 1126 static void 1127 rt2860_tx_intr(struct rt2860_softc *sc, int qid) 1128 { 1129 struct rt2860_tx_ring *ring = &sc->txq[qid]; 1130 uint32_t hw; 1131 1132 rt2860_drain_stats_fifo(sc); 1133 1134 hw = RAL_READ(sc, RT2860_TX_DTX_IDX(qid)); 1135 while (ring->next != hw) { 1136 struct rt2860_tx_data *data = ring->data[ring->next]; 1137 1138 if (data != NULL) { 1139 bus_dmamap_sync(sc->txwi_dmat, data->map, 1140 BUS_DMASYNC_POSTWRITE); 1141 bus_dmamap_unload(sc->txwi_dmat, data->map); 1142 ieee80211_tx_complete(data->ni, data->m, 0); 1143 data->ni = NULL; 1144 data->m = NULL; 1145 SLIST_INSERT_HEAD(&sc->data_pool, data, next); 1146 ring->data[ring->next] = NULL; 1147 } 1148 ring->queued--; 1149 ring->next = (ring->next + 1) % RT2860_TX_RING_COUNT; 1150 } 1151 1152 sc->sc_tx_timer = 0; 1153 if (ring->queued < RT2860_TX_RING_COUNT) 1154 sc->qfullmsk &= ~(1 << qid); 1155 rt2860_start(sc); 1156 } 1157 1158 /* 1159 * Return the Rx chain with the highest RSSI for a given frame. 1160 */ 1161 static __inline uint8_t 1162 rt2860_maxrssi_chain(struct rt2860_softc *sc, const struct rt2860_rxwi *rxwi) 1163 { 1164 uint8_t rxchain = 0; 1165 1166 if (sc->nrxchains > 1) { 1167 if (rxwi->rssi[1] > rxwi->rssi[rxchain]) 1168 rxchain = 1; 1169 if (sc->nrxchains > 2) 1170 if (rxwi->rssi[2] > rxwi->rssi[rxchain]) 1171 rxchain = 2; 1172 } 1173 return rxchain; 1174 } 1175 1176 static void 1177 rt2860_rx_intr(struct rt2860_softc *sc) 1178 { 1179 struct rt2860_rx_radiotap_header *tap; 1180 struct ieee80211com *ic = &sc->sc_ic; 1181 struct ieee80211_frame *wh; 1182 struct ieee80211_node *ni; 1183 struct mbuf *m, *m1; 1184 bus_addr_t physaddr; 1185 uint32_t hw; 1186 uint16_t phy; 1187 uint8_t ant; 1188 int8_t rssi, nf; 1189 int error; 1190 1191 hw = RAL_READ(sc, RT2860_FS_DRX_IDX) & 0xfff; 1192 while (sc->rxq.cur != hw) { 1193 struct rt2860_rx_data *data = &sc->rxq.data[sc->rxq.cur]; 1194 struct rt2860_rxd *rxd = &sc->rxq.rxd[sc->rxq.cur]; 1195 struct rt2860_rxwi *rxwi; 1196 1197 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1198 BUS_DMASYNC_POSTREAD); 1199 1200 if (__predict_false(!(rxd->sdl0 & htole16(RT2860_RX_DDONE)))) { 1201 DPRINTF(("RXD DDONE bit not set!\n")); 1202 break; /* should not happen */ 1203 } 1204 1205 if (__predict_false(rxd->flags & 1206 htole32(RT2860_RX_CRCERR | RT2860_RX_ICVERR))) { 1207 counter_u64_add(ic->ic_ierrors, 1); 1208 goto skip; 1209 } 1210 1211 #ifdef HW_CRYPTO 1212 if (__predict_false(rxd->flags & htole32(RT2860_RX_MICERR))) { 1213 /* report MIC failures to net80211 for TKIP */ 1214 ic->ic_stats.is_rx_locmicfail++; 1215 ieee80211_michael_mic_failure(ic, 0/* XXX */); 1216 counter_u64_add(ic->ic_ierrors, 1); 1217 goto skip; 1218 } 1219 #endif 1220 1221 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1222 if (__predict_false(m1 == NULL)) { 1223 counter_u64_add(ic->ic_ierrors, 1); 1224 goto skip; 1225 } 1226 1227 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1228 BUS_DMASYNC_POSTREAD); 1229 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1230 1231 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1232 mtod(m1, void *), MCLBYTES, rt2860_dma_map_addr, 1233 &physaddr, 0); 1234 if (__predict_false(error != 0)) { 1235 m_freem(m1); 1236 1237 /* try to reload the old mbuf */ 1238 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1239 mtod(data->m, void *), MCLBYTES, 1240 rt2860_dma_map_addr, &physaddr, 0); 1241 if (__predict_false(error != 0)) { 1242 panic("%s: could not load old rx mbuf", 1243 device_get_name(sc->sc_dev)); 1244 } 1245 /* physical address may have changed */ 1246 rxd->sdp0 = htole32(physaddr); 1247 counter_u64_add(ic->ic_ierrors, 1); 1248 goto skip; 1249 } 1250 1251 /* 1252 * New mbuf successfully loaded, update Rx ring and continue 1253 * processing. 1254 */ 1255 m = data->m; 1256 data->m = m1; 1257 rxd->sdp0 = htole32(physaddr); 1258 1259 rxwi = mtod(m, struct rt2860_rxwi *); 1260 1261 /* finalize mbuf */ 1262 m->m_data = (caddr_t)(rxwi + 1); 1263 m->m_pkthdr.len = m->m_len = le16toh(rxwi->len) & 0xfff; 1264 1265 wh = mtod(m, struct ieee80211_frame *); 1266 #ifdef HW_CRYPTO 1267 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1268 /* frame is decrypted by hardware */ 1269 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED; 1270 } 1271 #endif 1272 1273 /* HW may insert 2 padding bytes after 802.11 header */ 1274 if (rxd->flags & htole32(RT2860_RX_L2PAD)) { 1275 u_int hdrlen = ieee80211_hdrsize(wh); 1276 ovbcopy(wh, (caddr_t)wh + 2, hdrlen); 1277 m->m_data += 2; 1278 wh = mtod(m, struct ieee80211_frame *); 1279 } 1280 1281 ant = rt2860_maxrssi_chain(sc, rxwi); 1282 rssi = rt2860_rssi2dbm(sc, rxwi->rssi[ant], ant); 1283 nf = RT2860_NOISE_FLOOR; 1284 1285 if (ieee80211_radiotap_active(ic)) { 1286 tap = &sc->sc_rxtap; 1287 tap->wr_flags = 0; 1288 tap->wr_antenna = ant; 1289 tap->wr_antsignal = nf + rssi; 1290 tap->wr_antnoise = nf; 1291 /* in case it can't be found below */ 1292 tap->wr_rate = 2; 1293 phy = le16toh(rxwi->phy); 1294 switch (phy & RT2860_PHY_MODE) { 1295 case RT2860_PHY_CCK: 1296 switch ((phy & RT2860_PHY_MCS) & ~RT2860_PHY_SHPRE) { 1297 case 0: tap->wr_rate = 2; break; 1298 case 1: tap->wr_rate = 4; break; 1299 case 2: tap->wr_rate = 11; break; 1300 case 3: tap->wr_rate = 22; break; 1301 } 1302 if (phy & RT2860_PHY_SHPRE) 1303 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1304 break; 1305 case RT2860_PHY_OFDM: 1306 switch (phy & RT2860_PHY_MCS) { 1307 case 0: tap->wr_rate = 12; break; 1308 case 1: tap->wr_rate = 18; break; 1309 case 2: tap->wr_rate = 24; break; 1310 case 3: tap->wr_rate = 36; break; 1311 case 4: tap->wr_rate = 48; break; 1312 case 5: tap->wr_rate = 72; break; 1313 case 6: tap->wr_rate = 96; break; 1314 case 7: tap->wr_rate = 108; break; 1315 } 1316 break; 1317 } 1318 } 1319 1320 RAL_UNLOCK(sc); 1321 wh = mtod(m, struct ieee80211_frame *); 1322 1323 /* send the frame to the 802.11 layer */ 1324 ni = ieee80211_find_rxnode(ic, 1325 (struct ieee80211_frame_min *)wh); 1326 if (ni != NULL) { 1327 (void)ieee80211_input(ni, m, rssi - nf, nf); 1328 ieee80211_free_node(ni); 1329 } else 1330 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1331 1332 RAL_LOCK(sc); 1333 1334 skip: rxd->sdl0 &= ~htole16(RT2860_RX_DDONE); 1335 1336 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1337 BUS_DMASYNC_PREWRITE); 1338 1339 sc->rxq.cur = (sc->rxq.cur + 1) % RT2860_RX_RING_COUNT; 1340 } 1341 1342 /* tell HW what we have processed */ 1343 RAL_WRITE(sc, RT2860_RX_CALC_IDX, 1344 (sc->rxq.cur - 1) % RT2860_RX_RING_COUNT); 1345 } 1346 1347 static void 1348 rt2860_tbtt_intr(struct rt2860_softc *sc) 1349 { 1350 #if 0 1351 struct ieee80211com *ic = &sc->sc_ic; 1352 1353 #ifndef IEEE80211_STA_ONLY 1354 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1355 /* one less beacon until next DTIM */ 1356 if (ic->ic_dtim_count == 0) 1357 ic->ic_dtim_count = ic->ic_dtim_period - 1; 1358 else 1359 ic->ic_dtim_count--; 1360 1361 /* update dynamic parts of beacon */ 1362 rt2860_setup_beacon(sc); 1363 1364 /* flush buffered multicast frames */ 1365 if (ic->ic_dtim_count == 0) 1366 ieee80211_notify_dtim(ic); 1367 } 1368 #endif 1369 /* check if protection mode has changed */ 1370 if ((sc->sc_ic_flags ^ ic->ic_flags) & IEEE80211_F_USEPROT) { 1371 rt2860_updateprot(sc); 1372 sc->sc_ic_flags = ic->ic_flags; 1373 } 1374 #endif 1375 } 1376 1377 static void 1378 rt2860_gp_intr(struct rt2860_softc *sc) 1379 { 1380 struct ieee80211com *ic = &sc->sc_ic; 1381 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1382 1383 DPRINTFN(2, ("GP timeout state=%d\n", vap->iv_state)); 1384 1385 if (vap->iv_state == IEEE80211_S_RUN) 1386 rt2860_updatestats(sc); 1387 } 1388 1389 void 1390 rt2860_intr(void *arg) 1391 { 1392 struct rt2860_softc *sc = arg; 1393 uint32_t r; 1394 1395 RAL_LOCK(sc); 1396 1397 r = RAL_READ(sc, RT2860_INT_STATUS); 1398 if (__predict_false(r == 0xffffffff)) { 1399 RAL_UNLOCK(sc); 1400 return; /* device likely went away */ 1401 } 1402 if (r == 0) { 1403 RAL_UNLOCK(sc); 1404 return; /* not for us */ 1405 } 1406 1407 /* acknowledge interrupts */ 1408 RAL_WRITE(sc, RT2860_INT_STATUS, r); 1409 1410 if (r & RT2860_TX_RX_COHERENT) 1411 rt2860_intr_coherent(sc); 1412 1413 if (r & RT2860_MAC_INT_2) /* TX status */ 1414 rt2860_drain_stats_fifo(sc); 1415 1416 if (r & RT2860_TX_DONE_INT5) 1417 rt2860_tx_intr(sc, 5); 1418 1419 if (r & RT2860_RX_DONE_INT) 1420 rt2860_rx_intr(sc); 1421 1422 if (r & RT2860_TX_DONE_INT4) 1423 rt2860_tx_intr(sc, 4); 1424 1425 if (r & RT2860_TX_DONE_INT3) 1426 rt2860_tx_intr(sc, 3); 1427 1428 if (r & RT2860_TX_DONE_INT2) 1429 rt2860_tx_intr(sc, 2); 1430 1431 if (r & RT2860_TX_DONE_INT1) 1432 rt2860_tx_intr(sc, 1); 1433 1434 if (r & RT2860_TX_DONE_INT0) 1435 rt2860_tx_intr(sc, 0); 1436 1437 if (r & RT2860_MAC_INT_0) /* TBTT */ 1438 rt2860_tbtt_intr(sc); 1439 1440 if (r & RT2860_MAC_INT_3) /* Auto wakeup */ 1441 /* TBD wakeup */; 1442 1443 if (r & RT2860_MAC_INT_4) /* GP timer */ 1444 rt2860_gp_intr(sc); 1445 1446 RAL_UNLOCK(sc); 1447 } 1448 1449 static int 1450 rt2860_tx(struct rt2860_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1451 { 1452 struct ieee80211com *ic = &sc->sc_ic; 1453 struct ieee80211vap *vap = ni->ni_vap; 1454 struct rt2860_tx_ring *ring; 1455 struct rt2860_tx_data *data; 1456 struct rt2860_txd *txd; 1457 struct rt2860_txwi *txwi; 1458 struct ieee80211_frame *wh; 1459 const struct ieee80211_txparam *tp = ni->ni_txparms; 1460 struct ieee80211_key *k; 1461 struct mbuf *m1; 1462 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1463 bus_dma_segment_t *seg; 1464 u_int hdrlen; 1465 uint16_t qos, dur; 1466 uint8_t type, qsel, mcs, pid, qid; 1467 int i, nsegs, ntxds, pad, rate, ridx, error; 1468 1469 /* the data pool contains at least one element, pick the first */ 1470 data = SLIST_FIRST(&sc->data_pool); 1471 1472 wh = mtod(m, struct ieee80211_frame *); 1473 1474 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1475 k = ieee80211_crypto_encap(ni, m); 1476 if (k == NULL) { 1477 m_freem(m); 1478 return ENOBUFS; 1479 } 1480 1481 /* packet header may have moved, reset our local pointer */ 1482 wh = mtod(m, struct ieee80211_frame *); 1483 } 1484 1485 hdrlen = ieee80211_anyhdrsize(wh); 1486 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1487 1488 if (m->m_flags & M_EAPOL) { 1489 rate = tp->mgmtrate; 1490 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1491 rate = tp->mcastrate; 1492 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1493 rate = tp->ucastrate; 1494 } else { 1495 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1496 rate = ni->ni_txrate; 1497 } 1498 rate &= IEEE80211_RATE_VAL; 1499 1500 qid = M_WME_GETAC(m); 1501 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1502 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1503 } else { 1504 qos = 0; 1505 } 1506 ring = &sc->txq[qid]; 1507 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, rate); 1508 1509 /* get MCS code from rate index */ 1510 mcs = rt2860_rates[ridx].mcs; 1511 1512 /* setup TX Wireless Information */ 1513 txwi = data->txwi; 1514 txwi->flags = 0; 1515 /* let HW generate seq numbers for non-QoS frames */ 1516 txwi->xflags = qos ? 0 : RT2860_TX_NSEQ; 1517 if (type == IEEE80211_FC0_TYPE_DATA) 1518 txwi->wcid = IEEE80211_AID(ni->ni_associd); 1519 else 1520 txwi->wcid = 0xff; 1521 txwi->len = htole16(m->m_pkthdr.len); 1522 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1523 txwi->phy = htole16(RT2860_PHY_CCK); 1524 if (ridx != RT2860_RIDX_CCK1 && 1525 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1526 mcs |= RT2860_PHY_SHPRE; 1527 } else 1528 txwi->phy = htole16(RT2860_PHY_OFDM); 1529 txwi->phy |= htole16(mcs); 1530 1531 /* 1532 * We store the MCS code into the driver-private PacketID field. 1533 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1534 * that we know at which initial rate the frame was transmitted. 1535 * We add 1 to the MCS code because setting the PacketID field to 1536 * 0 means that we don't want feedback in TX_STAT_FIFO. 1537 */ 1538 pid = (mcs + 1) & 0xf; 1539 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1540 1541 /* check if RTS/CTS or CTS-to-self protection is required */ 1542 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1543 (m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold || 1544 ((ic->ic_flags & IEEE80211_F_USEPROT) && 1545 rt2860_rates[ridx].phy == IEEE80211_T_OFDM))) 1546 txwi->txop = RT2860_TX_TXOP_HT; 1547 else 1548 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1549 1550 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1551 (!qos || (qos & IEEE80211_QOS_ACKPOLICY) != 1552 IEEE80211_QOS_ACKPOLICY_NOACK)) { 1553 txwi->xflags |= RT2860_TX_ACK; 1554 1555 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1556 dur = rt2860_rates[ridx].sp_ack_dur; 1557 else 1558 dur = rt2860_rates[ridx].lp_ack_dur; 1559 *(uint16_t *)wh->i_dur = htole16(dur); 1560 } 1561 /* ask MAC to insert timestamp into probe responses */ 1562 if ((wh->i_fc[0] & 1563 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1564 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1565 /* NOTE: beacons do not pass through tx_data() */ 1566 txwi->flags |= RT2860_TX_TS; 1567 1568 if (ieee80211_radiotap_active_vap(vap)) { 1569 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1570 1571 tap->wt_flags = 0; 1572 tap->wt_rate = rate; 1573 if (mcs & RT2860_PHY_SHPRE) 1574 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1575 1576 ieee80211_radiotap_tx(vap, m); 1577 } 1578 1579 pad = (hdrlen + 3) & ~3; 1580 1581 /* copy and trim 802.11 header */ 1582 memcpy(txwi + 1, wh, hdrlen); 1583 m_adj(m, hdrlen); 1584 1585 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1586 &nsegs, 0); 1587 if (__predict_false(error != 0 && error != EFBIG)) { 1588 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1589 error); 1590 m_freem(m); 1591 return error; 1592 } 1593 if (__predict_true(error == 0)) { 1594 /* determine how many TXDs are required */ 1595 ntxds = 1 + (nsegs / 2); 1596 1597 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1598 /* not enough free TXDs, force mbuf defrag */ 1599 bus_dmamap_unload(sc->txwi_dmat, data->map); 1600 error = EFBIG; 1601 } 1602 } 1603 if (__predict_false(error != 0)) { 1604 m1 = m_defrag(m, M_NOWAIT); 1605 if (m1 == NULL) { 1606 device_printf(sc->sc_dev, 1607 "could not defragment mbuf\n"); 1608 m_freem(m); 1609 return ENOBUFS; 1610 } 1611 m = m1; 1612 1613 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1614 segs, &nsegs, 0); 1615 if (__predict_false(error != 0)) { 1616 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1617 error); 1618 m_freem(m); 1619 return error; 1620 } 1621 1622 /* determine how many TXDs are now required */ 1623 ntxds = 1 + (nsegs / 2); 1624 1625 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1626 /* this is a hopeless case, drop the mbuf! */ 1627 bus_dmamap_unload(sc->txwi_dmat, data->map); 1628 m_freem(m); 1629 return ENOBUFS; 1630 } 1631 } 1632 1633 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1634 1635 /* first segment is TXWI + 802.11 header */ 1636 txd = &ring->txd[ring->cur]; 1637 txd->sdp0 = htole32(data->paddr); 1638 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1639 txd->flags = qsel; 1640 1641 /* setup payload segments */ 1642 seg = &segs[0]; 1643 for (i = nsegs; i >= 2; i -= 2) { 1644 txd->sdp1 = htole32(seg->ds_addr); 1645 txd->sdl1 = htole16(seg->ds_len); 1646 seg++; 1647 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1648 /* grab a new Tx descriptor */ 1649 txd = &ring->txd[ring->cur]; 1650 txd->sdp0 = htole32(seg->ds_addr); 1651 txd->sdl0 = htole16(seg->ds_len); 1652 txd->flags = qsel; 1653 seg++; 1654 } 1655 /* finalize last segment */ 1656 if (i > 0) { 1657 txd->sdp1 = htole32(seg->ds_addr); 1658 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1659 } else { 1660 txd->sdl0 |= htole16(RT2860_TX_LS0); 1661 txd->sdl1 = 0; 1662 } 1663 1664 /* remove from the free pool and link it into the SW Tx slot */ 1665 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1666 data->m = m; 1667 data->ni = ni; 1668 ring->data[ring->cur] = data; 1669 1670 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1671 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1672 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1673 1674 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1675 qid, txwi->wcid, nsegs, ridx)); 1676 1677 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1678 ring->queued += ntxds; 1679 if (ring->queued >= RT2860_TX_RING_COUNT) 1680 sc->qfullmsk |= 1 << qid; 1681 1682 /* kick Tx */ 1683 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1684 1685 return 0; 1686 } 1687 1688 static int 1689 rt2860_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1690 const struct ieee80211_bpf_params *params) 1691 { 1692 struct ieee80211com *ic = ni->ni_ic; 1693 struct rt2860_softc *sc = ic->ic_softc; 1694 int error; 1695 1696 RAL_LOCK(sc); 1697 1698 /* prevent management frames from being sent if we're not ready */ 1699 if (!(sc->sc_flags & RT2860_RUNNING)) { 1700 RAL_UNLOCK(sc); 1701 m_freem(m); 1702 return ENETDOWN; 1703 } 1704 if (params == NULL) { 1705 /* 1706 * Legacy path; interpret frame contents to decide 1707 * precisely how to send the frame. 1708 */ 1709 error = rt2860_tx(sc, m, ni); 1710 } else { 1711 /* 1712 * Caller supplied explicit parameters to use in 1713 * sending the frame. 1714 */ 1715 error = rt2860_tx_raw(sc, m, ni, params); 1716 } 1717 sc->sc_tx_timer = 5; 1718 RAL_UNLOCK(sc); 1719 return error; 1720 } 1721 1722 static int 1723 rt2860_tx_raw(struct rt2860_softc *sc, struct mbuf *m, 1724 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 1725 { 1726 struct ieee80211com *ic = &sc->sc_ic; 1727 struct ieee80211vap *vap = ni->ni_vap; 1728 struct rt2860_tx_ring *ring; 1729 struct rt2860_tx_data *data; 1730 struct rt2860_txd *txd; 1731 struct rt2860_txwi *txwi; 1732 struct ieee80211_frame *wh; 1733 struct mbuf *m1; 1734 bus_dma_segment_t segs[RT2860_MAX_SCATTER]; 1735 bus_dma_segment_t *seg; 1736 u_int hdrlen; 1737 uint16_t dur; 1738 uint8_t qsel, mcs, pid, qid; 1739 int i, nsegs, ntxds, pad, rate, ridx, error; 1740 1741 /* the data pool contains at least one element, pick the first */ 1742 data = SLIST_FIRST(&sc->data_pool); 1743 1744 wh = mtod(m, struct ieee80211_frame *); 1745 hdrlen = ieee80211_hdrsize(wh); 1746 1747 /* Choose a TX rate index. */ 1748 rate = params->ibp_rate0; 1749 ridx = ieee80211_legacy_rate_lookup(ic->ic_rt, 1750 rate & IEEE80211_RATE_VAL); 1751 if (ridx == (uint8_t)-1) { 1752 /* XXX fall back to mcast/mgmt rate? */ 1753 m_freem(m); 1754 return EINVAL; 1755 } 1756 1757 qid = params->ibp_pri & 3; 1758 ring = &sc->txq[qid]; 1759 1760 /* get MCS code from rate index */ 1761 mcs = rt2860_rates[ridx].mcs; 1762 1763 /* setup TX Wireless Information */ 1764 txwi = data->txwi; 1765 txwi->flags = 0; 1766 /* let HW generate seq numbers for non-QoS frames */ 1767 txwi->xflags = params->ibp_pri & 3 ? 0 : RT2860_TX_NSEQ; 1768 txwi->wcid = 0xff; 1769 txwi->len = htole16(m->m_pkthdr.len); 1770 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) { 1771 txwi->phy = htole16(RT2860_PHY_CCK); 1772 if (ridx != RT2860_RIDX_CCK1 && 1773 (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1774 mcs |= RT2860_PHY_SHPRE; 1775 } else 1776 txwi->phy = htole16(RT2860_PHY_OFDM); 1777 txwi->phy |= htole16(mcs); 1778 1779 /* 1780 * We store the MCS code into the driver-private PacketID field. 1781 * The PacketID is latched into TX_STAT_FIFO when Tx completes so 1782 * that we know at which initial rate the frame was transmitted. 1783 * We add 1 to the MCS code because setting the PacketID field to 1784 * 0 means that we don't want feedback in TX_STAT_FIFO. 1785 */ 1786 pid = (mcs + 1) & 0xf; 1787 txwi->len |= htole16(pid << RT2860_TX_PID_SHIFT); 1788 1789 /* check if RTS/CTS or CTS-to-self protection is required */ 1790 if (params->ibp_flags & IEEE80211_BPF_RTS || 1791 params->ibp_flags & IEEE80211_BPF_CTS) 1792 txwi->txop = RT2860_TX_TXOP_HT; 1793 else 1794 txwi->txop = RT2860_TX_TXOP_BACKOFF; 1795 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 1796 txwi->xflags |= RT2860_TX_ACK; 1797 1798 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1799 dur = rt2860_rates[ridx].sp_ack_dur; 1800 else 1801 dur = rt2860_rates[ridx].lp_ack_dur; 1802 *(uint16_t *)wh->i_dur = htole16(dur); 1803 } 1804 /* ask MAC to insert timestamp into probe responses */ 1805 if ((wh->i_fc[0] & 1806 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1807 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1808 /* NOTE: beacons do not pass through tx_data() */ 1809 txwi->flags |= RT2860_TX_TS; 1810 1811 if (ieee80211_radiotap_active_vap(vap)) { 1812 struct rt2860_tx_radiotap_header *tap = &sc->sc_txtap; 1813 1814 tap->wt_flags = 0; 1815 tap->wt_rate = rate; 1816 if (mcs & RT2860_PHY_SHPRE) 1817 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 1818 1819 ieee80211_radiotap_tx(vap, m); 1820 } 1821 1822 pad = (hdrlen + 3) & ~3; 1823 1824 /* copy and trim 802.11 header */ 1825 memcpy(txwi + 1, wh, hdrlen); 1826 m_adj(m, hdrlen); 1827 1828 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, segs, 1829 &nsegs, 0); 1830 if (__predict_false(error != 0 && error != EFBIG)) { 1831 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1832 error); 1833 m_freem(m); 1834 return error; 1835 } 1836 if (__predict_true(error == 0)) { 1837 /* determine how many TXDs are required */ 1838 ntxds = 1 + (nsegs / 2); 1839 1840 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1841 /* not enough free TXDs, force mbuf defrag */ 1842 bus_dmamap_unload(sc->txwi_dmat, data->map); 1843 error = EFBIG; 1844 } 1845 } 1846 if (__predict_false(error != 0)) { 1847 m1 = m_defrag(m, M_NOWAIT); 1848 if (m1 == NULL) { 1849 device_printf(sc->sc_dev, 1850 "could not defragment mbuf\n"); 1851 m_freem(m); 1852 return ENOBUFS; 1853 } 1854 m = m1; 1855 1856 error = bus_dmamap_load_mbuf_sg(sc->txwi_dmat, data->map, m, 1857 segs, &nsegs, 0); 1858 if (__predict_false(error != 0)) { 1859 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", 1860 error); 1861 m_freem(m); 1862 return error; 1863 } 1864 1865 /* determine how many TXDs are now required */ 1866 ntxds = 1 + (nsegs / 2); 1867 1868 if (ring->queued + ntxds >= RT2860_TX_RING_COUNT) { 1869 /* this is a hopeless case, drop the mbuf! */ 1870 bus_dmamap_unload(sc->txwi_dmat, data->map); 1871 m_freem(m); 1872 return ENOBUFS; 1873 } 1874 } 1875 1876 qsel = (qid < WME_NUM_AC) ? RT2860_TX_QSEL_EDCA : RT2860_TX_QSEL_MGMT; 1877 1878 /* first segment is TXWI + 802.11 header */ 1879 txd = &ring->txd[ring->cur]; 1880 txd->sdp0 = htole32(data->paddr); 1881 txd->sdl0 = htole16(sizeof (struct rt2860_txwi) + pad); 1882 txd->flags = qsel; 1883 1884 /* setup payload segments */ 1885 seg = &segs[0]; 1886 for (i = nsegs; i >= 2; i -= 2) { 1887 txd->sdp1 = htole32(seg->ds_addr); 1888 txd->sdl1 = htole16(seg->ds_len); 1889 seg++; 1890 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1891 /* grab a new Tx descriptor */ 1892 txd = &ring->txd[ring->cur]; 1893 txd->sdp0 = htole32(seg->ds_addr); 1894 txd->sdl0 = htole16(seg->ds_len); 1895 txd->flags = qsel; 1896 seg++; 1897 } 1898 /* finalize last segment */ 1899 if (i > 0) { 1900 txd->sdp1 = htole32(seg->ds_addr); 1901 txd->sdl1 = htole16(seg->ds_len | RT2860_TX_LS1); 1902 } else { 1903 txd->sdl0 |= htole16(RT2860_TX_LS0); 1904 txd->sdl1 = 0; 1905 } 1906 1907 /* remove from the free pool and link it into the SW Tx slot */ 1908 SLIST_REMOVE_HEAD(&sc->data_pool, next); 1909 data->m = m; 1910 data->ni = ni; 1911 ring->data[ring->cur] = data; 1912 1913 bus_dmamap_sync(sc->txwi_dmat, sc->txwi_map, BUS_DMASYNC_PREWRITE); 1914 bus_dmamap_sync(sc->txwi_dmat, data->map, BUS_DMASYNC_PREWRITE); 1915 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 1916 1917 DPRINTFN(4, ("sending frame qid=%d wcid=%d nsegs=%d ridx=%d\n", 1918 qid, txwi->wcid, nsegs, ridx)); 1919 1920 ring->cur = (ring->cur + 1) % RT2860_TX_RING_COUNT; 1921 ring->queued += ntxds; 1922 if (ring->queued >= RT2860_TX_RING_COUNT) 1923 sc->qfullmsk |= 1 << qid; 1924 1925 /* kick Tx */ 1926 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), ring->cur); 1927 1928 return 0; 1929 } 1930 1931 static int 1932 rt2860_transmit(struct ieee80211com *ic, struct mbuf *m) 1933 { 1934 struct rt2860_softc *sc = ic->ic_softc; 1935 int error; 1936 1937 RAL_LOCK(sc); 1938 if ((sc->sc_flags & RT2860_RUNNING) == 0) { 1939 RAL_UNLOCK(sc); 1940 return (ENXIO); 1941 } 1942 error = mbufq_enqueue(&sc->sc_snd, m); 1943 if (error) { 1944 RAL_UNLOCK(sc); 1945 return (error); 1946 } 1947 rt2860_start(sc); 1948 RAL_UNLOCK(sc); 1949 1950 return (0); 1951 } 1952 1953 static void 1954 rt2860_start(struct rt2860_softc *sc) 1955 { 1956 struct ieee80211_node *ni; 1957 struct mbuf *m; 1958 1959 RAL_LOCK_ASSERT(sc); 1960 1961 if ((sc->sc_flags & RT2860_RUNNING) == 0) 1962 return; 1963 1964 while (!SLIST_EMPTY(&sc->data_pool) && sc->qfullmsk == 0 && 1965 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1966 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1967 if (rt2860_tx(sc, m, ni) != 0) { 1968 if_inc_counter(ni->ni_vap->iv_ifp, 1969 IFCOUNTER_OERRORS, 1); 1970 ieee80211_free_node(ni); 1971 continue; 1972 } 1973 sc->sc_tx_timer = 5; 1974 } 1975 } 1976 1977 static void 1978 rt2860_watchdog(void *arg) 1979 { 1980 struct rt2860_softc *sc = arg; 1981 1982 RAL_LOCK_ASSERT(sc); 1983 1984 KASSERT(sc->sc_flags & RT2860_RUNNING, ("not running")); 1985 1986 if (sc->sc_invalid) /* card ejected */ 1987 return; 1988 1989 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1990 device_printf(sc->sc_dev, "device timeout\n"); 1991 rt2860_stop_locked(sc); 1992 rt2860_init_locked(sc); 1993 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1994 return; 1995 } 1996 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 1997 } 1998 1999 static void 2000 rt2860_parent(struct ieee80211com *ic) 2001 { 2002 struct rt2860_softc *sc = ic->ic_softc; 2003 int startall = 0; 2004 2005 RAL_LOCK(sc); 2006 if (ic->ic_nrunning> 0) { 2007 if (!(sc->sc_flags & RT2860_RUNNING)) { 2008 rt2860_init_locked(sc); 2009 startall = 1; 2010 } else 2011 rt2860_update_promisc(ic); 2012 } else if (sc->sc_flags & RT2860_RUNNING) 2013 rt2860_stop_locked(sc); 2014 RAL_UNLOCK(sc); 2015 if (startall) 2016 ieee80211_start_all(ic); 2017 } 2018 2019 /* 2020 * Reading and writing from/to the BBP is different from RT2560 and RT2661. 2021 * We access the BBP through the 8051 microcontroller unit which means that 2022 * the microcode must be loaded first. 2023 */ 2024 void 2025 rt2860_mcu_bbp_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2026 { 2027 int ntries; 2028 2029 for (ntries = 0; ntries < 100; ntries++) { 2030 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2031 break; 2032 DELAY(1); 2033 } 2034 if (ntries == 100) { 2035 device_printf(sc->sc_dev, 2036 "could not write to BBP through MCU\n"); 2037 return; 2038 } 2039 2040 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2041 RT2860_BBP_CSR_KICK | reg << 8 | val); 2042 RAL_BARRIER_WRITE(sc); 2043 2044 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2045 DELAY(1000); 2046 } 2047 2048 uint8_t 2049 rt2860_mcu_bbp_read(struct rt2860_softc *sc, uint8_t reg) 2050 { 2051 uint32_t val; 2052 int ntries; 2053 2054 for (ntries = 0; ntries < 100; ntries++) { 2055 if (!(RAL_READ(sc, RT2860_H2M_BBPAGENT) & RT2860_BBP_CSR_KICK)) 2056 break; 2057 DELAY(1); 2058 } 2059 if (ntries == 100) { 2060 device_printf(sc->sc_dev, 2061 "could not read from BBP through MCU\n"); 2062 return 0; 2063 } 2064 2065 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, RT2860_BBP_RW_PARALLEL | 2066 RT2860_BBP_CSR_KICK | RT2860_BBP_CSR_READ | reg << 8); 2067 RAL_BARRIER_WRITE(sc); 2068 2069 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_BBP, 0, 0); 2070 DELAY(1000); 2071 2072 for (ntries = 0; ntries < 100; ntries++) { 2073 val = RAL_READ(sc, RT2860_H2M_BBPAGENT); 2074 if (!(val & RT2860_BBP_CSR_KICK)) 2075 return val & 0xff; 2076 DELAY(1); 2077 } 2078 device_printf(sc->sc_dev, "could not read from BBP through MCU\n"); 2079 2080 return 0; 2081 } 2082 2083 /* 2084 * Write to one of the 4 programmable 24-bit RF registers. 2085 */ 2086 static void 2087 rt2860_rf_write(struct rt2860_softc *sc, uint8_t reg, uint32_t val) 2088 { 2089 uint32_t tmp; 2090 int ntries; 2091 2092 for (ntries = 0; ntries < 100; ntries++) { 2093 if (!(RAL_READ(sc, RT2860_RF_CSR_CFG0) & RT2860_RF_REG_CTRL)) 2094 break; 2095 DELAY(1); 2096 } 2097 if (ntries == 100) { 2098 device_printf(sc->sc_dev, "could not write to RF\n"); 2099 return; 2100 } 2101 2102 /* RF registers are 24-bit on the RT2860 */ 2103 tmp = RT2860_RF_REG_CTRL | 24 << RT2860_RF_REG_WIDTH_SHIFT | 2104 (val & 0x3fffff) << 2 | (reg & 3); 2105 RAL_WRITE(sc, RT2860_RF_CSR_CFG0, tmp); 2106 } 2107 2108 static uint8_t 2109 rt3090_rf_read(struct rt2860_softc *sc, uint8_t reg) 2110 { 2111 uint32_t tmp; 2112 int ntries; 2113 2114 for (ntries = 0; ntries < 100; ntries++) { 2115 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2116 break; 2117 DELAY(1); 2118 } 2119 if (ntries == 100) { 2120 device_printf(sc->sc_dev, "could not read RF register\n"); 2121 return 0xff; 2122 } 2123 tmp = RT3070_RF_KICK | reg << 8; 2124 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2125 2126 for (ntries = 0; ntries < 100; ntries++) { 2127 tmp = RAL_READ(sc, RT3070_RF_CSR_CFG); 2128 if (!(tmp & RT3070_RF_KICK)) 2129 break; 2130 DELAY(1); 2131 } 2132 if (ntries == 100) { 2133 device_printf(sc->sc_dev, "could not read RF register\n"); 2134 return 0xff; 2135 } 2136 return tmp & 0xff; 2137 } 2138 2139 void 2140 rt3090_rf_write(struct rt2860_softc *sc, uint8_t reg, uint8_t val) 2141 { 2142 uint32_t tmp; 2143 int ntries; 2144 2145 for (ntries = 0; ntries < 10; ntries++) { 2146 if (!(RAL_READ(sc, RT3070_RF_CSR_CFG) & RT3070_RF_KICK)) 2147 break; 2148 DELAY(10); 2149 } 2150 if (ntries == 10) { 2151 device_printf(sc->sc_dev, "could not write to RF\n"); 2152 return; 2153 } 2154 2155 tmp = RT3070_RF_WRITE | RT3070_RF_KICK | reg << 8 | val; 2156 RAL_WRITE(sc, RT3070_RF_CSR_CFG, tmp); 2157 } 2158 2159 /* 2160 * Send a command to the 8051 microcontroller unit. 2161 */ 2162 int 2163 rt2860_mcu_cmd(struct rt2860_softc *sc, uint8_t cmd, uint16_t arg, int wait) 2164 { 2165 int slot, ntries; 2166 uint32_t tmp; 2167 uint8_t cid; 2168 2169 for (ntries = 0; ntries < 100; ntries++) { 2170 if (!(RAL_READ(sc, RT2860_H2M_MAILBOX) & RT2860_H2M_BUSY)) 2171 break; 2172 DELAY(2); 2173 } 2174 if (ntries == 100) 2175 return EIO; 2176 2177 cid = wait ? cmd : RT2860_TOKEN_NO_INTR; 2178 RAL_WRITE(sc, RT2860_H2M_MAILBOX, RT2860_H2M_BUSY | cid << 16 | arg); 2179 RAL_BARRIER_WRITE(sc); 2180 RAL_WRITE(sc, RT2860_HOST_CMD, cmd); 2181 2182 if (!wait) 2183 return 0; 2184 /* wait for the command to complete */ 2185 for (ntries = 0; ntries < 200; ntries++) { 2186 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_CID); 2187 /* find the command slot */ 2188 for (slot = 0; slot < 4; slot++, tmp >>= 8) 2189 if ((tmp & 0xff) == cid) 2190 break; 2191 if (slot < 4) 2192 break; 2193 DELAY(100); 2194 } 2195 if (ntries == 200) { 2196 /* clear command and status */ 2197 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2198 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2199 return ETIMEDOUT; 2200 } 2201 /* get command status (1 means success) */ 2202 tmp = RAL_READ(sc, RT2860_H2M_MAILBOX_STATUS); 2203 tmp = (tmp >> (slot * 8)) & 0xff; 2204 DPRINTF(("MCU command=0x%02x slot=%d status=0x%02x\n", 2205 cmd, slot, tmp)); 2206 /* clear command and status */ 2207 RAL_WRITE(sc, RT2860_H2M_MAILBOX_STATUS, 0xffffffff); 2208 RAL_WRITE(sc, RT2860_H2M_MAILBOX_CID, 0xffffffff); 2209 return (tmp == 1) ? 0 : EIO; 2210 } 2211 2212 static void 2213 rt2860_enable_mrr(struct rt2860_softc *sc) 2214 { 2215 #define CCK(mcs) (mcs) 2216 #define OFDM(mcs) (1U << 3 | (mcs)) 2217 RAL_WRITE(sc, RT2860_LG_FBK_CFG0, 2218 OFDM(6) << 28 | /* 54->48 */ 2219 OFDM(5) << 24 | /* 48->36 */ 2220 OFDM(4) << 20 | /* 36->24 */ 2221 OFDM(3) << 16 | /* 24->18 */ 2222 OFDM(2) << 12 | /* 18->12 */ 2223 OFDM(1) << 8 | /* 12-> 9 */ 2224 OFDM(0) << 4 | /* 9-> 6 */ 2225 OFDM(0)); /* 6-> 6 */ 2226 2227 RAL_WRITE(sc, RT2860_LG_FBK_CFG1, 2228 CCK(2) << 12 | /* 11->5.5 */ 2229 CCK(1) << 8 | /* 5.5-> 2 */ 2230 CCK(0) << 4 | /* 2-> 1 */ 2231 CCK(0)); /* 1-> 1 */ 2232 #undef OFDM 2233 #undef CCK 2234 } 2235 2236 static void 2237 rt2860_set_txpreamble(struct rt2860_softc *sc) 2238 { 2239 struct ieee80211com *ic = &sc->sc_ic; 2240 uint32_t tmp; 2241 2242 tmp = RAL_READ(sc, RT2860_AUTO_RSP_CFG); 2243 tmp &= ~RT2860_CCK_SHORT_EN; 2244 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 2245 tmp |= RT2860_CCK_SHORT_EN; 2246 RAL_WRITE(sc, RT2860_AUTO_RSP_CFG, tmp); 2247 } 2248 2249 void 2250 rt2860_set_basicrates(struct rt2860_softc *sc, 2251 const struct ieee80211_rateset *rs) 2252 { 2253 struct ieee80211com *ic = &sc->sc_ic; 2254 uint32_t mask = 0; 2255 uint8_t rate; 2256 int i; 2257 2258 for (i = 0; i < rs->rs_nrates; i++) { 2259 rate = rs->rs_rates[i]; 2260 2261 if (!(rate & IEEE80211_RATE_BASIC)) 2262 continue; 2263 2264 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 2265 IEEE80211_RV(rate)); 2266 } 2267 2268 RAL_WRITE(sc, RT2860_LEGACY_BASIC_RATE, mask); 2269 } 2270 2271 static void 2272 rt2860_scan_start(struct ieee80211com *ic) 2273 { 2274 struct rt2860_softc *sc = ic->ic_softc; 2275 uint32_t tmp; 2276 2277 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 2278 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, 2279 tmp & ~(RT2860_BCN_TX_EN | RT2860_TSF_TIMER_EN | 2280 RT2860_TBTT_TIMER_EN)); 2281 rt2860_set_gp_timer(sc, 0); 2282 } 2283 2284 static void 2285 rt2860_scan_end(struct ieee80211com *ic) 2286 { 2287 struct rt2860_softc *sc = ic->ic_softc; 2288 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2289 2290 if (vap->iv_state == IEEE80211_S_RUN) { 2291 rt2860_enable_tsf_sync(sc); 2292 rt2860_set_gp_timer(sc, 500); 2293 } 2294 } 2295 2296 static void 2297 rt2860_getradiocaps(struct ieee80211com *ic, int maxchans, int *nchans, 2298 struct ieee80211_channel chans[]) 2299 { 2300 struct rt2860_softc *sc = ic->ic_softc; 2301 uint8_t bands[IEEE80211_MODE_BYTES]; 2302 2303 memset(bands, 0, sizeof(bands)); 2304 setbit(bands, IEEE80211_MODE_11B); 2305 setbit(bands, IEEE80211_MODE_11G); 2306 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2307 2308 if (sc->rf_rev == RT2860_RF_2750 || sc->rf_rev == RT2860_RF_2850) { 2309 setbit(bands, IEEE80211_MODE_11A); 2310 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2311 rt2860_chan_5ghz, nitems(rt2860_chan_5ghz), bands, 0); 2312 } 2313 } 2314 2315 static void 2316 rt2860_set_channel(struct ieee80211com *ic) 2317 { 2318 struct rt2860_softc *sc = ic->ic_softc; 2319 2320 RAL_LOCK(sc); 2321 rt2860_switch_chan(sc, ic->ic_curchan); 2322 RAL_UNLOCK(sc); 2323 } 2324 2325 static void 2326 rt2860_select_chan_group(struct rt2860_softc *sc, int group) 2327 { 2328 uint32_t tmp; 2329 uint8_t agc; 2330 2331 rt2860_mcu_bbp_write(sc, 62, 0x37 - sc->lna[group]); 2332 rt2860_mcu_bbp_write(sc, 63, 0x37 - sc->lna[group]); 2333 rt2860_mcu_bbp_write(sc, 64, 0x37 - sc->lna[group]); 2334 rt2860_mcu_bbp_write(sc, 86, 0x00); 2335 2336 if (group == 0) { 2337 if (sc->ext_2ghz_lna) { 2338 rt2860_mcu_bbp_write(sc, 82, 0x62); 2339 rt2860_mcu_bbp_write(sc, 75, 0x46); 2340 } else { 2341 rt2860_mcu_bbp_write(sc, 82, 0x84); 2342 rt2860_mcu_bbp_write(sc, 75, 0x50); 2343 } 2344 } else { 2345 if (sc->ext_5ghz_lna) { 2346 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2347 rt2860_mcu_bbp_write(sc, 75, 0x46); 2348 } else { 2349 rt2860_mcu_bbp_write(sc, 82, 0xf2); 2350 rt2860_mcu_bbp_write(sc, 75, 0x50); 2351 } 2352 } 2353 2354 tmp = RAL_READ(sc, RT2860_TX_BAND_CFG); 2355 tmp &= ~(RT2860_5G_BAND_SEL_N | RT2860_5G_BAND_SEL_P); 2356 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N : RT2860_5G_BAND_SEL_P; 2357 RAL_WRITE(sc, RT2860_TX_BAND_CFG, tmp); 2358 2359 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */ 2360 tmp = RT2860_RFTR_EN | RT2860_TRSW_EN | RT2860_LNA_PE0_EN; 2361 if (sc->nrxchains > 1) 2362 tmp |= RT2860_LNA_PE1_EN; 2363 if (sc->mac_ver == 0x3593 && sc->nrxchains > 2) 2364 tmp |= RT3593_LNA_PE2_EN; 2365 if (group == 0) { /* 2GHz */ 2366 tmp |= RT2860_PA_PE_G0_EN; 2367 if (sc->ntxchains > 1) 2368 tmp |= RT2860_PA_PE_G1_EN; 2369 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2370 tmp |= RT3593_PA_PE_G2_EN; 2371 } else { /* 5GHz */ 2372 tmp |= RT2860_PA_PE_A0_EN; 2373 if (sc->ntxchains > 1) 2374 tmp |= RT2860_PA_PE_A1_EN; 2375 if (sc->mac_ver == 0x3593 && sc->ntxchains > 2) 2376 tmp |= RT3593_PA_PE_A2_EN; 2377 } 2378 RAL_WRITE(sc, RT2860_TX_PIN_CFG, tmp); 2379 2380 if (sc->mac_ver == 0x3593) { 2381 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 2382 if (sc->sc_flags & RT2860_PCIE) { 2383 tmp &= ~0x01010000; 2384 if (group == 0) 2385 tmp |= 0x00010000; 2386 } else { 2387 tmp &= ~0x00008080; 2388 if (group == 0) 2389 tmp |= 0x00000080; 2390 } 2391 tmp = (tmp & ~0x00001000) | 0x00000010; 2392 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp); 2393 } 2394 2395 /* set initial AGC value */ 2396 if (group == 0) { /* 2GHz band */ 2397 if (sc->mac_ver >= 0x3071) 2398 agc = 0x1c + sc->lna[0] * 2; 2399 else 2400 agc = 0x2e + sc->lna[0]; 2401 } else { /* 5GHz band */ 2402 agc = 0x32 + (sc->lna[group] * 5) / 3; 2403 } 2404 rt2860_mcu_bbp_write(sc, 66, agc); 2405 2406 DELAY(1000); 2407 } 2408 2409 static void 2410 rt2860_set_chan(struct rt2860_softc *sc, u_int chan) 2411 { 2412 const struct rfprog *rfprog = rt2860_rf2850; 2413 uint32_t r2, r3, r4; 2414 int8_t txpow1, txpow2; 2415 u_int i; 2416 2417 /* find the settings for this channel (we know it exists) */ 2418 for (i = 0; rfprog[i].chan != chan; i++); 2419 2420 r2 = rfprog[i].r2; 2421 if (sc->ntxchains == 1) 2422 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */ 2423 if (sc->nrxchains == 1) 2424 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */ 2425 else if (sc->nrxchains == 2) 2426 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */ 2427 2428 /* use Tx power values from EEPROM */ 2429 txpow1 = sc->txpow1[i]; 2430 txpow2 = sc->txpow2[i]; 2431 if (chan > 14) { 2432 if (txpow1 >= 0) 2433 txpow1 = txpow1 << 1 | 1; 2434 else 2435 txpow1 = (7 + txpow1) << 1; 2436 if (txpow2 >= 0) 2437 txpow2 = txpow2 << 1 | 1; 2438 else 2439 txpow2 = (7 + txpow2) << 1; 2440 } 2441 r3 = rfprog[i].r3 | txpow1 << 7; 2442 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4; 2443 2444 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2445 rt2860_rf_write(sc, RT2860_RF2, r2); 2446 rt2860_rf_write(sc, RT2860_RF3, r3); 2447 rt2860_rf_write(sc, RT2860_RF4, r4); 2448 2449 DELAY(200); 2450 2451 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2452 rt2860_rf_write(sc, RT2860_RF2, r2); 2453 rt2860_rf_write(sc, RT2860_RF3, r3 | 1); 2454 rt2860_rf_write(sc, RT2860_RF4, r4); 2455 2456 DELAY(200); 2457 2458 rt2860_rf_write(sc, RT2860_RF1, rfprog[i].r1); 2459 rt2860_rf_write(sc, RT2860_RF2, r2); 2460 rt2860_rf_write(sc, RT2860_RF3, r3); 2461 rt2860_rf_write(sc, RT2860_RF4, r4); 2462 } 2463 2464 static void 2465 rt3090_set_chan(struct rt2860_softc *sc, u_int chan) 2466 { 2467 int8_t txpow1, txpow2; 2468 uint8_t rf; 2469 int i; 2470 2471 /* RT3090 is 2GHz only */ 2472 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2473 2474 /* find the settings for this channel (we know it exists) */ 2475 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2476 2477 /* use Tx power values from EEPROM */ 2478 txpow1 = sc->txpow1[i]; 2479 txpow2 = sc->txpow2[i]; 2480 2481 rt3090_rf_write(sc, 2, rt3090_freqs[i].n); 2482 rf = rt3090_rf_read(sc, 3); 2483 rf = (rf & ~0x0f) | rt3090_freqs[i].k; 2484 rt3090_rf_write(sc, 3, rf); 2485 rf = rt3090_rf_read(sc, 6); 2486 rf = (rf & ~0x03) | rt3090_freqs[i].r; 2487 rt3090_rf_write(sc, 6, rf); 2488 2489 /* set Tx0 power */ 2490 rf = rt3090_rf_read(sc, 12); 2491 rf = (rf & ~0x1f) | txpow1; 2492 rt3090_rf_write(sc, 12, rf); 2493 2494 /* set Tx1 power */ 2495 rf = rt3090_rf_read(sc, 13); 2496 rf = (rf & ~0x1f) | txpow2; 2497 rt3090_rf_write(sc, 13, rf); 2498 2499 rf = rt3090_rf_read(sc, 1); 2500 rf &= ~0xfc; 2501 if (sc->ntxchains == 1) 2502 rf |= RT3070_TX1_PD | RT3070_TX2_PD; 2503 else if (sc->ntxchains == 2) 2504 rf |= RT3070_TX2_PD; 2505 if (sc->nrxchains == 1) 2506 rf |= RT3070_RX1_PD | RT3070_RX2_PD; 2507 else if (sc->nrxchains == 2) 2508 rf |= RT3070_RX2_PD; 2509 rt3090_rf_write(sc, 1, rf); 2510 2511 /* set RF offset */ 2512 rf = rt3090_rf_read(sc, 23); 2513 rf = (rf & ~0x7f) | sc->freq; 2514 rt3090_rf_write(sc, 23, rf); 2515 2516 /* program RF filter */ 2517 rf = rt3090_rf_read(sc, 24); /* Tx */ 2518 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2519 rt3090_rf_write(sc, 24, rf); 2520 rf = rt3090_rf_read(sc, 31); /* Rx */ 2521 rf = (rf & ~0x3f) | sc->rf24_20mhz; 2522 rt3090_rf_write(sc, 31, rf); 2523 2524 /* enable RF tuning */ 2525 rf = rt3090_rf_read(sc, 7); 2526 rt3090_rf_write(sc, 7, rf | RT3070_TUNE); 2527 } 2528 2529 static void 2530 rt5390_set_chan(struct rt2860_softc *sc, u_int chan) 2531 { 2532 uint8_t h20mhz, rf, tmp; 2533 int8_t txpow1, txpow2; 2534 int i; 2535 2536 /* RT5390 is 2GHz only */ 2537 KASSERT(chan >= 1 && chan <= 14, ("chan %d not support", chan)); 2538 2539 /* find the settings for this channel (we know it exists) */ 2540 for (i = 0; rt2860_rf2850[i].chan != chan; i++); 2541 2542 /* use Tx power values from EEPROM */ 2543 txpow1 = sc->txpow1[i]; 2544 txpow2 = sc->txpow2[i]; 2545 2546 rt3090_rf_write(sc, 8, rt3090_freqs[i].n); 2547 rt3090_rf_write(sc, 9, rt3090_freqs[i].k & 0x0f); 2548 rf = rt3090_rf_read(sc, 11); 2549 rf = (rf & ~0x03) | (rt3090_freqs[i].r & 0x03); 2550 rt3090_rf_write(sc, 11, rf); 2551 2552 rf = rt3090_rf_read(sc, 49); 2553 rf = (rf & ~0x3f) | (txpow1 & 0x3f); 2554 /* the valid range of the RF R49 is 0x00~0x27 */ 2555 if ((rf & 0x3f) > 0x27) 2556 rf = (rf & ~0x3f) | 0x27; 2557 rt3090_rf_write(sc, 49, rf); 2558 if (sc->mac_ver == 0x5392) { 2559 rf = rt3090_rf_read(sc, 50); 2560 rf = (rf & ~0x3f) | (txpow2 & 0x3f); 2561 /* the valid range of the RF R50 is 0x00~0x27 */ 2562 if ((rf & 0x3f) > 0x27) 2563 rf = (rf & ~0x3f) | 0x27; 2564 rt3090_rf_write(sc, 50, rf); 2565 } 2566 2567 rf = rt3090_rf_read(sc, 1); 2568 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | RT3070_TX0_PD; 2569 if (sc->mac_ver == 0x5392) 2570 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2571 rt3090_rf_write(sc, 1, rf); 2572 2573 rf = rt3090_rf_read(sc, 2); 2574 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2575 DELAY(1000); 2576 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2577 2578 rf = rt3090_rf_read(sc, 17); 2579 tmp = rf; 2580 rf = (rf & ~0x7f) | (sc->freq & 0x7f); 2581 rf = MIN(rf, 0x5f); 2582 if (tmp != rf) 2583 rt2860_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf, 0); 2584 2585 if (sc->mac_ver == 0x5390) { 2586 if (chan <= 4) 2587 rf = 0x73; 2588 else if (chan >= 5 && chan <= 6) 2589 rf = 0x63; 2590 else if (chan >= 7 && chan <= 10) 2591 rf = 0x53; 2592 else 2593 rf = 43; 2594 rt3090_rf_write(sc, 55, rf); 2595 2596 if (chan == 1) 2597 rf = 0x0c; 2598 else if (chan == 2) 2599 rf = 0x0b; 2600 else if (chan == 3) 2601 rf = 0x0a; 2602 else if (chan >= 4 && chan <= 6) 2603 rf = 0x09; 2604 else if (chan >= 7 && chan <= 12) 2605 rf = 0x08; 2606 else if (chan == 13) 2607 rf = 0x07; 2608 else 2609 rf = 0x06; 2610 rt3090_rf_write(sc, 59, rf); 2611 } 2612 2613 /* Tx/Rx h20M */ 2614 h20mhz = (sc->rf24_20mhz & 0x20) >> 5; 2615 rf = rt3090_rf_read(sc, 30); 2616 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); 2617 rt3090_rf_write(sc, 30, rf); 2618 2619 /* Rx BB filter VCM */ 2620 rf = rt3090_rf_read(sc, 30); 2621 rf = (rf & ~0x18) | 0x10; 2622 rt3090_rf_write(sc, 30, rf); 2623 2624 /* Initiate VCO calibration. */ 2625 rf = rt3090_rf_read(sc, 3); 2626 rf |= RT3593_VCOCAL; 2627 rt3090_rf_write(sc, 3, rf); 2628 } 2629 2630 static int 2631 rt3090_rf_init(struct rt2860_softc *sc) 2632 { 2633 uint32_t tmp; 2634 uint8_t rf, bbp; 2635 int i; 2636 2637 rf = rt3090_rf_read(sc, 30); 2638 /* toggle RF R30 bit 7 */ 2639 rt3090_rf_write(sc, 30, rf | 0x80); 2640 DELAY(1000); 2641 rt3090_rf_write(sc, 30, rf & ~0x80); 2642 2643 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2644 tmp &= ~0x1f000000; 2645 if (sc->patch_dac && sc->mac_rev < 0x0211) 2646 tmp |= 0x0d000000; /* 1.35V */ 2647 else 2648 tmp |= 0x01000000; /* 1.2V */ 2649 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2650 2651 /* patch LNA_PE_G1 */ 2652 tmp = RAL_READ(sc, RT3070_GPIO_SWITCH); 2653 RAL_WRITE(sc, RT3070_GPIO_SWITCH, tmp & ~0x20); 2654 2655 /* initialize RF registers to default value */ 2656 for (i = 0; i < nitems(rt3090_def_rf); i++) { 2657 rt3090_rf_write(sc, rt3090_def_rf[i].reg, 2658 rt3090_def_rf[i].val); 2659 } 2660 2661 /* select 20MHz bandwidth */ 2662 rt3090_rf_write(sc, 31, 0x14); 2663 2664 rf = rt3090_rf_read(sc, 6); 2665 rt3090_rf_write(sc, 6, rf | 0x40); 2666 2667 if (sc->mac_ver != 0x3593) { 2668 /* calibrate filter for 20MHz bandwidth */ 2669 sc->rf24_20mhz = 0x1f; /* default value */ 2670 rt3090_filter_calib(sc, 0x07, 0x16, &sc->rf24_20mhz); 2671 2672 /* select 40MHz bandwidth */ 2673 bbp = rt2860_mcu_bbp_read(sc, 4); 2674 rt2860_mcu_bbp_write(sc, 4, (bbp & ~0x08) | 0x10); 2675 rf = rt3090_rf_read(sc, 31); 2676 rt3090_rf_write(sc, 31, rf | 0x20); 2677 2678 /* calibrate filter for 40MHz bandwidth */ 2679 sc->rf24_40mhz = 0x2f; /* default value */ 2680 rt3090_filter_calib(sc, 0x27, 0x19, &sc->rf24_40mhz); 2681 2682 /* go back to 20MHz bandwidth */ 2683 bbp = rt2860_mcu_bbp_read(sc, 4); 2684 rt2860_mcu_bbp_write(sc, 4, bbp & ~0x18); 2685 } 2686 if (sc->mac_rev < 0x0211) 2687 rt3090_rf_write(sc, 27, 0x03); 2688 2689 tmp = RAL_READ(sc, RT3070_OPT_14); 2690 RAL_WRITE(sc, RT3070_OPT_14, tmp | 1); 2691 2692 if (sc->rf_rev == RT3070_RF_3020) 2693 rt3090_set_rx_antenna(sc, 0); 2694 2695 bbp = rt2860_mcu_bbp_read(sc, 138); 2696 if (sc->mac_ver == 0x3593) { 2697 if (sc->ntxchains == 1) 2698 bbp |= 0x60; /* turn off DAC1 and DAC2 */ 2699 else if (sc->ntxchains == 2) 2700 bbp |= 0x40; /* turn off DAC2 */ 2701 if (sc->nrxchains == 1) 2702 bbp &= ~0x06; /* turn off ADC1 and ADC2 */ 2703 else if (sc->nrxchains == 2) 2704 bbp &= ~0x04; /* turn off ADC2 */ 2705 } else { 2706 if (sc->ntxchains == 1) 2707 bbp |= 0x20; /* turn off DAC1 */ 2708 if (sc->nrxchains == 1) 2709 bbp &= ~0x02; /* turn off ADC1 */ 2710 } 2711 rt2860_mcu_bbp_write(sc, 138, bbp); 2712 2713 rf = rt3090_rf_read(sc, 1); 2714 rf &= ~(RT3070_RX0_PD | RT3070_TX0_PD); 2715 rf |= RT3070_RF_BLOCK | RT3070_RX1_PD | RT3070_TX1_PD; 2716 rt3090_rf_write(sc, 1, rf); 2717 2718 rf = rt3090_rf_read(sc, 15); 2719 rt3090_rf_write(sc, 15, rf & ~RT3070_TX_LO2); 2720 2721 rf = rt3090_rf_read(sc, 17); 2722 rf &= ~RT3070_TX_LO1; 2723 if (sc->mac_rev >= 0x0211 && !sc->ext_2ghz_lna) 2724 rf |= 0x20; /* fix for long range Rx issue */ 2725 if (sc->txmixgain_2ghz >= 2) 2726 rf = (rf & ~0x7) | sc->txmixgain_2ghz; 2727 rt3090_rf_write(sc, 17, rf); 2728 2729 rf = rt3090_rf_read(sc, 20); 2730 rt3090_rf_write(sc, 20, rf & ~RT3070_RX_LO1); 2731 2732 rf = rt3090_rf_read(sc, 21); 2733 rt3090_rf_write(sc, 21, rf & ~RT3070_RX_LO2); 2734 2735 return (0); 2736 } 2737 2738 static void 2739 rt5390_rf_init(struct rt2860_softc *sc) 2740 { 2741 uint8_t rf, bbp; 2742 int i; 2743 2744 rf = rt3090_rf_read(sc, 2); 2745 /* Toggle RF R2 bit 7. */ 2746 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2747 DELAY(1000); 2748 rt3090_rf_write(sc, 2, rf & ~RT3593_RESCAL); 2749 2750 /* Initialize RF registers to default value. */ 2751 if (sc->mac_ver == 0x5392) { 2752 for (i = 0; i < nitems(rt5392_def_rf); i++) { 2753 rt3090_rf_write(sc, rt5392_def_rf[i].reg, 2754 rt5392_def_rf[i].val); 2755 } 2756 } else { 2757 for (i = 0; i < nitems(rt5390_def_rf); i++) { 2758 rt3090_rf_write(sc, rt5390_def_rf[i].reg, 2759 rt5390_def_rf[i].val); 2760 } 2761 } 2762 2763 sc->rf24_20mhz = 0x1f; 2764 sc->rf24_40mhz = 0x2f; 2765 2766 if (sc->mac_rev < 0x0211) 2767 rt3090_rf_write(sc, 27, 0x03); 2768 2769 /* Set led open drain enable. */ 2770 RAL_WRITE(sc, RT3070_OPT_14, RAL_READ(sc, RT3070_OPT_14) | 1); 2771 2772 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2773 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2774 2775 if (sc->mac_ver == 0x5390) 2776 rt3090_set_rx_antenna(sc, 0); 2777 2778 /* Patch RSSI inaccurate issue. */ 2779 rt2860_mcu_bbp_write(sc, 79, 0x13); 2780 rt2860_mcu_bbp_write(sc, 80, 0x05); 2781 rt2860_mcu_bbp_write(sc, 81, 0x33); 2782 2783 /* Enable DC filter. */ 2784 if (sc->mac_rev >= 0x0211) 2785 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2786 2787 bbp = rt2860_mcu_bbp_read(sc, 138); 2788 if (sc->ntxchains == 1) 2789 bbp |= 0x20; /* Turn off DAC1. */ 2790 if (sc->nrxchains == 1) 2791 bbp &= ~0x02; /* Turn off ADC1. */ 2792 rt2860_mcu_bbp_write(sc, 138, bbp); 2793 2794 /* Enable RX LO1 and LO2. */ 2795 rt3090_rf_write(sc, 38, rt3090_rf_read(sc, 38) & ~RT5390_RX_LO1); 2796 rt3090_rf_write(sc, 39, rt3090_rf_read(sc, 39) & ~RT5390_RX_LO2); 2797 2798 /* Avoid data lost and CRC error. */ 2799 rt2860_mcu_bbp_write(sc, 4, 2800 rt2860_mcu_bbp_read(sc, 4) | RT5390_MAC_IF_CTRL); 2801 2802 rf = rt3090_rf_read(sc, 30); 2803 rf = (rf & ~0x18) | 0x10; 2804 rt3090_rf_write(sc, 30, rf); 2805 } 2806 2807 static void 2808 rt3090_rf_wakeup(struct rt2860_softc *sc) 2809 { 2810 uint32_t tmp; 2811 uint8_t rf; 2812 2813 if (sc->mac_ver == 0x3593) { 2814 /* enable VCO */ 2815 rf = rt3090_rf_read(sc, 1); 2816 rt3090_rf_write(sc, 1, rf | RT3593_VCO); 2817 2818 /* initiate VCO calibration */ 2819 rf = rt3090_rf_read(sc, 3); 2820 rt3090_rf_write(sc, 3, rf | RT3593_VCOCAL); 2821 2822 /* enable VCO bias current control */ 2823 rf = rt3090_rf_read(sc, 6); 2824 rt3090_rf_write(sc, 6, rf | RT3593_VCO_IC); 2825 2826 /* initiate res calibration */ 2827 rf = rt3090_rf_read(sc, 2); 2828 rt3090_rf_write(sc, 2, rf | RT3593_RESCAL); 2829 2830 /* set reference current control to 0.33 mA */ 2831 rf = rt3090_rf_read(sc, 22); 2832 rf &= ~RT3593_CP_IC_MASK; 2833 rf |= 1 << RT3593_CP_IC_SHIFT; 2834 rt3090_rf_write(sc, 22, rf); 2835 2836 /* enable RX CTB */ 2837 rf = rt3090_rf_read(sc, 46); 2838 rt3090_rf_write(sc, 46, rf | RT3593_RX_CTB); 2839 2840 rf = rt3090_rf_read(sc, 20); 2841 rf &= ~(RT3593_LDO_RF_VC_MASK | RT3593_LDO_PLL_VC_MASK); 2842 rt3090_rf_write(sc, 20, rf); 2843 } else { 2844 /* enable RF block */ 2845 rf = rt3090_rf_read(sc, 1); 2846 rt3090_rf_write(sc, 1, rf | RT3070_RF_BLOCK); 2847 2848 /* enable VCO bias current control */ 2849 rf = rt3090_rf_read(sc, 7); 2850 rt3090_rf_write(sc, 7, rf | 0x30); 2851 2852 rf = rt3090_rf_read(sc, 9); 2853 rt3090_rf_write(sc, 9, rf | 0x0e); 2854 2855 /* enable RX CTB */ 2856 rf = rt3090_rf_read(sc, 21); 2857 rt3090_rf_write(sc, 21, rf | RT3070_RX_CTB); 2858 2859 /* fix Tx to Rx IQ glitch by raising RF voltage */ 2860 rf = rt3090_rf_read(sc, 27); 2861 rf &= ~0x77; 2862 if (sc->mac_rev < 0x0211) 2863 rf |= 0x03; 2864 rt3090_rf_write(sc, 27, rf); 2865 } 2866 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2867 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2868 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2869 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2870 } 2871 } 2872 2873 static void 2874 rt5390_rf_wakeup(struct rt2860_softc *sc) 2875 { 2876 uint32_t tmp; 2877 uint8_t rf; 2878 2879 rf = rt3090_rf_read(sc, 1); 2880 rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD | 2881 RT3070_TX0_PD; 2882 if (sc->mac_ver == 0x5392) 2883 rf |= RT3070_RX1_PD | RT3070_TX1_PD; 2884 rt3090_rf_write(sc, 1, rf); 2885 2886 rf = rt3090_rf_read(sc, 6); 2887 rf |= RT3593_VCO_IC | RT3593_VCOCAL; 2888 if (sc->mac_ver == 0x5390) 2889 rf &= ~RT3593_VCO_IC; 2890 rt3090_rf_write(sc, 6, rf); 2891 2892 rt3090_rf_write(sc, 2, rt3090_rf_read(sc, 2) | RT3593_RESCAL); 2893 2894 rf = rt3090_rf_read(sc, 22); 2895 rf = (rf & ~0xe0) | 0x20; 2896 rt3090_rf_write(sc, 22, rf); 2897 2898 rt3090_rf_write(sc, 42, rt3090_rf_read(sc, 42) | RT5390_RX_CTB); 2899 rt3090_rf_write(sc, 20, rt3090_rf_read(sc, 20) & ~0x77); 2900 rt3090_rf_write(sc, 3, rt3090_rf_read(sc, 3) | RT3593_VCOCAL); 2901 2902 if (sc->patch_dac && sc->mac_rev < 0x0211) { 2903 tmp = RAL_READ(sc, RT3070_LDO_CFG0); 2904 tmp = (tmp & ~0x1f000000) | 0x0d000000; 2905 RAL_WRITE(sc, RT3070_LDO_CFG0, tmp); 2906 } 2907 } 2908 2909 static int 2910 rt3090_filter_calib(struct rt2860_softc *sc, uint8_t init, uint8_t target, 2911 uint8_t *val) 2912 { 2913 uint8_t rf22, rf24; 2914 uint8_t bbp55_pb, bbp55_sb, delta; 2915 int ntries; 2916 2917 /* program filter */ 2918 rf24 = rt3090_rf_read(sc, 24); 2919 rf24 = (rf24 & 0xc0) | init; /* initial filter value */ 2920 rt3090_rf_write(sc, 24, rf24); 2921 2922 /* enable baseband loopback mode */ 2923 rf22 = rt3090_rf_read(sc, 22); 2924 rt3090_rf_write(sc, 22, rf22 | RT3070_BB_LOOPBACK); 2925 2926 /* set power and frequency of passband test tone */ 2927 rt2860_mcu_bbp_write(sc, 24, 0x00); 2928 for (ntries = 0; ntries < 100; ntries++) { 2929 /* transmit test tone */ 2930 rt2860_mcu_bbp_write(sc, 25, 0x90); 2931 DELAY(1000); 2932 /* read received power */ 2933 bbp55_pb = rt2860_mcu_bbp_read(sc, 55); 2934 if (bbp55_pb != 0) 2935 break; 2936 } 2937 if (ntries == 100) 2938 return (ETIMEDOUT); 2939 2940 /* set power and frequency of stopband test tone */ 2941 rt2860_mcu_bbp_write(sc, 24, 0x06); 2942 for (ntries = 0; ntries < 100; ntries++) { 2943 /* transmit test tone */ 2944 rt2860_mcu_bbp_write(sc, 25, 0x90); 2945 DELAY(1000); 2946 /* read received power */ 2947 bbp55_sb = rt2860_mcu_bbp_read(sc, 55); 2948 2949 delta = bbp55_pb - bbp55_sb; 2950 if (delta > target) 2951 break; 2952 2953 /* reprogram filter */ 2954 rf24++; 2955 rt3090_rf_write(sc, 24, rf24); 2956 } 2957 if (ntries < 100) { 2958 if (rf24 != init) 2959 rf24--; /* backtrack */ 2960 *val = rf24; 2961 rt3090_rf_write(sc, 24, rf24); 2962 } 2963 2964 /* restore initial state */ 2965 rt2860_mcu_bbp_write(sc, 24, 0x00); 2966 2967 /* disable baseband loopback mode */ 2968 rf22 = rt3090_rf_read(sc, 22); 2969 rt3090_rf_write(sc, 22, rf22 & ~RT3070_BB_LOOPBACK); 2970 2971 return (0); 2972 } 2973 2974 static void 2975 rt3090_rf_setup(struct rt2860_softc *sc) 2976 { 2977 uint8_t bbp; 2978 int i; 2979 2980 if (sc->mac_rev >= 0x0211) { 2981 /* enable DC filter */ 2982 rt2860_mcu_bbp_write(sc, 103, 0xc0); 2983 2984 /* improve power consumption */ 2985 bbp = rt2860_mcu_bbp_read(sc, 31); 2986 rt2860_mcu_bbp_write(sc, 31, bbp & ~0x03); 2987 } 2988 2989 RAL_WRITE(sc, RT2860_TX_SW_CFG1, 0); 2990 if (sc->mac_rev < 0x0211) { 2991 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 2992 sc->patch_dac ? 0x2c : 0x0f); 2993 } else 2994 RAL_WRITE(sc, RT2860_TX_SW_CFG2, 0); 2995 2996 /* initialize RF registers from ROM */ 2997 if (sc->mac_ver < 0x5390) { 2998 for (i = 0; i < 10; i++) { 2999 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff) 3000 continue; 3001 rt3090_rf_write(sc, sc->rf[i].reg, sc->rf[i].val); 3002 } 3003 } 3004 } 3005 3006 static void 3007 rt2860_set_leds(struct rt2860_softc *sc, uint16_t which) 3008 { 3009 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LEDS, 3010 which | (sc->leds & 0x7f), 0); 3011 } 3012 3013 /* 3014 * Hardware has a general-purpose programmable timer interrupt that can 3015 * periodically raise MAC_INT_4. 3016 */ 3017 static void 3018 rt2860_set_gp_timer(struct rt2860_softc *sc, int ms) 3019 { 3020 uint32_t tmp; 3021 3022 /* disable GP timer before reprogramming it */ 3023 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3024 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp & ~RT2860_GP_TIMER_EN); 3025 3026 if (ms == 0) 3027 return; 3028 3029 tmp = RAL_READ(sc, RT2860_INT_TIMER_CFG); 3030 ms *= 16; /* Unit: 64us */ 3031 tmp = (tmp & 0xffff) | ms << RT2860_GP_TIMER_SHIFT; 3032 RAL_WRITE(sc, RT2860_INT_TIMER_CFG, tmp); 3033 3034 /* enable GP timer */ 3035 tmp = RAL_READ(sc, RT2860_INT_TIMER_EN); 3036 RAL_WRITE(sc, RT2860_INT_TIMER_EN, tmp | RT2860_GP_TIMER_EN); 3037 } 3038 3039 static void 3040 rt2860_set_bssid(struct rt2860_softc *sc, const uint8_t *bssid) 3041 { 3042 RAL_WRITE(sc, RT2860_MAC_BSSID_DW0, 3043 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24); 3044 RAL_WRITE(sc, RT2860_MAC_BSSID_DW1, 3045 bssid[4] | bssid[5] << 8); 3046 } 3047 3048 static void 3049 rt2860_set_macaddr(struct rt2860_softc *sc, const uint8_t *addr) 3050 { 3051 RAL_WRITE(sc, RT2860_MAC_ADDR_DW0, 3052 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 3053 RAL_WRITE(sc, RT2860_MAC_ADDR_DW1, 3054 addr[4] | addr[5] << 8 | 0xff << 16); 3055 } 3056 3057 static void 3058 rt2860_updateslot(struct ieee80211com *ic) 3059 { 3060 struct rt2860_softc *sc = ic->ic_softc; 3061 uint32_t tmp; 3062 3063 tmp = RAL_READ(sc, RT2860_BKOFF_SLOT_CFG); 3064 tmp &= ~0xff; 3065 tmp |= IEEE80211_GET_SLOTTIME(ic); 3066 RAL_WRITE(sc, RT2860_BKOFF_SLOT_CFG, tmp); 3067 } 3068 3069 static void 3070 rt2860_updateprot(struct rt2860_softc *sc) 3071 { 3072 struct ieee80211com *ic = &sc->sc_ic; 3073 uint32_t tmp; 3074 3075 tmp = RT2860_RTSTH_EN | RT2860_PROT_NAV_SHORT | RT2860_TXOP_ALLOW_ALL; 3076 /* setup protection frame rate (MCS code) */ 3077 tmp |= IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 3078 rt2860_rates[RT2860_RIDX_OFDM6].mcs : 3079 rt2860_rates[RT2860_RIDX_CCK11].mcs; 3080 3081 /* CCK frames don't require protection */ 3082 RAL_WRITE(sc, RT2860_CCK_PROT_CFG, tmp); 3083 3084 if (ic->ic_flags & IEEE80211_F_USEPROT) { 3085 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3086 tmp |= RT2860_PROT_CTRL_RTS_CTS; 3087 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3088 tmp |= RT2860_PROT_CTRL_CTS; 3089 } 3090 RAL_WRITE(sc, RT2860_OFDM_PROT_CFG, tmp); 3091 } 3092 3093 static void 3094 rt2860_update_promisc(struct ieee80211com *ic) 3095 { 3096 struct rt2860_softc *sc = ic->ic_softc; 3097 uint32_t tmp; 3098 3099 tmp = RAL_READ(sc, RT2860_RX_FILTR_CFG); 3100 tmp &= ~RT2860_DROP_NOT_MYBSS; 3101 if (ic->ic_promisc == 0) 3102 tmp |= RT2860_DROP_NOT_MYBSS; 3103 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3104 } 3105 3106 static int 3107 rt2860_updateedca(struct ieee80211com *ic) 3108 { 3109 struct rt2860_softc *sc = ic->ic_softc; 3110 struct chanAccParams chp; 3111 const struct wmeParams *wmep; 3112 int aci; 3113 3114 ieee80211_wme_ic_getparams(ic, &chp); 3115 3116 wmep = chp.cap_wmeParams; 3117 3118 /* update MAC TX configuration registers */ 3119 for (aci = 0; aci < WME_NUM_AC; aci++) { 3120 RAL_WRITE(sc, RT2860_EDCA_AC_CFG(aci), 3121 wmep[aci].wmep_logcwmax << 16 | 3122 wmep[aci].wmep_logcwmin << 12 | 3123 wmep[aci].wmep_aifsn << 8 | 3124 wmep[aci].wmep_txopLimit); 3125 } 3126 3127 /* update SCH/DMA registers too */ 3128 RAL_WRITE(sc, RT2860_WMM_AIFSN_CFG, 3129 wmep[WME_AC_VO].wmep_aifsn << 12 | 3130 wmep[WME_AC_VI].wmep_aifsn << 8 | 3131 wmep[WME_AC_BK].wmep_aifsn << 4 | 3132 wmep[WME_AC_BE].wmep_aifsn); 3133 RAL_WRITE(sc, RT2860_WMM_CWMIN_CFG, 3134 wmep[WME_AC_VO].wmep_logcwmin << 12 | 3135 wmep[WME_AC_VI].wmep_logcwmin << 8 | 3136 wmep[WME_AC_BK].wmep_logcwmin << 4 | 3137 wmep[WME_AC_BE].wmep_logcwmin); 3138 RAL_WRITE(sc, RT2860_WMM_CWMAX_CFG, 3139 wmep[WME_AC_VO].wmep_logcwmax << 12 | 3140 wmep[WME_AC_VI].wmep_logcwmax << 8 | 3141 wmep[WME_AC_BK].wmep_logcwmax << 4 | 3142 wmep[WME_AC_BE].wmep_logcwmax); 3143 RAL_WRITE(sc, RT2860_WMM_TXOP0_CFG, 3144 wmep[WME_AC_BK].wmep_txopLimit << 16 | 3145 wmep[WME_AC_BE].wmep_txopLimit); 3146 RAL_WRITE(sc, RT2860_WMM_TXOP1_CFG, 3147 wmep[WME_AC_VO].wmep_txopLimit << 16 | 3148 wmep[WME_AC_VI].wmep_txopLimit); 3149 3150 return 0; 3151 } 3152 3153 #ifdef HW_CRYPTO 3154 static int 3155 rt2860_set_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3156 struct ieee80211_key *k) 3157 { 3158 struct rt2860_softc *sc = ic->ic_softc; 3159 bus_size_t base; 3160 uint32_t attr; 3161 uint8_t mode, wcid, iv[8]; 3162 3163 /* defer setting of WEP keys until interface is brought up */ 3164 if ((ic->ic_if.if_flags & (IFF_UP | IFF_RUNNING)) != 3165 (IFF_UP | IFF_RUNNING)) 3166 return 0; 3167 3168 /* map net80211 cipher to RT2860 security mode */ 3169 switch (k->k_cipher) { 3170 case IEEE80211_CIPHER_WEP40: 3171 mode = RT2860_MODE_WEP40; 3172 break; 3173 case IEEE80211_CIPHER_WEP104: 3174 mode = RT2860_MODE_WEP104; 3175 break; 3176 case IEEE80211_CIPHER_TKIP: 3177 mode = RT2860_MODE_TKIP; 3178 break; 3179 case IEEE80211_CIPHER_CCMP: 3180 mode = RT2860_MODE_AES_CCMP; 3181 break; 3182 default: 3183 return EINVAL; 3184 } 3185 3186 if (k->k_flags & IEEE80211_KEY_GROUP) { 3187 wcid = 0; /* NB: update WCID0 for group keys */ 3188 base = RT2860_SKEY(0, k->k_id); 3189 } else { 3190 wcid = ((struct rt2860_node *)ni)->wcid; 3191 base = RT2860_PKEY(wcid); 3192 } 3193 3194 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3195 RAL_WRITE_REGION_1(sc, base, k->k_key, 16); 3196 #ifndef IEEE80211_STA_ONLY 3197 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 3198 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[16], 8); 3199 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[24], 8); 3200 } else 3201 #endif 3202 { 3203 RAL_WRITE_REGION_1(sc, base + 16, &k->k_key[24], 8); 3204 RAL_WRITE_REGION_1(sc, base + 24, &k->k_key[16], 8); 3205 } 3206 } else 3207 RAL_WRITE_REGION_1(sc, base, k->k_key, k->k_len); 3208 3209 if (!(k->k_flags & IEEE80211_KEY_GROUP) || 3210 (k->k_flags & IEEE80211_KEY_TX)) { 3211 /* set initial packet number in IV+EIV */ 3212 if (k->k_cipher == IEEE80211_CIPHER_WEP40 || 3213 k->k_cipher == IEEE80211_CIPHER_WEP104) { 3214 uint32_t val = arc4random(); 3215 /* skip weak IVs from Fluhrer/Mantin/Shamir */ 3216 if (val >= 0x03ff00 && (val & 0xf8ff00) == 0x00ff00) 3217 val += 0x000100; 3218 iv[0] = val; 3219 iv[1] = val >> 8; 3220 iv[2] = val >> 16; 3221 iv[3] = k->k_id << 6; 3222 iv[4] = iv[5] = iv[6] = iv[7] = 0; 3223 } else { 3224 if (k->k_cipher == IEEE80211_CIPHER_TKIP) { 3225 iv[0] = k->k_tsc >> 8; 3226 iv[1] = (iv[0] | 0x20) & 0x7f; 3227 iv[2] = k->k_tsc; 3228 } else /* CCMP */ { 3229 iv[0] = k->k_tsc; 3230 iv[1] = k->k_tsc >> 8; 3231 iv[2] = 0; 3232 } 3233 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV; 3234 iv[4] = k->k_tsc >> 16; 3235 iv[5] = k->k_tsc >> 24; 3236 iv[6] = k->k_tsc >> 32; 3237 iv[7] = k->k_tsc >> 40; 3238 } 3239 RAL_WRITE_REGION_1(sc, RT2860_IVEIV(wcid), iv, 8); 3240 } 3241 3242 if (k->k_flags & IEEE80211_KEY_GROUP) { 3243 /* install group key */ 3244 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3245 attr &= ~(0xf << (k->k_id * 4)); 3246 attr |= mode << (k->k_id * 4); 3247 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3248 } else { 3249 /* install pairwise key */ 3250 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3251 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN; 3252 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3253 } 3254 return 0; 3255 } 3256 3257 static void 3258 rt2860_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni, 3259 struct ieee80211_key *k) 3260 { 3261 struct rt2860_softc *sc = ic->ic_softc; 3262 uint32_t attr; 3263 uint8_t wcid; 3264 3265 if (k->k_flags & IEEE80211_KEY_GROUP) { 3266 /* remove group key */ 3267 attr = RAL_READ(sc, RT2860_SKEY_MODE_0_7); 3268 attr &= ~(0xf << (k->k_id * 4)); 3269 RAL_WRITE(sc, RT2860_SKEY_MODE_0_7, attr); 3270 3271 } else { 3272 /* remove pairwise key */ 3273 wcid = ((struct rt2860_node *)ni)->wcid; 3274 attr = RAL_READ(sc, RT2860_WCID_ATTR(wcid)); 3275 attr &= ~0xf; 3276 RAL_WRITE(sc, RT2860_WCID_ATTR(wcid), attr); 3277 } 3278 } 3279 #endif 3280 3281 static int8_t 3282 rt2860_rssi2dbm(struct rt2860_softc *sc, uint8_t rssi, uint8_t rxchain) 3283 { 3284 struct ieee80211com *ic = &sc->sc_ic; 3285 struct ieee80211_channel *c = ic->ic_curchan; 3286 int delta; 3287 3288 if (IEEE80211_IS_CHAN_5GHZ(c)) { 3289 u_int chan = ieee80211_chan2ieee(ic, c); 3290 delta = sc->rssi_5ghz[rxchain]; 3291 3292 /* determine channel group */ 3293 if (chan <= 64) 3294 delta -= sc->lna[1]; 3295 else if (chan <= 128) 3296 delta -= sc->lna[2]; 3297 else 3298 delta -= sc->lna[3]; 3299 } else 3300 delta = sc->rssi_2ghz[rxchain] - sc->lna[0]; 3301 3302 return -12 - delta - rssi; 3303 } 3304 3305 /* 3306 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word. 3307 * Used to adjust per-rate Tx power registers. 3308 */ 3309 static __inline uint32_t 3310 b4inc(uint32_t b32, int8_t delta) 3311 { 3312 int8_t i, b4; 3313 3314 for (i = 0; i < 8; i++) { 3315 b4 = b32 & 0xf; 3316 b4 += delta; 3317 if (b4 < 0) 3318 b4 = 0; 3319 else if (b4 > 0xf) 3320 b4 = 0xf; 3321 b32 = b32 >> 4 | (uint32_t)b4 << 28; 3322 } 3323 return b32; 3324 } 3325 3326 static const char * 3327 rt2860_get_rf(uint16_t rev) 3328 { 3329 switch (rev) { 3330 case RT2860_RF_2820: return "RT2820"; 3331 case RT2860_RF_2850: return "RT2850"; 3332 case RT2860_RF_2720: return "RT2720"; 3333 case RT2860_RF_2750: return "RT2750"; 3334 case RT3070_RF_3020: return "RT3020"; 3335 case RT3070_RF_2020: return "RT2020"; 3336 case RT3070_RF_3021: return "RT3021"; 3337 case RT3070_RF_3022: return "RT3022"; 3338 case RT3070_RF_3052: return "RT3052"; 3339 case RT3070_RF_3320: return "RT3320"; 3340 case RT3070_RF_3053: return "RT3053"; 3341 case RT5390_RF_5360: return "RT5360"; 3342 case RT5390_RF_5390: return "RT5390"; 3343 default: return "unknown"; 3344 } 3345 } 3346 3347 static int 3348 rt2860_read_eeprom(struct rt2860_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 3349 { 3350 int8_t delta_2ghz, delta_5ghz; 3351 uint32_t tmp; 3352 uint16_t val; 3353 int ridx, ant, i; 3354 3355 /* check whether the ROM is eFUSE ROM or EEPROM */ 3356 sc->sc_srom_read = rt2860_eeprom_read_2; 3357 if (sc->mac_ver >= 0x3071) { 3358 tmp = RAL_READ(sc, RT3070_EFUSE_CTRL); 3359 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp)); 3360 if (tmp & RT3070_SEL_EFUSE) 3361 sc->sc_srom_read = rt3090_efuse_read_2; 3362 } 3363 3364 #ifdef RAL_DEBUG 3365 /* read EEPROM version */ 3366 val = rt2860_srom_read(sc, RT2860_EEPROM_VERSION); 3367 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val >> 8, val & 0xff)); 3368 #endif 3369 3370 /* read MAC address */ 3371 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC01); 3372 macaddr[0] = val & 0xff; 3373 macaddr[1] = val >> 8; 3374 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC23); 3375 macaddr[2] = val & 0xff; 3376 macaddr[3] = val >> 8; 3377 val = rt2860_srom_read(sc, RT2860_EEPROM_MAC45); 3378 macaddr[4] = val & 0xff; 3379 macaddr[5] = val >> 8; 3380 3381 #ifdef RAL_DEBUG 3382 /* read country code */ 3383 val = rt2860_srom_read(sc, RT2860_EEPROM_COUNTRY); 3384 DPRINTF(("EEPROM region code=0x%04x\n", val)); 3385 #endif 3386 3387 /* read vendor BBP settings */ 3388 for (i = 0; i < 8; i++) { 3389 val = rt2860_srom_read(sc, RT2860_EEPROM_BBP_BASE + i); 3390 sc->bbp[i].val = val & 0xff; 3391 sc->bbp[i].reg = val >> 8; 3392 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg, sc->bbp[i].val)); 3393 } 3394 if (sc->mac_ver >= 0x3071) { 3395 /* read vendor RF settings */ 3396 for (i = 0; i < 10; i++) { 3397 val = rt2860_srom_read(sc, RT3071_EEPROM_RF_BASE + i); 3398 sc->rf[i].val = val & 0xff; 3399 sc->rf[i].reg = val >> 8; 3400 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg, 3401 sc->rf[i].val)); 3402 } 3403 } 3404 3405 /* read RF frequency offset from EEPROM */ 3406 val = rt2860_srom_read(sc, RT2860_EEPROM_FREQ_LEDS); 3407 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0; 3408 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff)); 3409 if ((val >> 8) != 0xff) { 3410 /* read LEDs operating mode */ 3411 sc->leds = val >> 8; 3412 sc->led[0] = rt2860_srom_read(sc, RT2860_EEPROM_LED1); 3413 sc->led[1] = rt2860_srom_read(sc, RT2860_EEPROM_LED2); 3414 sc->led[2] = rt2860_srom_read(sc, RT2860_EEPROM_LED3); 3415 } else { 3416 /* broken EEPROM, use default settings */ 3417 sc->leds = 0x01; 3418 sc->led[0] = 0x5555; 3419 sc->led[1] = 0x2221; 3420 sc->led[2] = 0xa9f8; 3421 } 3422 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n", 3423 sc->leds, sc->led[0], sc->led[1], sc->led[2])); 3424 3425 /* read RF information */ 3426 val = rt2860_srom_read(sc, RT2860_EEPROM_ANTENNA); 3427 if (sc->mac_ver >= 0x5390) 3428 sc->rf_rev = rt2860_srom_read(sc, RT2860_EEPROM_CHIPID); 3429 else 3430 sc->rf_rev = (val >> 8) & 0xf; 3431 sc->ntxchains = (val >> 4) & 0xf; 3432 sc->nrxchains = val & 0xf; 3433 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n", 3434 sc->rf_rev, sc->ntxchains, sc->nrxchains)); 3435 3436 /* check if RF supports automatic Tx access gain control */ 3437 val = rt2860_srom_read(sc, RT2860_EEPROM_CONFIG); 3438 DPRINTF(("EEPROM CFG 0x%04x\n", val)); 3439 /* check if driver should patch the DAC issue */ 3440 if ((val >> 8) != 0xff) 3441 sc->patch_dac = (val >> 15) & 1; 3442 if ((val & 0xff) != 0xff) { 3443 sc->ext_5ghz_lna = (val >> 3) & 1; 3444 sc->ext_2ghz_lna = (val >> 2) & 1; 3445 /* check if RF supports automatic Tx access gain control */ 3446 sc->calib_2ghz = sc->calib_5ghz = 0; /* XXX (val >> 1) & 1 */ 3447 /* check if we have a hardware radio switch */ 3448 sc->rfswitch = val & 1; 3449 } 3450 if (sc->sc_flags & RT2860_ADVANCED_PS) { 3451 /* read PCIe power save level */ 3452 val = rt2860_srom_read(sc, RT2860_EEPROM_PCIE_PSLEVEL); 3453 if ((val & 0xff) != 0xff) { 3454 sc->pslevel = val & 0x3; 3455 val = rt2860_srom_read(sc, RT2860_EEPROM_REV); 3456 if ((val & 0xff80) != 0x9280) 3457 sc->pslevel = MIN(sc->pslevel, 1); 3458 DPRINTF(("EEPROM PCIe PS Level=%d\n", sc->pslevel)); 3459 } 3460 } 3461 3462 /* read power settings for 2GHz channels */ 3463 for (i = 0; i < 14; i += 2) { 3464 val = rt2860_srom_read(sc, 3465 RT2860_EEPROM_PWR2GHZ_BASE1 + i / 2); 3466 sc->txpow1[i + 0] = (int8_t)(val & 0xff); 3467 sc->txpow1[i + 1] = (int8_t)(val >> 8); 3468 3469 if (sc->mac_ver != 0x5390) { 3470 val = rt2860_srom_read(sc, 3471 RT2860_EEPROM_PWR2GHZ_BASE2 + i / 2); 3472 sc->txpow2[i + 0] = (int8_t)(val & 0xff); 3473 sc->txpow2[i + 1] = (int8_t)(val >> 8); 3474 } 3475 } 3476 /* fix broken Tx power entries */ 3477 for (i = 0; i < 14; i++) { 3478 if (sc->txpow1[i] < 0 || 3479 sc->txpow1[i] > ((sc->mac_ver >= 0x5390) ? 39 : 31)) 3480 sc->txpow1[i] = 5; 3481 if (sc->mac_ver != 0x5390) { 3482 if (sc->txpow2[i] < 0 || 3483 sc->txpow2[i] > ((sc->mac_ver == 0x5392) ? 39 : 31)) 3484 sc->txpow2[i] = 5; 3485 } 3486 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3487 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i])); 3488 } 3489 /* read power settings for 5GHz channels */ 3490 for (i = 0; i < 40; i += 2) { 3491 val = rt2860_srom_read(sc, 3492 RT2860_EEPROM_PWR5GHZ_BASE1 + i / 2); 3493 sc->txpow1[i + 14] = (int8_t)(val & 0xff); 3494 sc->txpow1[i + 15] = (int8_t)(val >> 8); 3495 3496 val = rt2860_srom_read(sc, 3497 RT2860_EEPROM_PWR5GHZ_BASE2 + i / 2); 3498 sc->txpow2[i + 14] = (int8_t)(val & 0xff); 3499 sc->txpow2[i + 15] = (int8_t)(val >> 8); 3500 } 3501 /* fix broken Tx power entries */ 3502 for (i = 0; i < 40; i++) { 3503 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15) 3504 sc->txpow1[14 + i] = 5; 3505 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15) 3506 sc->txpow2[14 + i] = 5; 3507 DPRINTF(("chan %d: power1=%d, power2=%d\n", 3508 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i], 3509 sc->txpow2[14 + i])); 3510 } 3511 3512 /* read Tx power compensation for each Tx rate */ 3513 val = rt2860_srom_read(sc, RT2860_EEPROM_DELTAPWR); 3514 delta_2ghz = delta_5ghz = 0; 3515 if ((val & 0xff) != 0xff && (val & 0x80)) { 3516 delta_2ghz = val & 0xf; 3517 if (!(val & 0x40)) /* negative number */ 3518 delta_2ghz = -delta_2ghz; 3519 } 3520 val >>= 8; 3521 if ((val & 0xff) != 0xff && (val & 0x80)) { 3522 delta_5ghz = val & 0xf; 3523 if (!(val & 0x40)) /* negative number */ 3524 delta_5ghz = -delta_5ghz; 3525 } 3526 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n", 3527 delta_2ghz, delta_5ghz)); 3528 3529 for (ridx = 0; ridx < 5; ridx++) { 3530 uint32_t reg; 3531 3532 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2); 3533 reg = val; 3534 val = rt2860_srom_read(sc, RT2860_EEPROM_RPWR + ridx * 2 + 1); 3535 reg |= (uint32_t)val << 16; 3536 3537 sc->txpow20mhz[ridx] = reg; 3538 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz); 3539 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz); 3540 3541 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, " 3542 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx], 3543 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx])); 3544 } 3545 3546 /* read factory-calibrated samples for temperature compensation */ 3547 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_2GHZ); 3548 sc->tssi_2ghz[0] = val & 0xff; /* [-4] */ 3549 sc->tssi_2ghz[1] = val >> 8; /* [-3] */ 3550 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_2GHZ); 3551 sc->tssi_2ghz[2] = val & 0xff; /* [-2] */ 3552 sc->tssi_2ghz[3] = val >> 8; /* [-1] */ 3553 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_2GHZ); 3554 sc->tssi_2ghz[4] = val & 0xff; /* [+0] */ 3555 sc->tssi_2ghz[5] = val >> 8; /* [+1] */ 3556 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_2GHZ); 3557 sc->tssi_2ghz[6] = val & 0xff; /* [+2] */ 3558 sc->tssi_2ghz[7] = val >> 8; /* [+3] */ 3559 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_2GHZ); 3560 sc->tssi_2ghz[8] = val & 0xff; /* [+4] */ 3561 sc->step_2ghz = val >> 8; 3562 DPRINTF(("TSSI 2GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3563 "0x%02x 0x%02x step=%d\n", sc->tssi_2ghz[0], sc->tssi_2ghz[1], 3564 sc->tssi_2ghz[2], sc->tssi_2ghz[3], sc->tssi_2ghz[4], 3565 sc->tssi_2ghz[5], sc->tssi_2ghz[6], sc->tssi_2ghz[7], 3566 sc->tssi_2ghz[8], sc->step_2ghz)); 3567 /* check that ref value is correct, otherwise disable calibration */ 3568 if (sc->tssi_2ghz[4] == 0xff) 3569 sc->calib_2ghz = 0; 3570 3571 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI1_5GHZ); 3572 sc->tssi_5ghz[0] = val & 0xff; /* [-4] */ 3573 sc->tssi_5ghz[1] = val >> 8; /* [-3] */ 3574 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI2_5GHZ); 3575 sc->tssi_5ghz[2] = val & 0xff; /* [-2] */ 3576 sc->tssi_5ghz[3] = val >> 8; /* [-1] */ 3577 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI3_5GHZ); 3578 sc->tssi_5ghz[4] = val & 0xff; /* [+0] */ 3579 sc->tssi_5ghz[5] = val >> 8; /* [+1] */ 3580 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI4_5GHZ); 3581 sc->tssi_5ghz[6] = val & 0xff; /* [+2] */ 3582 sc->tssi_5ghz[7] = val >> 8; /* [+3] */ 3583 val = rt2860_srom_read(sc, RT2860_EEPROM_TSSI5_5GHZ); 3584 sc->tssi_5ghz[8] = val & 0xff; /* [+4] */ 3585 sc->step_5ghz = val >> 8; 3586 DPRINTF(("TSSI 5GHz: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x " 3587 "0x%02x 0x%02x step=%d\n", sc->tssi_5ghz[0], sc->tssi_5ghz[1], 3588 sc->tssi_5ghz[2], sc->tssi_5ghz[3], sc->tssi_5ghz[4], 3589 sc->tssi_5ghz[5], sc->tssi_5ghz[6], sc->tssi_5ghz[7], 3590 sc->tssi_5ghz[8], sc->step_5ghz)); 3591 /* check that ref value is correct, otherwise disable calibration */ 3592 if (sc->tssi_5ghz[4] == 0xff) 3593 sc->calib_5ghz = 0; 3594 3595 /* read RSSI offsets and LNA gains from EEPROM */ 3596 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_2GHZ); 3597 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */ 3598 sc->rssi_2ghz[1] = val >> 8; /* Ant B */ 3599 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_2GHZ); 3600 if (sc->mac_ver >= 0x3071) { 3601 /* 3602 * On RT3090 chips (limited to 2 Rx chains), this ROM 3603 * field contains the Tx mixer gain for the 2GHz band. 3604 */ 3605 if ((val & 0xff) != 0xff) 3606 sc->txmixgain_2ghz = val & 0x7; 3607 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz)); 3608 } else 3609 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */ 3610 sc->lna[2] = val >> 8; /* channel group 2 */ 3611 3612 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI1_5GHZ); 3613 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */ 3614 sc->rssi_5ghz[1] = val >> 8; /* Ant B */ 3615 val = rt2860_srom_read(sc, RT2860_EEPROM_RSSI2_5GHZ); 3616 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */ 3617 sc->lna[3] = val >> 8; /* channel group 3 */ 3618 3619 val = rt2860_srom_read(sc, RT2860_EEPROM_LNA); 3620 if (sc->mac_ver >= 0x3071) 3621 sc->lna[0] = RT3090_DEF_LNA; 3622 else /* channel group 0 */ 3623 sc->lna[0] = val & 0xff; 3624 sc->lna[1] = val >> 8; /* channel group 1 */ 3625 3626 /* fix broken 5GHz LNA entries */ 3627 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) { 3628 DPRINTF(("invalid LNA for channel group %d\n", 2)); 3629 sc->lna[2] = sc->lna[1]; 3630 } 3631 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) { 3632 DPRINTF(("invalid LNA for channel group %d\n", 3)); 3633 sc->lna[3] = sc->lna[1]; 3634 } 3635 3636 /* fix broken RSSI offset entries */ 3637 for (ant = 0; ant < 3; ant++) { 3638 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) { 3639 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n", 3640 ant + 1, sc->rssi_2ghz[ant])); 3641 sc->rssi_2ghz[ant] = 0; 3642 } 3643 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) { 3644 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n", 3645 ant + 1, sc->rssi_5ghz[ant])); 3646 sc->rssi_5ghz[ant] = 0; 3647 } 3648 } 3649 3650 return 0; 3651 } 3652 3653 static int 3654 rt2860_bbp_init(struct rt2860_softc *sc) 3655 { 3656 int i, ntries; 3657 3658 /* wait for BBP to wake up */ 3659 for (ntries = 0; ntries < 20; ntries++) { 3660 uint8_t bbp0 = rt2860_mcu_bbp_read(sc, 0); 3661 if (bbp0 != 0 && bbp0 != 0xff) 3662 break; 3663 } 3664 if (ntries == 20) { 3665 device_printf(sc->sc_dev, 3666 "timeout waiting for BBP to wake up\n"); 3667 return (ETIMEDOUT); 3668 } 3669 3670 /* initialize BBP registers to default values */ 3671 if (sc->mac_ver >= 0x5390) 3672 rt5390_bbp_init(sc); 3673 else { 3674 for (i = 0; i < nitems(rt2860_def_bbp); i++) { 3675 rt2860_mcu_bbp_write(sc, rt2860_def_bbp[i].reg, 3676 rt2860_def_bbp[i].val); 3677 } 3678 } 3679 3680 /* fix BBP84 for RT2860E */ 3681 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101) 3682 rt2860_mcu_bbp_write(sc, 84, 0x19); 3683 3684 if (sc->mac_ver >= 0x3071) { 3685 rt2860_mcu_bbp_write(sc, 79, 0x13); 3686 rt2860_mcu_bbp_write(sc, 80, 0x05); 3687 rt2860_mcu_bbp_write(sc, 81, 0x33); 3688 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) { 3689 rt2860_mcu_bbp_write(sc, 69, 0x16); 3690 rt2860_mcu_bbp_write(sc, 73, 0x12); 3691 } 3692 3693 return 0; 3694 } 3695 3696 static void 3697 rt5390_bbp_init(struct rt2860_softc *sc) 3698 { 3699 uint8_t bbp; 3700 int i; 3701 3702 /* Apply maximum likelihood detection for 2 stream case. */ 3703 if (sc->nrxchains > 1) { 3704 bbp = rt2860_mcu_bbp_read(sc, 105); 3705 rt2860_mcu_bbp_write(sc, 105, bbp | RT5390_MLD); 3706 } 3707 3708 /* Avoid data lost and CRC error. */ 3709 bbp = rt2860_mcu_bbp_read(sc, 4); 3710 rt2860_mcu_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL); 3711 3712 for (i = 0; i < nitems(rt5390_def_bbp); i++) { 3713 rt2860_mcu_bbp_write(sc, rt5390_def_bbp[i].reg, 3714 rt5390_def_bbp[i].val); 3715 } 3716 3717 if (sc->mac_ver == 0x5392) { 3718 rt2860_mcu_bbp_write(sc, 84, 0x9a); 3719 rt2860_mcu_bbp_write(sc, 95, 0x9a); 3720 rt2860_mcu_bbp_write(sc, 98, 0x12); 3721 rt2860_mcu_bbp_write(sc, 106, 0x05); 3722 rt2860_mcu_bbp_write(sc, 134, 0xd0); 3723 rt2860_mcu_bbp_write(sc, 135, 0xf6); 3724 } 3725 3726 bbp = rt2860_mcu_bbp_read(sc, 152); 3727 rt2860_mcu_bbp_write(sc, 152, bbp | 0x80); 3728 3729 /* Disable hardware antenna diversity. */ 3730 if (sc->mac_ver == 0x5390) 3731 rt2860_mcu_bbp_write(sc, 154, 0); 3732 } 3733 3734 static int 3735 rt2860_txrx_enable(struct rt2860_softc *sc) 3736 { 3737 struct ieee80211com *ic = &sc->sc_ic; 3738 uint32_t tmp; 3739 int ntries; 3740 3741 /* enable Tx/Rx DMA engine */ 3742 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_MAC_TX_EN); 3743 RAL_BARRIER_READ_WRITE(sc); 3744 for (ntries = 0; ntries < 200; ntries++) { 3745 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3746 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3747 break; 3748 DELAY(1000); 3749 } 3750 if (ntries == 200) { 3751 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3752 return ETIMEDOUT; 3753 } 3754 3755 DELAY(50); 3756 3757 tmp |= RT2860_RX_DMA_EN | RT2860_TX_DMA_EN | 3758 RT2860_WPDMA_BT_SIZE64 << RT2860_WPDMA_BT_SIZE_SHIFT; 3759 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3760 3761 /* set Rx filter */ 3762 tmp = RT2860_DROP_CRC_ERR | RT2860_DROP_PHY_ERR; 3763 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 3764 tmp |= RT2860_DROP_UC_NOME | RT2860_DROP_DUPL | 3765 RT2860_DROP_CTS | RT2860_DROP_BA | RT2860_DROP_ACK | 3766 RT2860_DROP_VER_ERR | RT2860_DROP_CTRL_RSV | 3767 RT2860_DROP_CFACK | RT2860_DROP_CFEND; 3768 if (ic->ic_opmode == IEEE80211_M_STA) 3769 tmp |= RT2860_DROP_RTS | RT2860_DROP_PSPOLL; 3770 } 3771 RAL_WRITE(sc, RT2860_RX_FILTR_CFG, tmp); 3772 3773 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 3774 RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 3775 3776 return 0; 3777 } 3778 3779 static void 3780 rt2860_init(void *arg) 3781 { 3782 struct rt2860_softc *sc = arg; 3783 struct ieee80211com *ic = &sc->sc_ic; 3784 3785 RAL_LOCK(sc); 3786 rt2860_init_locked(sc); 3787 RAL_UNLOCK(sc); 3788 3789 if (sc->sc_flags & RT2860_RUNNING) 3790 ieee80211_start_all(ic); 3791 } 3792 3793 static void 3794 rt2860_init_locked(struct rt2860_softc *sc) 3795 { 3796 struct ieee80211com *ic = &sc->sc_ic; 3797 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3798 uint32_t tmp; 3799 uint8_t bbp1, bbp3; 3800 int i, qid, ridx, ntries, error; 3801 3802 RAL_LOCK_ASSERT(sc); 3803 3804 if (sc->rfswitch) { 3805 /* hardware has a radio switch on GPIO pin 2 */ 3806 if (!(RAL_READ(sc, RT2860_GPIO_CTRL) & (1 << 2))) { 3807 device_printf(sc->sc_dev, 3808 "radio is disabled by hardware switch\n"); 3809 #ifdef notyet 3810 rt2860_stop_locked(sc); 3811 return; 3812 #endif 3813 } 3814 } 3815 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE); 3816 3817 /* disable DMA */ 3818 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3819 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3820 RT2860_TX_DMA_EN); 3821 tmp |= RT2860_TX_WB_DDONE; 3822 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3823 3824 /* reset DMA indexes */ 3825 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, RT2860_RST_DRX_IDX0 | 3826 RT2860_RST_DTX_IDX5 | RT2860_RST_DTX_IDX4 | RT2860_RST_DTX_IDX3 | 3827 RT2860_RST_DTX_IDX2 | RT2860_RST_DTX_IDX1 | RT2860_RST_DTX_IDX0); 3828 3829 /* PBF hardware reset */ 3830 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3831 RAL_BARRIER_WRITE(sc); 3832 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3833 3834 if ((error = rt2860_load_microcode(sc)) != 0) { 3835 device_printf(sc->sc_dev, "could not load 8051 microcode\n"); 3836 rt2860_stop_locked(sc); 3837 return; 3838 } 3839 3840 rt2860_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 3841 3842 /* init Tx power for all Tx rates (from EEPROM) */ 3843 for (ridx = 0; ridx < 5; ridx++) { 3844 if (sc->txpow20mhz[ridx] == 0xffffffff) 3845 continue; 3846 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), sc->txpow20mhz[ridx]); 3847 } 3848 3849 for (ntries = 0; ntries < 100; ntries++) { 3850 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3851 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3852 break; 3853 DELAY(1000); 3854 } 3855 if (ntries == 100) { 3856 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3857 rt2860_stop_locked(sc); 3858 return; 3859 } 3860 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3861 RT2860_TX_DMA_EN); 3862 tmp |= RT2860_TX_WB_DDONE; 3863 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3864 3865 /* reset Rx ring and all 6 Tx rings */ 3866 RAL_WRITE(sc, RT2860_WPDMA_RST_IDX, 0x1003f); 3867 3868 /* PBF hardware reset */ 3869 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe1f); 3870 RAL_BARRIER_WRITE(sc); 3871 RAL_WRITE(sc, RT2860_SYS_CTRL, 0xe00); 3872 3873 RAL_WRITE(sc, RT2860_PWR_PIN_CFG, RT2860_IO_RA_PE | RT2860_IO_RF_PE); 3874 3875 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 3876 RAL_BARRIER_WRITE(sc); 3877 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 3878 3879 for (i = 0; i < nitems(rt2860_def_mac); i++) 3880 RAL_WRITE(sc, rt2860_def_mac[i].reg, rt2860_def_mac[i].val); 3881 if (sc->mac_ver >= 0x5390) 3882 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 0x00000404); 3883 else if (sc->mac_ver >= 0x3071) { 3884 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */ 3885 RAL_WRITE(sc, RT2860_TX_SW_CFG0, 3886 4 << RT2860_DLY_PAPE_EN_SHIFT); 3887 } 3888 3889 if (!(RAL_READ(sc, RT2860_PCI_CFG) & RT2860_PCI_CFG_PCI)) { 3890 sc->sc_flags |= RT2860_PCIE; 3891 /* PCIe has different clock cycle count than PCI */ 3892 tmp = RAL_READ(sc, RT2860_US_CYC_CNT); 3893 tmp = (tmp & ~0xff) | 0x7d; 3894 RAL_WRITE(sc, RT2860_US_CYC_CNT, tmp); 3895 } 3896 3897 /* wait while MAC is busy */ 3898 for (ntries = 0; ntries < 100; ntries++) { 3899 if (!(RAL_READ(sc, RT2860_MAC_STATUS_REG) & 3900 (RT2860_RX_STATUS_BUSY | RT2860_TX_STATUS_BUSY))) 3901 break; 3902 DELAY(1000); 3903 } 3904 if (ntries == 100) { 3905 device_printf(sc->sc_dev, "timeout waiting for MAC\n"); 3906 rt2860_stop_locked(sc); 3907 return; 3908 } 3909 3910 /* clear Host to MCU mailbox */ 3911 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 3912 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 3913 3914 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 3915 DELAY(1000); 3916 3917 if ((error = rt2860_bbp_init(sc)) != 0) { 3918 rt2860_stop_locked(sc); 3919 return; 3920 } 3921 3922 /* clear RX WCID search table */ 3923 RAL_SET_REGION_4(sc, RT2860_WCID_ENTRY(0), 0, 512); 3924 /* clear pairwise key table */ 3925 RAL_SET_REGION_4(sc, RT2860_PKEY(0), 0, 2048); 3926 /* clear IV/EIV table */ 3927 RAL_SET_REGION_4(sc, RT2860_IVEIV(0), 0, 512); 3928 /* clear WCID attribute table */ 3929 RAL_SET_REGION_4(sc, RT2860_WCID_ATTR(0), 0, 256); 3930 /* clear shared key table */ 3931 RAL_SET_REGION_4(sc, RT2860_SKEY(0, 0), 0, 8 * 32); 3932 /* clear shared key mode */ 3933 RAL_SET_REGION_4(sc, RT2860_SKEY_MODE_0_7, 0, 4); 3934 3935 /* init Tx rings (4 EDCAs + HCCA + Mgt) */ 3936 for (qid = 0; qid < 6; qid++) { 3937 RAL_WRITE(sc, RT2860_TX_BASE_PTR(qid), sc->txq[qid].paddr); 3938 RAL_WRITE(sc, RT2860_TX_MAX_CNT(qid), RT2860_TX_RING_COUNT); 3939 RAL_WRITE(sc, RT2860_TX_CTX_IDX(qid), 0); 3940 } 3941 3942 /* init Rx ring */ 3943 RAL_WRITE(sc, RT2860_RX_BASE_PTR, sc->rxq.paddr); 3944 RAL_WRITE(sc, RT2860_RX_MAX_CNT, RT2860_RX_RING_COUNT); 3945 RAL_WRITE(sc, RT2860_RX_CALC_IDX, RT2860_RX_RING_COUNT - 1); 3946 3947 /* setup maximum buffer sizes */ 3948 RAL_WRITE(sc, RT2860_MAX_LEN_CFG, 1 << 12 | 3949 (MCLBYTES - sizeof (struct rt2860_rxwi) - 2)); 3950 3951 for (ntries = 0; ntries < 100; ntries++) { 3952 tmp = RAL_READ(sc, RT2860_WPDMA_GLO_CFG); 3953 if ((tmp & (RT2860_TX_DMA_BUSY | RT2860_RX_DMA_BUSY)) == 0) 3954 break; 3955 DELAY(1000); 3956 } 3957 if (ntries == 100) { 3958 device_printf(sc->sc_dev, "timeout waiting for DMA engine\n"); 3959 rt2860_stop_locked(sc); 3960 return; 3961 } 3962 tmp &= ~(RT2860_RX_DMA_BUSY | RT2860_RX_DMA_EN | RT2860_TX_DMA_BUSY | 3963 RT2860_TX_DMA_EN); 3964 tmp |= RT2860_TX_WB_DDONE; 3965 RAL_WRITE(sc, RT2860_WPDMA_GLO_CFG, tmp); 3966 3967 /* disable interrupts mitigation */ 3968 RAL_WRITE(sc, RT2860_DELAY_INT_CFG, 0); 3969 3970 /* write vendor-specific BBP values (from EEPROM) */ 3971 for (i = 0; i < 8; i++) { 3972 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff) 3973 continue; 3974 rt2860_mcu_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val); 3975 } 3976 3977 /* select Main antenna for 1T1R devices */ 3978 if (sc->rf_rev == RT3070_RF_2020 || 3979 sc->rf_rev == RT3070_RF_3020 || 3980 sc->rf_rev == RT3070_RF_3320 || 3981 sc->mac_ver == 0x5390) 3982 rt3090_set_rx_antenna(sc, 0); 3983 3984 /* send LEDs operating mode to microcontroller */ 3985 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED1, sc->led[0], 0); 3986 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED2, sc->led[1], 0); 3987 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_LED3, sc->led[2], 0); 3988 3989 if (sc->mac_ver >= 0x5390) 3990 rt5390_rf_init(sc); 3991 else if (sc->mac_ver >= 0x3071) { 3992 if ((error = rt3090_rf_init(sc)) != 0) { 3993 rt2860_stop_locked(sc); 3994 return; 3995 } 3996 } 3997 3998 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_SLEEP, 0x02ff, 1); 3999 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_WAKEUP, 0, 1); 4000 4001 if (sc->mac_ver >= 0x5390) 4002 rt5390_rf_wakeup(sc); 4003 else if (sc->mac_ver >= 0x3071) 4004 rt3090_rf_wakeup(sc); 4005 4006 /* disable non-existing Rx chains */ 4007 bbp3 = rt2860_mcu_bbp_read(sc, 3); 4008 bbp3 &= ~(1 << 3 | 1 << 4); 4009 if (sc->nrxchains == 2) 4010 bbp3 |= 1 << 3; 4011 else if (sc->nrxchains == 3) 4012 bbp3 |= 1 << 4; 4013 rt2860_mcu_bbp_write(sc, 3, bbp3); 4014 4015 /* disable non-existing Tx chains */ 4016 bbp1 = rt2860_mcu_bbp_read(sc, 1); 4017 if (sc->ntxchains == 1) 4018 bbp1 = (bbp1 & ~(1 << 3 | 1 << 4)); 4019 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 2) 4020 bbp1 = (bbp1 & ~(1 << 4)) | 1 << 3; 4021 else if (sc->mac_ver == 0x3593 && sc->ntxchains == 3) 4022 bbp1 = (bbp1 & ~(1 << 3)) | 1 << 4; 4023 rt2860_mcu_bbp_write(sc, 1, bbp1); 4024 4025 if (sc->mac_ver >= 0x3071) 4026 rt3090_rf_setup(sc); 4027 4028 /* select default channel */ 4029 rt2860_switch_chan(sc, ic->ic_curchan); 4030 4031 /* reset RF from MCU */ 4032 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET, 0, 0); 4033 4034 /* set RTS threshold */ 4035 tmp = RAL_READ(sc, RT2860_TX_RTS_CFG); 4036 tmp &= ~0xffff00; 4037 tmp |= IEEE80211_RTS_DEFAULT << 8; 4038 RAL_WRITE(sc, RT2860_TX_RTS_CFG, tmp); 4039 4040 /* setup initial protection mode */ 4041 rt2860_updateprot(sc); 4042 4043 /* turn radio LED on */ 4044 rt2860_set_leds(sc, RT2860_LED_RADIO); 4045 4046 /* enable Tx/Rx DMA engine */ 4047 if ((error = rt2860_txrx_enable(sc)) != 0) { 4048 rt2860_stop_locked(sc); 4049 return; 4050 } 4051 4052 /* clear pending interrupts */ 4053 RAL_WRITE(sc, RT2860_INT_STATUS, 0xffffffff); 4054 /* enable interrupts */ 4055 RAL_WRITE(sc, RT2860_INT_MASK, 0x3fffc); 4056 4057 if (sc->sc_flags & RT2860_ADVANCED_PS) 4058 rt2860_mcu_cmd(sc, RT2860_MCU_CMD_PSLEVEL, sc->pslevel, 0); 4059 4060 sc->sc_flags |= RT2860_RUNNING; 4061 4062 callout_reset(&sc->watchdog_ch, hz, rt2860_watchdog, sc); 4063 } 4064 4065 static void 4066 rt2860_stop(void *arg) 4067 { 4068 struct rt2860_softc *sc = arg; 4069 4070 RAL_LOCK(sc); 4071 rt2860_stop_locked(sc); 4072 RAL_UNLOCK(sc); 4073 } 4074 4075 static void 4076 rt2860_stop_locked(struct rt2860_softc *sc) 4077 { 4078 uint32_t tmp; 4079 int qid; 4080 4081 if (sc->sc_flags & RT2860_RUNNING) 4082 rt2860_set_leds(sc, 0); /* turn all LEDs off */ 4083 4084 callout_stop(&sc->watchdog_ch); 4085 sc->sc_tx_timer = 0; 4086 sc->sc_flags &= ~RT2860_RUNNING; 4087 4088 /* disable interrupts */ 4089 RAL_WRITE(sc, RT2860_INT_MASK, 0); 4090 4091 /* disable GP timer */ 4092 rt2860_set_gp_timer(sc, 0); 4093 4094 /* disable Rx */ 4095 tmp = RAL_READ(sc, RT2860_MAC_SYS_CTRL); 4096 tmp &= ~(RT2860_MAC_RX_EN | RT2860_MAC_TX_EN); 4097 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, tmp); 4098 4099 /* reset adapter */ 4100 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, RT2860_BBP_HRST | RT2860_MAC_SRST); 4101 RAL_BARRIER_WRITE(sc); 4102 RAL_WRITE(sc, RT2860_MAC_SYS_CTRL, 0); 4103 4104 /* reset Tx and Rx rings (and reclaim TXWIs) */ 4105 sc->qfullmsk = 0; 4106 for (qid = 0; qid < 6; qid++) 4107 rt2860_reset_tx_ring(sc, &sc->txq[qid]); 4108 rt2860_reset_rx_ring(sc, &sc->rxq); 4109 } 4110 4111 int 4112 rt2860_load_microcode(struct rt2860_softc *sc) 4113 { 4114 const struct firmware *fp; 4115 int ntries, error; 4116 4117 RAL_LOCK_ASSERT(sc); 4118 4119 RAL_UNLOCK(sc); 4120 fp = firmware_get("rt2860fw"); 4121 RAL_LOCK(sc); 4122 if (fp == NULL) { 4123 device_printf(sc->sc_dev, 4124 "unable to receive rt2860fw firmware image\n"); 4125 return EINVAL; 4126 } 4127 4128 /* set "host program ram write selection" bit */ 4129 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_HST_PM_SEL); 4130 /* write microcode image */ 4131 RAL_WRITE_REGION_1(sc, RT2860_FW_BASE, fp->data, fp->datasize); 4132 /* kick microcontroller unit */ 4133 RAL_WRITE(sc, RT2860_SYS_CTRL, 0); 4134 RAL_BARRIER_WRITE(sc); 4135 RAL_WRITE(sc, RT2860_SYS_CTRL, RT2860_MCU_RESET); 4136 4137 RAL_WRITE(sc, RT2860_H2M_BBPAGENT, 0); 4138 RAL_WRITE(sc, RT2860_H2M_MAILBOX, 0); 4139 4140 /* wait until microcontroller is ready */ 4141 RAL_BARRIER_READ_WRITE(sc); 4142 for (ntries = 0; ntries < 1000; ntries++) { 4143 if (RAL_READ(sc, RT2860_SYS_CTRL) & RT2860_MCU_READY) 4144 break; 4145 DELAY(1000); 4146 } 4147 if (ntries == 1000) { 4148 device_printf(sc->sc_dev, 4149 "timeout waiting for MCU to initialize\n"); 4150 error = ETIMEDOUT; 4151 } else 4152 error = 0; 4153 4154 firmware_put(fp, FIRMWARE_UNLOAD); 4155 return error; 4156 } 4157 4158 /* 4159 * This function is called periodically to adjust Tx power based on 4160 * temperature variation. 4161 */ 4162 #ifdef NOT_YET 4163 static void 4164 rt2860_calib(struct rt2860_softc *sc) 4165 { 4166 struct ieee80211com *ic = &sc->sc_ic; 4167 const uint8_t *tssi; 4168 uint8_t step, bbp49; 4169 int8_t ridx, d; 4170 4171 /* read current temperature */ 4172 bbp49 = rt2860_mcu_bbp_read(sc, 49); 4173 4174 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)) { 4175 tssi = &sc->tssi_2ghz[4]; 4176 step = sc->step_2ghz; 4177 } else { 4178 tssi = &sc->tssi_5ghz[4]; 4179 step = sc->step_5ghz; 4180 } 4181 4182 if (bbp49 < tssi[0]) { /* lower than reference */ 4183 /* use higher Tx power than default */ 4184 for (d = 0; d > -4 && bbp49 <= tssi[d - 1]; d--); 4185 } else if (bbp49 > tssi[0]) { /* greater than reference */ 4186 /* use lower Tx power than default */ 4187 for (d = 0; d < +4 && bbp49 >= tssi[d + 1]; d++); 4188 } else { 4189 /* use default Tx power */ 4190 d = 0; 4191 } 4192 d *= step; 4193 4194 DPRINTF(("BBP49=0x%02x, adjusting Tx power by %d\n", bbp49, d)); 4195 4196 /* write adjusted Tx power values for each Tx rate */ 4197 for (ridx = 0; ridx < 5; ridx++) { 4198 if (sc->txpow20mhz[ridx] == 0xffffffff) 4199 continue; 4200 RAL_WRITE(sc, RT2860_TX_PWR_CFG(ridx), 4201 b4inc(sc->txpow20mhz[ridx], d)); 4202 } 4203 } 4204 #endif 4205 4206 static void 4207 rt3090_set_rx_antenna(struct rt2860_softc *sc, int aux) 4208 { 4209 uint32_t tmp; 4210 4211 if (aux) { 4212 if (sc->mac_ver == 0x5390) { 4213 rt2860_mcu_bbp_write(sc, 152, 4214 rt2860_mcu_bbp_read(sc, 152) & ~0x80); 4215 } else { 4216 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4217 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp & ~RT2860_C); 4218 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4219 RAL_WRITE(sc, RT2860_GPIO_CTRL, (tmp & ~0x0808) | 0x08); 4220 } 4221 } else { 4222 if (sc->mac_ver == 0x5390) { 4223 rt2860_mcu_bbp_write(sc, 152, 4224 rt2860_mcu_bbp_read(sc, 152) | 0x80); 4225 } else { 4226 tmp = RAL_READ(sc, RT2860_PCI_EECTRL); 4227 RAL_WRITE(sc, RT2860_PCI_EECTRL, tmp | RT2860_C); 4228 tmp = RAL_READ(sc, RT2860_GPIO_CTRL); 4229 RAL_WRITE(sc, RT2860_GPIO_CTRL, tmp & ~0x0808); 4230 } 4231 } 4232 } 4233 4234 static void 4235 rt2860_switch_chan(struct rt2860_softc *sc, struct ieee80211_channel *c) 4236 { 4237 struct ieee80211com *ic = &sc->sc_ic; 4238 u_int chan, group; 4239 4240 chan = ieee80211_chan2ieee(ic, c); 4241 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 4242 return; 4243 4244 if (sc->mac_ver >= 0x5390) 4245 rt5390_set_chan(sc, chan); 4246 else if (sc->mac_ver >= 0x3071) 4247 rt3090_set_chan(sc, chan); 4248 else 4249 rt2860_set_chan(sc, chan); 4250 4251 /* determine channel group */ 4252 if (chan <= 14) 4253 group = 0; 4254 else if (chan <= 64) 4255 group = 1; 4256 else if (chan <= 128) 4257 group = 2; 4258 else 4259 group = 3; 4260 4261 /* XXX necessary only when group has changed! */ 4262 if (sc->mac_ver < 0x5390) 4263 rt2860_select_chan_group(sc, group); 4264 4265 DELAY(1000); 4266 } 4267 4268 static int 4269 rt2860_setup_beacon(struct rt2860_softc *sc, struct ieee80211vap *vap) 4270 { 4271 struct ieee80211com *ic = vap->iv_ic; 4272 struct rt2860_txwi txwi; 4273 struct mbuf *m; 4274 int ridx; 4275 4276 if ((m = ieee80211_beacon_alloc(vap->iv_bss)) == NULL) 4277 return ENOBUFS; 4278 4279 memset(&txwi, 0, sizeof txwi); 4280 txwi.wcid = 0xff; 4281 txwi.len = htole16(m->m_pkthdr.len); 4282 /* send beacons at the lowest available rate */ 4283 ridx = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 4284 RT2860_RIDX_OFDM6 : RT2860_RIDX_CCK1; 4285 txwi.phy = htole16(rt2860_rates[ridx].mcs); 4286 if (rt2860_rates[ridx].phy == IEEE80211_T_OFDM) 4287 txwi.phy |= htole16(RT2860_PHY_OFDM); 4288 txwi.txop = RT2860_TX_TXOP_HT; 4289 txwi.flags = RT2860_TX_TS; 4290 txwi.xflags = RT2860_TX_NSEQ; 4291 4292 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0), 4293 (uint8_t *)&txwi, sizeof txwi); 4294 RAL_WRITE_REGION_1(sc, RT2860_BCN_BASE(0) + sizeof txwi, 4295 mtod(m, uint8_t *), m->m_pkthdr.len); 4296 4297 m_freem(m); 4298 4299 return 0; 4300 } 4301 4302 static void 4303 rt2860_enable_tsf_sync(struct rt2860_softc *sc) 4304 { 4305 struct ieee80211com *ic = &sc->sc_ic; 4306 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 4307 uint32_t tmp; 4308 4309 tmp = RAL_READ(sc, RT2860_BCN_TIME_CFG); 4310 4311 tmp &= ~0x1fffff; 4312 tmp |= vap->iv_bss->ni_intval * 16; 4313 tmp |= RT2860_TSF_TIMER_EN | RT2860_TBTT_TIMER_EN; 4314 if (vap->iv_opmode == IEEE80211_M_STA) { 4315 /* 4316 * Local TSF is always updated with remote TSF on beacon 4317 * reception. 4318 */ 4319 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT; 4320 } 4321 else if (vap->iv_opmode == IEEE80211_M_IBSS || 4322 vap->iv_opmode == IEEE80211_M_MBSS) { 4323 tmp |= RT2860_BCN_TX_EN; 4324 /* 4325 * Local TSF is updated with remote TSF on beacon reception 4326 * only if the remote TSF is greater than local TSF. 4327 */ 4328 tmp |= 2 << RT2860_TSF_SYNC_MODE_SHIFT; 4329 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) { 4330 tmp |= RT2860_BCN_TX_EN; 4331 /* SYNC with nobody */ 4332 tmp |= 3 << RT2860_TSF_SYNC_MODE_SHIFT; 4333 } 4334 4335 RAL_WRITE(sc, RT2860_BCN_TIME_CFG, tmp); 4336 } 4337