1 2 /*- 3 * Copyright (c) 2006 4 * Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 /*- 21 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 22 * http://www.ralinktech.com/ 23 */ 24 25 #include <sys/param.h> 26 #include <sys/sysctl.h> 27 #include <sys/sockio.h> 28 #include <sys/mbuf.h> 29 #include <sys/kernel.h> 30 #include <sys/socket.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/module.h> 36 #include <sys/bus.h> 37 #include <sys/endian.h> 38 #include <sys/firmware.h> 39 40 #include <machine/bus.h> 41 #include <machine/resource.h> 42 #include <sys/rman.h> 43 44 #include <net/bpf.h> 45 #include <net/if.h> 46 #include <net/if_var.h> 47 #include <net/if_arp.h> 48 #include <net/ethernet.h> 49 #include <net/if_dl.h> 50 #include <net/if_media.h> 51 #include <net/if_types.h> 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_radiotap.h> 55 #include <net80211/ieee80211_regdomain.h> 56 #include <net80211/ieee80211_ratectl.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/ip.h> 62 #include <netinet/if_ether.h> 63 64 #include <dev/ral/rt2661reg.h> 65 #include <dev/ral/rt2661var.h> 66 67 #define RAL_DEBUG 68 #ifdef RAL_DEBUG 69 #define DPRINTF(sc, fmt, ...) do { \ 70 if (sc->sc_debug > 0) \ 71 printf(fmt, __VA_ARGS__); \ 72 } while (0) 73 #define DPRINTFN(sc, n, fmt, ...) do { \ 74 if (sc->sc_debug >= (n)) \ 75 printf(fmt, __VA_ARGS__); \ 76 } while (0) 77 #else 78 #define DPRINTF(sc, fmt, ...) 79 #define DPRINTFN(sc, n, fmt, ...) 80 #endif 81 82 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 83 const char [IFNAMSIZ], int, enum ieee80211_opmode, 84 int, const uint8_t [IEEE80211_ADDR_LEN], 85 const uint8_t [IEEE80211_ADDR_LEN]); 86 static void rt2661_vap_delete(struct ieee80211vap *); 87 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 88 int); 89 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 90 struct rt2661_tx_ring *, int); 91 static void rt2661_reset_tx_ring(struct rt2661_softc *, 92 struct rt2661_tx_ring *); 93 static void rt2661_free_tx_ring(struct rt2661_softc *, 94 struct rt2661_tx_ring *); 95 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 96 struct rt2661_rx_ring *, int); 97 static void rt2661_reset_rx_ring(struct rt2661_softc *, 98 struct rt2661_rx_ring *); 99 static void rt2661_free_rx_ring(struct rt2661_softc *, 100 struct rt2661_rx_ring *); 101 static int rt2661_newstate(struct ieee80211vap *, 102 enum ieee80211_state, int); 103 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 104 static void rt2661_rx_intr(struct rt2661_softc *); 105 static void rt2661_tx_intr(struct rt2661_softc *); 106 static void rt2661_tx_dma_intr(struct rt2661_softc *, 107 struct rt2661_tx_ring *); 108 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 109 static void rt2661_mcu_wakeup(struct rt2661_softc *); 110 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 111 static void rt2661_scan_start(struct ieee80211com *); 112 static void rt2661_scan_end(struct ieee80211com *); 113 static void rt2661_getradiocaps(struct ieee80211com *, int, int *, 114 struct ieee80211_channel[]); 115 static void rt2661_set_channel(struct ieee80211com *); 116 static void rt2661_setup_tx_desc(struct rt2661_softc *, 117 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 118 int, const bus_dma_segment_t *, int, int); 119 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 120 struct ieee80211_node *, int); 121 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 122 struct ieee80211_node *); 123 static int rt2661_transmit(struct ieee80211com *, struct mbuf *); 124 static void rt2661_start(struct rt2661_softc *); 125 static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 126 const struct ieee80211_bpf_params *); 127 static void rt2661_watchdog(void *); 128 static void rt2661_parent(struct ieee80211com *); 129 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 130 uint8_t); 131 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 132 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 133 uint32_t); 134 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 135 uint16_t); 136 static void rt2661_select_antenna(struct rt2661_softc *); 137 static void rt2661_enable_mrr(struct rt2661_softc *); 138 static void rt2661_set_txpreamble(struct rt2661_softc *); 139 static void rt2661_set_basicrates(struct rt2661_softc *, 140 const struct ieee80211_rateset *); 141 static void rt2661_select_band(struct rt2661_softc *, 142 struct ieee80211_channel *); 143 static void rt2661_set_chan(struct rt2661_softc *, 144 struct ieee80211_channel *); 145 static void rt2661_set_bssid(struct rt2661_softc *, 146 const uint8_t *); 147 static void rt2661_set_macaddr(struct rt2661_softc *, 148 const uint8_t *); 149 static void rt2661_update_promisc(struct ieee80211com *); 150 static int rt2661_wme_update(struct ieee80211com *) __unused; 151 static void rt2661_update_slot(struct ieee80211com *); 152 static const char *rt2661_get_rf(int); 153 static void rt2661_read_eeprom(struct rt2661_softc *, 154 uint8_t macaddr[IEEE80211_ADDR_LEN]); 155 static int rt2661_bbp_init(struct rt2661_softc *); 156 static void rt2661_init_locked(struct rt2661_softc *); 157 static void rt2661_init(void *); 158 static void rt2661_stop_locked(struct rt2661_softc *); 159 static void rt2661_stop(void *); 160 static int rt2661_load_microcode(struct rt2661_softc *); 161 #ifdef notyet 162 static void rt2661_rx_tune(struct rt2661_softc *); 163 static void rt2661_radar_start(struct rt2661_softc *); 164 static int rt2661_radar_stop(struct rt2661_softc *); 165 #endif 166 static int rt2661_prepare_beacon(struct rt2661_softc *, 167 struct ieee80211vap *); 168 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 169 static void rt2661_enable_tsf(struct rt2661_softc *); 170 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 171 172 static const struct { 173 uint32_t reg; 174 uint32_t val; 175 } rt2661_def_mac[] = { 176 RT2661_DEF_MAC 177 }; 178 179 static const struct { 180 uint8_t reg; 181 uint8_t val; 182 } rt2661_def_bbp[] = { 183 RT2661_DEF_BBP 184 }; 185 186 static const struct rfprog { 187 uint8_t chan; 188 uint32_t r1, r2, r3, r4; 189 } rt2661_rf5225_1[] = { 190 RT2661_RF5225_1 191 }, rt2661_rf5225_2[] = { 192 RT2661_RF5225_2 193 }; 194 195 static const uint8_t rt2661_chan_5ghz[] = 196 { 36, 40, 44, 48, 52, 56, 60, 64, 197 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 198 149, 153, 157, 161, 165 }; 199 200 int 201 rt2661_attach(device_t dev, int id) 202 { 203 struct rt2661_softc *sc = device_get_softc(dev); 204 struct ieee80211com *ic = &sc->sc_ic; 205 uint32_t val; 206 int error, ac, ntries; 207 208 sc->sc_id = id; 209 sc->sc_dev = dev; 210 211 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 212 MTX_DEF | MTX_RECURSE); 213 214 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 215 mbufq_init(&sc->sc_snd, ifqmaxlen); 216 217 /* wait for NIC to initialize */ 218 for (ntries = 0; ntries < 1000; ntries++) { 219 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 220 break; 221 DELAY(1000); 222 } 223 if (ntries == 1000) { 224 device_printf(sc->sc_dev, 225 "timeout waiting for NIC to initialize\n"); 226 error = EIO; 227 goto fail1; 228 } 229 230 /* retrieve RF rev. no and various other things from EEPROM */ 231 rt2661_read_eeprom(sc, ic->ic_macaddr); 232 233 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 234 rt2661_get_rf(sc->rf_rev)); 235 236 /* 237 * Allocate Tx and Rx rings. 238 */ 239 for (ac = 0; ac < 4; ac++) { 240 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 241 RT2661_TX_RING_COUNT); 242 if (error != 0) { 243 device_printf(sc->sc_dev, 244 "could not allocate Tx ring %d\n", ac); 245 goto fail2; 246 } 247 } 248 249 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 250 if (error != 0) { 251 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 252 goto fail2; 253 } 254 255 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 256 if (error != 0) { 257 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 258 goto fail3; 259 } 260 261 ic->ic_softc = sc; 262 ic->ic_name = device_get_nameunit(dev); 263 ic->ic_opmode = IEEE80211_M_STA; 264 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 265 266 /* set device capabilities */ 267 ic->ic_caps = 268 IEEE80211_C_STA /* station mode */ 269 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 270 | IEEE80211_C_HOSTAP /* hostap mode */ 271 | IEEE80211_C_MONITOR /* monitor mode */ 272 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 273 | IEEE80211_C_WDS /* 4-address traffic works */ 274 | IEEE80211_C_MBSS /* mesh point link mode */ 275 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 276 | IEEE80211_C_SHSLOT /* short slot time supported */ 277 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 278 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 279 #ifdef notyet 280 | IEEE80211_C_TXFRAG /* handle tx frags */ 281 | IEEE80211_C_WME /* 802.11e */ 282 #endif 283 ; 284 285 rt2661_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 286 ic->ic_channels); 287 288 ieee80211_ifattach(ic); 289 #if 0 290 ic->ic_wme.wme_update = rt2661_wme_update; 291 #endif 292 ic->ic_scan_start = rt2661_scan_start; 293 ic->ic_scan_end = rt2661_scan_end; 294 ic->ic_getradiocaps = rt2661_getradiocaps; 295 ic->ic_set_channel = rt2661_set_channel; 296 ic->ic_updateslot = rt2661_update_slot; 297 ic->ic_update_promisc = rt2661_update_promisc; 298 ic->ic_raw_xmit = rt2661_raw_xmit; 299 ic->ic_transmit = rt2661_transmit; 300 ic->ic_parent = rt2661_parent; 301 ic->ic_vap_create = rt2661_vap_create; 302 ic->ic_vap_delete = rt2661_vap_delete; 303 304 ieee80211_radiotap_attach(ic, 305 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 306 RT2661_TX_RADIOTAP_PRESENT, 307 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 308 RT2661_RX_RADIOTAP_PRESENT); 309 310 #ifdef RAL_DEBUG 311 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 312 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 313 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 314 #endif 315 if (bootverbose) 316 ieee80211_announce(ic); 317 318 return 0; 319 320 fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 321 fail2: while (--ac >= 0) 322 rt2661_free_tx_ring(sc, &sc->txq[ac]); 323 fail1: mtx_destroy(&sc->sc_mtx); 324 return error; 325 } 326 327 int 328 rt2661_detach(void *xsc) 329 { 330 struct rt2661_softc *sc = xsc; 331 struct ieee80211com *ic = &sc->sc_ic; 332 333 RAL_LOCK(sc); 334 rt2661_stop_locked(sc); 335 RAL_UNLOCK(sc); 336 337 ieee80211_ifdetach(ic); 338 mbufq_drain(&sc->sc_snd); 339 340 rt2661_free_tx_ring(sc, &sc->txq[0]); 341 rt2661_free_tx_ring(sc, &sc->txq[1]); 342 rt2661_free_tx_ring(sc, &sc->txq[2]); 343 rt2661_free_tx_ring(sc, &sc->txq[3]); 344 rt2661_free_tx_ring(sc, &sc->mgtq); 345 rt2661_free_rx_ring(sc, &sc->rxq); 346 347 mtx_destroy(&sc->sc_mtx); 348 349 return 0; 350 } 351 352 static struct ieee80211vap * 353 rt2661_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 354 enum ieee80211_opmode opmode, int flags, 355 const uint8_t bssid[IEEE80211_ADDR_LEN], 356 const uint8_t mac[IEEE80211_ADDR_LEN]) 357 { 358 struct rt2661_softc *sc = ic->ic_softc; 359 struct rt2661_vap *rvp; 360 struct ieee80211vap *vap; 361 362 switch (opmode) { 363 case IEEE80211_M_STA: 364 case IEEE80211_M_IBSS: 365 case IEEE80211_M_AHDEMO: 366 case IEEE80211_M_MONITOR: 367 case IEEE80211_M_HOSTAP: 368 case IEEE80211_M_MBSS: 369 /* XXXRP: TBD */ 370 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 371 device_printf(sc->sc_dev, "only 1 vap supported\n"); 372 return NULL; 373 } 374 if (opmode == IEEE80211_M_STA) 375 flags |= IEEE80211_CLONE_NOBEACONS; 376 break; 377 case IEEE80211_M_WDS: 378 if (TAILQ_EMPTY(&ic->ic_vaps) || 379 ic->ic_opmode != IEEE80211_M_HOSTAP) { 380 device_printf(sc->sc_dev, 381 "wds only supported in ap mode\n"); 382 return NULL; 383 } 384 /* 385 * Silently remove any request for a unique 386 * bssid; WDS vap's always share the local 387 * mac address. 388 */ 389 flags &= ~IEEE80211_CLONE_BSSID; 390 break; 391 default: 392 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode); 393 return NULL; 394 } 395 rvp = malloc(sizeof(struct rt2661_vap), M_80211_VAP, M_WAITOK | M_ZERO); 396 vap = &rvp->ral_vap; 397 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 398 399 /* override state transition machine */ 400 rvp->ral_newstate = vap->iv_newstate; 401 vap->iv_newstate = rt2661_newstate; 402 #if 0 403 vap->iv_update_beacon = rt2661_beacon_update; 404 #endif 405 406 ieee80211_ratectl_init(vap); 407 /* complete setup */ 408 ieee80211_vap_attach(vap, ieee80211_media_change, 409 ieee80211_media_status, mac); 410 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 411 ic->ic_opmode = opmode; 412 return vap; 413 } 414 415 static void 416 rt2661_vap_delete(struct ieee80211vap *vap) 417 { 418 struct rt2661_vap *rvp = RT2661_VAP(vap); 419 420 ieee80211_ratectl_deinit(vap); 421 ieee80211_vap_detach(vap); 422 free(rvp, M_80211_VAP); 423 } 424 425 void 426 rt2661_shutdown(void *xsc) 427 { 428 struct rt2661_softc *sc = xsc; 429 430 rt2661_stop(sc); 431 } 432 433 void 434 rt2661_suspend(void *xsc) 435 { 436 struct rt2661_softc *sc = xsc; 437 438 rt2661_stop(sc); 439 } 440 441 void 442 rt2661_resume(void *xsc) 443 { 444 struct rt2661_softc *sc = xsc; 445 446 if (sc->sc_ic.ic_nrunning > 0) 447 rt2661_init(sc); 448 } 449 450 static void 451 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 452 { 453 if (error != 0) 454 return; 455 456 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 457 458 *(bus_addr_t *)arg = segs[0].ds_addr; 459 } 460 461 static int 462 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 463 int count) 464 { 465 int i, error; 466 467 ring->count = count; 468 ring->queued = 0; 469 ring->cur = ring->next = ring->stat = 0; 470 471 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 472 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 473 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 474 0, NULL, NULL, &ring->desc_dmat); 475 if (error != 0) { 476 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 477 goto fail; 478 } 479 480 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 481 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 482 if (error != 0) { 483 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 484 goto fail; 485 } 486 487 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 488 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 489 0); 490 if (error != 0) { 491 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 492 goto fail; 493 } 494 495 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 496 M_NOWAIT | M_ZERO); 497 if (ring->data == NULL) { 498 device_printf(sc->sc_dev, "could not allocate soft data\n"); 499 error = ENOMEM; 500 goto fail; 501 } 502 503 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 504 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 505 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 506 if (error != 0) { 507 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 508 goto fail; 509 } 510 511 for (i = 0; i < count; i++) { 512 error = bus_dmamap_create(ring->data_dmat, 0, 513 &ring->data[i].map); 514 if (error != 0) { 515 device_printf(sc->sc_dev, "could not create DMA map\n"); 516 goto fail; 517 } 518 } 519 520 return 0; 521 522 fail: rt2661_free_tx_ring(sc, ring); 523 return error; 524 } 525 526 static void 527 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 528 { 529 struct rt2661_tx_desc *desc; 530 struct rt2661_tx_data *data; 531 int i; 532 533 for (i = 0; i < ring->count; i++) { 534 desc = &ring->desc[i]; 535 data = &ring->data[i]; 536 537 if (data->m != NULL) { 538 bus_dmamap_sync(ring->data_dmat, data->map, 539 BUS_DMASYNC_POSTWRITE); 540 bus_dmamap_unload(ring->data_dmat, data->map); 541 m_freem(data->m); 542 data->m = NULL; 543 } 544 545 if (data->ni != NULL) { 546 ieee80211_free_node(data->ni); 547 data->ni = NULL; 548 } 549 550 desc->flags = 0; 551 } 552 553 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 554 555 ring->queued = 0; 556 ring->cur = ring->next = ring->stat = 0; 557 } 558 559 static void 560 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 561 { 562 struct rt2661_tx_data *data; 563 int i; 564 565 if (ring->desc != NULL) { 566 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 567 BUS_DMASYNC_POSTWRITE); 568 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 569 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 570 } 571 572 if (ring->desc_dmat != NULL) 573 bus_dma_tag_destroy(ring->desc_dmat); 574 575 if (ring->data != NULL) { 576 for (i = 0; i < ring->count; i++) { 577 data = &ring->data[i]; 578 579 if (data->m != NULL) { 580 bus_dmamap_sync(ring->data_dmat, data->map, 581 BUS_DMASYNC_POSTWRITE); 582 bus_dmamap_unload(ring->data_dmat, data->map); 583 m_freem(data->m); 584 } 585 586 if (data->ni != NULL) 587 ieee80211_free_node(data->ni); 588 589 if (data->map != NULL) 590 bus_dmamap_destroy(ring->data_dmat, data->map); 591 } 592 593 free(ring->data, M_DEVBUF); 594 } 595 596 if (ring->data_dmat != NULL) 597 bus_dma_tag_destroy(ring->data_dmat); 598 } 599 600 static int 601 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 602 int count) 603 { 604 struct rt2661_rx_desc *desc; 605 struct rt2661_rx_data *data; 606 bus_addr_t physaddr; 607 int i, error; 608 609 ring->count = count; 610 ring->cur = ring->next = 0; 611 612 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 613 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 614 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 615 0, NULL, NULL, &ring->desc_dmat); 616 if (error != 0) { 617 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 618 goto fail; 619 } 620 621 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 622 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 623 if (error != 0) { 624 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 625 goto fail; 626 } 627 628 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 629 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 630 0); 631 if (error != 0) { 632 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 633 goto fail; 634 } 635 636 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 637 M_NOWAIT | M_ZERO); 638 if (ring->data == NULL) { 639 device_printf(sc->sc_dev, "could not allocate soft data\n"); 640 error = ENOMEM; 641 goto fail; 642 } 643 644 /* 645 * Pre-allocate Rx buffers and populate Rx ring. 646 */ 647 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 648 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 649 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 650 if (error != 0) { 651 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 652 goto fail; 653 } 654 655 for (i = 0; i < count; i++) { 656 desc = &sc->rxq.desc[i]; 657 data = &sc->rxq.data[i]; 658 659 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 660 if (error != 0) { 661 device_printf(sc->sc_dev, "could not create DMA map\n"); 662 goto fail; 663 } 664 665 data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 666 if (data->m == NULL) { 667 device_printf(sc->sc_dev, 668 "could not allocate rx mbuf\n"); 669 error = ENOMEM; 670 goto fail; 671 } 672 673 error = bus_dmamap_load(ring->data_dmat, data->map, 674 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 675 &physaddr, 0); 676 if (error != 0) { 677 device_printf(sc->sc_dev, 678 "could not load rx buf DMA map"); 679 goto fail; 680 } 681 682 desc->flags = htole32(RT2661_RX_BUSY); 683 desc->physaddr = htole32(physaddr); 684 } 685 686 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 687 688 return 0; 689 690 fail: rt2661_free_rx_ring(sc, ring); 691 return error; 692 } 693 694 static void 695 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 696 { 697 int i; 698 699 for (i = 0; i < ring->count; i++) 700 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 701 702 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 703 704 ring->cur = ring->next = 0; 705 } 706 707 static void 708 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 709 { 710 struct rt2661_rx_data *data; 711 int i; 712 713 if (ring->desc != NULL) { 714 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 715 BUS_DMASYNC_POSTWRITE); 716 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 717 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 718 } 719 720 if (ring->desc_dmat != NULL) 721 bus_dma_tag_destroy(ring->desc_dmat); 722 723 if (ring->data != NULL) { 724 for (i = 0; i < ring->count; i++) { 725 data = &ring->data[i]; 726 727 if (data->m != NULL) { 728 bus_dmamap_sync(ring->data_dmat, data->map, 729 BUS_DMASYNC_POSTREAD); 730 bus_dmamap_unload(ring->data_dmat, data->map); 731 m_freem(data->m); 732 } 733 734 if (data->map != NULL) 735 bus_dmamap_destroy(ring->data_dmat, data->map); 736 } 737 738 free(ring->data, M_DEVBUF); 739 } 740 741 if (ring->data_dmat != NULL) 742 bus_dma_tag_destroy(ring->data_dmat); 743 } 744 745 static int 746 rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 747 { 748 struct rt2661_vap *rvp = RT2661_VAP(vap); 749 struct ieee80211com *ic = vap->iv_ic; 750 struct rt2661_softc *sc = ic->ic_softc; 751 int error; 752 753 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 754 uint32_t tmp; 755 756 /* abort TSF synchronization */ 757 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 758 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 759 } 760 761 error = rvp->ral_newstate(vap, nstate, arg); 762 763 if (error == 0 && nstate == IEEE80211_S_RUN) { 764 struct ieee80211_node *ni = vap->iv_bss; 765 766 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 767 rt2661_enable_mrr(sc); 768 rt2661_set_txpreamble(sc); 769 rt2661_set_basicrates(sc, &ni->ni_rates); 770 rt2661_set_bssid(sc, ni->ni_bssid); 771 } 772 773 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 774 vap->iv_opmode == IEEE80211_M_IBSS || 775 vap->iv_opmode == IEEE80211_M_MBSS) { 776 error = rt2661_prepare_beacon(sc, vap); 777 if (error != 0) 778 return error; 779 } 780 if (vap->iv_opmode != IEEE80211_M_MONITOR) 781 rt2661_enable_tsf_sync(sc); 782 else 783 rt2661_enable_tsf(sc); 784 } 785 return error; 786 } 787 788 /* 789 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 790 * 93C66). 791 */ 792 static uint16_t 793 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 794 { 795 uint32_t tmp; 796 uint16_t val; 797 int n; 798 799 /* clock C once before the first command */ 800 RT2661_EEPROM_CTL(sc, 0); 801 802 RT2661_EEPROM_CTL(sc, RT2661_S); 803 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 804 RT2661_EEPROM_CTL(sc, RT2661_S); 805 806 /* write start bit (1) */ 807 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 808 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 809 810 /* write READ opcode (10) */ 811 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 812 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 813 RT2661_EEPROM_CTL(sc, RT2661_S); 814 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 815 816 /* write address (A5-A0 or A7-A0) */ 817 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 818 for (; n >= 0; n--) { 819 RT2661_EEPROM_CTL(sc, RT2661_S | 820 (((addr >> n) & 1) << RT2661_SHIFT_D)); 821 RT2661_EEPROM_CTL(sc, RT2661_S | 822 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 823 } 824 825 RT2661_EEPROM_CTL(sc, RT2661_S); 826 827 /* read data Q15-Q0 */ 828 val = 0; 829 for (n = 15; n >= 0; n--) { 830 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 831 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 832 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 833 RT2661_EEPROM_CTL(sc, RT2661_S); 834 } 835 836 RT2661_EEPROM_CTL(sc, 0); 837 838 /* clear Chip Select and clock C */ 839 RT2661_EEPROM_CTL(sc, RT2661_S); 840 RT2661_EEPROM_CTL(sc, 0); 841 RT2661_EEPROM_CTL(sc, RT2661_C); 842 843 return val; 844 } 845 846 static void 847 rt2661_tx_intr(struct rt2661_softc *sc) 848 { 849 struct ieee80211_ratectl_tx_status *txs = &sc->sc_txs; 850 struct rt2661_tx_ring *txq; 851 struct rt2661_tx_data *data; 852 uint32_t val; 853 int error, qid; 854 855 txs->flags = IEEE80211_RATECTL_TX_FAIL_LONG; 856 for (;;) { 857 struct ieee80211_node *ni; 858 struct mbuf *m; 859 860 val = RAL_READ(sc, RT2661_STA_CSR4); 861 if (!(val & RT2661_TX_STAT_VALID)) 862 break; 863 864 /* retrieve the queue in which this frame was sent */ 865 qid = RT2661_TX_QID(val); 866 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 867 868 /* retrieve rate control algorithm context */ 869 data = &txq->data[txq->stat]; 870 m = data->m; 871 data->m = NULL; 872 ni = data->ni; 873 data->ni = NULL; 874 875 /* if no frame has been sent, ignore */ 876 if (ni == NULL) 877 continue; 878 879 switch (RT2661_TX_RESULT(val)) { 880 case RT2661_TX_SUCCESS: 881 txs->status = IEEE80211_RATECTL_TX_SUCCESS; 882 txs->long_retries = RT2661_TX_RETRYCNT(val); 883 884 DPRINTFN(sc, 10, "data frame sent successfully after " 885 "%d retries\n", txs->long_retries); 886 if (data->rix != IEEE80211_FIXED_RATE_NONE) 887 ieee80211_ratectl_tx_complete(ni, txs); 888 error = 0; 889 break; 890 891 case RT2661_TX_RETRY_FAIL: 892 txs->status = IEEE80211_RATECTL_TX_FAIL_LONG; 893 txs->long_retries = RT2661_TX_RETRYCNT(val); 894 895 DPRINTFN(sc, 9, "%s\n", 896 "sending data frame failed (too much retries)"); 897 if (data->rix != IEEE80211_FIXED_RATE_NONE) 898 ieee80211_ratectl_tx_complete(ni, txs); 899 error = 1; 900 break; 901 902 default: 903 /* other failure */ 904 device_printf(sc->sc_dev, 905 "sending data frame failed 0x%08x\n", val); 906 error = 1; 907 } 908 909 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 910 911 txq->queued--; 912 if (++txq->stat >= txq->count) /* faster than % count */ 913 txq->stat = 0; 914 915 ieee80211_tx_complete(ni, m, error); 916 } 917 918 sc->sc_tx_timer = 0; 919 920 rt2661_start(sc); 921 } 922 923 static void 924 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 925 { 926 struct rt2661_tx_desc *desc; 927 struct rt2661_tx_data *data; 928 929 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 930 931 for (;;) { 932 desc = &txq->desc[txq->next]; 933 data = &txq->data[txq->next]; 934 935 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 936 !(le32toh(desc->flags) & RT2661_TX_VALID)) 937 break; 938 939 bus_dmamap_sync(txq->data_dmat, data->map, 940 BUS_DMASYNC_POSTWRITE); 941 bus_dmamap_unload(txq->data_dmat, data->map); 942 943 /* descriptor is no longer valid */ 944 desc->flags &= ~htole32(RT2661_TX_VALID); 945 946 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 947 948 if (++txq->next >= txq->count) /* faster than % count */ 949 txq->next = 0; 950 } 951 952 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 953 } 954 955 static void 956 rt2661_rx_intr(struct rt2661_softc *sc) 957 { 958 struct ieee80211com *ic = &sc->sc_ic; 959 struct rt2661_rx_desc *desc; 960 struct rt2661_rx_data *data; 961 bus_addr_t physaddr; 962 struct ieee80211_frame *wh; 963 struct ieee80211_node *ni; 964 struct mbuf *mnew, *m; 965 int error; 966 967 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 968 BUS_DMASYNC_POSTREAD); 969 970 for (;;) { 971 int8_t rssi, nf; 972 973 desc = &sc->rxq.desc[sc->rxq.cur]; 974 data = &sc->rxq.data[sc->rxq.cur]; 975 976 if (le32toh(desc->flags) & RT2661_RX_BUSY) 977 break; 978 979 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 980 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 981 /* 982 * This should not happen since we did not request 983 * to receive those frames when we filled TXRX_CSR0. 984 */ 985 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 986 le32toh(desc->flags)); 987 counter_u64_add(ic->ic_ierrors, 1); 988 goto skip; 989 } 990 991 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 992 counter_u64_add(ic->ic_ierrors, 1); 993 goto skip; 994 } 995 996 /* 997 * Try to allocate a new mbuf for this ring element and load it 998 * before processing the current mbuf. If the ring element 999 * cannot be loaded, drop the received packet and reuse the old 1000 * mbuf. In the unlikely case that the old mbuf can't be 1001 * reloaded either, explicitly panic. 1002 */ 1003 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1004 if (mnew == NULL) { 1005 counter_u64_add(ic->ic_ierrors, 1); 1006 goto skip; 1007 } 1008 1009 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1010 BUS_DMASYNC_POSTREAD); 1011 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1012 1013 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1014 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1015 &physaddr, 0); 1016 if (error != 0) { 1017 m_freem(mnew); 1018 1019 /* try to reload the old mbuf */ 1020 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1021 mtod(data->m, void *), MCLBYTES, 1022 rt2661_dma_map_addr, &physaddr, 0); 1023 if (error != 0) { 1024 /* very unlikely that it will fail... */ 1025 panic("%s: could not load old rx mbuf", 1026 device_get_name(sc->sc_dev)); 1027 } 1028 counter_u64_add(ic->ic_ierrors, 1); 1029 goto skip; 1030 } 1031 1032 /* 1033 * New mbuf successfully loaded, update Rx ring and continue 1034 * processing. 1035 */ 1036 m = data->m; 1037 data->m = mnew; 1038 desc->physaddr = htole32(physaddr); 1039 1040 /* finalize mbuf */ 1041 m->m_pkthdr.len = m->m_len = 1042 (le32toh(desc->flags) >> 16) & 0xfff; 1043 1044 rssi = rt2661_get_rssi(sc, desc->rssi); 1045 /* Error happened during RSSI conversion. */ 1046 if (rssi < 0) 1047 rssi = -30; /* XXX ignored by net80211 */ 1048 nf = RT2661_NOISE_FLOOR; 1049 1050 if (ieee80211_radiotap_active(ic)) { 1051 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1052 uint32_t tsf_lo, tsf_hi; 1053 1054 /* get timestamp (low and high 32 bits) */ 1055 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1056 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1057 1058 tap->wr_tsf = 1059 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1060 tap->wr_flags = 0; 1061 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1062 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1063 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1064 tap->wr_antsignal = nf + rssi; 1065 tap->wr_antnoise = nf; 1066 } 1067 sc->sc_flags |= RAL_INPUT_RUNNING; 1068 RAL_UNLOCK(sc); 1069 wh = mtod(m, struct ieee80211_frame *); 1070 1071 /* send the frame to the 802.11 layer */ 1072 ni = ieee80211_find_rxnode(ic, 1073 (struct ieee80211_frame_min *)wh); 1074 if (ni != NULL) { 1075 (void) ieee80211_input(ni, m, rssi, nf); 1076 ieee80211_free_node(ni); 1077 } else 1078 (void) ieee80211_input_all(ic, m, rssi, nf); 1079 1080 RAL_LOCK(sc); 1081 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1082 1083 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1084 1085 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1086 1087 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1088 } 1089 1090 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1091 BUS_DMASYNC_PREWRITE); 1092 } 1093 1094 /* ARGSUSED */ 1095 static void 1096 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1097 { 1098 /* do nothing */ 1099 } 1100 1101 static void 1102 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1103 { 1104 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1105 1106 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1107 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1108 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1109 1110 /* send wakeup command to MCU */ 1111 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1112 } 1113 1114 static void 1115 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1116 { 1117 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1118 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1119 } 1120 1121 void 1122 rt2661_intr(void *arg) 1123 { 1124 struct rt2661_softc *sc = arg; 1125 uint32_t r1, r2; 1126 1127 RAL_LOCK(sc); 1128 1129 /* disable MAC and MCU interrupts */ 1130 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1131 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1132 1133 /* don't re-enable interrupts if we're shutting down */ 1134 if (!(sc->sc_flags & RAL_RUNNING)) { 1135 RAL_UNLOCK(sc); 1136 return; 1137 } 1138 1139 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1140 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1141 1142 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1143 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1144 1145 if (r1 & RT2661_MGT_DONE) 1146 rt2661_tx_dma_intr(sc, &sc->mgtq); 1147 1148 if (r1 & RT2661_RX_DONE) 1149 rt2661_rx_intr(sc); 1150 1151 if (r1 & RT2661_TX0_DMA_DONE) 1152 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1153 1154 if (r1 & RT2661_TX1_DMA_DONE) 1155 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1156 1157 if (r1 & RT2661_TX2_DMA_DONE) 1158 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1159 1160 if (r1 & RT2661_TX3_DMA_DONE) 1161 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1162 1163 if (r1 & RT2661_TX_DONE) 1164 rt2661_tx_intr(sc); 1165 1166 if (r2 & RT2661_MCU_CMD_DONE) 1167 rt2661_mcu_cmd_intr(sc); 1168 1169 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1170 rt2661_mcu_beacon_expire(sc); 1171 1172 if (r2 & RT2661_MCU_WAKEUP) 1173 rt2661_mcu_wakeup(sc); 1174 1175 /* re-enable MAC and MCU interrupts */ 1176 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1177 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1178 1179 RAL_UNLOCK(sc); 1180 } 1181 1182 static uint8_t 1183 rt2661_plcp_signal(int rate) 1184 { 1185 switch (rate) { 1186 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1187 case 12: return 0xb; 1188 case 18: return 0xf; 1189 case 24: return 0xa; 1190 case 36: return 0xe; 1191 case 48: return 0x9; 1192 case 72: return 0xd; 1193 case 96: return 0x8; 1194 case 108: return 0xc; 1195 1196 /* CCK rates (NB: not IEEE std, device-specific) */ 1197 case 2: return 0x0; 1198 case 4: return 0x1; 1199 case 11: return 0x2; 1200 case 22: return 0x3; 1201 } 1202 return 0xff; /* XXX unsupported/unknown rate */ 1203 } 1204 1205 static void 1206 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1207 uint32_t flags, uint16_t xflags, int len, int rate, 1208 const bus_dma_segment_t *segs, int nsegs, int ac) 1209 { 1210 struct ieee80211com *ic = &sc->sc_ic; 1211 uint16_t plcp_length; 1212 int i, remainder; 1213 1214 desc->flags = htole32(flags); 1215 desc->flags |= htole32(len << 16); 1216 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1217 1218 desc->xflags = htole16(xflags); 1219 desc->xflags |= htole16(nsegs << 13); 1220 1221 desc->wme = htole16( 1222 RT2661_QID(ac) | 1223 RT2661_AIFSN(2) | 1224 RT2661_LOGCWMIN(4) | 1225 RT2661_LOGCWMAX(10)); 1226 1227 /* 1228 * Remember in which queue this frame was sent. This field is driver 1229 * private data only. It will be made available by the NIC in STA_CSR4 1230 * on Tx interrupts. 1231 */ 1232 desc->qid = ac; 1233 1234 /* setup PLCP fields */ 1235 desc->plcp_signal = rt2661_plcp_signal(rate); 1236 desc->plcp_service = 4; 1237 1238 len += IEEE80211_CRC_LEN; 1239 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1240 desc->flags |= htole32(RT2661_TX_OFDM); 1241 1242 plcp_length = len & 0xfff; 1243 desc->plcp_length_hi = plcp_length >> 6; 1244 desc->plcp_length_lo = plcp_length & 0x3f; 1245 } else { 1246 plcp_length = howmany(16 * len, rate); 1247 if (rate == 22) { 1248 remainder = (16 * len) % 22; 1249 if (remainder != 0 && remainder < 7) 1250 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1251 } 1252 desc->plcp_length_hi = plcp_length >> 8; 1253 desc->plcp_length_lo = plcp_length & 0xff; 1254 1255 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1256 desc->plcp_signal |= 0x08; 1257 } 1258 1259 /* RT2x61 supports scatter with up to 5 segments */ 1260 for (i = 0; i < nsegs; i++) { 1261 desc->addr[i] = htole32(segs[i].ds_addr); 1262 desc->len [i] = htole16(segs[i].ds_len); 1263 } 1264 } 1265 1266 static int 1267 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1268 struct ieee80211_node *ni) 1269 { 1270 struct ieee80211vap *vap = ni->ni_vap; 1271 struct ieee80211com *ic = ni->ni_ic; 1272 struct rt2661_tx_desc *desc; 1273 struct rt2661_tx_data *data; 1274 struct ieee80211_frame *wh; 1275 struct ieee80211_key *k; 1276 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1277 uint16_t dur; 1278 uint32_t flags = 0; /* XXX HWSEQ */ 1279 int nsegs, rate, error; 1280 1281 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1282 data = &sc->mgtq.data[sc->mgtq.cur]; 1283 1284 rate = ni->ni_txparms->mgmtrate; 1285 1286 wh = mtod(m0, struct ieee80211_frame *); 1287 1288 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1289 k = ieee80211_crypto_encap(ni, m0); 1290 if (k == NULL) { 1291 m_freem(m0); 1292 return ENOBUFS; 1293 } 1294 } 1295 1296 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1297 segs, &nsegs, 0); 1298 if (error != 0) { 1299 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1300 error); 1301 m_freem(m0); 1302 return error; 1303 } 1304 1305 if (ieee80211_radiotap_active_vap(vap)) { 1306 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1307 1308 tap->wt_flags = 0; 1309 tap->wt_rate = rate; 1310 1311 ieee80211_radiotap_tx(vap, m0); 1312 } 1313 1314 data->m = m0; 1315 data->ni = ni; 1316 /* management frames are not taken into account for amrr */ 1317 data->rix = IEEE80211_FIXED_RATE_NONE; 1318 1319 wh = mtod(m0, struct ieee80211_frame *); 1320 1321 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1322 flags |= RT2661_TX_NEED_ACK; 1323 1324 dur = ieee80211_ack_duration(ic->ic_rt, 1325 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1326 *(uint16_t *)wh->i_dur = htole16(dur); 1327 1328 /* tell hardware to add timestamp in probe responses */ 1329 if ((wh->i_fc[0] & 1330 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1331 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1332 flags |= RT2661_TX_TIMESTAMP; 1333 } 1334 1335 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1336 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1337 1338 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1339 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1340 BUS_DMASYNC_PREWRITE); 1341 1342 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1343 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1344 1345 /* kick mgt */ 1346 sc->mgtq.queued++; 1347 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1348 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1349 1350 return 0; 1351 } 1352 1353 static int 1354 rt2661_sendprot(struct rt2661_softc *sc, int ac, 1355 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1356 { 1357 struct ieee80211com *ic = ni->ni_ic; 1358 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1359 struct rt2661_tx_desc *desc; 1360 struct rt2661_tx_data *data; 1361 struct mbuf *mprot; 1362 int protrate, flags, error; 1363 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1364 int nsegs; 1365 1366 mprot = ieee80211_alloc_prot(ni, m, rate, prot); 1367 if (mprot == NULL) { 1368 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 1369 device_printf(sc->sc_dev, 1370 "could not allocate mbuf for protection mode %d\n", prot); 1371 return ENOBUFS; 1372 } 1373 1374 data = &txq->data[txq->cur]; 1375 desc = &txq->desc[txq->cur]; 1376 1377 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1378 &nsegs, 0); 1379 if (error != 0) { 1380 device_printf(sc->sc_dev, 1381 "could not map mbuf (error %d)\n", error); 1382 m_freem(mprot); 1383 return error; 1384 } 1385 1386 data->m = mprot; 1387 data->ni = ieee80211_ref_node(ni); 1388 /* ctl frames are not taken into account for amrr */ 1389 data->rix = IEEE80211_FIXED_RATE_NONE; 1390 1391 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1392 flags = RT2661_TX_MORE_FRAG; 1393 if (prot == IEEE80211_PROT_RTSCTS) 1394 flags |= RT2661_TX_NEED_ACK; 1395 1396 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1397 protrate, segs, 1, ac); 1398 1399 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1400 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1401 1402 txq->queued++; 1403 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1404 1405 return 0; 1406 } 1407 1408 static int 1409 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1410 struct ieee80211_node *ni, int ac) 1411 { 1412 struct ieee80211vap *vap = ni->ni_vap; 1413 struct ieee80211com *ic = &sc->sc_ic; 1414 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1415 struct rt2661_tx_desc *desc; 1416 struct rt2661_tx_data *data; 1417 struct ieee80211_frame *wh; 1418 const struct ieee80211_txparam *tp = ni->ni_txparms; 1419 struct ieee80211_key *k; 1420 struct mbuf *mnew; 1421 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1422 uint16_t dur; 1423 uint32_t flags; 1424 int error, nsegs, rate, noack = 0; 1425 1426 wh = mtod(m0, struct ieee80211_frame *); 1427 1428 if (m0->m_flags & M_EAPOL) { 1429 rate = tp->mgmtrate; 1430 } else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1431 rate = tp->mcastrate; 1432 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1433 rate = tp->ucastrate; 1434 } else { 1435 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1436 rate = ni->ni_txrate; 1437 } 1438 rate &= IEEE80211_RATE_VAL; 1439 1440 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS_DATA) 1441 noack = !! ieee80211_wme_vap_ac_is_noack(vap, ac); 1442 1443 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1444 k = ieee80211_crypto_encap(ni, m0); 1445 if (k == NULL) { 1446 m_freem(m0); 1447 return ENOBUFS; 1448 } 1449 1450 /* packet header may have moved, reset our local pointer */ 1451 wh = mtod(m0, struct ieee80211_frame *); 1452 } 1453 1454 flags = 0; 1455 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1456 int prot = IEEE80211_PROT_NONE; 1457 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1458 prot = IEEE80211_PROT_RTSCTS; 1459 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1460 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1461 prot = ic->ic_protmode; 1462 if (prot != IEEE80211_PROT_NONE) { 1463 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1464 if (error) { 1465 m_freem(m0); 1466 return error; 1467 } 1468 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1469 } 1470 } 1471 1472 data = &txq->data[txq->cur]; 1473 desc = &txq->desc[txq->cur]; 1474 1475 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1476 &nsegs, 0); 1477 if (error != 0 && error != EFBIG) { 1478 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1479 error); 1480 m_freem(m0); 1481 return error; 1482 } 1483 if (error != 0) { 1484 mnew = m_defrag(m0, M_NOWAIT); 1485 if (mnew == NULL) { 1486 device_printf(sc->sc_dev, 1487 "could not defragment mbuf\n"); 1488 m_freem(m0); 1489 return ENOBUFS; 1490 } 1491 m0 = mnew; 1492 1493 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1494 segs, &nsegs, 0); 1495 if (error != 0) { 1496 device_printf(sc->sc_dev, 1497 "could not map mbuf (error %d)\n", error); 1498 m_freem(m0); 1499 return error; 1500 } 1501 1502 /* packet header have moved, reset our local pointer */ 1503 wh = mtod(m0, struct ieee80211_frame *); 1504 } 1505 1506 if (ieee80211_radiotap_active_vap(vap)) { 1507 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1508 1509 tap->wt_flags = 0; 1510 tap->wt_rate = rate; 1511 1512 ieee80211_radiotap_tx(vap, m0); 1513 } 1514 1515 data->m = m0; 1516 data->ni = ni; 1517 1518 /* remember link conditions for rate adaptation algorithm */ 1519 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1520 data->rix = ni->ni_txrate; 1521 /* XXX probably need last rssi value and not avg */ 1522 data->rssi = ic->ic_node_getrssi(ni); 1523 } else 1524 data->rix = IEEE80211_FIXED_RATE_NONE; 1525 1526 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1527 flags |= RT2661_TX_NEED_ACK; 1528 1529 dur = ieee80211_ack_duration(ic->ic_rt, 1530 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1531 *(uint16_t *)wh->i_dur = htole16(dur); 1532 } 1533 1534 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1535 nsegs, ac); 1536 1537 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1538 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1539 1540 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1541 m0->m_pkthdr.len, txq->cur, rate); 1542 1543 /* kick Tx */ 1544 txq->queued++; 1545 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1546 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1547 1548 return 0; 1549 } 1550 1551 static int 1552 rt2661_transmit(struct ieee80211com *ic, struct mbuf *m) 1553 { 1554 struct rt2661_softc *sc = ic->ic_softc; 1555 int error; 1556 1557 RAL_LOCK(sc); 1558 if ((sc->sc_flags & RAL_RUNNING) == 0) { 1559 RAL_UNLOCK(sc); 1560 return (ENXIO); 1561 } 1562 error = mbufq_enqueue(&sc->sc_snd, m); 1563 if (error) { 1564 RAL_UNLOCK(sc); 1565 return (error); 1566 } 1567 rt2661_start(sc); 1568 RAL_UNLOCK(sc); 1569 1570 return (0); 1571 } 1572 1573 static void 1574 rt2661_start(struct rt2661_softc *sc) 1575 { 1576 struct mbuf *m; 1577 struct ieee80211_node *ni; 1578 int ac; 1579 1580 RAL_LOCK_ASSERT(sc); 1581 1582 /* prevent management frames from being sent if we're not ready */ 1583 if (!(sc->sc_flags & RAL_RUNNING) || sc->sc_invalid) 1584 return; 1585 1586 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1587 ac = M_WME_GETAC(m); 1588 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1589 /* there is no place left in this ring */ 1590 mbufq_prepend(&sc->sc_snd, m); 1591 break; 1592 } 1593 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1594 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1595 if_inc_counter(ni->ni_vap->iv_ifp, 1596 IFCOUNTER_OERRORS, 1); 1597 ieee80211_free_node(ni); 1598 break; 1599 } 1600 sc->sc_tx_timer = 5; 1601 } 1602 } 1603 1604 static int 1605 rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1606 const struct ieee80211_bpf_params *params) 1607 { 1608 struct ieee80211com *ic = ni->ni_ic; 1609 struct rt2661_softc *sc = ic->ic_softc; 1610 1611 RAL_LOCK(sc); 1612 1613 /* prevent management frames from being sent if we're not ready */ 1614 if (!(sc->sc_flags & RAL_RUNNING)) { 1615 RAL_UNLOCK(sc); 1616 m_freem(m); 1617 return ENETDOWN; 1618 } 1619 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1620 RAL_UNLOCK(sc); 1621 m_freem(m); 1622 return ENOBUFS; /* XXX */ 1623 } 1624 1625 /* 1626 * Legacy path; interpret frame contents to decide 1627 * precisely how to send the frame. 1628 * XXX raw path 1629 */ 1630 if (rt2661_tx_mgt(sc, m, ni) != 0) 1631 goto bad; 1632 sc->sc_tx_timer = 5; 1633 1634 RAL_UNLOCK(sc); 1635 1636 return 0; 1637 bad: 1638 RAL_UNLOCK(sc); 1639 return EIO; /* XXX */ 1640 } 1641 1642 static void 1643 rt2661_watchdog(void *arg) 1644 { 1645 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1646 1647 RAL_LOCK_ASSERT(sc); 1648 1649 KASSERT(sc->sc_flags & RAL_RUNNING, ("not running")); 1650 1651 if (sc->sc_invalid) /* card ejected */ 1652 return; 1653 1654 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1655 device_printf(sc->sc_dev, "device timeout\n"); 1656 rt2661_init_locked(sc); 1657 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1658 /* NB: callout is reset in rt2661_init() */ 1659 return; 1660 } 1661 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1662 } 1663 1664 static void 1665 rt2661_parent(struct ieee80211com *ic) 1666 { 1667 struct rt2661_softc *sc = ic->ic_softc; 1668 int startall = 0; 1669 1670 RAL_LOCK(sc); 1671 if (ic->ic_nrunning > 0) { 1672 if ((sc->sc_flags & RAL_RUNNING) == 0) { 1673 rt2661_init_locked(sc); 1674 startall = 1; 1675 } else 1676 rt2661_update_promisc(ic); 1677 } else if (sc->sc_flags & RAL_RUNNING) 1678 rt2661_stop_locked(sc); 1679 RAL_UNLOCK(sc); 1680 if (startall) 1681 ieee80211_start_all(ic); 1682 } 1683 1684 static void 1685 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1686 { 1687 uint32_t tmp; 1688 int ntries; 1689 1690 for (ntries = 0; ntries < 100; ntries++) { 1691 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1692 break; 1693 DELAY(1); 1694 } 1695 if (ntries == 100) { 1696 device_printf(sc->sc_dev, "could not write to BBP\n"); 1697 return; 1698 } 1699 1700 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1701 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1702 1703 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1704 } 1705 1706 static uint8_t 1707 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1708 { 1709 uint32_t val; 1710 int ntries; 1711 1712 for (ntries = 0; ntries < 100; ntries++) { 1713 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1714 break; 1715 DELAY(1); 1716 } 1717 if (ntries == 100) { 1718 device_printf(sc->sc_dev, "could not read from BBP\n"); 1719 return 0; 1720 } 1721 1722 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1723 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1724 1725 for (ntries = 0; ntries < 100; ntries++) { 1726 val = RAL_READ(sc, RT2661_PHY_CSR3); 1727 if (!(val & RT2661_BBP_BUSY)) 1728 return val & 0xff; 1729 DELAY(1); 1730 } 1731 1732 device_printf(sc->sc_dev, "could not read from BBP\n"); 1733 return 0; 1734 } 1735 1736 static void 1737 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1738 { 1739 uint32_t tmp; 1740 int ntries; 1741 1742 for (ntries = 0; ntries < 100; ntries++) { 1743 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1744 break; 1745 DELAY(1); 1746 } 1747 if (ntries == 100) { 1748 device_printf(sc->sc_dev, "could not write to RF\n"); 1749 return; 1750 } 1751 1752 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1753 (reg & 3); 1754 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1755 1756 /* remember last written value in sc */ 1757 sc->rf_regs[reg] = val; 1758 1759 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1760 } 1761 1762 static int 1763 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1764 { 1765 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1766 return EIO; /* there is already a command pending */ 1767 1768 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1769 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1770 1771 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1772 1773 return 0; 1774 } 1775 1776 static void 1777 rt2661_select_antenna(struct rt2661_softc *sc) 1778 { 1779 uint8_t bbp4, bbp77; 1780 uint32_t tmp; 1781 1782 bbp4 = rt2661_bbp_read(sc, 4); 1783 bbp77 = rt2661_bbp_read(sc, 77); 1784 1785 /* TBD */ 1786 1787 /* make sure Rx is disabled before switching antenna */ 1788 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1789 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1790 1791 rt2661_bbp_write(sc, 4, bbp4); 1792 rt2661_bbp_write(sc, 77, bbp77); 1793 1794 /* restore Rx filter */ 1795 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1796 } 1797 1798 /* 1799 * Enable multi-rate retries for frames sent at OFDM rates. 1800 * In 802.11b/g mode, allow fallback to CCK rates. 1801 */ 1802 static void 1803 rt2661_enable_mrr(struct rt2661_softc *sc) 1804 { 1805 struct ieee80211com *ic = &sc->sc_ic; 1806 uint32_t tmp; 1807 1808 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1809 1810 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1811 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1812 tmp |= RT2661_MRR_CCK_FALLBACK; 1813 tmp |= RT2661_MRR_ENABLED; 1814 1815 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1816 } 1817 1818 static void 1819 rt2661_set_txpreamble(struct rt2661_softc *sc) 1820 { 1821 struct ieee80211com *ic = &sc->sc_ic; 1822 uint32_t tmp; 1823 1824 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1825 1826 tmp &= ~RT2661_SHORT_PREAMBLE; 1827 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1828 tmp |= RT2661_SHORT_PREAMBLE; 1829 1830 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1831 } 1832 1833 static void 1834 rt2661_set_basicrates(struct rt2661_softc *sc, 1835 const struct ieee80211_rateset *rs) 1836 { 1837 struct ieee80211com *ic = &sc->sc_ic; 1838 uint32_t mask = 0; 1839 uint8_t rate; 1840 int i; 1841 1842 for (i = 0; i < rs->rs_nrates; i++) { 1843 rate = rs->rs_rates[i]; 1844 1845 if (!(rate & IEEE80211_RATE_BASIC)) 1846 continue; 1847 1848 mask |= 1 << ieee80211_legacy_rate_lookup(ic->ic_rt, 1849 IEEE80211_RV(rate)); 1850 } 1851 1852 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1853 1854 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1855 } 1856 1857 /* 1858 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1859 * driver. 1860 */ 1861 static void 1862 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1863 { 1864 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1865 uint32_t tmp; 1866 1867 /* update all BBP registers that depend on the band */ 1868 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 1869 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 1870 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1871 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 1872 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 1873 } 1874 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1875 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1876 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 1877 } 1878 1879 rt2661_bbp_write(sc, 17, bbp17); 1880 rt2661_bbp_write(sc, 96, bbp96); 1881 rt2661_bbp_write(sc, 104, bbp104); 1882 1883 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 1884 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 1885 rt2661_bbp_write(sc, 75, 0x80); 1886 rt2661_bbp_write(sc, 86, 0x80); 1887 rt2661_bbp_write(sc, 88, 0x80); 1888 } 1889 1890 rt2661_bbp_write(sc, 35, bbp35); 1891 rt2661_bbp_write(sc, 97, bbp97); 1892 rt2661_bbp_write(sc, 98, bbp98); 1893 1894 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 1895 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 1896 if (IEEE80211_IS_CHAN_2GHZ(c)) 1897 tmp |= RT2661_PA_PE_2GHZ; 1898 else 1899 tmp |= RT2661_PA_PE_5GHZ; 1900 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 1901 } 1902 1903 static void 1904 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 1905 { 1906 struct ieee80211com *ic = &sc->sc_ic; 1907 const struct rfprog *rfprog; 1908 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 1909 int8_t power; 1910 u_int i, chan; 1911 1912 chan = ieee80211_chan2ieee(ic, c); 1913 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 1914 1915 /* select the appropriate RF settings based on what EEPROM says */ 1916 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 1917 1918 /* find the settings for this channel (we know it exists) */ 1919 for (i = 0; rfprog[i].chan != chan; i++); 1920 1921 power = sc->txpow[i]; 1922 if (power < 0) { 1923 bbp94 += power; 1924 power = 0; 1925 } else if (power > 31) { 1926 bbp94 += power - 31; 1927 power = 31; 1928 } 1929 1930 /* 1931 * If we are switching from the 2GHz band to the 5GHz band or 1932 * vice-versa, BBP registers need to be reprogrammed. 1933 */ 1934 if (c->ic_flags != sc->sc_curchan->ic_flags) { 1935 rt2661_select_band(sc, c); 1936 rt2661_select_antenna(sc); 1937 } 1938 sc->sc_curchan = c; 1939 1940 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 1941 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 1942 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 1943 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 1944 1945 DELAY(200); 1946 1947 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 1948 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 1949 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 1950 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 1951 1952 DELAY(200); 1953 1954 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 1955 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 1956 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 1957 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 1958 1959 /* enable smart mode for MIMO-capable RFs */ 1960 bbp3 = rt2661_bbp_read(sc, 3); 1961 1962 bbp3 &= ~RT2661_SMART_MODE; 1963 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 1964 bbp3 |= RT2661_SMART_MODE; 1965 1966 rt2661_bbp_write(sc, 3, bbp3); 1967 1968 if (bbp94 != RT2661_BBPR94_DEFAULT) 1969 rt2661_bbp_write(sc, 94, bbp94); 1970 1971 /* 5GHz radio needs a 1ms delay here */ 1972 if (IEEE80211_IS_CHAN_5GHZ(c)) 1973 DELAY(1000); 1974 } 1975 1976 static void 1977 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 1978 { 1979 uint32_t tmp; 1980 1981 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 1982 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 1983 1984 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 1985 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 1986 } 1987 1988 static void 1989 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 1990 { 1991 uint32_t tmp; 1992 1993 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 1994 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 1995 1996 tmp = addr[4] | addr[5] << 8; 1997 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 1998 } 1999 2000 static void 2001 rt2661_update_promisc(struct ieee80211com *ic) 2002 { 2003 struct rt2661_softc *sc = ic->ic_softc; 2004 uint32_t tmp; 2005 2006 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2007 2008 tmp &= ~RT2661_DROP_NOT_TO_ME; 2009 if (ic->ic_promisc == 0) 2010 tmp |= RT2661_DROP_NOT_TO_ME; 2011 2012 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2013 2014 DPRINTF(sc, "%s promiscuous mode\n", 2015 (ic->ic_promisc > 0) ? "entering" : "leaving"); 2016 } 2017 2018 /* 2019 * Update QoS (802.11e) settings for each h/w Tx ring. 2020 */ 2021 static int 2022 rt2661_wme_update(struct ieee80211com *ic) 2023 { 2024 struct rt2661_softc *sc = ic->ic_softc; 2025 struct chanAccParams chp; 2026 const struct wmeParams *wmep; 2027 2028 ieee80211_wme_ic_getparams(ic, &chp); 2029 2030 wmep = chp.cap_wmeParams; 2031 2032 /* XXX: not sure about shifts. */ 2033 /* XXX: the reference driver plays with AC_VI settings too. */ 2034 2035 /* update TxOp */ 2036 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2037 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2038 wmep[WME_AC_BK].wmep_txopLimit); 2039 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2040 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2041 wmep[WME_AC_VO].wmep_txopLimit); 2042 2043 /* update CWmin */ 2044 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2045 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2046 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2047 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2048 wmep[WME_AC_VO].wmep_logcwmin); 2049 2050 /* update CWmax */ 2051 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2052 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2053 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2054 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2055 wmep[WME_AC_VO].wmep_logcwmax); 2056 2057 /* update Aifsn */ 2058 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2059 wmep[WME_AC_BE].wmep_aifsn << 12 | 2060 wmep[WME_AC_BK].wmep_aifsn << 8 | 2061 wmep[WME_AC_VI].wmep_aifsn << 4 | 2062 wmep[WME_AC_VO].wmep_aifsn); 2063 2064 return 0; 2065 } 2066 2067 static void 2068 rt2661_update_slot(struct ieee80211com *ic) 2069 { 2070 struct rt2661_softc *sc = ic->ic_softc; 2071 uint8_t slottime; 2072 uint32_t tmp; 2073 2074 slottime = IEEE80211_GET_SLOTTIME(ic); 2075 2076 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2077 tmp = (tmp & ~0xff) | slottime; 2078 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2079 } 2080 2081 static const char * 2082 rt2661_get_rf(int rev) 2083 { 2084 switch (rev) { 2085 case RT2661_RF_5225: return "RT5225"; 2086 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2087 case RT2661_RF_2527: return "RT2527"; 2088 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2089 default: return "unknown"; 2090 } 2091 } 2092 2093 static void 2094 rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 2095 { 2096 uint16_t val; 2097 int i; 2098 2099 /* read MAC address */ 2100 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2101 macaddr[0] = val & 0xff; 2102 macaddr[1] = val >> 8; 2103 2104 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2105 macaddr[2] = val & 0xff; 2106 macaddr[3] = val >> 8; 2107 2108 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2109 macaddr[4] = val & 0xff; 2110 macaddr[5] = val >> 8; 2111 2112 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2113 /* XXX: test if different from 0xffff? */ 2114 sc->rf_rev = (val >> 11) & 0x1f; 2115 sc->hw_radio = (val >> 10) & 0x1; 2116 sc->rx_ant = (val >> 4) & 0x3; 2117 sc->tx_ant = (val >> 2) & 0x3; 2118 sc->nb_ant = val & 0x3; 2119 2120 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2121 2122 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2123 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2124 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2125 2126 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2127 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2128 2129 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2130 if ((val & 0xff) != 0xff) 2131 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2132 2133 /* Only [-10, 10] is valid */ 2134 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2135 sc->rssi_2ghz_corr = 0; 2136 2137 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2138 if ((val & 0xff) != 0xff) 2139 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2140 2141 /* Only [-10, 10] is valid */ 2142 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2143 sc->rssi_5ghz_corr = 0; 2144 2145 /* adjust RSSI correction for external low-noise amplifier */ 2146 if (sc->ext_2ghz_lna) 2147 sc->rssi_2ghz_corr -= 14; 2148 if (sc->ext_5ghz_lna) 2149 sc->rssi_5ghz_corr -= 14; 2150 2151 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2152 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2153 2154 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2155 if ((val >> 8) != 0xff) 2156 sc->rfprog = (val >> 8) & 0x3; 2157 if ((val & 0xff) != 0xff) 2158 sc->rffreq = val & 0xff; 2159 2160 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2161 2162 /* read Tx power for all a/b/g channels */ 2163 for (i = 0; i < 19; i++) { 2164 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2165 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2166 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2167 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2168 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2169 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2170 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2171 } 2172 2173 /* read vendor-specific BBP values */ 2174 for (i = 0; i < 16; i++) { 2175 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2176 if (val == 0 || val == 0xffff) 2177 continue; /* skip invalid entries */ 2178 sc->bbp_prom[i].reg = val >> 8; 2179 sc->bbp_prom[i].val = val & 0xff; 2180 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2181 sc->bbp_prom[i].val); 2182 } 2183 } 2184 2185 static int 2186 rt2661_bbp_init(struct rt2661_softc *sc) 2187 { 2188 int i, ntries; 2189 uint8_t val; 2190 2191 /* wait for BBP to be ready */ 2192 for (ntries = 0; ntries < 100; ntries++) { 2193 val = rt2661_bbp_read(sc, 0); 2194 if (val != 0 && val != 0xff) 2195 break; 2196 DELAY(100); 2197 } 2198 if (ntries == 100) { 2199 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2200 return EIO; 2201 } 2202 2203 /* initialize BBP registers to default values */ 2204 for (i = 0; i < nitems(rt2661_def_bbp); i++) { 2205 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2206 rt2661_def_bbp[i].val); 2207 } 2208 2209 /* write vendor-specific BBP values (from EEPROM) */ 2210 for (i = 0; i < 16; i++) { 2211 if (sc->bbp_prom[i].reg == 0) 2212 continue; 2213 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2214 } 2215 2216 return 0; 2217 } 2218 2219 static void 2220 rt2661_init_locked(struct rt2661_softc *sc) 2221 { 2222 struct ieee80211com *ic = &sc->sc_ic; 2223 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2224 uint32_t tmp, sta[3]; 2225 int i, error, ntries; 2226 2227 RAL_LOCK_ASSERT(sc); 2228 2229 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2230 error = rt2661_load_microcode(sc); 2231 if (error != 0) { 2232 device_printf(sc->sc_dev, 2233 "%s: could not load 8051 microcode, error %d\n", 2234 __func__, error); 2235 return; 2236 } 2237 sc->sc_flags |= RAL_FW_LOADED; 2238 } 2239 2240 rt2661_stop_locked(sc); 2241 2242 /* initialize Tx rings */ 2243 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2244 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2245 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2246 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2247 2248 /* initialize Mgt ring */ 2249 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2250 2251 /* initialize Rx ring */ 2252 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2253 2254 /* initialize Tx rings sizes */ 2255 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2256 RT2661_TX_RING_COUNT << 24 | 2257 RT2661_TX_RING_COUNT << 16 | 2258 RT2661_TX_RING_COUNT << 8 | 2259 RT2661_TX_RING_COUNT); 2260 2261 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2262 RT2661_TX_DESC_WSIZE << 16 | 2263 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2264 RT2661_MGT_RING_COUNT); 2265 2266 /* initialize Rx rings */ 2267 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2268 RT2661_RX_DESC_BACK << 16 | 2269 RT2661_RX_DESC_WSIZE << 8 | 2270 RT2661_RX_RING_COUNT); 2271 2272 /* XXX: some magic here */ 2273 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2274 2275 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2276 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2277 2278 /* load base address of Rx ring */ 2279 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2280 2281 /* initialize MAC registers to default values */ 2282 for (i = 0; i < nitems(rt2661_def_mac); i++) 2283 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2284 2285 rt2661_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2286 2287 /* set host ready */ 2288 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2289 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2290 2291 /* wait for BBP/RF to wakeup */ 2292 for (ntries = 0; ntries < 1000; ntries++) { 2293 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2294 break; 2295 DELAY(1000); 2296 } 2297 if (ntries == 1000) { 2298 printf("timeout waiting for BBP/RF to wakeup\n"); 2299 rt2661_stop_locked(sc); 2300 return; 2301 } 2302 2303 if (rt2661_bbp_init(sc) != 0) { 2304 rt2661_stop_locked(sc); 2305 return; 2306 } 2307 2308 /* select default channel */ 2309 sc->sc_curchan = ic->ic_curchan; 2310 rt2661_select_band(sc, sc->sc_curchan); 2311 rt2661_select_antenna(sc); 2312 rt2661_set_chan(sc, sc->sc_curchan); 2313 2314 /* update Rx filter */ 2315 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2316 2317 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2318 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2319 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2320 RT2661_DROP_ACKCTS; 2321 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 2322 ic->ic_opmode != IEEE80211_M_MBSS) 2323 tmp |= RT2661_DROP_TODS; 2324 if (ic->ic_promisc == 0) 2325 tmp |= RT2661_DROP_NOT_TO_ME; 2326 } 2327 2328 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2329 2330 /* clear STA registers */ 2331 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, nitems(sta)); 2332 2333 /* initialize ASIC */ 2334 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2335 2336 /* clear any pending interrupt */ 2337 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2338 2339 /* enable interrupts */ 2340 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2341 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2342 2343 /* kick Rx */ 2344 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2345 2346 sc->sc_flags |= RAL_RUNNING; 2347 2348 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2349 } 2350 2351 static void 2352 rt2661_init(void *priv) 2353 { 2354 struct rt2661_softc *sc = priv; 2355 struct ieee80211com *ic = &sc->sc_ic; 2356 2357 RAL_LOCK(sc); 2358 rt2661_init_locked(sc); 2359 RAL_UNLOCK(sc); 2360 2361 if (sc->sc_flags & RAL_RUNNING) 2362 ieee80211_start_all(ic); /* start all vap's */ 2363 } 2364 2365 void 2366 rt2661_stop_locked(struct rt2661_softc *sc) 2367 { 2368 volatile int *flags = &sc->sc_flags; 2369 uint32_t tmp; 2370 2371 while (*flags & RAL_INPUT_RUNNING) 2372 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2373 2374 callout_stop(&sc->watchdog_ch); 2375 sc->sc_tx_timer = 0; 2376 2377 if (sc->sc_flags & RAL_RUNNING) { 2378 sc->sc_flags &= ~RAL_RUNNING; 2379 2380 /* abort Tx (for all 5 Tx rings) */ 2381 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2382 2383 /* disable Rx (value remains after reset!) */ 2384 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2385 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2386 2387 /* reset ASIC */ 2388 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2389 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2390 2391 /* disable interrupts */ 2392 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2393 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2394 2395 /* clear any pending interrupt */ 2396 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2397 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2398 2399 /* reset Tx and Rx rings */ 2400 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2401 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2402 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2403 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2404 rt2661_reset_tx_ring(sc, &sc->mgtq); 2405 rt2661_reset_rx_ring(sc, &sc->rxq); 2406 } 2407 } 2408 2409 void 2410 rt2661_stop(void *priv) 2411 { 2412 struct rt2661_softc *sc = priv; 2413 2414 RAL_LOCK(sc); 2415 rt2661_stop_locked(sc); 2416 RAL_UNLOCK(sc); 2417 } 2418 2419 static int 2420 rt2661_load_microcode(struct rt2661_softc *sc) 2421 { 2422 const struct firmware *fp; 2423 const char *imagename; 2424 int ntries, error; 2425 2426 RAL_LOCK_ASSERT(sc); 2427 2428 switch (sc->sc_id) { 2429 case 0x0301: imagename = "rt2561sfw"; break; 2430 case 0x0302: imagename = "rt2561fw"; break; 2431 case 0x0401: imagename = "rt2661fw"; break; 2432 default: 2433 device_printf(sc->sc_dev, "%s: unexpected pci device id 0x%x, " 2434 "don't know how to retrieve firmware\n", 2435 __func__, sc->sc_id); 2436 return EINVAL; 2437 } 2438 RAL_UNLOCK(sc); 2439 fp = firmware_get(imagename); 2440 RAL_LOCK(sc); 2441 if (fp == NULL) { 2442 device_printf(sc->sc_dev, 2443 "%s: unable to retrieve firmware image %s\n", 2444 __func__, imagename); 2445 return EINVAL; 2446 } 2447 2448 /* 2449 * Load 8051 microcode into NIC. 2450 */ 2451 /* reset 8051 */ 2452 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2453 2454 /* cancel any pending Host to MCU command */ 2455 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2456 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2457 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2458 2459 /* write 8051's microcode */ 2460 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2461 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2462 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2463 2464 /* kick 8051's ass */ 2465 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2466 2467 /* wait for 8051 to initialize */ 2468 for (ntries = 0; ntries < 500; ntries++) { 2469 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2470 break; 2471 DELAY(100); 2472 } 2473 if (ntries == 500) { 2474 device_printf(sc->sc_dev, 2475 "%s: timeout waiting for MCU to initialize\n", __func__); 2476 error = EIO; 2477 } else 2478 error = 0; 2479 2480 firmware_put(fp, FIRMWARE_UNLOAD); 2481 return error; 2482 } 2483 2484 #ifdef notyet 2485 /* 2486 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2487 * false CCA count. This function is called periodically (every seconds) when 2488 * in the RUN state. Values taken from the reference driver. 2489 */ 2490 static void 2491 rt2661_rx_tune(struct rt2661_softc *sc) 2492 { 2493 uint8_t bbp17; 2494 uint16_t cca; 2495 int lo, hi, dbm; 2496 2497 /* 2498 * Tuning range depends on operating band and on the presence of an 2499 * external low-noise amplifier. 2500 */ 2501 lo = 0x20; 2502 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2503 lo += 0x08; 2504 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2505 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2506 lo += 0x10; 2507 hi = lo + 0x20; 2508 2509 /* retrieve false CCA count since last call (clear on read) */ 2510 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2511 2512 if (dbm >= -35) { 2513 bbp17 = 0x60; 2514 } else if (dbm >= -58) { 2515 bbp17 = hi; 2516 } else if (dbm >= -66) { 2517 bbp17 = lo + 0x10; 2518 } else if (dbm >= -74) { 2519 bbp17 = lo + 0x08; 2520 } else { 2521 /* RSSI < -74dBm, tune using false CCA count */ 2522 2523 bbp17 = sc->bbp17; /* current value */ 2524 2525 hi -= 2 * (-74 - dbm); 2526 if (hi < lo) 2527 hi = lo; 2528 2529 if (bbp17 > hi) { 2530 bbp17 = hi; 2531 2532 } else if (cca > 512) { 2533 if (++bbp17 > hi) 2534 bbp17 = hi; 2535 } else if (cca < 100) { 2536 if (--bbp17 < lo) 2537 bbp17 = lo; 2538 } 2539 } 2540 2541 if (bbp17 != sc->bbp17) { 2542 rt2661_bbp_write(sc, 17, bbp17); 2543 sc->bbp17 = bbp17; 2544 } 2545 } 2546 2547 /* 2548 * Enter/Leave radar detection mode. 2549 * This is for 802.11h additional regulatory domains. 2550 */ 2551 static void 2552 rt2661_radar_start(struct rt2661_softc *sc) 2553 { 2554 uint32_t tmp; 2555 2556 /* disable Rx */ 2557 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2558 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2559 2560 rt2661_bbp_write(sc, 82, 0x20); 2561 rt2661_bbp_write(sc, 83, 0x00); 2562 rt2661_bbp_write(sc, 84, 0x40); 2563 2564 /* save current BBP registers values */ 2565 sc->bbp18 = rt2661_bbp_read(sc, 18); 2566 sc->bbp21 = rt2661_bbp_read(sc, 21); 2567 sc->bbp22 = rt2661_bbp_read(sc, 22); 2568 sc->bbp16 = rt2661_bbp_read(sc, 16); 2569 sc->bbp17 = rt2661_bbp_read(sc, 17); 2570 sc->bbp64 = rt2661_bbp_read(sc, 64); 2571 2572 rt2661_bbp_write(sc, 18, 0xff); 2573 rt2661_bbp_write(sc, 21, 0x3f); 2574 rt2661_bbp_write(sc, 22, 0x3f); 2575 rt2661_bbp_write(sc, 16, 0xbd); 2576 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2577 rt2661_bbp_write(sc, 64, 0x21); 2578 2579 /* restore Rx filter */ 2580 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2581 } 2582 2583 static int 2584 rt2661_radar_stop(struct rt2661_softc *sc) 2585 { 2586 uint8_t bbp66; 2587 2588 /* read radar detection result */ 2589 bbp66 = rt2661_bbp_read(sc, 66); 2590 2591 /* restore BBP registers values */ 2592 rt2661_bbp_write(sc, 16, sc->bbp16); 2593 rt2661_bbp_write(sc, 17, sc->bbp17); 2594 rt2661_bbp_write(sc, 18, sc->bbp18); 2595 rt2661_bbp_write(sc, 21, sc->bbp21); 2596 rt2661_bbp_write(sc, 22, sc->bbp22); 2597 rt2661_bbp_write(sc, 64, sc->bbp64); 2598 2599 return bbp66 == 1; 2600 } 2601 #endif 2602 2603 static int 2604 rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2605 { 2606 struct ieee80211com *ic = vap->iv_ic; 2607 struct rt2661_tx_desc desc; 2608 struct mbuf *m0; 2609 int rate; 2610 2611 if ((m0 = ieee80211_beacon_alloc(vap->iv_bss))== NULL) { 2612 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2613 return ENOBUFS; 2614 } 2615 2616 /* send beacons at the lowest available rate */ 2617 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2618 2619 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2620 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2621 2622 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2623 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2624 2625 /* copy beacon header and payload into NIC memory */ 2626 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2627 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2628 2629 m_freem(m0); 2630 2631 return 0; 2632 } 2633 2634 /* 2635 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2636 * and HostAP operating modes. 2637 */ 2638 static void 2639 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2640 { 2641 struct ieee80211com *ic = &sc->sc_ic; 2642 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2643 uint32_t tmp; 2644 2645 if (vap->iv_opmode != IEEE80211_M_STA) { 2646 /* 2647 * Change default 16ms TBTT adjustment to 8ms. 2648 * Must be done before enabling beacon generation. 2649 */ 2650 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2651 } 2652 2653 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2654 2655 /* set beacon interval (in 1/16ms unit) */ 2656 tmp |= vap->iv_bss->ni_intval * 16; 2657 2658 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2659 if (vap->iv_opmode == IEEE80211_M_STA) 2660 tmp |= RT2661_TSF_MODE(1); 2661 else 2662 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2663 2664 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2665 } 2666 2667 static void 2668 rt2661_enable_tsf(struct rt2661_softc *sc) 2669 { 2670 RAL_WRITE(sc, RT2661_TXRX_CSR9, 2671 (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) 2672 | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); 2673 } 2674 2675 /* 2676 * Retrieve the "Received Signal Strength Indicator" from the raw values 2677 * contained in Rx descriptors. The computation depends on which band the 2678 * frame was received. Correction values taken from the reference driver. 2679 */ 2680 static int 2681 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2682 { 2683 int lna, agc, rssi; 2684 2685 lna = (raw >> 5) & 0x3; 2686 agc = raw & 0x1f; 2687 2688 if (lna == 0) { 2689 /* 2690 * No mapping available. 2691 * 2692 * NB: Since RSSI is relative to noise floor, -1 is 2693 * adequate for caller to know error happened. 2694 */ 2695 return -1; 2696 } 2697 2698 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2699 2700 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2701 rssi += sc->rssi_2ghz_corr; 2702 2703 if (lna == 1) 2704 rssi -= 64; 2705 else if (lna == 2) 2706 rssi -= 74; 2707 else if (lna == 3) 2708 rssi -= 90; 2709 } else { 2710 rssi += sc->rssi_5ghz_corr; 2711 2712 if (lna == 1) 2713 rssi -= 64; 2714 else if (lna == 2) 2715 rssi -= 86; 2716 else if (lna == 3) 2717 rssi -= 100; 2718 } 2719 return rssi; 2720 } 2721 2722 static void 2723 rt2661_scan_start(struct ieee80211com *ic) 2724 { 2725 struct rt2661_softc *sc = ic->ic_softc; 2726 uint32_t tmp; 2727 2728 /* abort TSF synchronization */ 2729 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2730 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2731 rt2661_set_bssid(sc, ieee80211broadcastaddr); 2732 } 2733 2734 static void 2735 rt2661_scan_end(struct ieee80211com *ic) 2736 { 2737 struct rt2661_softc *sc = ic->ic_softc; 2738 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2739 2740 rt2661_enable_tsf_sync(sc); 2741 /* XXX keep local copy */ 2742 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2743 } 2744 2745 static void 2746 rt2661_getradiocaps(struct ieee80211com *ic, 2747 int maxchans, int *nchans, struct ieee80211_channel chans[]) 2748 { 2749 struct rt2661_softc *sc = ic->ic_softc; 2750 uint8_t bands[IEEE80211_MODE_BYTES]; 2751 2752 memset(bands, 0, sizeof(bands)); 2753 setbit(bands, IEEE80211_MODE_11B); 2754 setbit(bands, IEEE80211_MODE_11G); 2755 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 2756 2757 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) { 2758 setbit(bands, IEEE80211_MODE_11A); 2759 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 2760 rt2661_chan_5ghz, nitems(rt2661_chan_5ghz), bands, 0); 2761 } 2762 } 2763 2764 static void 2765 rt2661_set_channel(struct ieee80211com *ic) 2766 { 2767 struct rt2661_softc *sc = ic->ic_softc; 2768 2769 RAL_LOCK(sc); 2770 rt2661_set_chan(sc, ic->ic_curchan); 2771 RAL_UNLOCK(sc); 2772 2773 } 2774