1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /*- 24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include <sys/param.h> 29 #include <sys/sysctl.h> 30 #include <sys/sockio.h> 31 #include <sys/mbuf.h> 32 #include <sys/kernel.h> 33 #include <sys/socket.h> 34 #include <sys/systm.h> 35 #include <sys/malloc.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/endian.h> 41 #include <sys/firmware.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_arp.h> 50 #include <net/ethernet.h> 51 #include <net/if_dl.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 55 #include <net80211/ieee80211_var.h> 56 #include <net80211/ieee80211_phy.h> 57 #include <net80211/ieee80211_radiotap.h> 58 #include <net80211/ieee80211_regdomain.h> 59 #include <net80211/ieee80211_amrr.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/in_var.h> 64 #include <netinet/ip.h> 65 #include <netinet/if_ether.h> 66 67 #include <dev/ral/rt2661reg.h> 68 #include <dev/ral/rt2661var.h> 69 70 #define RAL_DEBUG 71 #ifdef RAL_DEBUG 72 #define DPRINTF(sc, fmt, ...) do { \ 73 if (sc->sc_debug > 0) \ 74 printf(fmt, __VA_ARGS__); \ 75 } while (0) 76 #define DPRINTFN(sc, n, fmt, ...) do { \ 77 if (sc->sc_debug >= (n)) \ 78 printf(fmt, __VA_ARGS__); \ 79 } while (0) 80 #else 81 #define DPRINTF(sc, fmt, ...) 82 #define DPRINTFN(sc, n, fmt, ...) 83 #endif 84 85 static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, 86 const char name[IFNAMSIZ], int unit, int opmode, 87 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], 88 const uint8_t mac[IEEE80211_ADDR_LEN]); 89 static void rt2661_vap_delete(struct ieee80211vap *); 90 static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, 91 int); 92 static int rt2661_alloc_tx_ring(struct rt2661_softc *, 93 struct rt2661_tx_ring *, int); 94 static void rt2661_reset_tx_ring(struct rt2661_softc *, 95 struct rt2661_tx_ring *); 96 static void rt2661_free_tx_ring(struct rt2661_softc *, 97 struct rt2661_tx_ring *); 98 static int rt2661_alloc_rx_ring(struct rt2661_softc *, 99 struct rt2661_rx_ring *, int); 100 static void rt2661_reset_rx_ring(struct rt2661_softc *, 101 struct rt2661_rx_ring *); 102 static void rt2661_free_rx_ring(struct rt2661_softc *, 103 struct rt2661_rx_ring *); 104 static struct ieee80211_node *rt2661_node_alloc( 105 struct ieee80211_node_table *); 106 static void rt2661_newassoc(struct ieee80211_node *, int); 107 static int rt2661_newstate(struct ieee80211vap *, 108 enum ieee80211_state, int); 109 static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); 110 static void rt2661_rx_intr(struct rt2661_softc *); 111 static void rt2661_tx_intr(struct rt2661_softc *); 112 static void rt2661_tx_dma_intr(struct rt2661_softc *, 113 struct rt2661_tx_ring *); 114 static void rt2661_mcu_beacon_expire(struct rt2661_softc *); 115 static void rt2661_mcu_wakeup(struct rt2661_softc *); 116 static void rt2661_mcu_cmd_intr(struct rt2661_softc *); 117 static void rt2661_scan_start(struct ieee80211com *); 118 static void rt2661_scan_end(struct ieee80211com *); 119 static void rt2661_set_channel(struct ieee80211com *); 120 static void rt2661_setup_tx_desc(struct rt2661_softc *, 121 struct rt2661_tx_desc *, uint32_t, uint16_t, int, 122 int, const bus_dma_segment_t *, int, int); 123 static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, 124 struct ieee80211_node *, int); 125 static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, 126 struct ieee80211_node *); 127 static void rt2661_start_locked(struct ifnet *); 128 static void rt2661_start(struct ifnet *); 129 static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, 130 const struct ieee80211_bpf_params *); 131 static void rt2661_watchdog(void *); 132 static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); 133 static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, 134 uint8_t); 135 static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); 136 static void rt2661_rf_write(struct rt2661_softc *, uint8_t, 137 uint32_t); 138 static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, 139 uint16_t); 140 static void rt2661_select_antenna(struct rt2661_softc *); 141 static void rt2661_enable_mrr(struct rt2661_softc *); 142 static void rt2661_set_txpreamble(struct rt2661_softc *); 143 static void rt2661_set_basicrates(struct rt2661_softc *, 144 const struct ieee80211_rateset *); 145 static void rt2661_select_band(struct rt2661_softc *, 146 struct ieee80211_channel *); 147 static void rt2661_set_chan(struct rt2661_softc *, 148 struct ieee80211_channel *); 149 static void rt2661_set_bssid(struct rt2661_softc *, 150 const uint8_t *); 151 static void rt2661_set_macaddr(struct rt2661_softc *, 152 const uint8_t *); 153 static void rt2661_update_promisc(struct ifnet *); 154 static int rt2661_wme_update(struct ieee80211com *) __unused; 155 static void rt2661_update_slot(struct ifnet *); 156 static const char *rt2661_get_rf(int); 157 static void rt2661_read_eeprom(struct rt2661_softc *, 158 struct ieee80211com *); 159 static int rt2661_bbp_init(struct rt2661_softc *); 160 static void rt2661_init_locked(struct rt2661_softc *); 161 static void rt2661_init(void *); 162 static void rt2661_stop_locked(struct rt2661_softc *); 163 static void rt2661_stop(void *); 164 static int rt2661_load_microcode(struct rt2661_softc *); 165 #ifdef notyet 166 static void rt2661_rx_tune(struct rt2661_softc *); 167 static void rt2661_radar_start(struct rt2661_softc *); 168 static int rt2661_radar_stop(struct rt2661_softc *); 169 #endif 170 static int rt2661_prepare_beacon(struct rt2661_softc *, 171 struct ieee80211vap *); 172 static void rt2661_enable_tsf_sync(struct rt2661_softc *); 173 static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); 174 175 static const struct { 176 uint32_t reg; 177 uint32_t val; 178 } rt2661_def_mac[] = { 179 RT2661_DEF_MAC 180 }; 181 182 static const struct { 183 uint8_t reg; 184 uint8_t val; 185 } rt2661_def_bbp[] = { 186 RT2661_DEF_BBP 187 }; 188 189 static const struct rfprog { 190 uint8_t chan; 191 uint32_t r1, r2, r3, r4; 192 } rt2661_rf5225_1[] = { 193 RT2661_RF5225_1 194 }, rt2661_rf5225_2[] = { 195 RT2661_RF5225_2 196 }; 197 198 int 199 rt2661_attach(device_t dev, int id) 200 { 201 struct rt2661_softc *sc = device_get_softc(dev); 202 struct ieee80211com *ic; 203 struct ifnet *ifp; 204 uint32_t val; 205 int error, ac, ntries; 206 uint8_t bands; 207 208 sc->sc_id = id; 209 sc->sc_dev = dev; 210 211 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 212 if (ifp == NULL) { 213 device_printf(sc->sc_dev, "can not if_alloc()\n"); 214 return ENOMEM; 215 } 216 ic = ifp->if_l2com; 217 218 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 219 MTX_DEF | MTX_RECURSE); 220 221 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 222 223 /* wait for NIC to initialize */ 224 for (ntries = 0; ntries < 1000; ntries++) { 225 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) 226 break; 227 DELAY(1000); 228 } 229 if (ntries == 1000) { 230 device_printf(sc->sc_dev, 231 "timeout waiting for NIC to initialize\n"); 232 error = EIO; 233 goto fail1; 234 } 235 236 /* retrieve RF rev. no and various other things from EEPROM */ 237 rt2661_read_eeprom(sc, ic); 238 239 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, 240 rt2661_get_rf(sc->rf_rev)); 241 242 /* 243 * Allocate Tx and Rx rings. 244 */ 245 for (ac = 0; ac < 4; ac++) { 246 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], 247 RT2661_TX_RING_COUNT); 248 if (error != 0) { 249 device_printf(sc->sc_dev, 250 "could not allocate Tx ring %d\n", ac); 251 goto fail2; 252 } 253 } 254 255 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); 256 if (error != 0) { 257 device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); 258 goto fail2; 259 } 260 261 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); 262 if (error != 0) { 263 device_printf(sc->sc_dev, "could not allocate Rx ring\n"); 264 goto fail3; 265 } 266 267 ifp->if_softc = sc; 268 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 269 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 270 ifp->if_init = rt2661_init; 271 ifp->if_ioctl = rt2661_ioctl; 272 ifp->if_start = rt2661_start; 273 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 274 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 275 IFQ_SET_READY(&ifp->if_snd); 276 277 ic->ic_ifp = ifp; 278 ic->ic_opmode = IEEE80211_M_STA; 279 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 280 281 /* set device capabilities */ 282 ic->ic_caps = 283 IEEE80211_C_STA /* station mode */ 284 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 285 | IEEE80211_C_HOSTAP /* hostap mode */ 286 | IEEE80211_C_MONITOR /* monitor mode */ 287 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 288 | IEEE80211_C_WDS /* 4-address traffic works */ 289 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 290 | IEEE80211_C_SHSLOT /* short slot time supported */ 291 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 292 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 293 #ifdef notyet 294 | IEEE80211_C_TXFRAG /* handle tx frags */ 295 | IEEE80211_C_WME /* 802.11e */ 296 #endif 297 ; 298 299 bands = 0; 300 setbit(&bands, IEEE80211_MODE_11B); 301 setbit(&bands, IEEE80211_MODE_11G); 302 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) 303 setbit(&bands, IEEE80211_MODE_11A); 304 ieee80211_init_channels(ic, NULL, &bands); 305 306 ieee80211_ifattach(ic); 307 ic->ic_newassoc = rt2661_newassoc; 308 ic->ic_node_alloc = rt2661_node_alloc; 309 #if 0 310 ic->ic_wme.wme_update = rt2661_wme_update; 311 #endif 312 ic->ic_scan_start = rt2661_scan_start; 313 ic->ic_scan_end = rt2661_scan_end; 314 ic->ic_set_channel = rt2661_set_channel; 315 ic->ic_updateslot = rt2661_update_slot; 316 ic->ic_update_promisc = rt2661_update_promisc; 317 ic->ic_raw_xmit = rt2661_raw_xmit; 318 319 ic->ic_vap_create = rt2661_vap_create; 320 ic->ic_vap_delete = rt2661_vap_delete; 321 322 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 323 324 bpfattach(ifp, DLT_IEEE802_11_RADIO, 325 sizeof (struct ieee80211_frame) + sizeof (sc->sc_txtap)); 326 327 sc->sc_rxtap_len = sizeof sc->sc_rxtap; 328 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len); 329 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT); 330 331 sc->sc_txtap_len = sizeof sc->sc_txtap; 332 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len); 333 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT); 334 335 #ifdef RAL_DEBUG 336 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 337 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 338 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); 339 #endif 340 if (bootverbose) 341 ieee80211_announce(ic); 342 343 return 0; 344 345 fail3: rt2661_free_tx_ring(sc, &sc->mgtq); 346 fail2: while (--ac >= 0) 347 rt2661_free_tx_ring(sc, &sc->txq[ac]); 348 fail1: mtx_destroy(&sc->sc_mtx); 349 if_free(ifp); 350 return error; 351 } 352 353 int 354 rt2661_detach(void *xsc) 355 { 356 struct rt2661_softc *sc = xsc; 357 struct ifnet *ifp = sc->sc_ifp; 358 struct ieee80211com *ic = ifp->if_l2com; 359 360 RAL_LOCK(sc); 361 rt2661_stop_locked(sc); 362 RAL_UNLOCK(sc); 363 364 bpfdetach(ifp); 365 ieee80211_ifdetach(ic); 366 367 rt2661_free_tx_ring(sc, &sc->txq[0]); 368 rt2661_free_tx_ring(sc, &sc->txq[1]); 369 rt2661_free_tx_ring(sc, &sc->txq[2]); 370 rt2661_free_tx_ring(sc, &sc->txq[3]); 371 rt2661_free_tx_ring(sc, &sc->mgtq); 372 rt2661_free_rx_ring(sc, &sc->rxq); 373 374 if_free(ifp); 375 376 mtx_destroy(&sc->sc_mtx); 377 378 return 0; 379 } 380 381 static struct ieee80211vap * 382 rt2661_vap_create(struct ieee80211com *ic, 383 const char name[IFNAMSIZ], int unit, int opmode, int flags, 384 const uint8_t bssid[IEEE80211_ADDR_LEN], 385 const uint8_t mac[IEEE80211_ADDR_LEN]) 386 { 387 struct ifnet *ifp = ic->ic_ifp; 388 struct rt2661_vap *rvp; 389 struct ieee80211vap *vap; 390 391 switch (opmode) { 392 case IEEE80211_M_STA: 393 case IEEE80211_M_IBSS: 394 case IEEE80211_M_AHDEMO: 395 case IEEE80211_M_MONITOR: 396 case IEEE80211_M_HOSTAP: 397 if (!TAILQ_EMPTY(&ic->ic_vaps)) { 398 if_printf(ifp, "only 1 vap supported\n"); 399 return NULL; 400 } 401 if (opmode == IEEE80211_M_STA) 402 flags |= IEEE80211_CLONE_NOBEACONS; 403 break; 404 case IEEE80211_M_WDS: 405 if (TAILQ_EMPTY(&ic->ic_vaps) || 406 ic->ic_opmode != IEEE80211_M_HOSTAP) { 407 if_printf(ifp, "wds only supported in ap mode\n"); 408 return NULL; 409 } 410 /* 411 * Silently remove any request for a unique 412 * bssid; WDS vap's always share the local 413 * mac address. 414 */ 415 flags &= ~IEEE80211_CLONE_BSSID; 416 break; 417 default: 418 if_printf(ifp, "unknown opmode %d\n", opmode); 419 return NULL; 420 } 421 rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap), 422 M_80211_VAP, M_NOWAIT | M_ZERO); 423 if (rvp == NULL) 424 return NULL; 425 vap = &rvp->ral_vap; 426 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); 427 428 /* override state transition machine */ 429 rvp->ral_newstate = vap->iv_newstate; 430 vap->iv_newstate = rt2661_newstate; 431 #if 0 432 vap->iv_update_beacon = rt2661_beacon_update; 433 #endif 434 435 ieee80211_amrr_init(&rvp->amrr, vap, 436 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 437 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 438 500 /* ms */); 439 440 /* complete setup */ 441 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 442 if (TAILQ_FIRST(&ic->ic_vaps) == vap) 443 ic->ic_opmode = opmode; 444 return vap; 445 } 446 447 static void 448 rt2661_vap_delete(struct ieee80211vap *vap) 449 { 450 struct rt2661_vap *rvp = RT2661_VAP(vap); 451 452 ieee80211_amrr_cleanup(&rvp->amrr); 453 ieee80211_vap_detach(vap); 454 free(rvp, M_80211_VAP); 455 } 456 457 void 458 rt2661_shutdown(void *xsc) 459 { 460 struct rt2661_softc *sc = xsc; 461 462 rt2661_stop(sc); 463 } 464 465 void 466 rt2661_suspend(void *xsc) 467 { 468 struct rt2661_softc *sc = xsc; 469 470 rt2661_stop(sc); 471 } 472 473 void 474 rt2661_resume(void *xsc) 475 { 476 struct rt2661_softc *sc = xsc; 477 struct ifnet *ifp = sc->sc_ifp; 478 479 if (ifp->if_flags & IFF_UP) 480 rt2661_init(sc); 481 } 482 483 static void 484 rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 485 { 486 if (error != 0) 487 return; 488 489 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 490 491 *(bus_addr_t *)arg = segs[0].ds_addr; 492 } 493 494 static int 495 rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, 496 int count) 497 { 498 int i, error; 499 500 ring->count = count; 501 ring->queued = 0; 502 ring->cur = ring->next = ring->stat = 0; 503 504 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 505 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 506 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, 507 0, NULL, NULL, &ring->desc_dmat); 508 if (error != 0) { 509 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 510 goto fail; 511 } 512 513 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 514 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 515 if (error != 0) { 516 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 517 goto fail; 518 } 519 520 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 521 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 522 0); 523 if (error != 0) { 524 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 525 goto fail; 526 } 527 528 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, 529 M_NOWAIT | M_ZERO); 530 if (ring->data == NULL) { 531 device_printf(sc->sc_dev, "could not allocate soft data\n"); 532 error = ENOMEM; 533 goto fail; 534 } 535 536 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 537 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 538 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 539 if (error != 0) { 540 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 541 goto fail; 542 } 543 544 for (i = 0; i < count; i++) { 545 error = bus_dmamap_create(ring->data_dmat, 0, 546 &ring->data[i].map); 547 if (error != 0) { 548 device_printf(sc->sc_dev, "could not create DMA map\n"); 549 goto fail; 550 } 551 } 552 553 return 0; 554 555 fail: rt2661_free_tx_ring(sc, ring); 556 return error; 557 } 558 559 static void 560 rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 561 { 562 struct rt2661_tx_desc *desc; 563 struct rt2661_tx_data *data; 564 int i; 565 566 for (i = 0; i < ring->count; i++) { 567 desc = &ring->desc[i]; 568 data = &ring->data[i]; 569 570 if (data->m != NULL) { 571 bus_dmamap_sync(ring->data_dmat, data->map, 572 BUS_DMASYNC_POSTWRITE); 573 bus_dmamap_unload(ring->data_dmat, data->map); 574 m_freem(data->m); 575 data->m = NULL; 576 } 577 578 if (data->ni != NULL) { 579 ieee80211_free_node(data->ni); 580 data->ni = NULL; 581 } 582 583 desc->flags = 0; 584 } 585 586 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 587 588 ring->queued = 0; 589 ring->cur = ring->next = ring->stat = 0; 590 } 591 592 static void 593 rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) 594 { 595 struct rt2661_tx_data *data; 596 int i; 597 598 if (ring->desc != NULL) { 599 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 600 BUS_DMASYNC_POSTWRITE); 601 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 602 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 603 } 604 605 if (ring->desc_dmat != NULL) 606 bus_dma_tag_destroy(ring->desc_dmat); 607 608 if (ring->data != NULL) { 609 for (i = 0; i < ring->count; i++) { 610 data = &ring->data[i]; 611 612 if (data->m != NULL) { 613 bus_dmamap_sync(ring->data_dmat, data->map, 614 BUS_DMASYNC_POSTWRITE); 615 bus_dmamap_unload(ring->data_dmat, data->map); 616 m_freem(data->m); 617 } 618 619 if (data->ni != NULL) 620 ieee80211_free_node(data->ni); 621 622 if (data->map != NULL) 623 bus_dmamap_destroy(ring->data_dmat, data->map); 624 } 625 626 free(ring->data, M_DEVBUF); 627 } 628 629 if (ring->data_dmat != NULL) 630 bus_dma_tag_destroy(ring->data_dmat); 631 } 632 633 static int 634 rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, 635 int count) 636 { 637 struct rt2661_rx_desc *desc; 638 struct rt2661_rx_data *data; 639 bus_addr_t physaddr; 640 int i, error; 641 642 ring->count = count; 643 ring->cur = ring->next = 0; 644 645 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, 646 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 647 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, 648 0, NULL, NULL, &ring->desc_dmat); 649 if (error != 0) { 650 device_printf(sc->sc_dev, "could not create desc DMA tag\n"); 651 goto fail; 652 } 653 654 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, 655 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); 656 if (error != 0) { 657 device_printf(sc->sc_dev, "could not allocate DMA memory\n"); 658 goto fail; 659 } 660 661 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, 662 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, 663 0); 664 if (error != 0) { 665 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 666 goto fail; 667 } 668 669 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, 670 M_NOWAIT | M_ZERO); 671 if (ring->data == NULL) { 672 device_printf(sc->sc_dev, "could not allocate soft data\n"); 673 error = ENOMEM; 674 goto fail; 675 } 676 677 /* 678 * Pre-allocate Rx buffers and populate Rx ring. 679 */ 680 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 681 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 682 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); 683 if (error != 0) { 684 device_printf(sc->sc_dev, "could not create data DMA tag\n"); 685 goto fail; 686 } 687 688 for (i = 0; i < count; i++) { 689 desc = &sc->rxq.desc[i]; 690 data = &sc->rxq.data[i]; 691 692 error = bus_dmamap_create(ring->data_dmat, 0, &data->map); 693 if (error != 0) { 694 device_printf(sc->sc_dev, "could not create DMA map\n"); 695 goto fail; 696 } 697 698 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 699 if (data->m == NULL) { 700 device_printf(sc->sc_dev, 701 "could not allocate rx mbuf\n"); 702 error = ENOMEM; 703 goto fail; 704 } 705 706 error = bus_dmamap_load(ring->data_dmat, data->map, 707 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, 708 &physaddr, 0); 709 if (error != 0) { 710 device_printf(sc->sc_dev, 711 "could not load rx buf DMA map"); 712 goto fail; 713 } 714 715 desc->flags = htole32(RT2661_RX_BUSY); 716 desc->physaddr = htole32(physaddr); 717 } 718 719 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 720 721 return 0; 722 723 fail: rt2661_free_rx_ring(sc, ring); 724 return error; 725 } 726 727 static void 728 rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 729 { 730 int i; 731 732 for (i = 0; i < ring->count; i++) 733 ring->desc[i].flags = htole32(RT2661_RX_BUSY); 734 735 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); 736 737 ring->cur = ring->next = 0; 738 } 739 740 static void 741 rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) 742 { 743 struct rt2661_rx_data *data; 744 int i; 745 746 if (ring->desc != NULL) { 747 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, 748 BUS_DMASYNC_POSTWRITE); 749 bus_dmamap_unload(ring->desc_dmat, ring->desc_map); 750 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); 751 } 752 753 if (ring->desc_dmat != NULL) 754 bus_dma_tag_destroy(ring->desc_dmat); 755 756 if (ring->data != NULL) { 757 for (i = 0; i < ring->count; i++) { 758 data = &ring->data[i]; 759 760 if (data->m != NULL) { 761 bus_dmamap_sync(ring->data_dmat, data->map, 762 BUS_DMASYNC_POSTREAD); 763 bus_dmamap_unload(ring->data_dmat, data->map); 764 m_freem(data->m); 765 } 766 767 if (data->map != NULL) 768 bus_dmamap_destroy(ring->data_dmat, data->map); 769 } 770 771 free(ring->data, M_DEVBUF); 772 } 773 774 if (ring->data_dmat != NULL) 775 bus_dma_tag_destroy(ring->data_dmat); 776 } 777 778 static struct ieee80211_node * 779 rt2661_node_alloc(struct ieee80211_node_table *nt) 780 { 781 struct rt2661_node *rn; 782 783 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, 784 M_NOWAIT | M_ZERO); 785 786 return (rn != NULL) ? &rn->ni : NULL; 787 } 788 789 static void 790 rt2661_newassoc(struct ieee80211_node *ni, int isnew) 791 { 792 struct ieee80211vap *vap = ni->ni_vap; 793 794 ieee80211_amrr_node_init(&RT2661_VAP(vap)->amrr, 795 &RT2661_NODE(ni)->amrr, ni); 796 } 797 798 static int 799 rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 800 { 801 struct rt2661_vap *rvp = RT2661_VAP(vap); 802 struct ieee80211com *ic = vap->iv_ic; 803 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 804 int error; 805 806 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { 807 uint32_t tmp; 808 809 /* abort TSF synchronization */ 810 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 811 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); 812 } 813 814 error = rvp->ral_newstate(vap, nstate, arg); 815 816 if (error == 0 && nstate == IEEE80211_S_RUN) { 817 struct ieee80211_node *ni = vap->iv_bss; 818 819 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 820 rt2661_enable_mrr(sc); 821 rt2661_set_txpreamble(sc); 822 rt2661_set_basicrates(sc, &ni->ni_rates); 823 rt2661_set_bssid(sc, ni->ni_bssid); 824 } 825 826 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 827 vap->iv_opmode == IEEE80211_M_IBSS) { 828 error = rt2661_prepare_beacon(sc, vap); 829 if (error != 0) 830 return error; 831 } 832 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 833 if (vap->iv_opmode == IEEE80211_M_STA) { 834 /* fake a join to init the tx rate */ 835 rt2661_newassoc(ni, 1); 836 } 837 rt2661_enable_tsf_sync(sc); 838 } 839 } 840 return error; 841 } 842 843 /* 844 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 845 * 93C66). 846 */ 847 static uint16_t 848 rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) 849 { 850 uint32_t tmp; 851 uint16_t val; 852 int n; 853 854 /* clock C once before the first command */ 855 RT2661_EEPROM_CTL(sc, 0); 856 857 RT2661_EEPROM_CTL(sc, RT2661_S); 858 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 859 RT2661_EEPROM_CTL(sc, RT2661_S); 860 861 /* write start bit (1) */ 862 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 863 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 864 865 /* write READ opcode (10) */ 866 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); 867 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); 868 RT2661_EEPROM_CTL(sc, RT2661_S); 869 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 870 871 /* write address (A5-A0 or A7-A0) */ 872 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; 873 for (; n >= 0; n--) { 874 RT2661_EEPROM_CTL(sc, RT2661_S | 875 (((addr >> n) & 1) << RT2661_SHIFT_D)); 876 RT2661_EEPROM_CTL(sc, RT2661_S | 877 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); 878 } 879 880 RT2661_EEPROM_CTL(sc, RT2661_S); 881 882 /* read data Q15-Q0 */ 883 val = 0; 884 for (n = 15; n >= 0; n--) { 885 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); 886 tmp = RAL_READ(sc, RT2661_E2PROM_CSR); 887 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; 888 RT2661_EEPROM_CTL(sc, RT2661_S); 889 } 890 891 RT2661_EEPROM_CTL(sc, 0); 892 893 /* clear Chip Select and clock C */ 894 RT2661_EEPROM_CTL(sc, RT2661_S); 895 RT2661_EEPROM_CTL(sc, 0); 896 RT2661_EEPROM_CTL(sc, RT2661_C); 897 898 return val; 899 } 900 901 static void 902 rt2661_tx_intr(struct rt2661_softc *sc) 903 { 904 struct ifnet *ifp = sc->sc_ifp; 905 struct rt2661_tx_ring *txq; 906 struct rt2661_tx_data *data; 907 struct rt2661_node *rn; 908 uint32_t val; 909 int qid, retrycnt; 910 911 for (;;) { 912 struct ieee80211_node *ni; 913 struct mbuf *m; 914 915 val = RAL_READ(sc, RT2661_STA_CSR4); 916 if (!(val & RT2661_TX_STAT_VALID)) 917 break; 918 919 /* retrieve the queue in which this frame was sent */ 920 qid = RT2661_TX_QID(val); 921 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; 922 923 /* retrieve rate control algorithm context */ 924 data = &txq->data[txq->stat]; 925 m = data->m; 926 data->m = NULL; 927 ni = data->ni; 928 data->ni = NULL; 929 930 /* if no frame has been sent, ignore */ 931 if (ni == NULL) 932 continue; 933 934 rn = RT2661_NODE(ni); 935 936 switch (RT2661_TX_RESULT(val)) { 937 case RT2661_TX_SUCCESS: 938 retrycnt = RT2661_TX_RETRYCNT(val); 939 940 DPRINTFN(sc, 10, "data frame sent successfully after " 941 "%d retries\n", retrycnt); 942 if (data->rix != IEEE80211_FIXED_RATE_NONE) 943 ieee80211_amrr_tx_complete(&rn->amrr, 944 IEEE80211_AMRR_SUCCESS, retrycnt); 945 ifp->if_opackets++; 946 break; 947 948 case RT2661_TX_RETRY_FAIL: 949 retrycnt = RT2661_TX_RETRYCNT(val); 950 951 DPRINTFN(sc, 9, "%s\n", 952 "sending data frame failed (too much retries)"); 953 if (data->rix != IEEE80211_FIXED_RATE_NONE) 954 ieee80211_amrr_tx_complete(&rn->amrr, 955 IEEE80211_AMRR_FAILURE, retrycnt); 956 ifp->if_oerrors++; 957 break; 958 959 default: 960 /* other failure */ 961 device_printf(sc->sc_dev, 962 "sending data frame failed 0x%08x\n", val); 963 ifp->if_oerrors++; 964 } 965 966 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); 967 968 txq->queued--; 969 if (++txq->stat >= txq->count) /* faster than % count */ 970 txq->stat = 0; 971 972 if (m->m_flags & M_TXCB) 973 ieee80211_process_callback(ni, m, 974 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); 975 m_freem(m); 976 ieee80211_free_node(ni); 977 } 978 979 sc->sc_tx_timer = 0; 980 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 981 982 rt2661_start_locked(ifp); 983 } 984 985 static void 986 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) 987 { 988 struct rt2661_tx_desc *desc; 989 struct rt2661_tx_data *data; 990 991 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); 992 993 for (;;) { 994 desc = &txq->desc[txq->next]; 995 data = &txq->data[txq->next]; 996 997 if ((le32toh(desc->flags) & RT2661_TX_BUSY) || 998 !(le32toh(desc->flags) & RT2661_TX_VALID)) 999 break; 1000 1001 bus_dmamap_sync(txq->data_dmat, data->map, 1002 BUS_DMASYNC_POSTWRITE); 1003 bus_dmamap_unload(txq->data_dmat, data->map); 1004 1005 /* descriptor is no longer valid */ 1006 desc->flags &= ~htole32(RT2661_TX_VALID); 1007 1008 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); 1009 1010 if (++txq->next >= txq->count) /* faster than % count */ 1011 txq->next = 0; 1012 } 1013 1014 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1015 } 1016 1017 static void 1018 rt2661_rx_intr(struct rt2661_softc *sc) 1019 { 1020 struct ifnet *ifp = sc->sc_ifp; 1021 struct ieee80211com *ic = ifp->if_l2com; 1022 struct rt2661_rx_desc *desc; 1023 struct rt2661_rx_data *data; 1024 bus_addr_t physaddr; 1025 struct ieee80211_frame *wh; 1026 struct ieee80211_node *ni; 1027 struct mbuf *mnew, *m; 1028 int error; 1029 1030 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1031 BUS_DMASYNC_POSTREAD); 1032 1033 for (;;) { 1034 int rssi; 1035 1036 desc = &sc->rxq.desc[sc->rxq.cur]; 1037 data = &sc->rxq.data[sc->rxq.cur]; 1038 1039 if (le32toh(desc->flags) & RT2661_RX_BUSY) 1040 break; 1041 1042 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || 1043 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { 1044 /* 1045 * This should not happen since we did not request 1046 * to receive those frames when we filled TXRX_CSR0. 1047 */ 1048 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", 1049 le32toh(desc->flags)); 1050 ifp->if_ierrors++; 1051 goto skip; 1052 } 1053 1054 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { 1055 ifp->if_ierrors++; 1056 goto skip; 1057 } 1058 1059 /* 1060 * Try to allocate a new mbuf for this ring element and load it 1061 * before processing the current mbuf. If the ring element 1062 * cannot be loaded, drop the received packet and reuse the old 1063 * mbuf. In the unlikely case that the old mbuf can't be 1064 * reloaded either, explicitly panic. 1065 */ 1066 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1067 if (mnew == NULL) { 1068 ifp->if_ierrors++; 1069 goto skip; 1070 } 1071 1072 bus_dmamap_sync(sc->rxq.data_dmat, data->map, 1073 BUS_DMASYNC_POSTREAD); 1074 bus_dmamap_unload(sc->rxq.data_dmat, data->map); 1075 1076 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1077 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, 1078 &physaddr, 0); 1079 if (error != 0) { 1080 m_freem(mnew); 1081 1082 /* try to reload the old mbuf */ 1083 error = bus_dmamap_load(sc->rxq.data_dmat, data->map, 1084 mtod(data->m, void *), MCLBYTES, 1085 rt2661_dma_map_addr, &physaddr, 0); 1086 if (error != 0) { 1087 /* very unlikely that it will fail... */ 1088 panic("%s: could not load old rx mbuf", 1089 device_get_name(sc->sc_dev)); 1090 } 1091 ifp->if_ierrors++; 1092 goto skip; 1093 } 1094 1095 /* 1096 * New mbuf successfully loaded, update Rx ring and continue 1097 * processing. 1098 */ 1099 m = data->m; 1100 data->m = mnew; 1101 desc->physaddr = htole32(physaddr); 1102 1103 /* finalize mbuf */ 1104 m->m_pkthdr.rcvif = ifp; 1105 m->m_pkthdr.len = m->m_len = 1106 (le32toh(desc->flags) >> 16) & 0xfff; 1107 1108 rssi = rt2661_get_rssi(sc, desc->rssi); 1109 1110 if (bpf_peers_present(ifp->if_bpf)) { 1111 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; 1112 uint32_t tsf_lo, tsf_hi; 1113 1114 /* get timestamp (low and high 32 bits) */ 1115 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); 1116 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); 1117 1118 tap->wr_tsf = 1119 htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 1120 tap->wr_flags = 0; 1121 tap->wr_rate = ieee80211_plcp2rate(desc->rate, 1122 (desc->flags & htole32(RT2661_RX_OFDM)) ? 1123 IEEE80211_T_OFDM : IEEE80211_T_CCK); 1124 tap->wr_antsignal = rssi < 0 ? 0 : rssi; 1125 1126 bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m); 1127 } 1128 sc->sc_flags |= RAL_INPUT_RUNNING; 1129 RAL_UNLOCK(sc); 1130 wh = mtod(m, struct ieee80211_frame *); 1131 1132 /* send the frame to the 802.11 layer */ 1133 ni = ieee80211_find_rxnode(ic, 1134 (struct ieee80211_frame_min *)wh); 1135 if (ni != NULL) { 1136 /* Error happened during RSSI conversion. */ 1137 if (rssi < 0) 1138 rssi = -30; /* XXX ignored by net80211 */ 1139 1140 (void) ieee80211_input(ni, m, rssi, 1141 RT2661_NOISE_FLOOR, 0); 1142 ieee80211_free_node(ni); 1143 } else 1144 (void) ieee80211_input_all(ic, m, rssi, 1145 RT2661_NOISE_FLOOR, 0); 1146 1147 RAL_LOCK(sc); 1148 sc->sc_flags &= ~RAL_INPUT_RUNNING; 1149 1150 skip: desc->flags |= htole32(RT2661_RX_BUSY); 1151 1152 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); 1153 1154 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; 1155 } 1156 1157 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, 1158 BUS_DMASYNC_PREWRITE); 1159 } 1160 1161 /* ARGSUSED */ 1162 static void 1163 rt2661_mcu_beacon_expire(struct rt2661_softc *sc) 1164 { 1165 /* do nothing */ 1166 } 1167 1168 static void 1169 rt2661_mcu_wakeup(struct rt2661_softc *sc) 1170 { 1171 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); 1172 1173 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); 1174 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); 1175 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); 1176 1177 /* send wakeup command to MCU */ 1178 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); 1179 } 1180 1181 static void 1182 rt2661_mcu_cmd_intr(struct rt2661_softc *sc) 1183 { 1184 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); 1185 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 1186 } 1187 1188 void 1189 rt2661_intr(void *arg) 1190 { 1191 struct rt2661_softc *sc = arg; 1192 struct ifnet *ifp = sc->sc_ifp; 1193 uint32_t r1, r2; 1194 1195 RAL_LOCK(sc); 1196 1197 /* disable MAC and MCU interrupts */ 1198 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); 1199 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 1200 1201 /* don't re-enable interrupts if we're shutting down */ 1202 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1203 RAL_UNLOCK(sc); 1204 return; 1205 } 1206 1207 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); 1208 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); 1209 1210 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); 1211 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); 1212 1213 if (r1 & RT2661_MGT_DONE) 1214 rt2661_tx_dma_intr(sc, &sc->mgtq); 1215 1216 if (r1 & RT2661_RX_DONE) 1217 rt2661_rx_intr(sc); 1218 1219 if (r1 & RT2661_TX0_DMA_DONE) 1220 rt2661_tx_dma_intr(sc, &sc->txq[0]); 1221 1222 if (r1 & RT2661_TX1_DMA_DONE) 1223 rt2661_tx_dma_intr(sc, &sc->txq[1]); 1224 1225 if (r1 & RT2661_TX2_DMA_DONE) 1226 rt2661_tx_dma_intr(sc, &sc->txq[2]); 1227 1228 if (r1 & RT2661_TX3_DMA_DONE) 1229 rt2661_tx_dma_intr(sc, &sc->txq[3]); 1230 1231 if (r1 & RT2661_TX_DONE) 1232 rt2661_tx_intr(sc); 1233 1234 if (r2 & RT2661_MCU_CMD_DONE) 1235 rt2661_mcu_cmd_intr(sc); 1236 1237 if (r2 & RT2661_MCU_BEACON_EXPIRE) 1238 rt2661_mcu_beacon_expire(sc); 1239 1240 if (r2 & RT2661_MCU_WAKEUP) 1241 rt2661_mcu_wakeup(sc); 1242 1243 /* re-enable MAC and MCU interrupts */ 1244 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 1245 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 1246 1247 RAL_UNLOCK(sc); 1248 } 1249 1250 static uint8_t 1251 rt2661_plcp_signal(int rate) 1252 { 1253 switch (rate) { 1254 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1255 case 12: return 0xb; 1256 case 18: return 0xf; 1257 case 24: return 0xa; 1258 case 36: return 0xe; 1259 case 48: return 0x9; 1260 case 72: return 0xd; 1261 case 96: return 0x8; 1262 case 108: return 0xc; 1263 1264 /* CCK rates (NB: not IEEE std, device-specific) */ 1265 case 2: return 0x0; 1266 case 4: return 0x1; 1267 case 11: return 0x2; 1268 case 22: return 0x3; 1269 } 1270 return 0xff; /* XXX unsupported/unknown rate */ 1271 } 1272 1273 static void 1274 rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, 1275 uint32_t flags, uint16_t xflags, int len, int rate, 1276 const bus_dma_segment_t *segs, int nsegs, int ac) 1277 { 1278 struct ifnet *ifp = sc->sc_ifp; 1279 struct ieee80211com *ic = ifp->if_l2com; 1280 uint16_t plcp_length; 1281 int i, remainder; 1282 1283 desc->flags = htole32(flags); 1284 desc->flags |= htole32(len << 16); 1285 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); 1286 1287 desc->xflags = htole16(xflags); 1288 desc->xflags |= htole16(nsegs << 13); 1289 1290 desc->wme = htole16( 1291 RT2661_QID(ac) | 1292 RT2661_AIFSN(2) | 1293 RT2661_LOGCWMIN(4) | 1294 RT2661_LOGCWMAX(10)); 1295 1296 /* 1297 * Remember in which queue this frame was sent. This field is driver 1298 * private data only. It will be made available by the NIC in STA_CSR4 1299 * on Tx interrupts. 1300 */ 1301 desc->qid = ac; 1302 1303 /* setup PLCP fields */ 1304 desc->plcp_signal = rt2661_plcp_signal(rate); 1305 desc->plcp_service = 4; 1306 1307 len += IEEE80211_CRC_LEN; 1308 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 1309 desc->flags |= htole32(RT2661_TX_OFDM); 1310 1311 plcp_length = len & 0xfff; 1312 desc->plcp_length_hi = plcp_length >> 6; 1313 desc->plcp_length_lo = plcp_length & 0x3f; 1314 } else { 1315 plcp_length = (16 * len + rate - 1) / rate; 1316 if (rate == 22) { 1317 remainder = (16 * len) % 22; 1318 if (remainder != 0 && remainder < 7) 1319 desc->plcp_service |= RT2661_PLCP_LENGEXT; 1320 } 1321 desc->plcp_length_hi = plcp_length >> 8; 1322 desc->plcp_length_lo = plcp_length & 0xff; 1323 1324 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1325 desc->plcp_signal |= 0x08; 1326 } 1327 1328 /* RT2x61 supports scatter with up to 5 segments */ 1329 for (i = 0; i < nsegs; i++) { 1330 desc->addr[i] = htole32(segs[i].ds_addr); 1331 desc->len [i] = htole16(segs[i].ds_len); 1332 } 1333 } 1334 1335 static int 1336 rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, 1337 struct ieee80211_node *ni) 1338 { 1339 struct ieee80211vap *vap = ni->ni_vap; 1340 struct ieee80211com *ic = ni->ni_ic; 1341 struct ifnet *ifp = sc->sc_ifp; 1342 struct rt2661_tx_desc *desc; 1343 struct rt2661_tx_data *data; 1344 struct ieee80211_frame *wh; 1345 struct ieee80211_key *k; 1346 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1347 uint16_t dur; 1348 uint32_t flags = 0; /* XXX HWSEQ */ 1349 int nsegs, rate, error; 1350 1351 desc = &sc->mgtq.desc[sc->mgtq.cur]; 1352 data = &sc->mgtq.data[sc->mgtq.cur]; 1353 1354 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; 1355 1356 wh = mtod(m0, struct ieee80211_frame *); 1357 1358 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1359 k = ieee80211_crypto_encap(ni, m0); 1360 if (k == NULL) { 1361 m_freem(m0); 1362 return ENOBUFS; 1363 } 1364 } 1365 1366 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, 1367 segs, &nsegs, 0); 1368 if (error != 0) { 1369 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1370 error); 1371 m_freem(m0); 1372 return error; 1373 } 1374 1375 if (bpf_peers_present(ifp->if_bpf)) { 1376 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1377 1378 tap->wt_flags = 0; 1379 tap->wt_rate = rate; 1380 1381 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0); 1382 } 1383 1384 data->m = m0; 1385 data->ni = ni; 1386 /* management frames are not taken into account for amrr */ 1387 data->rix = IEEE80211_FIXED_RATE_NONE; 1388 1389 wh = mtod(m0, struct ieee80211_frame *); 1390 1391 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1392 flags |= RT2661_TX_NEED_ACK; 1393 1394 dur = ieee80211_ack_duration(sc->sc_rates, 1395 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1396 *(uint16_t *)wh->i_dur = htole16(dur); 1397 1398 /* tell hardware to add timestamp in probe responses */ 1399 if ((wh->i_fc[0] & 1400 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == 1401 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) 1402 flags |= RT2661_TX_TIMESTAMP; 1403 } 1404 1405 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, 1406 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); 1407 1408 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1409 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, 1410 BUS_DMASYNC_PREWRITE); 1411 1412 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", 1413 m0->m_pkthdr.len, sc->mgtq.cur, rate); 1414 1415 /* kick mgt */ 1416 sc->mgtq.queued++; 1417 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; 1418 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); 1419 1420 return 0; 1421 } 1422 1423 static int 1424 rt2661_sendprot(struct rt2661_softc *sc, int ac, 1425 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1426 { 1427 struct ieee80211com *ic = ni->ni_ic; 1428 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1429 const struct ieee80211_frame *wh; 1430 struct rt2661_tx_desc *desc; 1431 struct rt2661_tx_data *data; 1432 struct mbuf *mprot; 1433 int protrate, ackrate, pktlen, flags, isshort, error; 1434 uint16_t dur; 1435 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1436 int nsegs; 1437 1438 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1439 ("protection %d", prot)); 1440 1441 wh = mtod(m, const struct ieee80211_frame *); 1442 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1443 1444 protrate = ieee80211_ctl_rate(sc->sc_rates, rate); 1445 ackrate = ieee80211_ack_rate(sc->sc_rates, rate); 1446 1447 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1448 dur = ieee80211_compute_duration(sc->sc_rates, pktlen, rate, isshort) 1449 + ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1450 flags = RT2661_TX_MORE_FRAG; 1451 if (prot == IEEE80211_PROT_RTSCTS) { 1452 /* NB: CTS is the same size as an ACK */ 1453 dur += ieee80211_ack_duration(sc->sc_rates, rate, isshort); 1454 flags |= RT2661_TX_NEED_ACK; 1455 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1456 } else { 1457 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1458 } 1459 if (mprot == NULL) { 1460 /* XXX stat + msg */ 1461 return ENOBUFS; 1462 } 1463 1464 data = &txq->data[txq->cur]; 1465 desc = &txq->desc[txq->cur]; 1466 1467 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, 1468 &nsegs, 0); 1469 if (error != 0) { 1470 device_printf(sc->sc_dev, 1471 "could not map mbuf (error %d)\n", error); 1472 m_freem(mprot); 1473 return error; 1474 } 1475 1476 data->m = mprot; 1477 data->ni = ieee80211_ref_node(ni); 1478 /* ctl frames are not taken into account for amrr */ 1479 data->rix = IEEE80211_FIXED_RATE_NONE; 1480 1481 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, 1482 protrate, segs, 1, ac); 1483 1484 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1485 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1486 1487 txq->queued++; 1488 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1489 1490 return 0; 1491 } 1492 1493 static int 1494 rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, 1495 struct ieee80211_node *ni, int ac) 1496 { 1497 struct ieee80211vap *vap = ni->ni_vap; 1498 struct ifnet *ifp = sc->sc_ifp; 1499 struct ieee80211com *ic = ifp->if_l2com; 1500 struct rt2661_tx_ring *txq = &sc->txq[ac]; 1501 struct rt2661_tx_desc *desc; 1502 struct rt2661_tx_data *data; 1503 struct ieee80211_frame *wh; 1504 const struct ieee80211_txparam *tp; 1505 struct ieee80211_key *k; 1506 const struct chanAccParams *cap; 1507 struct mbuf *mnew; 1508 bus_dma_segment_t segs[RT2661_MAX_SCATTER]; 1509 uint16_t dur; 1510 uint32_t flags; 1511 int error, nsegs, rate, noack = 0; 1512 1513 wh = mtod(m0, struct ieee80211_frame *); 1514 1515 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1516 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1517 rate = tp->mcastrate; 1518 } else if (m0->m_flags & M_EAPOL) { 1519 rate = tp->mgmtrate; 1520 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 1521 rate = tp->ucastrate; 1522 } else { 1523 (void) ieee80211_amrr_choose(ni, &RT2661_NODE(ni)->amrr); 1524 rate = ni->ni_txrate; 1525 } 1526 rate &= IEEE80211_RATE_VAL; 1527 1528 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 1529 cap = &ic->ic_wme.wme_chanParams; 1530 noack = cap->cap_wmeParams[ac].wmep_noackPolicy; 1531 } 1532 1533 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1534 k = ieee80211_crypto_encap(ni, m0); 1535 if (k == NULL) { 1536 m_freem(m0); 1537 return ENOBUFS; 1538 } 1539 1540 /* packet header may have moved, reset our local pointer */ 1541 wh = mtod(m0, struct ieee80211_frame *); 1542 } 1543 1544 flags = 0; 1545 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1546 int prot = IEEE80211_PROT_NONE; 1547 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1548 prot = IEEE80211_PROT_RTSCTS; 1549 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1550 ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 1551 prot = ic->ic_protmode; 1552 if (prot != IEEE80211_PROT_NONE) { 1553 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); 1554 if (error) { 1555 m_freem(m0); 1556 return error; 1557 } 1558 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; 1559 } 1560 } 1561 1562 data = &txq->data[txq->cur]; 1563 desc = &txq->desc[txq->cur]; 1564 1565 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, 1566 &nsegs, 0); 1567 if (error != 0 && error != EFBIG) { 1568 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", 1569 error); 1570 m_freem(m0); 1571 return error; 1572 } 1573 if (error != 0) { 1574 mnew = m_defrag(m0, M_DONTWAIT); 1575 if (mnew == NULL) { 1576 device_printf(sc->sc_dev, 1577 "could not defragment mbuf\n"); 1578 m_freem(m0); 1579 return ENOBUFS; 1580 } 1581 m0 = mnew; 1582 1583 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, 1584 segs, &nsegs, 0); 1585 if (error != 0) { 1586 device_printf(sc->sc_dev, 1587 "could not map mbuf (error %d)\n", error); 1588 m_freem(m0); 1589 return error; 1590 } 1591 1592 /* packet header have moved, reset our local pointer */ 1593 wh = mtod(m0, struct ieee80211_frame *); 1594 } 1595 1596 if (bpf_peers_present(ifp->if_bpf)) { 1597 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; 1598 1599 tap->wt_flags = 0; 1600 tap->wt_rate = rate; 1601 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1602 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1603 1604 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0); 1605 } 1606 1607 data->m = m0; 1608 data->ni = ni; 1609 1610 /* remember link conditions for rate adaptation algorithm */ 1611 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { 1612 data->rix = ni->ni_txrate; 1613 /* XXX probably need last rssi value and not avg */ 1614 data->rssi = ic->ic_node_getrssi(ni); 1615 } else 1616 data->rix = IEEE80211_FIXED_RATE_NONE; 1617 1618 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1619 flags |= RT2661_TX_NEED_ACK; 1620 1621 dur = ieee80211_ack_duration(sc->sc_rates, 1622 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1623 *(uint16_t *)wh->i_dur = htole16(dur); 1624 } 1625 1626 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, 1627 nsegs, ac); 1628 1629 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); 1630 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); 1631 1632 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", 1633 m0->m_pkthdr.len, txq->cur, rate); 1634 1635 /* kick Tx */ 1636 txq->queued++; 1637 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; 1638 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); 1639 1640 return 0; 1641 } 1642 1643 static void 1644 rt2661_start_locked(struct ifnet *ifp) 1645 { 1646 struct rt2661_softc *sc = ifp->if_softc; 1647 struct mbuf *m; 1648 struct ieee80211_node *ni; 1649 int ac; 1650 1651 RAL_LOCK_ASSERT(sc); 1652 1653 /* prevent management frames from being sent if we're not ready */ 1654 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid) 1655 return; 1656 1657 for (;;) { 1658 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1659 if (m == NULL) 1660 break; 1661 1662 ac = M_WME_GETAC(m); 1663 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { 1664 /* there is no place left in this ring */ 1665 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1666 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1667 break; 1668 } 1669 1670 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1671 m = ieee80211_encap(ni, m); 1672 if (m == NULL) { 1673 ieee80211_free_node(ni); 1674 ifp->if_oerrors++; 1675 continue; 1676 } 1677 1678 if (rt2661_tx_data(sc, m, ni, ac) != 0) { 1679 ieee80211_free_node(ni); 1680 ifp->if_oerrors++; 1681 break; 1682 } 1683 1684 sc->sc_tx_timer = 5; 1685 } 1686 } 1687 1688 static void 1689 rt2661_start(struct ifnet *ifp) 1690 { 1691 struct rt2661_softc *sc = ifp->if_softc; 1692 1693 RAL_LOCK(sc); 1694 rt2661_start_locked(ifp); 1695 RAL_UNLOCK(sc); 1696 } 1697 1698 static int 1699 rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1700 const struct ieee80211_bpf_params *params) 1701 { 1702 struct ieee80211com *ic = ni->ni_ic; 1703 struct ifnet *ifp = ic->ic_ifp; 1704 struct rt2661_softc *sc = ifp->if_softc; 1705 1706 RAL_LOCK(sc); 1707 1708 /* prevent management frames from being sent if we're not ready */ 1709 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1710 RAL_UNLOCK(sc); 1711 m_freem(m); 1712 ieee80211_free_node(ni); 1713 return ENETDOWN; 1714 } 1715 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { 1716 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1717 RAL_UNLOCK(sc); 1718 m_freem(m); 1719 ieee80211_free_node(ni); 1720 return ENOBUFS; /* XXX */ 1721 } 1722 1723 ifp->if_opackets++; 1724 1725 /* 1726 * Legacy path; interpret frame contents to decide 1727 * precisely how to send the frame. 1728 * XXX raw path 1729 */ 1730 if (rt2661_tx_mgt(sc, m, ni) != 0) 1731 goto bad; 1732 sc->sc_tx_timer = 5; 1733 1734 RAL_UNLOCK(sc); 1735 1736 return 0; 1737 bad: 1738 ifp->if_oerrors++; 1739 ieee80211_free_node(ni); 1740 RAL_UNLOCK(sc); 1741 return EIO; /* XXX */ 1742 } 1743 1744 static void 1745 rt2661_watchdog(void *arg) 1746 { 1747 struct rt2661_softc *sc = (struct rt2661_softc *)arg; 1748 struct ifnet *ifp = sc->sc_ifp; 1749 1750 RAL_LOCK_ASSERT(sc); 1751 1752 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); 1753 1754 if (sc->sc_invalid) /* card ejected */ 1755 return; 1756 1757 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { 1758 if_printf(ifp, "device timeout\n"); 1759 rt2661_init_locked(sc); 1760 ifp->if_oerrors++; 1761 /* NB: callout is reset in rt2661_init() */ 1762 return; 1763 } 1764 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 1765 } 1766 1767 static int 1768 rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1769 { 1770 struct rt2661_softc *sc = ifp->if_softc; 1771 struct ieee80211com *ic = ifp->if_l2com; 1772 struct ifreq *ifr = (struct ifreq *) data; 1773 int error = 0, startall = 0; 1774 1775 switch (cmd) { 1776 case SIOCSIFFLAGS: 1777 RAL_LOCK(sc); 1778 if (ifp->if_flags & IFF_UP) { 1779 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1780 rt2661_init_locked(sc); 1781 startall = 1; 1782 } else 1783 rt2661_update_promisc(ifp); 1784 } else { 1785 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1786 rt2661_stop_locked(sc); 1787 } 1788 RAL_UNLOCK(sc); 1789 if (startall) 1790 ieee80211_start_all(ic); 1791 break; 1792 case SIOCGIFMEDIA: 1793 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1794 break; 1795 case SIOCGIFADDR: 1796 error = ether_ioctl(ifp, cmd, data); 1797 break; 1798 default: 1799 error = EINVAL; 1800 break; 1801 } 1802 return error; 1803 } 1804 1805 static void 1806 rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) 1807 { 1808 uint32_t tmp; 1809 int ntries; 1810 1811 for (ntries = 0; ntries < 100; ntries++) { 1812 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1813 break; 1814 DELAY(1); 1815 } 1816 if (ntries == 100) { 1817 device_printf(sc->sc_dev, "could not write to BBP\n"); 1818 return; 1819 } 1820 1821 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; 1822 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); 1823 1824 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); 1825 } 1826 1827 static uint8_t 1828 rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) 1829 { 1830 uint32_t val; 1831 int ntries; 1832 1833 for (ntries = 0; ntries < 100; ntries++) { 1834 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) 1835 break; 1836 DELAY(1); 1837 } 1838 if (ntries == 100) { 1839 device_printf(sc->sc_dev, "could not read from BBP\n"); 1840 return 0; 1841 } 1842 1843 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; 1844 RAL_WRITE(sc, RT2661_PHY_CSR3, val); 1845 1846 for (ntries = 0; ntries < 100; ntries++) { 1847 val = RAL_READ(sc, RT2661_PHY_CSR3); 1848 if (!(val & RT2661_BBP_BUSY)) 1849 return val & 0xff; 1850 DELAY(1); 1851 } 1852 1853 device_printf(sc->sc_dev, "could not read from BBP\n"); 1854 return 0; 1855 } 1856 1857 static void 1858 rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) 1859 { 1860 uint32_t tmp; 1861 int ntries; 1862 1863 for (ntries = 0; ntries < 100; ntries++) { 1864 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) 1865 break; 1866 DELAY(1); 1867 } 1868 if (ntries == 100) { 1869 device_printf(sc->sc_dev, "could not write to RF\n"); 1870 return; 1871 } 1872 1873 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | 1874 (reg & 3); 1875 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); 1876 1877 /* remember last written value in sc */ 1878 sc->rf_regs[reg] = val; 1879 1880 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); 1881 } 1882 1883 static int 1884 rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) 1885 { 1886 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) 1887 return EIO; /* there is already a command pending */ 1888 1889 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 1890 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); 1891 1892 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); 1893 1894 return 0; 1895 } 1896 1897 static void 1898 rt2661_select_antenna(struct rt2661_softc *sc) 1899 { 1900 uint8_t bbp4, bbp77; 1901 uint32_t tmp; 1902 1903 bbp4 = rt2661_bbp_read(sc, 4); 1904 bbp77 = rt2661_bbp_read(sc, 77); 1905 1906 /* TBD */ 1907 1908 /* make sure Rx is disabled before switching antenna */ 1909 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 1910 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 1911 1912 rt2661_bbp_write(sc, 4, bbp4); 1913 rt2661_bbp_write(sc, 77, bbp77); 1914 1915 /* restore Rx filter */ 1916 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 1917 } 1918 1919 /* 1920 * Enable multi-rate retries for frames sent at OFDM rates. 1921 * In 802.11b/g mode, allow fallback to CCK rates. 1922 */ 1923 static void 1924 rt2661_enable_mrr(struct rt2661_softc *sc) 1925 { 1926 struct ifnet *ifp = sc->sc_ifp; 1927 struct ieee80211com *ic = ifp->if_l2com; 1928 uint32_t tmp; 1929 1930 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1931 1932 tmp &= ~RT2661_MRR_CCK_FALLBACK; 1933 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) 1934 tmp |= RT2661_MRR_CCK_FALLBACK; 1935 tmp |= RT2661_MRR_ENABLED; 1936 1937 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1938 } 1939 1940 static void 1941 rt2661_set_txpreamble(struct rt2661_softc *sc) 1942 { 1943 struct ifnet *ifp = sc->sc_ifp; 1944 struct ieee80211com *ic = ifp->if_l2com; 1945 uint32_t tmp; 1946 1947 tmp = RAL_READ(sc, RT2661_TXRX_CSR4); 1948 1949 tmp &= ~RT2661_SHORT_PREAMBLE; 1950 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1951 tmp |= RT2661_SHORT_PREAMBLE; 1952 1953 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); 1954 } 1955 1956 static void 1957 rt2661_set_basicrates(struct rt2661_softc *sc, 1958 const struct ieee80211_rateset *rs) 1959 { 1960 #define RV(r) ((r) & IEEE80211_RATE_VAL) 1961 struct ifnet *ifp = sc->sc_ifp; 1962 struct ieee80211com *ic = ifp->if_l2com; 1963 uint32_t mask = 0; 1964 uint8_t rate; 1965 int i, j; 1966 1967 for (i = 0; i < rs->rs_nrates; i++) { 1968 rate = rs->rs_rates[i]; 1969 1970 if (!(rate & IEEE80211_RATE_BASIC)) 1971 continue; 1972 1973 /* 1974 * Find h/w rate index. We know it exists because the rate 1975 * set has already been negotiated. 1976 */ 1977 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); 1978 1979 mask |= 1 << j; 1980 } 1981 1982 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); 1983 1984 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); 1985 #undef RV 1986 } 1987 1988 /* 1989 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference 1990 * driver. 1991 */ 1992 static void 1993 rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) 1994 { 1995 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; 1996 uint32_t tmp; 1997 1998 /* update all BBP registers that depend on the band */ 1999 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; 2000 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; 2001 if (IEEE80211_IS_CHAN_5GHZ(c)) { 2002 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; 2003 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; 2004 } 2005 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2006 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2007 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; 2008 } 2009 2010 rt2661_bbp_write(sc, 17, bbp17); 2011 rt2661_bbp_write(sc, 96, bbp96); 2012 rt2661_bbp_write(sc, 104, bbp104); 2013 2014 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || 2015 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { 2016 rt2661_bbp_write(sc, 75, 0x80); 2017 rt2661_bbp_write(sc, 86, 0x80); 2018 rt2661_bbp_write(sc, 88, 0x80); 2019 } 2020 2021 rt2661_bbp_write(sc, 35, bbp35); 2022 rt2661_bbp_write(sc, 97, bbp97); 2023 rt2661_bbp_write(sc, 98, bbp98); 2024 2025 tmp = RAL_READ(sc, RT2661_PHY_CSR0); 2026 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); 2027 if (IEEE80211_IS_CHAN_2GHZ(c)) 2028 tmp |= RT2661_PA_PE_2GHZ; 2029 else 2030 tmp |= RT2661_PA_PE_5GHZ; 2031 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); 2032 } 2033 2034 static void 2035 rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) 2036 { 2037 struct ifnet *ifp = sc->sc_ifp; 2038 struct ieee80211com *ic = ifp->if_l2com; 2039 const struct rfprog *rfprog; 2040 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; 2041 int8_t power; 2042 u_int i, chan; 2043 2044 chan = ieee80211_chan2ieee(ic, c); 2045 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); 2046 2047 sc->sc_rates = ieee80211_get_ratetable(c); 2048 2049 /* select the appropriate RF settings based on what EEPROM says */ 2050 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; 2051 2052 /* find the settings for this channel (we know it exists) */ 2053 for (i = 0; rfprog[i].chan != chan; i++); 2054 2055 power = sc->txpow[i]; 2056 if (power < 0) { 2057 bbp94 += power; 2058 power = 0; 2059 } else if (power > 31) { 2060 bbp94 += power - 31; 2061 power = 31; 2062 } 2063 2064 /* 2065 * If we are switching from the 2GHz band to the 5GHz band or 2066 * vice-versa, BBP registers need to be reprogrammed. 2067 */ 2068 if (c->ic_flags != sc->sc_curchan->ic_flags) { 2069 rt2661_select_band(sc, c); 2070 rt2661_select_antenna(sc); 2071 } 2072 sc->sc_curchan = c; 2073 2074 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2075 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2076 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2077 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2078 2079 DELAY(200); 2080 2081 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2082 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2083 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); 2084 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2085 2086 DELAY(200); 2087 2088 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); 2089 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); 2090 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); 2091 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); 2092 2093 /* enable smart mode for MIMO-capable RFs */ 2094 bbp3 = rt2661_bbp_read(sc, 3); 2095 2096 bbp3 &= ~RT2661_SMART_MODE; 2097 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) 2098 bbp3 |= RT2661_SMART_MODE; 2099 2100 rt2661_bbp_write(sc, 3, bbp3); 2101 2102 if (bbp94 != RT2661_BBPR94_DEFAULT) 2103 rt2661_bbp_write(sc, 94, bbp94); 2104 2105 /* 5GHz radio needs a 1ms delay here */ 2106 if (IEEE80211_IS_CHAN_5GHZ(c)) 2107 DELAY(1000); 2108 } 2109 2110 static void 2111 rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) 2112 { 2113 uint32_t tmp; 2114 2115 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 2116 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); 2117 2118 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; 2119 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); 2120 } 2121 2122 static void 2123 rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) 2124 { 2125 uint32_t tmp; 2126 2127 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 2128 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); 2129 2130 tmp = addr[4] | addr[5] << 8; 2131 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); 2132 } 2133 2134 static void 2135 rt2661_update_promisc(struct ifnet *ifp) 2136 { 2137 struct rt2661_softc *sc = ifp->if_softc; 2138 uint32_t tmp; 2139 2140 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2141 2142 tmp &= ~RT2661_DROP_NOT_TO_ME; 2143 if (!(ifp->if_flags & IFF_PROMISC)) 2144 tmp |= RT2661_DROP_NOT_TO_ME; 2145 2146 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2147 2148 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 2149 "entering" : "leaving"); 2150 } 2151 2152 /* 2153 * Update QoS (802.11e) settings for each h/w Tx ring. 2154 */ 2155 static int 2156 rt2661_wme_update(struct ieee80211com *ic) 2157 { 2158 struct rt2661_softc *sc = ic->ic_ifp->if_softc; 2159 const struct wmeParams *wmep; 2160 2161 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; 2162 2163 /* XXX: not sure about shifts. */ 2164 /* XXX: the reference driver plays with AC_VI settings too. */ 2165 2166 /* update TxOp */ 2167 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, 2168 wmep[WME_AC_BE].wmep_txopLimit << 16 | 2169 wmep[WME_AC_BK].wmep_txopLimit); 2170 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, 2171 wmep[WME_AC_VI].wmep_txopLimit << 16 | 2172 wmep[WME_AC_VO].wmep_txopLimit); 2173 2174 /* update CWmin */ 2175 RAL_WRITE(sc, RT2661_CWMIN_CSR, 2176 wmep[WME_AC_BE].wmep_logcwmin << 12 | 2177 wmep[WME_AC_BK].wmep_logcwmin << 8 | 2178 wmep[WME_AC_VI].wmep_logcwmin << 4 | 2179 wmep[WME_AC_VO].wmep_logcwmin); 2180 2181 /* update CWmax */ 2182 RAL_WRITE(sc, RT2661_CWMAX_CSR, 2183 wmep[WME_AC_BE].wmep_logcwmax << 12 | 2184 wmep[WME_AC_BK].wmep_logcwmax << 8 | 2185 wmep[WME_AC_VI].wmep_logcwmax << 4 | 2186 wmep[WME_AC_VO].wmep_logcwmax); 2187 2188 /* update Aifsn */ 2189 RAL_WRITE(sc, RT2661_AIFSN_CSR, 2190 wmep[WME_AC_BE].wmep_aifsn << 12 | 2191 wmep[WME_AC_BK].wmep_aifsn << 8 | 2192 wmep[WME_AC_VI].wmep_aifsn << 4 | 2193 wmep[WME_AC_VO].wmep_aifsn); 2194 2195 return 0; 2196 } 2197 2198 static void 2199 rt2661_update_slot(struct ifnet *ifp) 2200 { 2201 struct rt2661_softc *sc = ifp->if_softc; 2202 struct ieee80211com *ic = ifp->if_l2com; 2203 uint8_t slottime; 2204 uint32_t tmp; 2205 2206 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 2207 2208 tmp = RAL_READ(sc, RT2661_MAC_CSR9); 2209 tmp = (tmp & ~0xff) | slottime; 2210 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); 2211 } 2212 2213 static const char * 2214 rt2661_get_rf(int rev) 2215 { 2216 switch (rev) { 2217 case RT2661_RF_5225: return "RT5225"; 2218 case RT2661_RF_5325: return "RT5325 (MIMO XR)"; 2219 case RT2661_RF_2527: return "RT2527"; 2220 case RT2661_RF_2529: return "RT2529 (MIMO XR)"; 2221 default: return "unknown"; 2222 } 2223 } 2224 2225 static void 2226 rt2661_read_eeprom(struct rt2661_softc *sc, struct ieee80211com *ic) 2227 { 2228 uint16_t val; 2229 int i; 2230 2231 /* read MAC address */ 2232 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); 2233 ic->ic_myaddr[0] = val & 0xff; 2234 ic->ic_myaddr[1] = val >> 8; 2235 2236 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); 2237 ic->ic_myaddr[2] = val & 0xff; 2238 ic->ic_myaddr[3] = val >> 8; 2239 2240 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); 2241 ic->ic_myaddr[4] = val & 0xff; 2242 ic->ic_myaddr[5] = val >> 8; 2243 2244 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); 2245 /* XXX: test if different from 0xffff? */ 2246 sc->rf_rev = (val >> 11) & 0x1f; 2247 sc->hw_radio = (val >> 10) & 0x1; 2248 sc->rx_ant = (val >> 4) & 0x3; 2249 sc->tx_ant = (val >> 2) & 0x3; 2250 sc->nb_ant = val & 0x3; 2251 2252 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); 2253 2254 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); 2255 sc->ext_5ghz_lna = (val >> 6) & 0x1; 2256 sc->ext_2ghz_lna = (val >> 4) & 0x1; 2257 2258 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", 2259 sc->ext_2ghz_lna, sc->ext_5ghz_lna); 2260 2261 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); 2262 if ((val & 0xff) != 0xff) 2263 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ 2264 2265 /* Only [-10, 10] is valid */ 2266 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) 2267 sc->rssi_2ghz_corr = 0; 2268 2269 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); 2270 if ((val & 0xff) != 0xff) 2271 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ 2272 2273 /* Only [-10, 10] is valid */ 2274 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) 2275 sc->rssi_5ghz_corr = 0; 2276 2277 /* adjust RSSI correction for external low-noise amplifier */ 2278 if (sc->ext_2ghz_lna) 2279 sc->rssi_2ghz_corr -= 14; 2280 if (sc->ext_5ghz_lna) 2281 sc->rssi_5ghz_corr -= 14; 2282 2283 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", 2284 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); 2285 2286 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); 2287 if ((val >> 8) != 0xff) 2288 sc->rfprog = (val >> 8) & 0x3; 2289 if ((val & 0xff) != 0xff) 2290 sc->rffreq = val & 0xff; 2291 2292 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); 2293 2294 /* read Tx power for all a/b/g channels */ 2295 for (i = 0; i < 19; i++) { 2296 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); 2297 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ 2298 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2299 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); 2300 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ 2301 DPRINTF(sc, "Channel=%d Tx power=%d\n", 2302 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); 2303 } 2304 2305 /* read vendor-specific BBP values */ 2306 for (i = 0; i < 16; i++) { 2307 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); 2308 if (val == 0 || val == 0xffff) 2309 continue; /* skip invalid entries */ 2310 sc->bbp_prom[i].reg = val >> 8; 2311 sc->bbp_prom[i].val = val & 0xff; 2312 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, 2313 sc->bbp_prom[i].val); 2314 } 2315 } 2316 2317 static int 2318 rt2661_bbp_init(struct rt2661_softc *sc) 2319 { 2320 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2321 int i, ntries; 2322 uint8_t val; 2323 2324 /* wait for BBP to be ready */ 2325 for (ntries = 0; ntries < 100; ntries++) { 2326 val = rt2661_bbp_read(sc, 0); 2327 if (val != 0 && val != 0xff) 2328 break; 2329 DELAY(100); 2330 } 2331 if (ntries == 100) { 2332 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 2333 return EIO; 2334 } 2335 2336 /* initialize BBP registers to default values */ 2337 for (i = 0; i < N(rt2661_def_bbp); i++) { 2338 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, 2339 rt2661_def_bbp[i].val); 2340 } 2341 2342 /* write vendor-specific BBP values (from EEPROM) */ 2343 for (i = 0; i < 16; i++) { 2344 if (sc->bbp_prom[i].reg == 0) 2345 continue; 2346 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2347 } 2348 2349 return 0; 2350 #undef N 2351 } 2352 2353 static void 2354 rt2661_init_locked(struct rt2661_softc *sc) 2355 { 2356 #define N(a) (sizeof (a) / sizeof ((a)[0])) 2357 struct ifnet *ifp = sc->sc_ifp; 2358 struct ieee80211com *ic = ifp->if_l2com; 2359 uint32_t tmp, sta[3]; 2360 int i, error, ntries; 2361 2362 RAL_LOCK_ASSERT(sc); 2363 2364 if ((sc->sc_flags & RAL_FW_LOADED) == 0) { 2365 error = rt2661_load_microcode(sc); 2366 if (error != 0) { 2367 if_printf(ifp, 2368 "%s: could not load 8051 microcode, error %d\n", 2369 __func__, error); 2370 return; 2371 } 2372 sc->sc_flags |= RAL_FW_LOADED; 2373 } 2374 2375 rt2661_stop_locked(sc); 2376 2377 /* initialize Tx rings */ 2378 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); 2379 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); 2380 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); 2381 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); 2382 2383 /* initialize Mgt ring */ 2384 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); 2385 2386 /* initialize Rx ring */ 2387 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); 2388 2389 /* initialize Tx rings sizes */ 2390 RAL_WRITE(sc, RT2661_TX_RING_CSR0, 2391 RT2661_TX_RING_COUNT << 24 | 2392 RT2661_TX_RING_COUNT << 16 | 2393 RT2661_TX_RING_COUNT << 8 | 2394 RT2661_TX_RING_COUNT); 2395 2396 RAL_WRITE(sc, RT2661_TX_RING_CSR1, 2397 RT2661_TX_DESC_WSIZE << 16 | 2398 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ 2399 RT2661_MGT_RING_COUNT); 2400 2401 /* initialize Rx rings */ 2402 RAL_WRITE(sc, RT2661_RX_RING_CSR, 2403 RT2661_RX_DESC_BACK << 16 | 2404 RT2661_RX_DESC_WSIZE << 8 | 2405 RT2661_RX_RING_COUNT); 2406 2407 /* XXX: some magic here */ 2408 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); 2409 2410 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ 2411 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); 2412 2413 /* load base address of Rx ring */ 2414 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); 2415 2416 /* initialize MAC registers to default values */ 2417 for (i = 0; i < N(rt2661_def_mac); i++) 2418 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); 2419 2420 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 2421 rt2661_set_macaddr(sc, ic->ic_myaddr); 2422 2423 /* set host ready */ 2424 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2425 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2426 2427 /* wait for BBP/RF to wakeup */ 2428 for (ntries = 0; ntries < 1000; ntries++) { 2429 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) 2430 break; 2431 DELAY(1000); 2432 } 2433 if (ntries == 1000) { 2434 printf("timeout waiting for BBP/RF to wakeup\n"); 2435 rt2661_stop_locked(sc); 2436 return; 2437 } 2438 2439 if (rt2661_bbp_init(sc) != 0) { 2440 rt2661_stop_locked(sc); 2441 return; 2442 } 2443 2444 /* select default channel */ 2445 sc->sc_curchan = ic->ic_curchan; 2446 rt2661_select_band(sc, sc->sc_curchan); 2447 rt2661_select_antenna(sc); 2448 rt2661_set_chan(sc, sc->sc_curchan); 2449 2450 /* update Rx filter */ 2451 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; 2452 2453 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; 2454 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2455 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | 2456 RT2661_DROP_ACKCTS; 2457 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2458 tmp |= RT2661_DROP_TODS; 2459 if (!(ifp->if_flags & IFF_PROMISC)) 2460 tmp |= RT2661_DROP_NOT_TO_ME; 2461 } 2462 2463 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2464 2465 /* clear STA registers */ 2466 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); 2467 2468 /* initialize ASIC */ 2469 RAL_WRITE(sc, RT2661_MAC_CSR1, 4); 2470 2471 /* clear any pending interrupt */ 2472 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2473 2474 /* enable interrupts */ 2475 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); 2476 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); 2477 2478 /* kick Rx */ 2479 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); 2480 2481 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2482 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2483 2484 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); 2485 #undef N 2486 } 2487 2488 static void 2489 rt2661_init(void *priv) 2490 { 2491 struct rt2661_softc *sc = priv; 2492 struct ifnet *ifp = sc->sc_ifp; 2493 struct ieee80211com *ic = ifp->if_l2com; 2494 2495 RAL_LOCK(sc); 2496 rt2661_init_locked(sc); 2497 RAL_UNLOCK(sc); 2498 2499 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2500 ieee80211_start_all(ic); /* start all vap's */ 2501 } 2502 2503 void 2504 rt2661_stop_locked(struct rt2661_softc *sc) 2505 { 2506 struct ifnet *ifp = sc->sc_ifp; 2507 uint32_t tmp; 2508 volatile int *flags = &sc->sc_flags; 2509 2510 while (*flags & RAL_INPUT_RUNNING) 2511 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); 2512 2513 callout_stop(&sc->watchdog_ch); 2514 sc->sc_tx_timer = 0; 2515 2516 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2517 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2518 2519 /* abort Tx (for all 5 Tx rings) */ 2520 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); 2521 2522 /* disable Rx (value remains after reset!) */ 2523 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2524 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2525 2526 /* reset ASIC */ 2527 RAL_WRITE(sc, RT2661_MAC_CSR1, 3); 2528 RAL_WRITE(sc, RT2661_MAC_CSR1, 0); 2529 2530 /* disable interrupts */ 2531 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); 2532 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); 2533 2534 /* clear any pending interrupt */ 2535 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); 2536 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); 2537 2538 /* reset Tx and Rx rings */ 2539 rt2661_reset_tx_ring(sc, &sc->txq[0]); 2540 rt2661_reset_tx_ring(sc, &sc->txq[1]); 2541 rt2661_reset_tx_ring(sc, &sc->txq[2]); 2542 rt2661_reset_tx_ring(sc, &sc->txq[3]); 2543 rt2661_reset_tx_ring(sc, &sc->mgtq); 2544 rt2661_reset_rx_ring(sc, &sc->rxq); 2545 } 2546 } 2547 2548 void 2549 rt2661_stop(void *priv) 2550 { 2551 struct rt2661_softc *sc = priv; 2552 2553 RAL_LOCK(sc); 2554 rt2661_stop_locked(sc); 2555 RAL_UNLOCK(sc); 2556 } 2557 2558 static int 2559 rt2661_load_microcode(struct rt2661_softc *sc) 2560 { 2561 struct ifnet *ifp = sc->sc_ifp; 2562 const struct firmware *fp; 2563 const char *imagename; 2564 int ntries, error; 2565 2566 RAL_LOCK_ASSERT(sc); 2567 2568 switch (sc->sc_id) { 2569 case 0x0301: imagename = "rt2561sfw"; break; 2570 case 0x0302: imagename = "rt2561fw"; break; 2571 case 0x0401: imagename = "rt2661fw"; break; 2572 default: 2573 if_printf(ifp, "%s: unexpected pci device id 0x%x, " 2574 "don't know how to retrieve firmware\n", 2575 __func__, sc->sc_id); 2576 return EINVAL; 2577 } 2578 RAL_UNLOCK(sc); 2579 fp = firmware_get(imagename); 2580 RAL_LOCK(sc); 2581 if (fp == NULL) { 2582 if_printf(ifp, "%s: unable to retrieve firmware image %s\n", 2583 __func__, imagename); 2584 return EINVAL; 2585 } 2586 2587 /* 2588 * Load 8051 microcode into NIC. 2589 */ 2590 /* reset 8051 */ 2591 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2592 2593 /* cancel any pending Host to MCU command */ 2594 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); 2595 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); 2596 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); 2597 2598 /* write 8051's microcode */ 2599 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); 2600 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); 2601 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); 2602 2603 /* kick 8051's ass */ 2604 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); 2605 2606 /* wait for 8051 to initialize */ 2607 for (ntries = 0; ntries < 500; ntries++) { 2608 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) 2609 break; 2610 DELAY(100); 2611 } 2612 if (ntries == 500) { 2613 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", 2614 __func__); 2615 error = EIO; 2616 } else 2617 error = 0; 2618 2619 firmware_put(fp, FIRMWARE_UNLOAD); 2620 return error; 2621 } 2622 2623 #ifdef notyet 2624 /* 2625 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and 2626 * false CCA count. This function is called periodically (every seconds) when 2627 * in the RUN state. Values taken from the reference driver. 2628 */ 2629 static void 2630 rt2661_rx_tune(struct rt2661_softc *sc) 2631 { 2632 uint8_t bbp17; 2633 uint16_t cca; 2634 int lo, hi, dbm; 2635 2636 /* 2637 * Tuning range depends on operating band and on the presence of an 2638 * external low-noise amplifier. 2639 */ 2640 lo = 0x20; 2641 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) 2642 lo += 0x08; 2643 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || 2644 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) 2645 lo += 0x10; 2646 hi = lo + 0x20; 2647 2648 /* retrieve false CCA count since last call (clear on read) */ 2649 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; 2650 2651 if (dbm >= -35) { 2652 bbp17 = 0x60; 2653 } else if (dbm >= -58) { 2654 bbp17 = hi; 2655 } else if (dbm >= -66) { 2656 bbp17 = lo + 0x10; 2657 } else if (dbm >= -74) { 2658 bbp17 = lo + 0x08; 2659 } else { 2660 /* RSSI < -74dBm, tune using false CCA count */ 2661 2662 bbp17 = sc->bbp17; /* current value */ 2663 2664 hi -= 2 * (-74 - dbm); 2665 if (hi < lo) 2666 hi = lo; 2667 2668 if (bbp17 > hi) { 2669 bbp17 = hi; 2670 2671 } else if (cca > 512) { 2672 if (++bbp17 > hi) 2673 bbp17 = hi; 2674 } else if (cca < 100) { 2675 if (--bbp17 < lo) 2676 bbp17 = lo; 2677 } 2678 } 2679 2680 if (bbp17 != sc->bbp17) { 2681 rt2661_bbp_write(sc, 17, bbp17); 2682 sc->bbp17 = bbp17; 2683 } 2684 } 2685 2686 /* 2687 * Enter/Leave radar detection mode. 2688 * This is for 802.11h additional regulatory domains. 2689 */ 2690 static void 2691 rt2661_radar_start(struct rt2661_softc *sc) 2692 { 2693 uint32_t tmp; 2694 2695 /* disable Rx */ 2696 tmp = RAL_READ(sc, RT2661_TXRX_CSR0); 2697 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); 2698 2699 rt2661_bbp_write(sc, 82, 0x20); 2700 rt2661_bbp_write(sc, 83, 0x00); 2701 rt2661_bbp_write(sc, 84, 0x40); 2702 2703 /* save current BBP registers values */ 2704 sc->bbp18 = rt2661_bbp_read(sc, 18); 2705 sc->bbp21 = rt2661_bbp_read(sc, 21); 2706 sc->bbp22 = rt2661_bbp_read(sc, 22); 2707 sc->bbp16 = rt2661_bbp_read(sc, 16); 2708 sc->bbp17 = rt2661_bbp_read(sc, 17); 2709 sc->bbp64 = rt2661_bbp_read(sc, 64); 2710 2711 rt2661_bbp_write(sc, 18, 0xff); 2712 rt2661_bbp_write(sc, 21, 0x3f); 2713 rt2661_bbp_write(sc, 22, 0x3f); 2714 rt2661_bbp_write(sc, 16, 0xbd); 2715 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); 2716 rt2661_bbp_write(sc, 64, 0x21); 2717 2718 /* restore Rx filter */ 2719 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); 2720 } 2721 2722 static int 2723 rt2661_radar_stop(struct rt2661_softc *sc) 2724 { 2725 uint8_t bbp66; 2726 2727 /* read radar detection result */ 2728 bbp66 = rt2661_bbp_read(sc, 66); 2729 2730 /* restore BBP registers values */ 2731 rt2661_bbp_write(sc, 16, sc->bbp16); 2732 rt2661_bbp_write(sc, 17, sc->bbp17); 2733 rt2661_bbp_write(sc, 18, sc->bbp18); 2734 rt2661_bbp_write(sc, 21, sc->bbp21); 2735 rt2661_bbp_write(sc, 22, sc->bbp22); 2736 rt2661_bbp_write(sc, 64, sc->bbp64); 2737 2738 return bbp66 == 1; 2739 } 2740 #endif 2741 2742 static int 2743 rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) 2744 { 2745 struct ieee80211com *ic = vap->iv_ic; 2746 struct ieee80211_beacon_offsets bo; 2747 struct rt2661_tx_desc desc; 2748 struct mbuf *m0; 2749 int rate; 2750 2751 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); 2752 if (m0 == NULL) { 2753 device_printf(sc->sc_dev, "could not allocate beacon frame\n"); 2754 return ENOBUFS; 2755 } 2756 2757 /* send beacons at the lowest available rate */ 2758 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; 2759 2760 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, 2761 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); 2762 2763 /* copy the first 24 bytes of Tx descriptor into NIC memory */ 2764 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); 2765 2766 /* copy beacon header and payload into NIC memory */ 2767 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, 2768 mtod(m0, uint8_t *), m0->m_pkthdr.len); 2769 2770 m_freem(m0); 2771 2772 return 0; 2773 } 2774 2775 /* 2776 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS 2777 * and HostAP operating modes. 2778 */ 2779 static void 2780 rt2661_enable_tsf_sync(struct rt2661_softc *sc) 2781 { 2782 struct ifnet *ifp = sc->sc_ifp; 2783 struct ieee80211com *ic = ifp->if_l2com; 2784 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2785 uint32_t tmp; 2786 2787 if (vap->iv_opmode != IEEE80211_M_STA) { 2788 /* 2789 * Change default 16ms TBTT adjustment to 8ms. 2790 * Must be done before enabling beacon generation. 2791 */ 2792 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); 2793 } 2794 2795 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; 2796 2797 /* set beacon interval (in 1/16ms unit) */ 2798 tmp |= vap->iv_bss->ni_intval * 16; 2799 2800 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; 2801 if (vap->iv_opmode == IEEE80211_M_STA) 2802 tmp |= RT2661_TSF_MODE(1); 2803 else 2804 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; 2805 2806 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); 2807 } 2808 2809 /* 2810 * Retrieve the "Received Signal Strength Indicator" from the raw values 2811 * contained in Rx descriptors. The computation depends on which band the 2812 * frame was received. Correction values taken from the reference driver. 2813 */ 2814 static int 2815 rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) 2816 { 2817 int lna, agc, rssi; 2818 2819 lna = (raw >> 5) & 0x3; 2820 agc = raw & 0x1f; 2821 2822 if (lna == 0) { 2823 /* 2824 * No mapping available. 2825 * 2826 * NB: Since RSSI is relative to noise floor, -1 is 2827 * adequate for caller to know error happened. 2828 */ 2829 return -1; 2830 } 2831 2832 rssi = (2 * agc) - RT2661_NOISE_FLOOR; 2833 2834 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { 2835 rssi += sc->rssi_2ghz_corr; 2836 2837 if (lna == 1) 2838 rssi -= 64; 2839 else if (lna == 2) 2840 rssi -= 74; 2841 else if (lna == 3) 2842 rssi -= 90; 2843 } else { 2844 rssi += sc->rssi_5ghz_corr; 2845 2846 if (lna == 1) 2847 rssi -= 64; 2848 else if (lna == 2) 2849 rssi -= 86; 2850 else if (lna == 3) 2851 rssi -= 100; 2852 } 2853 return rssi; 2854 } 2855 2856 static void 2857 rt2661_scan_start(struct ieee80211com *ic) 2858 { 2859 struct ifnet *ifp = ic->ic_ifp; 2860 struct rt2661_softc *sc = ifp->if_softc; 2861 uint32_t tmp; 2862 2863 /* abort TSF synchronization */ 2864 tmp = RAL_READ(sc, RT2661_TXRX_CSR9); 2865 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); 2866 rt2661_set_bssid(sc, ifp->if_broadcastaddr); 2867 } 2868 2869 static void 2870 rt2661_scan_end(struct ieee80211com *ic) 2871 { 2872 struct ifnet *ifp = ic->ic_ifp; 2873 struct rt2661_softc *sc = ifp->if_softc; 2874 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2875 2876 rt2661_enable_tsf_sync(sc); 2877 /* XXX keep local copy */ 2878 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); 2879 } 2880 2881 static void 2882 rt2661_set_channel(struct ieee80211com *ic) 2883 { 2884 struct ifnet *ifp = ic->ic_ifp; 2885 struct rt2661_softc *sc = ifp->if_softc; 2886 2887 RAL_LOCK(sc); 2888 rt2661_set_chan(sc, ic->ic_curchan); 2889 2890 sc->sc_txtap.wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 2891 sc->sc_txtap.wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 2892 sc->sc_rxtap.wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 2893 sc->sc_rxtap.wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 2894 RAL_UNLOCK(sc); 2895 2896 } 2897