xref: /freebsd/sys/dev/ral/rt2560reg.h (revision db33c6f3ae9d1231087710068ee4ea5398aacca7)
1 
2 /*-
3  * Copyright (c) 2005, 2006
4  *	Damien Bergamini <damien.bergamini@free.fr>
5  *
6  * Permission to use, copy, modify, and distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #define RT2560_DEFAULT_RSSI_CORR	0x79
20 #define RT2560_NOISE_FLOOR		-95
21 
22 #define RT2560_TX_RING_COUNT		48
23 #define RT2560_ATIM_RING_COUNT		4
24 #define RT2560_PRIO_RING_COUNT		16
25 #define RT2560_BEACON_RING_COUNT	1
26 #define RT2560_RX_RING_COUNT		32
27 
28 #define RT2560_TX_DESC_SIZE	(sizeof (struct rt2560_tx_desc))
29 #define RT2560_RX_DESC_SIZE	(sizeof (struct rt2560_rx_desc))
30 
31 #define RT2560_MAX_SCATTER	1
32 
33 /*
34  * Control and status registers.
35  */
36 #define RT2560_CSR0		0x0000	/* ASIC version number */
37 #define RT2560_CSR1		0x0004	/* System control */
38 #define RT2560_CSR3		0x000c	/* STA MAC address 0 */
39 #define RT2560_CSR4		0x0010	/* STA MAC address 1 */
40 #define RT2560_CSR5		0x0014	/* BSSID 0 */
41 #define RT2560_CSR6		0x0018	/* BSSID 1 */
42 #define RT2560_CSR7		0x001c	/* Interrupt source */
43 #define RT2560_CSR8		0x0020	/* Interrupt mask */
44 #define RT2560_CSR9		0x0024	/* Maximum frame length */
45 #define RT2560_SECCSR0		0x0028	/* WEP control */
46 #define RT2560_CSR11		0x002c	/* Back-off control */
47 #define RT2560_CSR12		0x0030	/* Synchronization configuration 0 */
48 #define RT2560_CSR13		0x0034	/* Synchronization configuration 1 */
49 #define RT2560_CSR14		0x0038	/* Synchronization control */
50 #define RT2560_CSR15		0x003c	/* Synchronization status */
51 #define RT2560_CSR16		0x0040	/* TSF timer 0 */
52 #define RT2560_CSR17		0x0044	/* TSF timer 1 */
53 #define RT2560_CSR18		0x0048	/* IFS timer 0 */
54 #define RT2560_CSR19		0x004c	/* IFS timer 1 */
55 #define RT2560_CSR20		0x0050	/* WAKEUP timer */
56 #define RT2560_CSR21		0x0054	/* EEPROM control */
57 #define RT2560_CSR22		0x0058	/* CFP control */
58 #define RT2560_TXCSR0		0x0060	/* TX control */
59 #define RT2560_TXCSR1		0x0064	/* TX configuration */
60 #define RT2560_TXCSR2		0x0068	/* TX descriptor configuration */
61 #define RT2560_TXCSR3		0x006c	/* TX ring base address */
62 #define RT2560_TXCSR4		0x0070	/* TX ATIM ring base address */
63 #define RT2560_TXCSR5		0x0074	/* TX PRIO ring base address */
64 #define RT2560_TXCSR6		0x0078	/* Beacon base address */
65 #define RT2560_TXCSR7		0x007c	/* AutoResponder control */
66 #define RT2560_RXCSR0		0x0080	/* RX control */
67 #define RT2560_RXCSR1		0x0084	/* RX descriptor configuration */
68 #define RT2560_RXCSR2		0x0088	/* RX ring base address */
69 #define RT2560_PCICSR		0x008c	/* PCI control */
70 #define RT2560_RXCSR3		0x0090	/* BBP ID 0 */
71 #define RT2560_TXCSR9		0x0094	/* OFDM TX BBP */
72 #define RT2560_ARSP_PLCP_0	0x0098	/* Auto Responder PLCP address */
73 #define RT2560_ARSP_PLCP_1	0x009c	/* Auto Responder Basic Rate mask */
74 #define RT2560_CNT0		0x00a0	/* FCS error counter */
75 #define RT2560_CNT1		0x00ac	/* PLCP error counter */
76 #define RT2560_CNT2		0x00b0	/* Long error counter */
77 #define RT2560_CNT3		0x00b8	/* CCA false alarm counter */
78 #define RT2560_CNT4		0x00bc	/* RX FIFO Overflow counter */
79 #define RT2560_CNT5		0x00c0	/* Tx FIFO Underrun counter */
80 #define RT2560_PWRCSR0		0x00c4	/* Power mode configuration */
81 #define RT2560_PSCSR0		0x00c8	/* Power state transition time */
82 #define RT2560_PSCSR1		0x00cc	/* Power state transition time */
83 #define RT2560_PSCSR2		0x00d0	/* Power state transition time */
84 #define RT2560_PSCSR3		0x00d4	/* Power state transition time */
85 #define RT2560_PWRCSR1		0x00d8	/* Manual power control/status */
86 #define RT2560_TIMECSR		0x00dc	/* Timer control */
87 #define RT2560_MACCSR0		0x00e0	/* MAC configuration */
88 #define RT2560_MACCSR1		0x00e4	/* MAC configuration */
89 #define RT2560_RALINKCSR	0x00e8	/* Ralink RX auto-reset BBCR */
90 #define RT2560_BCNCSR		0x00ec	/* Beacon interval control */
91 #define RT2560_BBPCSR		0x00f0	/* BBP serial control */
92 #define RT2560_RFCSR		0x00f4	/* RF serial control */
93 #define RT2560_LEDCSR		0x00f8	/* LED control */
94 #define RT2560_SECCSR3		0x00fc	/* XXX not documented */
95 #define RT2560_DMACSR0		0x0100	/* Current RX ring address */
96 #define RT2560_DMACSR1		0x0104	/* Current Tx ring address */
97 #define RT2560_DMACSR2		0x0104	/* Current Priority ring address */
98 #define RT2560_DMACSR3		0x0104	/* Current ATIM ring address */
99 #define RT2560_TXACKCSR0	0x0110	/* XXX not documented */
100 #define RT2560_GPIOCSR		0x0120	/* */
101 #define RT2560_BBBPPCSR		0x0124	/* BBP Pin Control */
102 #define RT2560_FIFOCSR0		0x0128	/* TX FIFO pointer */
103 #define RT2560_FIFOCSR1		0x012c	/* RX FIFO pointer */
104 #define RT2560_BCNOCSR		0x0130	/* Beacon time offset */
105 #define RT2560_RLPWCSR		0x0134	/* RX_PE Low Width */
106 #define RT2560_TESTCSR		0x0138	/* Test Mode Select */
107 #define RT2560_PLCP1MCSR	0x013c	/* Signal/Service/Length of ACK @1M */
108 #define RT2560_PLCP2MCSR	0x0140	/* Signal/Service/Length of ACK @2M */
109 #define RT2560_PLCP5p5MCSR	0x0144	/* Signal/Service/Length of ACK @5.5M */
110 #define RT2560_PLCP11MCSR	0x0148	/* Signal/Service/Length of ACK @11M */
111 #define RT2560_ACKPCTCSR	0x014c	/* ACK/CTS padload consume time */
112 #define RT2560_ARTCSR1		0x0150	/* ACK/CTS padload consume time */
113 #define RT2560_ARTCSR2		0x0154	/* ACK/CTS padload consume time */
114 #define RT2560_SECCSR1		0x0158	/* WEP control */
115 #define RT2560_BBPCSR1		0x015c	/* BBP TX Configuration */
116 
117 /* possible flags for register RXCSR0 */
118 #define RT2560_DISABLE_RX		(1 << 0)
119 #define RT2560_DROP_CRC_ERROR		(1 << 1)
120 #define RT2560_DROP_PHY_ERROR		(1 << 2)
121 #define RT2560_DROP_CTL			(1 << 3)
122 #define RT2560_DROP_NOT_TO_ME		(1 << 4)
123 #define RT2560_DROP_TODS		(1 << 5)
124 #define RT2560_DROP_VERSION_ERROR	(1 << 6)
125 
126 /* possible flags for register CSR1 */
127 #define RT2560_RESET_ASIC	(1 << 0)
128 #define RT2560_RESET_BBP	(1 << 1)
129 #define RT2560_HOST_READY	(1 << 2)
130 
131 /* possible flags for register CSR14 */
132 #define RT2560_ENABLE_TSF		(1 << 0)
133 #define RT2560_ENABLE_TSF_SYNC(x)	(((x) & 0x3) << 1)
134 #define RT2560_ENABLE_TBCN		(1 << 3)
135 #define RT2560_ENABLE_BEACON_GENERATOR	(1 << 6)
136 
137 /* possible flags for register CSR21 */
138 #define RT2560_C	(1 << 1)
139 #define RT2560_S	(1 << 2)
140 #define RT2560_D	(1 << 3)
141 #define RT2560_Q	(1 << 4)
142 #define RT2560_93C46	(1 << 5)
143 
144 #define RT2560_SHIFT_D	3
145 #define RT2560_SHIFT_Q	4
146 
147 /* possible flags for register TXCSR0 */
148 #define RT2560_KICK_TX		(1 << 0)
149 #define RT2560_KICK_ATIM	(1 << 1)
150 #define RT2560_KICK_PRIO	(1 << 2)
151 #define RT2560_ABORT_TX		(1 << 3)
152 
153 /* possible flags for register SECCSR0 */
154 #define RT2560_KICK_DECRYPT	(1 << 0)
155 
156 /* possible flags for register SECCSR1 */
157 #define RT2560_KICK_ENCRYPT	(1 << 0)
158 
159 /* possible flags for register CSR7 */
160 #define RT2560_BEACON_EXPIRE	0x00000001
161 #define RT2560_WAKEUP_EXPIRE	0x00000002
162 #define RT2560_ATIM_EXPIRE	0x00000004
163 #define RT2560_TX_DONE		0x00000008
164 #define RT2560_ATIM_DONE	0x00000010
165 #define RT2560_PRIO_DONE	0x00000020
166 #define RT2560_RX_DONE		0x00000040
167 #define RT2560_DECRYPTION_DONE	0x00000080
168 #define RT2560_ENCRYPTION_DONE	0x00000100
169 
170 #define RT2560_INTR_MASK							\
171 	(~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE |	\
172 	   RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE |		\
173 	   RT2560_ENCRYPTION_DONE))
174 
175 /* Tx descriptor */
176 struct rt2560_tx_desc {
177 	uint32_t	flags;
178 #define RT2560_TX_BUSY			(1 << 0)
179 #define RT2560_TX_VALID			(1 << 1)
180 
181 #define RT2560_TX_RESULT_MASK		0x0000001c
182 #define RT2560_TX_SUCCESS		(0 << 2)
183 #define RT2560_TX_SUCCESS_RETRY		(1 << 2)
184 #define RT2560_TX_FAIL_RETRY		(2 << 2)
185 #define RT2560_TX_FAIL_INVALID		(3 << 2)
186 #define RT2560_TX_FAIL_OTHER		(4 << 2)
187 
188 #define RT2560_TX_MORE_FRAG		(1 << 8)
189 #define RT2560_TX_ACK			(1 << 9)
190 #define RT2560_TX_TIMESTAMP		(1 << 10)
191 #define RT2560_TX_OFDM			(1 << 11)
192 #define RT2560_TX_CIPHER_BUSY		(1 << 12)
193 
194 #define RT2560_TX_IFS_MASK		0x00006000
195 #define RT2560_TX_IFS_BACKOFF		(0 << 13)
196 #define RT2560_TX_IFS_SIFS		(1 << 13)
197 #define RT2560_TX_IFS_NEWBACKOFF	(2 << 13)
198 #define RT2560_TX_IFS_NONE		(3 << 13)
199 
200 #define RT2560_TX_LONG_RETRY		(1 << 15)
201 
202 #define RT2560_TX_CIPHER_MASK		0xe0000000
203 #define RT2560_TX_CIPHER_NONE		(0 << 29)
204 #define RT2560_TX_CIPHER_WEP40		(1 << 29)
205 #define RT2560_TX_CIPHER_WEP104		(2 << 29)
206 #define RT2560_TX_CIPHER_TKIP		(3 << 29)
207 #define RT2560_TX_CIPHER_AES		(4 << 29)
208 
209 #define RT2560_TX_RETRYCNT(v)	(((v) >> 5) & 0x7)
210 
211 	uint32_t	physaddr;
212 	uint16_t	wme;
213 #define RT2560_LOGCWMAX(x)	(((x) & 0xf) << 12)
214 #define RT2560_LOGCWMIN(x)	(((x) & 0xf) << 8)
215 #define RT2560_AIFSN(x)		(((x) & 0x3) << 6)
216 #define RT2560_IVOFFSET(x)	(((x) & 0x3f))
217 
218 	uint16_t	reserved1;
219 	uint8_t		plcp_signal;
220 	uint8_t		plcp_service;
221 #define RT2560_PLCP_LENGEXT	0x80
222 
223 	uint8_t		plcp_length_lo;
224 	uint8_t		plcp_length_hi;
225 	uint32_t	iv;
226 	uint32_t	eiv;
227 	uint8_t		key[IEEE80211_KEYBUF_SIZE];
228 	uint32_t	reserved2[2];
229 } __packed;
230 
231 /* Rx descriptor */
232 struct rt2560_rx_desc {
233 	uint32_t	flags;
234 #define RT2560_RX_BUSY		(1 << 0)
235 #define RT2560_RX_CRC_ERROR	(1 << 5)
236 #define RT2560_RX_OFDM		(1 << 6)
237 #define RT2560_RX_PHY_ERROR	(1 << 7)
238 #define RT2560_RX_CIPHER_BUSY	(1 << 8)
239 #define RT2560_RX_ICV_ERROR	(1 << 9)
240 
241 #define RT2560_RX_CIPHER_MASK	0xe0000000
242 #define RT2560_RX_CIPHER_NONE	(0 << 29)
243 #define RT2560_RX_CIPHER_WEP40	(1 << 29)
244 #define RT2560_RX_CIPHER_WEP104	(2 << 29)
245 #define RT2560_RX_CIPHER_TKIP	(3 << 29)
246 #define RT2560_RX_CIPHER_AES	(4 << 29)
247 
248 	uint32_t	physaddr;
249 	uint8_t		rate;
250 	uint8_t		rssi;
251 	uint8_t		ta[IEEE80211_ADDR_LEN];
252 	uint32_t	iv;
253 	uint32_t	eiv;
254 	uint8_t		key[IEEE80211_KEYBUF_SIZE];
255 	uint32_t	reserved[2];
256 } __packed;
257 
258 #define RAL_RF1	0
259 #define RAL_RF2	2
260 #define RAL_RF3	1
261 #define RAL_RF4	3
262 
263 #define RT2560_RF1_AUTOTUNE	0x08000
264 #define RT2560_RF3_AUTOTUNE	0x00040
265 
266 #define RT2560_BBP_BUSY		(1 << 15)
267 #define RT2560_BBP_WRITE	(1 << 16)
268 #define RT2560_RF_20BIT		(20 << 24)
269 #define RT2560_RF_BUSY		(1U << 31)
270 
271 #define RT2560_RF_2522	0x00
272 #define RT2560_RF_2523	0x01
273 #define RT2560_RF_2524	0x02
274 #define RT2560_RF_2525	0x03
275 #define RT2560_RF_2525E	0x04
276 #define RT2560_RF_2526	0x05
277 /* dual-band RF */
278 #define RT2560_RF_5222	0x10
279 
280 #define RT2560_BBP_VERSION	0
281 #define RT2560_BBP_TX		2
282 #define RT2560_BBP_RX		14
283 
284 #define RT2560_BBP_ANTA		0x00
285 #define RT2560_BBP_DIVERSITY	0x01
286 #define RT2560_BBP_ANTB		0x02
287 #define RT2560_BBP_ANTMASK	0x03
288 #define RT2560_BBP_FLIPIQ	0x04
289 
290 #define RT2560_LED_MODE_DEFAULT		0
291 #define RT2560_LED_MODE_TXRX_ACTIVITY	1
292 #define RT2560_LED_MODE_SINGLE		2
293 #define RT2560_LED_MODE_ASUS		3
294 
295 #define RT2560_JAPAN_FILTER	0x8
296 
297 #define RT2560_EEPROM_DELAY	1	/* minimum hold time (microsecond) */
298 
299 #define RT2560_EEPROM_CONFIG0	16
300 #define RT2560_EEPROM_BBP_BASE	19
301 #define RT2560_EEPROM_TXPOWER	35
302 #define RT2560_EEPROM_CALIBRATE	62
303 
304 /*
305  * control and status registers access macros
306  */
307 #define RAL_READ(sc, reg)						\
308 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
309 
310 #define RAL_WRITE(sc, reg, val)						\
311 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
312 
313 /*
314  * EEPROM access macro
315  */
316 #define RT2560_EEPROM_CTL(sc, val) do {					\
317 	RAL_WRITE((sc), RT2560_CSR21, (val));				\
318 	DELAY(RT2560_EEPROM_DELAY);					\
319 } while (/* CONSTCOND */0)
320 
321 /*
322  * Default values for MAC registers; values taken from the reference driver.
323  */
324 #define RT2560_DEF_MAC				\
325 	{ RT2560_PSCSR0,      0x00020002 },	\
326 	{ RT2560_PSCSR1,      0x00000002 },	\
327 	{ RT2560_PSCSR2,      0x00020002 },	\
328 	{ RT2560_PSCSR3,      0x00000002 },	\
329 	{ RT2560_TIMECSR,     0x00003f21 },	\
330 	{ RT2560_CSR9,        0x00000780 },	\
331 	{ RT2560_CSR11,       0x07041483 },	\
332 	{ RT2560_CNT3,        0x00000000 },	\
333 	{ RT2560_TXCSR1,      0x07614562 },	\
334 	{ RT2560_ARSP_PLCP_0, 0x8c8d8b8a },	\
335 	{ RT2560_ACKPCTCSR,   0x7038140a },	\
336 	{ RT2560_ARTCSR1,     0x21212929 },	\
337 	{ RT2560_ARTCSR2,     0x1d1d1d1d },	\
338 	{ RT2560_RXCSR0,      0xffffffff },	\
339 	{ RT2560_RXCSR3,      0xb3aab3af },	\
340 	{ RT2560_PCICSR,      0x000003b8 },	\
341 	{ RT2560_PWRCSR0,     0x3f3b3100 },	\
342 	{ RT2560_GPIOCSR,     0x0000ff00 },	\
343 	{ RT2560_TESTCSR,     0x000000f0 },	\
344 	{ RT2560_PWRCSR1,     0x000001ff },	\
345 	{ RT2560_MACCSR0,     0x00213223 },	\
346 	{ RT2560_MACCSR1,     0x00235518 },	\
347 	{ RT2560_RLPWCSR,     0x00000040 },	\
348 	{ RT2560_RALINKCSR,   0x9a009a11 },	\
349 	{ RT2560_CSR7,        0xffffffff },	\
350 	{ RT2560_BBPCSR1,     0x82188200 },	\
351 	{ RT2560_TXACKCSR0,   0x00000020 },	\
352 	{ RT2560_SECCSR3,     0x0000e78f }
353 
354 /*
355  * Default values for BBP registers; values taken from the reference driver.
356  */
357 #define RT2560_DEF_BBP	\
358 	{  3, 0x02 },	\
359 	{  4, 0x19 },	\
360 	{ 14, 0x1c },	\
361 	{ 15, 0x30 },	\
362 	{ 16, 0xac },	\
363 	{ 17, 0x48 },	\
364 	{ 18, 0x18 },	\
365 	{ 19, 0xff },	\
366 	{ 20, 0x1e },	\
367 	{ 21, 0x08 },	\
368 	{ 22, 0x08 },	\
369 	{ 23, 0x08 },	\
370 	{ 24, 0x80 },	\
371 	{ 25, 0x50 },	\
372 	{ 26, 0x08 },	\
373 	{ 27, 0x23 },	\
374 	{ 30, 0x10 },	\
375 	{ 31, 0x2b },	\
376 	{ 32, 0xb9 },	\
377 	{ 34, 0x12 },	\
378 	{ 35, 0x50 },	\
379 	{ 39, 0xc4 },	\
380 	{ 40, 0x02 },	\
381 	{ 41, 0x60 },	\
382 	{ 53, 0x10 },	\
383 	{ 54, 0x18 },	\
384 	{ 56, 0x08 },	\
385 	{ 57, 0x10 },	\
386 	{ 58, 0x08 },	\
387 	{ 61, 0x60 },	\
388 	{ 62, 0x10 },	\
389 	{ 75, 0xff }
390 
391 /*
392  * Default values for RF register R2 indexed by channel numbers; values taken
393  * from the reference driver.
394  */
395 #define RT2560_RF2522_R2						\
396 {									\
397 	0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814,	\
398 	0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e	\
399 }
400 
401 #define RT2560_RF2523_R2						\
402 {									\
403 	0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,	\
404 	0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346	\
405 }
406 
407 #define RT2560_RF2524_R2						\
408 {									\
409 	0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d,	\
410 	0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346	\
411 }
412 
413 #define RT2560_RF2525_R2						\
414 {									\
415 	0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d,	\
416 	0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346	\
417 }
418 
419 #define RT2560_RF2525_HI_R2						\
420 {									\
421 	0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345,	\
422 	0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e	\
423 }
424 
425 #define RT2560_RF2525E_R2						\
426 {									\
427 	0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463,	\
428 	0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b	\
429 }
430 
431 #define RT2560_RF2526_HI_R2						\
432 {									\
433 	0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d,	\
434 	0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241	\
435 }
436 
437 #define RT2560_RF2526_R2						\
438 {									\
439 	0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229,	\
440 	0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d	\
441 }
442 
443 /*
444  * For dual-band RF, RF registers R1 and R4 also depend on channel number;
445  * values taken from the reference driver.
446  */
447 #define RT2560_RF5222				\
448 	{   1, 0x08808, 0x0044d, 0x00282 },	\
449 	{   2, 0x08808, 0x0044e, 0x00282 },	\
450 	{   3, 0x08808, 0x0044f, 0x00282 },	\
451 	{   4, 0x08808, 0x00460, 0x00282 },	\
452 	{   5, 0x08808, 0x00461, 0x00282 },	\
453 	{   6, 0x08808, 0x00462, 0x00282 },	\
454 	{   7, 0x08808, 0x00463, 0x00282 },	\
455 	{   8, 0x08808, 0x00464, 0x00282 },	\
456 	{   9, 0x08808, 0x00465, 0x00282 },	\
457 	{  10, 0x08808, 0x00466, 0x00282 },	\
458 	{  11, 0x08808, 0x00467, 0x00282 },	\
459 	{  12, 0x08808, 0x00468, 0x00282 },	\
460 	{  13, 0x08808, 0x00469, 0x00282 },	\
461 	{  14, 0x08808, 0x0046b, 0x00286 },	\
462 						\
463 	{  36, 0x08804, 0x06225, 0x00287 },	\
464 	{  40, 0x08804, 0x06226, 0x00287 },	\
465 	{  44, 0x08804, 0x06227, 0x00287 },	\
466 	{  48, 0x08804, 0x06228, 0x00287 },	\
467 	{  52, 0x08804, 0x06229, 0x00287 },	\
468 	{  56, 0x08804, 0x0622a, 0x00287 },	\
469 	{  60, 0x08804, 0x0622b, 0x00287 },	\
470 	{  64, 0x08804, 0x0622c, 0x00287 },	\
471 						\
472 	{ 100, 0x08804, 0x02200, 0x00283 },	\
473 	{ 104, 0x08804, 0x02201, 0x00283 },	\
474 	{ 108, 0x08804, 0x02202, 0x00283 },	\
475 	{ 112, 0x08804, 0x02203, 0x00283 },	\
476 	{ 116, 0x08804, 0x02204, 0x00283 },	\
477 	{ 120, 0x08804, 0x02205, 0x00283 },	\
478 	{ 124, 0x08804, 0x02206, 0x00283 },	\
479 	{ 128, 0x08804, 0x02207, 0x00283 },	\
480 	{ 132, 0x08804, 0x02208, 0x00283 },	\
481 	{ 136, 0x08804, 0x02209, 0x00283 },	\
482 	{ 140, 0x08804, 0x0220a, 0x00283 },	\
483 						\
484 	{ 149, 0x08808, 0x02429, 0x00281 },	\
485 	{ 153, 0x08808, 0x0242b, 0x00281 },	\
486 	{ 157, 0x08808, 0x0242d, 0x00281 },	\
487 	{ 161, 0x08808, 0x0242f, 0x00281 }
488