1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2014 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /* 30 * File: qls_hw.h 31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32 */ 33 #ifndef _QLS_HW_H_ 34 #define _QLS_HW_H_ 35 36 #define Q8_MAX_NUM_MULTICAST_ADDRS 32 37 #define Q8_MAC_ADDR_LEN 6 38 39 #define BIT_0 (0x1 << 0) 40 #define BIT_1 (0x1 << 1) 41 #define BIT_2 (0x1 << 2) 42 #define BIT_3 (0x1 << 3) 43 #define BIT_4 (0x1 << 4) 44 #define BIT_5 (0x1 << 5) 45 #define BIT_6 (0x1 << 6) 46 #define BIT_7 (0x1 << 7) 47 #define BIT_8 (0x1 << 8) 48 #define BIT_9 (0x1 << 9) 49 #define BIT_10 (0x1 << 10) 50 #define BIT_11 (0x1 << 11) 51 #define BIT_12 (0x1 << 12) 52 #define BIT_13 (0x1 << 13) 53 #define BIT_14 (0x1 << 14) 54 #define BIT_15 (0x1 << 15) 55 #define BIT_16 (0x1 << 16) 56 #define BIT_17 (0x1 << 17) 57 #define BIT_18 (0x1 << 18) 58 #define BIT_19 (0x1 << 19) 59 #define BIT_20 (0x1 << 20) 60 #define BIT_21 (0x1 << 21) 61 #define BIT_22 (0x1 << 22) 62 #define BIT_23 (0x1 << 23) 63 #define BIT_24 (0x1 << 24) 64 #define BIT_25 (0x1 << 25) 65 #define BIT_11 (0x1 << 11) 66 #define BIT_12 (0x1 << 12) 67 #define BIT_13 (0x1 << 13) 68 #define BIT_14 (0x1 << 14) 69 #define BIT_15 (0x1 << 15) 70 #define BIT_16 (0x1 << 16) 71 #define BIT_17 (0x1 << 17) 72 #define BIT_18 (0x1 << 18) 73 #define BIT_19 (0x1 << 19) 74 #define BIT_20 (0x1 << 20) 75 #define BIT_21 (0x1 << 21) 76 #define BIT_22 (0x1 << 22) 77 #define BIT_23 (0x1 << 23) 78 #define BIT_24 (0x1 << 24) 79 #define BIT_25 (0x1 << 25) 80 #define BIT_26 (0x1 << 26) 81 #define BIT_27 (0x1 << 27) 82 #define BIT_28 (0x1 << 28) 83 #define BIT_29 (0x1 << 29) 84 #define BIT_30 (0x1 << 30) 85 #define BIT_31 (0x1 << 31) 86 87 /* 88 * Firmware Interface 89 */ 90 91 /********************************************************************* 92 * Work Queue Register Map 93 *********************************************************************/ 94 #define Q81_WRKQ_INDEX_REG 0x00 95 #define Q81_WRKQ_CONS_INDEX_MASK 0xFFFF0000 96 #define Q81_WRKQ_PROD_INDEX_MASK 0x0000FFFF 97 #define Q81_WRKQ_VALID_REG 0x04 98 #define Q81_WRKQ_VALID_ONQ BIT_25 99 #define Q81_WRKQ_VALID_V BIT_4 100 101 /********************************************************************* 102 * Completion Queue Register Map 103 *********************************************************************/ 104 #define Q81_COMPQ_INDEX_REG 0x00 105 #define Q81_COMPQ_PROD_INDEX_MASK 0xFFFF0000 106 #define Q81_COMPQ_CONS_INDEX_MASK 0x0000FFFF 107 #define Q81_COMPQ_VALID_REG 0x04 108 #define Q81_COMPQ_VALID_V BIT_4 109 #define Q81_LRGBQ_INDEX_REG 0x18 110 #define Q81_LRGBQ_CONS_INDEX_MASK 0xFFFF0000 111 #define Q81_LRGBQ_PROD_INDEX_MASK 0x0000FFFF 112 #define Q81_SMBQ_INDEX_REG 0x1C 113 #define Q81_SMBQ_CONS_INDEX_MASK 0xFFFF0000 114 #define Q81_SMBQ_PROD_INDEX_MASK 0x0000FFFF 115 116 /********************************************************************* 117 * Control Register Definitions 118 * (Access, Function Specific, Shared via Semaphore, Control by MPI FW) 119 *********************************************************************/ 120 #define Q81_CTL_PROC_ADDR 0x00 /* R/W - Y - */ 121 #define Q81_CTL_PROC_DATA 0x04 /* R/W - Y - */ 122 #define Q81_CTL_SYSTEM 0x08 /* MWR - - - */ 123 #define Q81_CTL_RESET 0x0C /* MWR Y - - */ 124 #define Q81_CTL_FUNC_SPECIFIC 0x10 /* MWR Y - - */ 125 #define Q81_CTL_HOST_CMD_STATUS 0x14 /* R/W Y - - */ 126 #define Q81_CTL_LED 0x18 /* R/W Y - Y */ 127 #define Q81_CTL_ICB_ACCESS_ADDR_LO 0x20 /* R/W - Y - */ 128 #define Q81_CTL_ICB_ACCESS_ADDR_HI 0x24 /* R/W - Y - */ 129 #define Q81_CTL_CONFIG 0x28 /* MWR - - - */ 130 #define Q81_CTL_STATUS 0x30 /* MWR Y - - */ 131 #define Q81_CTL_INTR_ENABLE 0x34 /* MWR Y - - */ 132 #define Q81_CTL_INTR_MASK 0x38 /* MWR Y - - */ 133 #define Q81_CTL_INTR_STATUS1 0x3C /* RO Y - - */ 134 #define Q81_CTL_INTR_STATUS2 0x40 /* RO Y - - */ 135 #define Q81_CTL_INTR_STATUS3 0x44 /* RO Y - - */ 136 #define Q81_CTL_INTR_STATUS4 0x48 /* RO Y - - */ 137 #define Q81_CTL_REV_ID 0x4C /* RO - - - */ 138 #define Q81_CTL_FATAL_ERR_STATUS 0x54 /* RO Y - - */ 139 #define Q81_CTL_COR_ECC_ERR_COUNTER 0x60 /* RO Y - - */ 140 #define Q81_CTL_SEMAPHORE 0x64 /* MWR Y - - */ 141 #define Q81_CTL_GPIO1 0x68 /* MWR Y - - */ 142 #define Q81_CTL_GPIO2 0x6C /* MWR Y - - */ 143 #define Q81_CTL_GPIO3 0x70 /* MWR Y - - */ 144 #define Q81_CTL_XGMAC_ADDR 0x78 /* R/W Y Y - */ 145 #define Q81_CTL_XGMAC_DATA 0x7C /* R/W Y Y Y */ 146 #define Q81_CTL_NIC_ENH_TX_SCHD 0x80 /* R/W Y - Y */ 147 #define Q81_CTL_CNA_ENH_TX_SCHD 0x84 /* R/W Y - Y */ 148 #define Q81_CTL_FLASH_ADDR 0x88 /* R/W - Y - */ 149 #define Q81_CTL_FLASH_DATA 0x8C /* R/W - Y - */ 150 #define Q81_CTL_STOP_CQ_PROCESSING 0x90 /* MWR Y - - */ 151 #define Q81_CTL_MAC_PROTO_ADDR_INDEX 0xA8 /* R/W - Y - */ 152 #define Q81_CTL_MAC_PROTO_ADDR_DATA 0xAC /* R/W - Y - */ 153 #define Q81_CTL_COS_DEF_CQ1 0xB0 /* R/W Y - - */ 154 #define Q81_CTL_COS_DEF_CQ2 0xB4 /* R/W Y - - */ 155 #define Q81_CTL_ETHERTYPE_SKIP_1 0xB8 /* R/W Y - - */ 156 #define Q81_CTL_ETHERTYPE_SKIP_2 0xBC /* R/W Y - - */ 157 #define Q81_CTL_SPLIT_HDR 0xC0 /* R/W Y - - */ 158 #define Q81_CTL_NIC_PAUSE_THRES 0xC8 /* R/W Y - Y */ 159 #define Q81_CTL_NIC_RCV_CONFIG 0xD4 /* MWR Y - Y */ 160 #define Q81_CTL_COS_TAGS_IN_NIC_FIFO 0xDC /* R/W Y - Y */ 161 #define Q81_CTL_MGMT_RCV_CONFIG 0xE0 /* MWR Y - Y */ 162 #define Q81_CTL_ROUTING_INDEX 0xE4 /* R/W Y Y - */ 163 #define Q81_CTL_ROUTING_DATA 0xE8 /* R/W Y Y - */ 164 #define Q81_CTL_XG_SERDES_ADDR 0xF0 /* R/W Y Y Y */ 165 #define Q81_CTL_XG_SERDES_DATA 0xF4 /* R/W Y Y Y */ 166 #define Q81_CTL_XG_PROBE_MUX_ADDR 0xF8 /* R/W - Y - */ 167 #define Q81_CTL_XG_PROBE_MUX_DATA 0xFC /* R/W - Y - */ 168 169 /* 170 * Process Address Register (0x00) 171 */ 172 #define Q81_CTL_PROC_ADDR_RDY BIT_31 173 #define Q81_CTL_PROC_ADDR_READ BIT_30 174 #define Q81_CTL_PROC_ADDR_ERR BIT_29 175 #define Q81_CTL_PROC_ADDR_MPI_RISC (0x00 << 16) 176 #define Q81_CTL_PROC_ADDR_MDE (0x01 << 16) 177 #define Q81_CTL_PROC_ADDR_REG_BLOCK (0x02 << 16) 178 #define Q81_CTL_PROC_ADDR_RISC_INT_REG (0x03 << 16) 179 180 /* 181 * System Register (0x08) 182 */ 183 #define Q81_CTL_SYSTEM_MASK_SHIFT 16 184 #define Q81_CTL_SYSTEM_ENABLE_VQM_WR BIT_5 185 #define Q81_CTL_SYSTEM_ENABLE_DWC BIT_4 186 #define Q81_CTL_SYSTEM_ENABLE_DA_SINGLE_THRD BIT_3 187 #define Q81_CTL_SYSTEM_ENABLE_MDC BIT_2 188 #define Q81_CTL_SYSTEM_ENABLE_FAE BIT_1 189 #define Q81_CTL_SYSTEM_ENABLE_EFE BIT_0 190 191 /* 192 * Reset Register (0x0C) 193 */ 194 #define Q81_CTL_RESET_MASK_SHIFT 16 195 #define Q81_CTL_RESET_FUNC BIT_15 196 #define Q81_CTL_RESET_RR_SHIFT 1 197 198 /* 199 * Function Specific Control Register (0x10) 200 */ 201 #define Q81_CTL_FUNC_SPECIFIC_MASK_SHIFT 16 202 203 #define Q81_CTL_FUNC_SPECIFIC_FE BIT_15 204 #define Q81_CTL_FUNC_SPECIFIC_STE BIT_13 205 #define Q81_CTL_FUNC_SPECIFIC_DSB BIT_12 206 #define Q81_CTL_FUNC_SPECIFIC_SH BIT_11 207 208 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_MASK (0x7 << 8) 209 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_2K (0x1 << 8) 210 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_4K (0x2 << 8) 211 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_8K (0x3 << 8) 212 #define Q81_CTL_FUNC_SPECIFIC_VM_PGSIZE_64K (0x6 << 8) 213 214 #define Q81_CTL_FUNC_SPECIFIC_EPC_O BIT_7 215 #define Q81_CTL_FUNC_SPECIFIC_EPC_I BIT_6 216 #define Q81_CTL_FUNC_SPECIFIC_EC BIT_5 217 #define Q81_CTL_FUNC_SPECIFIC_DBL_DBRST (0x00 << 3) 218 #define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_PAYLDSZ (0x01 << 3) 219 #define Q81_CTL_FUNC_SPECIFIC_DBL_MAX_RDBRSTSZ (0x02 << 3) 220 #define Q81_CTL_FUNC_SPECIFIC_DBL_128 (0x03 << 3) 221 #define Q81_CTL_FUNC_SPECIFIC_DBRST_256 0x00 222 #define Q81_CTL_FUNC_SPECIFIC_DBRST_512 0x01 223 #define Q81_CTL_FUNC_SPECIFIC_DBRST_768 0x02 224 #define Q81_CTL_FUNC_SPECIFIC_DBRST_1024 0x03 225 226 /* 227 * Host Command/Status Register (0x14) 228 */ 229 #define Q81_CTL_HCS_CMD_NOP (0x00 << 28) 230 #define Q81_CTL_HCS_CMD_SET_RISC_RESET (0x01 << 28) 231 #define Q81_CTL_HCS_CMD_CLR_RISC_RESET (0x02 << 28) 232 #define Q81_CTL_HCS_CMD_SET_RISC_PAUSE (0x03 << 28) 233 #define Q81_CTL_HCS_CMD_CLR_RISC_PAUSE (0x04 << 28) 234 #define Q81_CTL_HCS_CMD_SET_HTR_INTR (0x05 << 28) 235 #define Q81_CTL_HCS_CMD_CLR_HTR_INTR (0x06 << 28) 236 #define Q81_CTL_HCS_CMD_SET_PARITY_EN (0x07 << 28) 237 #define Q81_CTL_HCS_CMD_FORCE_BAD_PARITY (0x08 << 28) 238 #define Q81_CTL_HCS_CMD_CLR_BAD_PARITY (0x09 << 28) 239 #define Q81_CTL_HCS_CMD_CLR_RTH_INTR (0x0A << 28) 240 241 #define Q81_CTL_HCS_CMD_PAR_SHIFT 22 242 #define Q81_CTL_HCS_RISC_PAUSED BIT_10 243 #define Q81_CTL_HCS_HTR_INTR BIT_9 244 #define Q81_CTL_HCS_RISC_RESET BIT_8 245 #define Q81_CTL_HCS_ERR_STATUS_MASK 0x3F 246 247 /* 248 * Configuration Register (0x28) 249 */ 250 #define Q81_CTL_CONFIG_MASK_SHIFT 16 251 #define Q81_CTL_CONFIG_Q_NUM_SHIFT 8 252 #define Q81_CTL_CONFIG_Q_NUM_MASK (0x7F << Q81_CTL_CONFIG_Q_NUM_SHIFT) 253 #define Q81_CTL_CONFIG_DCQ BIT_7 254 #define Q81_CTL_CONFIG_LCQ BIT_6 255 #define Q81_CTL_CONFIG_LE BIT_5 256 #define Q81_CTL_CONFIG_DR BIT_3 257 #define Q81_CTL_CONFIG_LR BIT_2 258 #define Q81_CTL_CONFIG_DRQ BIT_1 259 #define Q81_CTL_CONFIG_LRQ BIT_0 260 261 /* 262 * Status Register (0x30) 263 */ 264 #define Q81_CTL_STATUS_MASK_SHIFT 16 265 #define Q81_CTL_STATUS_NFE BIT_12 266 #define Q81_CTL_STATUS_F3E BIT_11 267 #define Q81_CTL_STATUS_F2E BIT_10 268 #define Q81_CTL_STATUS_F1E BIT_9 269 #define Q81_CTL_STATUS_F0E BIT_8 270 #define Q81_CTL_STATUS_FUNC_SHIFT 6 271 #define Q81_CTL_STATUS_PI1 BIT_5 272 #define Q81_CTL_STATUS_PI0 BIT_4 273 #define Q81_CTL_STATUS_PL1 BIT_3 274 #define Q81_CTL_STATUS_PL0 BIT_2 275 #define Q81_CTL_STATUS_PI BIT_1 276 #define Q81_CTL_STATUS_FE BIT_0 277 278 /* 279 * Interrupt Enable Register (0x34) 280 */ 281 #define Q81_CTL_INTRE_MASK_SHIFT 16 282 #define Q81_CTL_INTRE_EN BIT_15 283 #define Q81_CTL_INTRE_EI BIT_14 284 #define Q81_CTL_INTRE_IHD BIT_13 285 #define Q81_CTL_INTRE_RTYPE_MASK (0x3 << 8) 286 #define Q81_CTL_INTRE_RTYPE_ENABLE (0x1 << 8) 287 #define Q81_CTL_INTRE_RTYPE_DISABLE (0x2 << 8) 288 #define Q81_CTL_INTRE_RTYPE_SETUP_TO_RD (0x3 << 8) 289 #define Q81_CTL_INTRE_HOST_INTR_MASK 0x7F 290 291 /* 292 * Interrupt Mask Register (0x38) 293 */ 294 #define Q81_CTL_INTRM_MASK_SHIFT 16 295 #define Q81_CTL_INTRM_MC BIT_7 296 #define Q81_CTL_INTRM_LSC BIT_6 297 #define Q81_CTL_INTRM_LH1 BIT_4 298 #define Q81_CTL_INTRM_HL1 BIT_3 299 #define Q81_CTL_INTRM_LH0 BIT_2 300 #define Q81_CTL_INTRM_HL0 BIT_1 301 #define Q81_CTL_INTRM_PI BIT_0 302 303 /* 304 * Interrupt Status 1 Register (0x3C) 305 */ 306 #define Q81_CTL_INTRS1_COMPQ(i) (0x1 << i) 307 308 /* 309 * Interrupt Status 2 Register (0x40) 310 */ 311 #define Q81_CTL_INTRS2_COMPQ(i) (0x1 << i) 312 313 /* 314 * Interrupt Status 3 Register (0x44) 315 */ 316 #define Q81_CTL_INTRS3_COMPQ(i) (0x1 << i) 317 318 /* 319 * Interrupt Status 4 Register (0x48) 320 */ 321 #define Q81_CTL_INTRS4_COMPQ(i) (0x1 << i) 322 323 /* 324 * Revision ID Register (0x4C) 325 */ 326 #define Q81_CTL_REV_ID_CHIP_REV_MASK (0xF << 28) 327 #define Q81_CTL_REV_ID_XGMAC_RCV_MASK (0xF << 16) 328 #define Q81_CTL_REV_ID_XGMAC_ROLL_MASK (0xF << 8) 329 #define Q81_CTL_REV_ID_NIC_REV_MASK (0xF << 4) 330 #define Q81_CTL_REV_ID_NIC_ROLL_MASK (0xF << 0) 331 332 /* 333 * Semaphore Register (0x64) 334 */ 335 336 #define Q81_CTL_SEM_MASK_PROC_ADDR_NIC_RCV 0xC0000000 337 338 #define Q81_CTL_SEM_MASK_RIDX_DATAREG 0x30000000 339 340 #define Q81_CTL_SEM_MASK_FLASH 0x03000000 341 342 #define Q81_CTL_SEM_MASK_MAC_SERDES 0x00C00000 343 344 #define Q81_CTL_SEM_MASK_ICB 0x00300000 345 346 #define Q81_CTL_SEM_MASK_XGMAC1 0x000C0000 347 348 #define Q81_CTL_SEM_MASK_XGMAC0 0x00030000 349 350 #define Q81_CTL_SEM_SET_PROC_ADDR_NIC_RCV 0x4000 351 #define Q81_CTL_SEM_SET_RIDX_DATAREG 0x1000 352 #define Q81_CTL_SEM_SET_FLASH 0x0100 353 #define Q81_CTL_SEM_SET_MAC_SERDES 0x0040 354 #define Q81_CTL_SEM_SET_ICB 0x0010 355 #define Q81_CTL_SEM_SET_XGMAC1 0x0004 356 #define Q81_CTL_SEM_SET_XGMAC0 0x0001 357 358 /* 359 * Flash Address Register (0x88) 360 */ 361 #define Q81_CTL_FLASH_ADDR_RDY BIT_31 362 #define Q81_CTL_FLASH_ADDR_R BIT_30 363 #define Q81_CTL_FLASH_ADDR_ERR BIT_29 364 #define Q81_CTL_FLASH_ADDR_MASK 0x7FFFFF 365 366 /* 367 * Stop CQ Processing Register (0x90) 368 */ 369 #define Q81_CTL_STOP_CQ_MASK_SHIFT 16 370 #define Q81_CTL_STOP_CQ_EN BIT_15 371 #define Q81_CTL_STOP_CQ_RQ_STARTQ (0x1 << 8) 372 #define Q81_CTL_STOP_CQ_RQ_STOPQ (0x2 << 8) 373 #define Q81_CTL_STOP_CQ_RQ_READ (0x3 << 8) 374 #define Q81_CTL_STOP_CQ_MASK 0x7F 375 376 /* 377 * MAC Protocol Address Index Register (0xA8) 378 */ 379 #define Q81_CTL_MAC_PROTO_AI_MW BIT_31 380 #define Q81_CTL_MAC_PROTO_AI_MR BIT_30 381 #define Q81_CTL_MAC_PROTO_AI_E BIT_27 382 #define Q81_CTL_MAC_PROTO_AI_RS BIT_26 383 #define Q81_CTL_MAC_PROTO_AI_ADR BIT_25 384 #define Q81_CTL_MAC_PROTO_AI_TYPE_SHIFT 16 385 #define Q81_CTL_MAC_PROTO_AI_TYPE_MASK 0xF0000 386 #define Q81_CTL_MAC_PROTO_AI_IDX_SHIFT 4 387 #define Q81_CTL_MAC_PROTO_AI_IDX_MASK 0xFFF0 388 #define Q81_CTL_MAC_PROTO_AI_OFF_MASK 0xF 389 390 #define Q81_CTL_MAC_PROTO_AI_TYPE_CAM_MAC (0 << 16) 391 #define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST (1 << 16) 392 #define Q81_CTL_MAC_PROTO_AI_TYPE_VLAN (2 << 16) 393 #define Q81_CTL_MAC_PROTO_AI_TYPE_MCAST_FILTER (3 << 16) 394 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_MAC (5 << 16) 395 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMMT_VLAN (6 << 16) 396 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV4 (7 << 16) 397 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_IPV6 (8 << 16) 398 #define Q81_CTL_MAC_PROTO_AI_TYPE_MGMT_PORT (9 << 16) /* TCP/UDP Port */ 399 400 /* 401 * CAM MAC offset 2 definitions 402 */ 403 #define Q81_CAM_MAC_OFF2_ROUTE_FC 0x00000000 404 #define Q81_CAM_MAC_OFF2_ROUTE_NIC 0x00000001 405 #define Q81_CAM_MAC_OFF2_FUNC_SHIFT 2 406 #define Q81_CAM_MAC_OFF2_RV 0x00000010 407 #define Q81_CAM_MAC_OFF2_CQID_SHIFT 5 408 #define Q81_CAM_MAC_OFF2_SH 0x00008000 409 #define Q81_CAM_MAC_OFF2_MHT 0x40000000 410 #define Q81_CAM_MAC_OFF2_VLD 0x80000000 411 412 /* 413 * NIC Pause Threshold Register (0xC8) 414 */ 415 #define Q81_CTL_NIC_PAUSE_THRES_PAUSE_SHIFT 16 416 #define Q81_CTL_NIC_PAUSE_THRES_RESUME_SHIFT 0 417 418 /* 419 * NIC Receive Configuration Register (0xD4) 420 */ 421 #define Q81_CTL_NIC_RCVC_MASK_SHIFT 16 422 #define Q81_CTL_NIC_RCVC_DCQ_SHIFT 8 423 #define Q81_CTL_NIC_RCVC_DCQ_MASK 0x7F00 424 #define Q81_CTL_NIC_RCVC_DTP BIT_5 425 #define Q81_CTL_NIC_RCVC_R4T BIT_4 426 #define Q81_CTL_NIC_RCVC_RV BIT_3 427 #define Q81_CTL_NIC_RCVC_VLAN_ALL (0x0 << 1) 428 #define Q81_CTL_NIC_RCVC_VLAN_ONLY (0x1 << 1) 429 #define Q81_CTL_NIC_RCVC_VLAN_NON_VLAN (0x2 << 1) 430 #define Q81_CTL_NIC_RCVC_VLAN_REJECT (0x3 << 1) 431 #define Q81_CTL_NIC_RCVC_PPE BIT_0 432 433 /* 434 * Routing Index Register (0xE4) 435 */ 436 #define Q81_CTL_RI_MW BIT_31 437 #define Q81_CTL_RI_MR BIT_30 438 #define Q81_CTL_RI_E BIT_27 439 #define Q81_CTL_RI_RS BIT_26 440 441 #define Q81_CTL_RI_DST_RSS (0x00 << 20) 442 #define Q81_CTL_RI_DST_CAMQ (0x01 << 20) 443 #define Q81_CTL_RI_DST_COSQ (0x02 << 20) 444 #define Q81_CTL_RI_DST_DFLTQ (0x03 << 20) 445 #define Q81_CTL_RI_DST_DESTQ (0x04 << 20) 446 #define Q81_CTL_RI_DST_DROP (0x07 << 20) 447 448 #define Q81_CTL_RI_TYPE_RTMASK (0x00 << 16) 449 #define Q81_CTL_RI_TYPE_RTINVMASK (0x01 << 16) 450 #define Q81_CTL_RI_TYPE_NICQMASK (0x02 << 16) 451 #define Q81_CTL_RI_TYPE_NICQINVMASK (0x03 << 16) 452 453 /* these indices for the Routing Index Register are user defined */ 454 #define Q81_CTL_RI_IDX_ALL_ERROR (0x00 << 8) 455 #define Q81_CTL_RI_IDX_MAC_ERROR (0x00 << 8) 456 #define Q81_CTL_RI_IDX_IPCSUM_ERROR (0x01 << 8) 457 #define Q81_CTL_RI_IDX_TCPCSUM_ERROR (0x02 << 8) 458 #define Q81_CTL_RI_IDX_BCAST (0x03 << 8) 459 #define Q81_CTL_RI_IDX_MCAST_MATCH (0x04 << 8) 460 #define Q81_CTL_RI_IDX_ALLMULTI (0x05 << 8) 461 #define Q81_CTL_RI_IDX_RSS_MATCH (0x08 << 8) 462 #define Q81_CTL_RI_IDX_RSS_IPV4 (0x08 << 8) 463 #define Q81_CTL_RI_IDX_RSS_IPV6 (0x09 << 8) 464 #define Q81_CTL_RI_IDX_RSS_TCPV4 (0x0A << 8) 465 #define Q81_CTL_RI_IDX_RSS_TCPV6 (0x0B << 8) 466 #define Q81_CTL_RI_IDX_CAM_HIT (0x0C << 8) 467 #define Q81_CTL_RI_IDX_PROMISCUOUS (0x0F << 8) 468 469 /* Routing Masks to be loaded into Routing Data Register */ 470 #define Q81_CTL_RD_BCAST BIT_0 471 #define Q81_CTL_RD_MCAST BIT_1 472 #define Q81_CTL_RD_MCAST_MATCH BIT_2 473 #define Q81_CTL_RD_MCAST_REG_MATCH BIT_3 474 #define Q81_CTL_RD_MCAST_HASH_MATCH BIT_4 475 #define Q81_CTL_RD_CAM_HIT BIT_7 476 #define Q81_CTL_RD_CAM_BIT0 BIT_8 477 #define Q81_CTL_RD_CAM_BIT1 BIT_9 478 #define Q81_CTL_RD_VLAN_TAG_PRESENT BIT_10 479 #define Q81_CTL_RD_VLAN_MATCH BIT_11 480 #define Q81_CTL_RD_VLAN_FILTER_PASS BIT_12 481 #define Q81_CTL_RD_SKIP_ETHERTYPE_1 BIT_13 482 #define Q81_CTL_RD_SKIP_ETHERTYPE_2 BIT_14 483 #define Q81_CTL_RD_BCAST_OR_MCAST_MATCH BIT_15 484 #define Q81_CTL_RD_802_3_PKT BIT_16 485 #define Q81_CTL_RD_LLDP_PKT BIT_17 486 #define Q81_CTL_RD_TUNNELED_PKT BIT_18 487 #define Q81_CTL_RD_ERROR_PKT BIT_22 488 #define Q81_CTL_RD_VALID_PKT BIT_23 489 #define Q81_CTL_RD_TCP_UDP_CSUM_ERR BIT_24 490 #define Q81_CTL_RD_IPCSUM_ERR BIT_25 491 #define Q81_CTL_RD_MAC_ERR BIT_26 492 #define Q81_CTL_RD_RSS_TCP_IPV6 BIT_27 493 #define Q81_CTL_RD_RSS_TCP_IPV4 BIT_28 494 #define Q81_CTL_RD_RSS_IPV6 BIT_29 495 #define Q81_CTL_RD_RSS_IPV4 BIT_30 496 #define Q81_CTL_RD_RSS_MATCH BIT_31 497 498 /********************************************************************* 499 * Host Data Structures * 500 *********************************************************************/ 501 502 /* 503 * Work Queue Initialization Control Block 504 */ 505 506 typedef struct _q81_wq_icb { 507 uint16_t length_v; 508 #define Q81_WQ_ICB_VALID BIT_4 509 510 uint8_t pri; 511 #define Q81_WQ_ICB_PRI_SHIFT 1 512 513 uint8_t flags; 514 #define Q81_WQ_ICB_FLAGS_LO BIT_7 515 #define Q81_WQ_ICB_FLAGS_LI BIT_6 516 #define Q81_WQ_ICB_FLAGS_LB BIT_5 517 #define Q81_WQ_ICB_FLAGS_LC BIT_4 518 519 uint16_t wqcqid_rss; 520 #define Q81_WQ_ICB_RSS_V BIT_15 521 522 uint16_t rsrvd; 523 524 uint32_t baddr_lo; 525 uint32_t baddr_hi; 526 527 uint32_t ci_addr_lo; 528 uint32_t ci_addr_hi; 529 } __packed q81_wq_icb_t; 530 531 /* 532 * Completion Queue Initialization Control Block 533 */ 534 535 typedef struct _q81_cq_icb { 536 uint8_t msix_vector; 537 uint16_t rsrvd0; 538 uint8_t flags; 539 #define Q81_CQ_ICB_FLAGS_LC BIT_7 540 #define Q81_CQ_ICB_FLAGS_LI BIT_6 541 #define Q81_CQ_ICB_FLAGS_LL BIT_5 542 #define Q81_CQ_ICB_FLAGS_LS BIT_4 543 #define Q81_CQ_ICB_FLAGS_LV BIT_3 544 545 uint16_t length_v; 546 #define Q81_CQ_ICB_VALID BIT_4 547 548 uint16_t rsrvd1; 549 550 uint32_t cq_baddr_lo; 551 uint32_t cq_baddr_hi; 552 553 uint32_t cqi_addr_lo; 554 uint32_t cqi_addr_hi; 555 556 uint16_t pkt_idelay; 557 uint16_t idelay; 558 559 uint32_t lbq_baddr_lo; 560 uint32_t lbq_baddr_hi; 561 uint16_t lbq_bsize; 562 uint16_t lbq_length; 563 564 uint32_t sbq_baddr_lo; 565 uint32_t sbq_baddr_hi; 566 uint16_t sbq_bsize; 567 uint16_t sbq_length; 568 } __packed q81_cq_icb_t; 569 570 /* 571 * RSS Initialization Control Block 572 */ 573 typedef struct _q81_rss_icb { 574 uint16_t flags_base_cq_num; 575 #define Q81_RSS_ICB_FLAGS_L4K BIT_7 576 #define Q81_RSS_ICB_FLAGS_L6K BIT_8 577 #define Q81_RSS_ICB_FLAGS_LI BIT_9 578 #define Q81_RSS_ICB_FLAGS_LB BIT_10 579 #define Q81_RSS_ICB_FLAGS_LM BIT_11 580 #define Q81_RSS_ICB_FLAGS_RI4 BIT_12 581 #define Q81_RSS_ICB_FLAGS_RT4 BIT_13 582 #define Q81_RSS_ICB_FLAGS_RI6 BIT_14 583 #define Q81_RSS_ICB_FLAGS_RT6 BIT_15 584 585 uint16_t mask; /* bits 9-0 are valid */ 586 587 #define Q81_RSS_ICB_NUM_INDTBL_ENTRIES 1024 588 /* Indirection Table */ 589 uint8_t cq_id[Q81_RSS_ICB_NUM_INDTBL_ENTRIES]; 590 591 /* Hash Keys */ 592 uint32_t ipv6_rss_hash_key[10]; 593 uint32_t ipv4_rss_hash_key[4]; 594 } __packed q81_rss_icb_t; 595 596 /* 597 * Transmit Buffer Descriptor 598 */ 599 600 typedef struct _q81_txb_desc { 601 uint64_t baddr; 602 uint16_t length; 603 604 uint16_t flags; 605 #define Q81_TXB_DESC_FLAGS_E BIT_15 606 #define Q81_TXB_DESC_FLAGS_C BIT_14 607 608 } __packed q81_txb_desc_t; 609 610 /* 611 * Receive Buffer Descriptor 612 */ 613 614 typedef struct _q81_rxb_desc { 615 uint32_t baddr_lo; 616 #define Q81_RXB_DESC_BADDR_LO_S BIT_1 617 618 uint64_t baddr; 619 620 uint16_t length; 621 622 uint16_t flags; 623 #define Q81_RXB_DESC_FLAGS_E BIT_15 624 #define Q81_RXB_DESC_FLAGS_C BIT_14 625 626 } __packed q81_rxb_desc_t; 627 628 /* 629 * IOCB Types 630 */ 631 632 #define Q81_IOCB_TX_MAC 0x01 633 #define Q81_IOCB_TX_TSO 0x02 634 #define Q81_IOCB_RX 0x20 635 #define Q81_IOCB_MPI 0x21 636 #define Q81_IOCB_SYS 0x3F 637 638 /* 639 * IOCB Definitions 640 */ 641 642 /* 643 * MAC Tx Frame IOCB 644 * Total Size of each IOCB Entry = 4 * 32 = 128 bytes 645 */ 646 #define MAX_TX_MAC_DESC 8 647 648 typedef struct _q81_tx_mac { 649 uint8_t opcode; 650 651 uint16_t flags; 652 #define Q81_TX_MAC_FLAGS_D BIT_3 653 #define Q81_TX_MAC_FLAGS_I BIT_1 654 #define Q81_TX_MAC_FLAGS_OI BIT_0 655 656 uint8_t vlan_off; 657 #define Q81_TX_MAC_VLAN_OFF_SHIFT 3 658 #define Q81_TX_MAC_VLAN_OFF_V BIT_2 659 #define Q81_TX_MAC_VLAN_OFF_DFP BIT_1 660 661 uint32_t rsrvd1; 662 uint32_t rsrvd2; 663 664 uint16_t frame_length; /* only bits0-13 are valid */ 665 uint16_t rsrvd3; 666 667 uint32_t tid_lo; 668 uint32_t tid_hi; 669 670 uint32_t rsrvd4; 671 672 uint16_t vlan_tci; 673 uint16_t rsrvd5; 674 675 q81_txb_desc_t txd[MAX_TX_MAC_DESC]; 676 } __packed q81_tx_mac_t; 677 678 /* 679 * MAC Tx Frame with TSO IOCB 680 * Total Size of each IOCB Entry = 4 * 32 = 128 bytes 681 */ 682 typedef struct _q81_tx_tso { 683 uint8_t opcode; 684 685 uint16_t flags; 686 #define Q81_TX_TSO_FLAGS_OI BIT_0 687 #define Q81_TX_TSO_FLAGS_I BIT_1 688 #define Q81_TX_TSO_FLAGS_D BIT_3 689 #define Q81_TX_TSO_FLAGS_IPV4 BIT_6 690 #define Q81_TX_TSO_FLAGS_IPV6 BIT_7 691 #define Q81_TX_TSO_FLAGS_LSO BIT_13 692 #define Q81_TX_TSO_FLAGS_UC BIT_14 693 #define Q81_TX_TSO_FLAGS_TC BIT_15 694 695 uint8_t vlan_off; 696 #define Q81_TX_TSO_VLAN_OFF_SHIFT 3 697 #define Q81_TX_TSO_VLAN_OFF_V BIT_2 698 #define Q81_TX_TSO_VLAN_OFF_DFP BIT_1 699 #define Q81_TX_TSO_VLAN_OFF_IC BIT_0 700 701 uint32_t rsrvd1; 702 uint32_t rsrvd2; 703 704 uint32_t length; 705 uint32_t tid_lo; 706 uint32_t tid_hi; 707 708 uint16_t phdr_length; 709 710 uint16_t phdr_offsets; 711 #define Q81_TX_TSO_PHDR_SHIFT 6 712 713 uint16_t vlan_tci; 714 uint16_t mss; 715 716 q81_txb_desc_t txd[MAX_TX_MAC_DESC]; 717 } __packed q81_tx_tso_t; 718 719 typedef struct _q81_tx_cmd { 720 uint8_t bytes[128]; 721 } __packed q81_tx_cmd_t; 722 723 /* 724 * MAC TX Frame Completion 725 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 726 */ 727 728 typedef struct _q81_tx_mac_comp { 729 uint8_t opcode; 730 731 uint8_t flags; 732 #define Q81_TX_MAC_COMP_FLAGS_OI BIT_0 733 #define Q81_TX_MAC_COMP_FLAGS_I BIT_1 734 #define Q81_TX_MAC_COMP_FLAGS_E BIT_3 735 #define Q81_TX_MAC_COMP_FLAGS_S BIT_4 736 #define Q81_TX_MAC_COMP_FLAGS_L BIT_5 737 #define Q81_TX_MAC_COMP_FLAGS_P BIT_6 738 739 uint8_t rsrvd0; 740 741 uint8_t err; 742 #define Q81_TX_MAC_COMP_ERR_B BIT_7 743 744 uint32_t tid_lo; 745 uint32_t tid_hi; 746 747 uint32_t rsrvd1[13]; 748 } __packed q81_tx_mac_comp_t; 749 750 /* 751 * MAC TX Frame with LSO Completion 752 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 753 */ 754 755 typedef struct _q81_tx_tso_comp { 756 uint8_t opcode; 757 758 uint8_t flags; 759 #define Q81_TX_TSO_COMP_FLAGS_OI BIT_0 760 #define Q81_TX_TSO_COMP_FLAGS_I BIT_1 761 #define Q81_TX_TSO_COMP_FLAGS_E BIT_3 762 #define Q81_TX_TSO_COMP_FLAGS_S BIT_4 763 #define Q81_TX_TSO_COMP_FLAGS_P BIT_6 764 765 uint8_t rsrvd0; 766 767 uint8_t err; 768 #define Q81_TX_TSO_COMP_ERR_B BIT_7 769 770 uint32_t tid_lo; 771 uint32_t tid_hi; 772 773 uint32_t rsrvd1[13]; 774 } __packed q81_tx_tso_comp_t; 775 776 /* 777 * SYS - Chip Event Notification Completion 778 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 779 */ 780 781 typedef struct _q81_sys_comp { 782 uint8_t opcode; 783 784 uint8_t flags; 785 #define Q81_SYS_COMP_FLAGS_OI BIT_0 786 #define Q81_SYS_COMP_FLAGS_I BIT_1 787 788 uint8_t etype; 789 #define Q81_SYS_COMPE_LINK_UP 0x00 790 #define Q81_SYS_COMPE_LINK_DOWN 0x01 791 #define Q81_SYS_COMPE_MULTI_CAM_LOOKUP 0x06 792 #define Q81_SYS_COMPE_SOFT_ECC 0x07 793 #define Q81_SYS_COMPE_MPI_FATAL_ERROR 0x08 794 #define Q81_SYS_COMPE_MAC_INTR 0x09 795 #define Q81_SYS_COMPE_GPI0_HTOL 0x10 796 #define Q81_SYS_COMPE_GPI0_LTOH 0x20 797 #define Q81_SYS_COMPE_GPI1_HTOL 0x11 798 #define Q81_SYS_COMPE_GPI1_LTOH 0x21 799 800 uint8_t q_id; /* only bits 0-6 are valid */ 801 802 uint32_t rsrvd1[15]; 803 } __packed q81_sys_comp_t; 804 805 /* 806 * Mac Rx Packet Completion 807 * Total Size of each IOCB Entry = 4 * 16 = 64 bytes 808 */ 809 810 typedef struct _q81_rx { 811 uint8_t opcode; 812 813 uint8_t flags0; 814 #define Q81_RX_FLAGS0_OI BIT_0 815 #define Q81_RX_FLAGS0_I BIT_1 816 #define Q81_RX_FLAGS0_TE BIT_2 817 #define Q81_RX_FLAGS0_NU BIT_3 818 #define Q81_RX_FLAGS0_IE BIT_4 819 820 #define Q81_RX_FLAGS0_MCAST_MASK (0x03 << 5) 821 #define Q81_RX_FLAGS0_MCAST_NONE (0x00 << 5) 822 #define Q81_RX_FLAGS0_MCAST_HASH_MATCH (0x01 << 5) 823 #define Q81_RX_FLAGS0_MCAST_REG_MATCH (0x02 << 5) 824 #define Q81_RX_FLAGS0_MCAST_PROMISC (0x03 << 5) 825 826 #define Q81_RX_FLAGS0_B BIT_7 827 828 uint16_t flags1; 829 #define Q81_RX_FLAGS1_P BIT_0 830 #define Q81_RX_FLAGS1_V BIT_1 831 832 #define Q81_RX_FLAGS1_ERR_NONE (0x00 << 2) 833 #define Q81_RX_FLAGS1_ERR_CODE (0x01 << 2) 834 #define Q81_RX_FLAGS1_ERR_OSIZE (0x02 << 2) 835 #define Q81_RX_FLAGS1_ERR_USIZE (0x04 << 2) 836 #define Q81_RX_FLAGS1_ERR_PREAMBLE (0x05 << 2) 837 #define Q81_RX_FLAGS1_ERR_FRAMELENGTH (0x06 << 2) 838 #define Q81_RX_FLAGS1_ERR_CRC (0x07 << 2) 839 #define Q81_RX_FLAGS1_ERR_MASK (0x07 << 2) 840 841 #define Q81_RX_FLAGS1_U BIT_5 842 #define Q81_RX_FLAGS1_T BIT_6 843 #define Q81_RX_FLAGS1_FO BIT_7 844 #define Q81_RX_FLAGS1_RSS_NO_MATCH (0x00 << 8) 845 #define Q81_RX_FLAGS1_RSS_IPV4_MATCH (0x04 << 8) 846 #define Q81_RX_FLAGS1_RSS_IPV6_MATCH (0x02 << 8) 847 #define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8) 848 #define Q81_RX_FLAGS1_RSS_TCPIPV4_MATCH (0x05 << 8) 849 #define Q81_RX_FLAGS1_RSS_MATCH_MASK (0x07 << 8) 850 #define Q81_RX_FLAGS1_V4 BIT_11 851 #define Q81_RX_FLAGS1_V6 BIT_12 852 #define Q81_RX_FLAGS1_IH BIT_13 853 #define Q81_RX_FLAGS1_DS BIT_14 854 #define Q81_RX_FLAGS1_DL BIT_15 855 856 uint32_t length; 857 uint64_t b_paddr; 858 859 uint32_t rss; 860 uint16_t vlan_tag; 861 uint16_t rsrvd; 862 uint32_t rsrvd1; 863 uint32_t flags2; 864 #define Q81_RX_FLAGS2_HV BIT_13 865 #define Q81_RX_FLAGS2_HS BIT_14 866 #define Q81_RX_FLAGS2_HL BIT_15 867 868 uint32_t hdr_length; 869 uint32_t hdr_baddr_lo; 870 uint32_t hdr_baddr_hi; 871 872 } __packed q81_rx_t; 873 874 typedef struct _q81_cq_e { 875 uint8_t opcode; 876 uint8_t bytes[63]; 877 } __packed q81_cq_e_t; 878 879 typedef struct _q81_bq_addr_e { 880 uint32_t addr_lo; 881 uint32_t addr_hi; 882 } __packed q81_bq_addr_e_t; 883 884 /* 885 * Macros for reading and writing registers 886 */ 887 888 #if defined(__i386__) || defined(__amd64__) 889 #define Q8_MB() __asm volatile("mfence" ::: "memory") 890 #define Q8_WMB() __asm volatile("sfence" ::: "memory") 891 #define Q8_RMB() __asm volatile("lfence" ::: "memory") 892 #else 893 #define Q8_MB() 894 #define Q8_WMB() 895 #define Q8_RMB() 896 #endif 897 898 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 899 #define READ_REG64(ha, reg) bus_read_8((ha->pci_reg), reg) 900 901 #define WRITE_REG32_ONLY(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) 902 903 #define WRITE_REG32(ha, reg, val) bus_write_4((ha->pci_reg), reg, val) 904 905 #define Q81_CTL_INTRE_MASK_VALUE \ 906 (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \ 907 Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_ENABLE) 908 909 #define Q81_ENABLE_INTR(ha, idx) \ 910 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx)) 911 912 #define Q81_CTL_INTRD_MASK_VALUE \ 913 (((Q81_CTL_INTRE_RTYPE_MASK | Q81_CTL_INTRE_HOST_INTR_MASK) << \ 914 Q81_CTL_INTRE_MASK_SHIFT) | Q81_CTL_INTRE_RTYPE_DISABLE) 915 916 #define Q81_DISABLE_INTR(ha, idx) \ 917 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx)) 918 919 #define Q81_WR_WQ_PROD_IDX(wq_idx, idx) bus_write_4((ha->pci_reg1),\ 920 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG), idx) 921 922 #define Q81_RD_WQ_IDX(wq_idx) bus_read_4((ha->pci_reg1),\ 923 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_INDEX_REG)) 924 925 #define Q81_SET_WQ_VALID(wq_idx) bus_write_4((ha->pci_reg1),\ 926 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ 927 Q81_COMPQ_VALID_V) 928 929 #define Q81_SET_WQ_INVALID(wq_idx) bus_write_4((ha->pci_reg1),\ 930 (ha->tx_ring[wq_idx].wq_db_offset + Q81_WRKQ_VALID_REG),\ 931 (~Q81_COMPQ_VALID_V)) 932 933 #define Q81_WR_CQ_CONS_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 934 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG), idx) 935 936 #define Q81_RD_CQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 937 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_INDEX_REG)) 938 939 #define Q81_SET_CQ_VALID(cq_idx) bus_write_4((ha->pci_reg1),\ 940 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\ 941 Q81_COMPQ_VALID_V) 942 943 #define Q81_SET_CQ_INVALID(cq_idx) bus_write_4((ha->pci_reg1),\ 944 (ha->rx_ring[cq_idx].cq_db_offset + Q81_COMPQ_VALID_REG),\ 945 ~Q81_COMPQ_VALID_V) 946 947 #define Q81_WR_LBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 948 (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG), idx) 949 950 #define Q81_RD_LBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 951 (ha->rx_ring[cq_idx].cq_db_offset + Q81_LRGBQ_INDEX_REG)) 952 953 #define Q81_WR_SBQ_PROD_IDX(cq_idx, idx) bus_write_4((ha->pci_reg1),\ 954 (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG), idx) 955 956 #define Q81_RD_SBQ_IDX(cq_idx) bus_read_4((ha->pci_reg1),\ 957 (ha->rx_ring[cq_idx].cq_db_offset + Q81_SMBQ_INDEX_REG)) 958 959 /* 960 * Flash Related 961 */ 962 963 #define Q81_F0_FLASH_OFFSET 0x140200 964 #define Q81_F1_FLASH_OFFSET 0x140600 965 #define Q81_FLASH_ID "8000" 966 967 typedef struct _q81_flash { 968 uint8_t id[4]; /* equal to "8000" */ 969 970 uint16_t version; 971 uint16_t size; 972 uint16_t csum; 973 uint16_t rsrvd0; 974 uint16_t total_size; 975 uint16_t nentries; 976 977 uint8_t dtype0; 978 uint8_t dsize0; 979 uint8_t mac_addr0[6]; 980 981 uint8_t dtype1; 982 uint8_t dsize1; 983 uint8_t mac_addr1[6]; 984 985 uint8_t dtype2; 986 uint8_t dsize2; 987 uint16_t vlan_id; 988 989 uint8_t dtype3; 990 uint8_t dsize3; 991 uint16_t last; 992 993 uint8_t rsrvd1[464]; 994 995 uint16_t subsys_vid; 996 uint16_t subsys_did; 997 998 uint8_t rsrvd2[4]; 999 } __packed q81_flash_t; 1000 1001 /* 1002 * MPI Related 1003 */ 1004 1005 #define Q81_NUM_MBX_REGISTERS 16 1006 #define Q81_NUM_AEN_REGISTERS 9 1007 1008 #define Q81_FUNC0_MBX_IN_REG0 0x1180 1009 #define Q81_FUNC0_MBX_OUT_REG0 0x1190 1010 1011 #define Q81_FUNC1_MBX_IN_REG0 0x1280 1012 #define Q81_FUNC1_MBX_OUT_REG0 0x1290 1013 1014 #define Q81_MBX_NOP 0x0000 1015 #define Q81_MBX_EXEC_FW 0x0002 1016 #define Q81_MBX_REG_TEST 0x0006 1017 #define Q81_MBX_VERIFY_CHKSUM 0x0007 1018 #define Q81_MBX_ABOUT_FW 0x0008 1019 #define Q81_MBX_RISC_MEMCPY 0x000A 1020 #define Q81_MBX_LOAD_RISC_RAM 0x000B 1021 #define Q81_MBX_DUMP_RISC_RAM 0x000C 1022 #define Q81_MBX_WR_RAM_WORD 0x000D 1023 #define Q81_MBX_INIT_RISC_RAM 0x000E 1024 #define Q81_MBX_RD_RAM_WORD 0x000F 1025 #define Q81_MBX_STOP_FW 0x0014 1026 #define Q81_MBX_GEN_SYS_ERR 0x002A 1027 #define Q81_MBX_WR_SFP_PLUS 0x0030 1028 #define Q81_MBX_RD_SFP_PLUS 0x0031 1029 #define Q81_MBX_INIT_FW 0x0060 1030 #define Q81_MBX_GET_IFCB 0x0061 1031 #define Q81_MBX_GET_FW_STATE 0x0069 1032 #define Q81_MBX_IDC_REQ 0x0100 1033 #define Q81_MBX_IDC_ACK 0x0101 1034 #define Q81_MBX_IDC_TIME_EXTEND 0x0102 1035 #define Q81_MBX_WOL_MODE 0x0110 1036 #define Q81_MBX_SET_WOL_FILTER 0x0111 1037 #define Q81_MBX_CLR_WOL_FILTER 0x0112 1038 #define Q81_MBX_SET_WOL_MAGIC 0x0113 1039 #define Q81_MBX_WOL_MODE_IMM 0x0115 1040 #define Q81_MBX_PORT_RESET 0x0120 1041 #define Q81_MBX_SET_PORT_CFG 0x0122 1042 #define Q81_MBX_GET_PORT_CFG 0x0123 1043 #define Q81_MBX_GET_LNK_STATUS 0x0124 1044 #define Q81_MBX_SET_LED_CFG 0x0125 1045 #define Q81_MBX_GET_LED_CFG 0x0126 1046 #define Q81_MBX_SET_DCBX_CTLB 0x0130 1047 #define Q81_MBX_GET_DCBX_CTLB 0x0131 1048 #define Q81_MBX_GET_DCBX_TLV 0x0132 1049 #define Q81_MBX_DIAG_CMDS 0x0150 1050 #define Q81_MBX_SET_MGMT_CTL 0x0160 1051 #define Q81_MBX_SET_MGMT_CTL_STOP 0x01 1052 #define Q81_MBX_SET_MGMT_CTL_RESUME 0x02 1053 #define Q81_MBX_GET_MGMT_CTL 0x0161 1054 #define Q81_MBX_GET_MGMT_CTL_MASK ~0x3 1055 #define Q81_MBX_GET_MGMT_CTL_FIFO_EMPTY 0x02 1056 #define Q81_MBX_GET_MGMT_CTL_SET_MGMT 0x01 1057 1058 #define Q81_MBX_CMD_COMPLETE 0x4000 1059 #define Q81_MBX_CMD_INVALID 0x4001 1060 #define Q81_MBX_CMD_TEST_FAILED 0x4003 1061 #define Q81_MBX_CMD_ERROR 0x4005 1062 #define Q81_MBX_CMD_PARAM_ERROR 0x4006 1063 1064 #endif /* #ifndef _QLS_HW_H_ */ 1065