1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2014 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * File: qls_dump.h 32 */ 33 34 #ifndef _QLS_DUMP_H_ 35 #define _QLS_DUMP_H_ 36 37 #define Q81_MPID_COOKIE 0x5555aaaa 38 39 typedef struct qls_mpid_glbl_hdr 40 { 41 uint32_t cookie; 42 uint8_t id[16]; 43 uint32_t time_lo; 44 uint32_t time_hi; 45 uint32_t img_size; 46 uint32_t hdr_size; 47 uint8_t info[220]; 48 } qls_mpid_glbl_hdr_t; 49 50 typedef struct qls_mpid_seg_hdr 51 { 52 uint32_t cookie; 53 uint32_t seg_num; 54 uint32_t seg_size; 55 uint32_t extra; 56 uint8_t desc[16]; 57 } qls_mpid_seg_hdr_t; 58 59 enum 60 { 61 Q81_MPI_CORE_REGS_ADDR = 0x00030000, 62 Q81_MPI_CORE_REGS_CNT = 127, 63 Q81_MPI_CORE_SH_REGS_CNT = 16, 64 Q81_TEST_REGS_ADDR = 0x00001000, 65 Q81_TEST_REGS_CNT = 23, 66 Q81_RMII_REGS_ADDR = 0x00001040, 67 Q81_RMII_REGS_CNT = 64, 68 Q81_FCMAC1_REGS_ADDR = 0x00001080, 69 Q81_FCMAC2_REGS_ADDR = 0x000010c0, 70 Q81_FCMAC_REGS_CNT = 64, 71 Q81_FC1_MBX_REGS_ADDR = 0x00001100, 72 Q81_FC2_MBX_REGS_ADDR = 0x00001240, 73 Q81_FC_MBX_REGS_CNT = 64, 74 Q81_IDE_REGS_ADDR = 0x00001140, 75 Q81_IDE_REGS_CNT = 64, 76 Q81_NIC1_MBX_REGS_ADDR = 0x00001180, 77 Q81_NIC2_MBX_REGS_ADDR = 0x00001280, 78 Q81_NIC_MBX_REGS_CNT = 64, 79 Q81_SMBUS_REGS_ADDR = 0x00001200, 80 Q81_SMBUS_REGS_CNT = 64, 81 Q81_I2C_REGS_ADDR = 0x00001fc0, 82 Q81_I2C_REGS_CNT = 64, 83 Q81_MEMC_REGS_ADDR = 0x00003000, 84 Q81_MEMC_REGS_CNT = 256, 85 Q81_PBUS_REGS_ADDR = 0x00007c00, 86 Q81_PBUS_REGS_CNT = 256, 87 Q81_MDE_REGS_ADDR = 0x00010000, 88 Q81_MDE_REGS_CNT = 6, 89 Q81_CODE_RAM_ADDR = 0x00020000, 90 Q81_CODE_RAM_CNT = 0x2000, 91 Q81_MEMC_RAM_ADDR = 0x00100000, 92 Q81_MEMC_RAM_CNT = 0x2000, 93 Q81_XGMAC_REGISTER_END = 0x740, 94 }; 95 96 #define Q81_PROBE_DATA_LENGTH_WORDS ((64*2) + 1) 97 #define Q81_NUMBER_OF_PROBES 34 98 99 #define Q81_PROBE_SIZE \ 100 (Q81_PROBE_DATA_LENGTH_WORDS * Q81_NUMBER_OF_PROBES) 101 102 #define Q81_NUMBER_ROUTING_REG_ENTRIES 48 103 #define Q81_WORDS_PER_ROUTING_REG_ENTRY 4 104 105 #define Q81_ROUT_REG_SIZE \ 106 (Q81_NUMBER_ROUTING_REG_ENTRIES * Q81_WORDS_PER_ROUTING_REG_ENTRY) 107 108 #define Q81_MAC_PROTOCOL_REGISTER_WORDS ((512 * 3) + (32 * 2) + (4096 * 1) +\ 109 (4096 * 1) + (4 * 2) +\ 110 (8 * 2) + (16 * 1) +\ 111 (4 * 1) + (4 * 4) + (4 * 1)) 112 113 #define Q81_WORDS_PER_MAC_PROT_ENTRY 2 114 #define Q81_MAC_REG_SIZE \ 115 (Q81_MAC_PROTOCOL_REGISTER_WORDS * Q81_WORDS_PER_MAC_PROT_ENTRY) 116 117 #define Q81_MAX_SEMAPHORE_FUNCTIONS 5 118 119 #define Q81_WQC_WORD_SIZE 6 120 #define Q81_NUMBER_OF_WQCS 128 121 #define Q81_WQ_SIZE (Q81_WQC_WORD_SIZE * Q81_NUMBER_OF_WQCS) 122 123 #define Q81_CQC_WORD_SIZE 13 124 #define Q81_NUMBER_OF_CQCS 128 125 #define Q81_CQ_SIZE (Q81_CQC_WORD_SIZE * Q81_NUMBER_OF_CQCS) 126 127 struct qls_mpi_coredump { 128 qls_mpid_glbl_hdr_t mpi_global_header; 129 130 qls_mpid_seg_hdr_t core_regs_seg_hdr; 131 uint32_t mpi_core_regs[Q81_MPI_CORE_REGS_CNT]; 132 uint32_t mpi_core_sh_regs[Q81_MPI_CORE_SH_REGS_CNT]; 133 134 qls_mpid_seg_hdr_t test_logic_regs_seg_hdr; 135 uint32_t test_logic_regs[Q81_TEST_REGS_CNT]; 136 137 qls_mpid_seg_hdr_t rmii_regs_seg_hdr; 138 uint32_t rmii_regs[Q81_RMII_REGS_CNT]; 139 140 qls_mpid_seg_hdr_t fcmac1_regs_seg_hdr; 141 uint32_t fcmac1_regs[Q81_FCMAC_REGS_CNT]; 142 143 qls_mpid_seg_hdr_t fcmac2_regs_seg_hdr; 144 uint32_t fcmac2_regs[Q81_FCMAC_REGS_CNT]; 145 146 qls_mpid_seg_hdr_t fc1_mbx_regs_seg_hdr; 147 uint32_t fc1_mbx_regs[Q81_FC_MBX_REGS_CNT]; 148 149 qls_mpid_seg_hdr_t ide_regs_seg_hdr; 150 uint32_t ide_regs[Q81_IDE_REGS_CNT]; 151 152 qls_mpid_seg_hdr_t nic1_mbx_regs_seg_hdr; 153 uint32_t nic1_mbx_regs[Q81_NIC_MBX_REGS_CNT]; 154 155 qls_mpid_seg_hdr_t smbus_regs_seg_hdr; 156 uint32_t smbus_regs[Q81_SMBUS_REGS_CNT]; 157 158 qls_mpid_seg_hdr_t fc2_mbx_regs_seg_hdr; 159 uint32_t fc2_mbx_regs[Q81_FC_MBX_REGS_CNT]; 160 161 qls_mpid_seg_hdr_t nic2_mbx_regs_seg_hdr; 162 uint32_t nic2_mbx_regs[Q81_NIC_MBX_REGS_CNT]; 163 164 qls_mpid_seg_hdr_t i2c_regs_seg_hdr; 165 uint32_t i2c_regs[Q81_I2C_REGS_CNT]; 166 167 qls_mpid_seg_hdr_t memc_regs_seg_hdr; 168 uint32_t memc_regs[Q81_MEMC_REGS_CNT]; 169 170 qls_mpid_seg_hdr_t pbus_regs_seg_hdr; 171 uint32_t pbus_regs[Q81_PBUS_REGS_CNT]; 172 173 qls_mpid_seg_hdr_t mde_regs_seg_hdr; 174 uint32_t mde_regs[Q81_MDE_REGS_CNT]; 175 176 qls_mpid_seg_hdr_t xaui1_an_hdr; 177 uint32_t serdes1_xaui_an[14]; 178 179 qls_mpid_seg_hdr_t xaui1_hss_pcs_hdr; 180 uint32_t serdes1_xaui_hss_pcs[33]; 181 182 qls_mpid_seg_hdr_t xfi1_an_hdr; 183 uint32_t serdes1_xfi_an[14]; 184 185 qls_mpid_seg_hdr_t xfi1_train_hdr; 186 uint32_t serdes1_xfi_train[12]; 187 188 qls_mpid_seg_hdr_t xfi1_hss_pcs_hdr; 189 uint32_t serdes1_xfi_hss_pcs[15]; 190 191 qls_mpid_seg_hdr_t xfi1_hss_tx_hdr; 192 uint32_t serdes1_xfi_hss_tx[32]; 193 194 qls_mpid_seg_hdr_t xfi1_hss_rx_hdr; 195 uint32_t serdes1_xfi_hss_rx[32]; 196 197 qls_mpid_seg_hdr_t xfi1_hss_pll_hdr; 198 uint32_t serdes1_xfi_hss_pll[32]; 199 200 qls_mpid_seg_hdr_t xaui2_an_hdr; 201 uint32_t serdes2_xaui_an[14]; 202 203 qls_mpid_seg_hdr_t xaui2_hss_pcs_hdr; 204 uint32_t serdes2_xaui_hss_pcs[33]; 205 206 qls_mpid_seg_hdr_t xfi2_an_hdr; 207 uint32_t serdes2_xfi_an[14]; 208 209 qls_mpid_seg_hdr_t xfi2_train_hdr; 210 uint32_t serdes2_xfi_train[12]; 211 212 qls_mpid_seg_hdr_t xfi2_hss_pcs_hdr; 213 uint32_t serdes2_xfi_hss_pcs[15]; 214 215 qls_mpid_seg_hdr_t xfi2_hss_tx_hdr; 216 uint32_t serdes2_xfi_hss_tx[32]; 217 218 qls_mpid_seg_hdr_t xfi2_hss_rx_hdr; 219 uint32_t serdes2_xfi_hss_rx[32]; 220 221 qls_mpid_seg_hdr_t xfi2_hss_pll_hdr; 222 uint32_t serdes2_xfi_hss_pll[32]; 223 224 qls_mpid_seg_hdr_t nic1_regs_seg_hdr; 225 uint32_t nic1_regs[64]; 226 227 qls_mpid_seg_hdr_t nic2_regs_seg_hdr; 228 uint32_t nic2_regs[64]; 229 230 qls_mpid_seg_hdr_t intr_states_seg_hdr; 231 uint32_t intr_states[MAX_RX_RINGS]; 232 233 qls_mpid_seg_hdr_t xgmac1_seg_hdr; 234 uint32_t xgmac1[Q81_XGMAC_REGISTER_END]; 235 236 qls_mpid_seg_hdr_t xgmac2_seg_hdr; 237 uint32_t xgmac2[Q81_XGMAC_REGISTER_END]; 238 239 qls_mpid_seg_hdr_t probe_dump_seg_hdr; 240 uint32_t probe_dump[Q81_PROBE_SIZE]; 241 242 qls_mpid_seg_hdr_t routing_reg_seg_hdr; 243 uint32_t routing_regs[Q81_ROUT_REG_SIZE]; 244 245 qls_mpid_seg_hdr_t mac_prot_reg_seg_hdr; 246 uint32_t mac_prot_regs[Q81_MAC_REG_SIZE]; 247 248 qls_mpid_seg_hdr_t sem_regs_seg_hdr; 249 uint32_t sem_regs[Q81_MAX_SEMAPHORE_FUNCTIONS]; 250 251 qls_mpid_seg_hdr_t ets_seg_hdr; 252 uint32_t ets[8+2]; 253 254 qls_mpid_seg_hdr_t wqc1_seg_hdr; 255 uint32_t wqc1[Q81_WQ_SIZE]; 256 257 qls_mpid_seg_hdr_t cqc1_seg_hdr; 258 uint32_t cqc1[Q81_CQ_SIZE]; 259 260 qls_mpid_seg_hdr_t wqc2_seg_hdr; 261 uint32_t wqc2[Q81_WQ_SIZE]; 262 263 qls_mpid_seg_hdr_t cqc2_seg_hdr; 264 uint32_t cqc2[Q81_CQ_SIZE]; 265 266 qls_mpid_seg_hdr_t code_ram_seg_hdr; 267 uint32_t code_ram[Q81_CODE_RAM_CNT]; 268 269 qls_mpid_seg_hdr_t memc_ram_seg_hdr; 270 uint32_t memc_ram[Q81_MEMC_RAM_CNT]; 271 }; 272 typedef struct qls_mpi_coredump qls_mpi_coredump_t; 273 274 #define Q81_BAD_DATA 0xDEADBEEF 275 276 #endif /* #ifndef _QLS_DUMP_H_ */ 277