1*718cf2ccSPedro F. Giffuni /*- 2*718cf2ccSPedro F. Giffuni * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3*718cf2ccSPedro F. Giffuni * 4711bcba0SDavid C Somayajulu * Copyright (c) 2013-2014 Qlogic Corporation 5711bcba0SDavid C Somayajulu * All rights reserved. 6711bcba0SDavid C Somayajulu * 7711bcba0SDavid C Somayajulu * Redistribution and use in source and binary forms, with or without 8711bcba0SDavid C Somayajulu * modification, are permitted provided that the following conditions 9711bcba0SDavid C Somayajulu * are met: 10711bcba0SDavid C Somayajulu * 11711bcba0SDavid C Somayajulu * 1. Redistributions of source code must retain the above copyright 12711bcba0SDavid C Somayajulu * notice, this list of conditions and the following disclaimer. 13711bcba0SDavid C Somayajulu * 2. Redistributions in binary form must reproduce the above copyright 14711bcba0SDavid C Somayajulu * notice, this list of conditions and the following disclaimer in the 15711bcba0SDavid C Somayajulu * documentation and/or other materials provided with the distribution. 16711bcba0SDavid C Somayajulu * 17711bcba0SDavid C Somayajulu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18711bcba0SDavid C Somayajulu * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19711bcba0SDavid C Somayajulu * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20711bcba0SDavid C Somayajulu * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21711bcba0SDavid C Somayajulu * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22711bcba0SDavid C Somayajulu * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23711bcba0SDavid C Somayajulu * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24711bcba0SDavid C Somayajulu * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25711bcba0SDavid C Somayajulu * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26711bcba0SDavid C Somayajulu * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27711bcba0SDavid C Somayajulu * POSSIBILITY OF SUCH DAMAGE. 28711bcba0SDavid C Somayajulu * 29711bcba0SDavid C Somayajulu * $FreeBSD$ 30711bcba0SDavid C Somayajulu */ 31711bcba0SDavid C Somayajulu 32711bcba0SDavid C Somayajulu /* 33711bcba0SDavid C Somayajulu * File: qls_dump.h 34711bcba0SDavid C Somayajulu */ 35711bcba0SDavid C Somayajulu 36711bcba0SDavid C Somayajulu #ifndef _QLS_DUMP_H_ 37711bcba0SDavid C Somayajulu #define _QLS_DUMP_H_ 38711bcba0SDavid C Somayajulu 39711bcba0SDavid C Somayajulu #define Q81_MPID_COOKIE 0x5555aaaa 40711bcba0SDavid C Somayajulu 41711bcba0SDavid C Somayajulu typedef struct qls_mpid_glbl_hdr 42711bcba0SDavid C Somayajulu { 43711bcba0SDavid C Somayajulu uint32_t cookie; 44711bcba0SDavid C Somayajulu uint8_t id[16]; 45711bcba0SDavid C Somayajulu uint32_t time_lo; 46711bcba0SDavid C Somayajulu uint32_t time_hi; 47711bcba0SDavid C Somayajulu uint32_t img_size; 48711bcba0SDavid C Somayajulu uint32_t hdr_size; 49711bcba0SDavid C Somayajulu uint8_t info[220]; 50711bcba0SDavid C Somayajulu } qls_mpid_glbl_hdr_t; 51711bcba0SDavid C Somayajulu 52711bcba0SDavid C Somayajulu typedef struct qls_mpid_seg_hdr 53711bcba0SDavid C Somayajulu { 54711bcba0SDavid C Somayajulu uint32_t cookie; 55711bcba0SDavid C Somayajulu uint32_t seg_num; 56711bcba0SDavid C Somayajulu uint32_t seg_size; 57711bcba0SDavid C Somayajulu uint32_t extra; 58711bcba0SDavid C Somayajulu uint8_t desc[16]; 59711bcba0SDavid C Somayajulu } qls_mpid_seg_hdr_t; 60711bcba0SDavid C Somayajulu 61711bcba0SDavid C Somayajulu enum 62711bcba0SDavid C Somayajulu { 63711bcba0SDavid C Somayajulu Q81_MPI_CORE_REGS_ADDR = 0x00030000, 64711bcba0SDavid C Somayajulu Q81_MPI_CORE_REGS_CNT = 127, 65711bcba0SDavid C Somayajulu Q81_MPI_CORE_SH_REGS_CNT = 16, 66711bcba0SDavid C Somayajulu Q81_TEST_REGS_ADDR = 0x00001000, 67711bcba0SDavid C Somayajulu Q81_TEST_REGS_CNT = 23, 68711bcba0SDavid C Somayajulu Q81_RMII_REGS_ADDR = 0x00001040, 69711bcba0SDavid C Somayajulu Q81_RMII_REGS_CNT = 64, 70711bcba0SDavid C Somayajulu Q81_FCMAC1_REGS_ADDR = 0x00001080, 71711bcba0SDavid C Somayajulu Q81_FCMAC2_REGS_ADDR = 0x000010c0, 72711bcba0SDavid C Somayajulu Q81_FCMAC_REGS_CNT = 64, 73711bcba0SDavid C Somayajulu Q81_FC1_MBX_REGS_ADDR = 0x00001100, 74711bcba0SDavid C Somayajulu Q81_FC2_MBX_REGS_ADDR = 0x00001240, 75711bcba0SDavid C Somayajulu Q81_FC_MBX_REGS_CNT = 64, 76711bcba0SDavid C Somayajulu Q81_IDE_REGS_ADDR = 0x00001140, 77711bcba0SDavid C Somayajulu Q81_IDE_REGS_CNT = 64, 78711bcba0SDavid C Somayajulu Q81_NIC1_MBX_REGS_ADDR = 0x00001180, 79711bcba0SDavid C Somayajulu Q81_NIC2_MBX_REGS_ADDR = 0x00001280, 80711bcba0SDavid C Somayajulu Q81_NIC_MBX_REGS_CNT = 64, 81711bcba0SDavid C Somayajulu Q81_SMBUS_REGS_ADDR = 0x00001200, 82711bcba0SDavid C Somayajulu Q81_SMBUS_REGS_CNT = 64, 83711bcba0SDavid C Somayajulu Q81_I2C_REGS_ADDR = 0x00001fc0, 84711bcba0SDavid C Somayajulu Q81_I2C_REGS_CNT = 64, 85711bcba0SDavid C Somayajulu Q81_MEMC_REGS_ADDR = 0x00003000, 86711bcba0SDavid C Somayajulu Q81_MEMC_REGS_CNT = 256, 87711bcba0SDavid C Somayajulu Q81_PBUS_REGS_ADDR = 0x00007c00, 88711bcba0SDavid C Somayajulu Q81_PBUS_REGS_CNT = 256, 89711bcba0SDavid C Somayajulu Q81_MDE_REGS_ADDR = 0x00010000, 90711bcba0SDavid C Somayajulu Q81_MDE_REGS_CNT = 6, 91711bcba0SDavid C Somayajulu Q81_CODE_RAM_ADDR = 0x00020000, 92711bcba0SDavid C Somayajulu Q81_CODE_RAM_CNT = 0x2000, 93711bcba0SDavid C Somayajulu Q81_MEMC_RAM_ADDR = 0x00100000, 94711bcba0SDavid C Somayajulu Q81_MEMC_RAM_CNT = 0x2000, 95711bcba0SDavid C Somayajulu Q81_XGMAC_REGISTER_END = 0x740, 96711bcba0SDavid C Somayajulu }; 97711bcba0SDavid C Somayajulu 98711bcba0SDavid C Somayajulu #define Q81_PROBE_DATA_LENGTH_WORDS ((64*2) + 1) 99711bcba0SDavid C Somayajulu #define Q81_NUMBER_OF_PROBES 34 100711bcba0SDavid C Somayajulu 101711bcba0SDavid C Somayajulu #define Q81_PROBE_SIZE \ 102711bcba0SDavid C Somayajulu (Q81_PROBE_DATA_LENGTH_WORDS * Q81_NUMBER_OF_PROBES) 103711bcba0SDavid C Somayajulu 104711bcba0SDavid C Somayajulu #define Q81_NUMBER_ROUTING_REG_ENTRIES 48 105711bcba0SDavid C Somayajulu #define Q81_WORDS_PER_ROUTING_REG_ENTRY 4 106711bcba0SDavid C Somayajulu 107711bcba0SDavid C Somayajulu #define Q81_ROUT_REG_SIZE \ 108711bcba0SDavid C Somayajulu (Q81_NUMBER_ROUTING_REG_ENTRIES * Q81_WORDS_PER_ROUTING_REG_ENTRY) 109711bcba0SDavid C Somayajulu 110711bcba0SDavid C Somayajulu #define Q81_MAC_PROTOCOL_REGISTER_WORDS ((512 * 3) + (32 * 2) + (4096 * 1) +\ 111711bcba0SDavid C Somayajulu (4096 * 1) + (4 * 2) +\ 112711bcba0SDavid C Somayajulu (8 * 2) + (16 * 1) +\ 113711bcba0SDavid C Somayajulu (4 * 1) + (4 * 4) + (4 * 1)) 114711bcba0SDavid C Somayajulu 115711bcba0SDavid C Somayajulu #define Q81_WORDS_PER_MAC_PROT_ENTRY 2 116711bcba0SDavid C Somayajulu #define Q81_MAC_REG_SIZE \ 117711bcba0SDavid C Somayajulu (Q81_MAC_PROTOCOL_REGISTER_WORDS * Q81_WORDS_PER_MAC_PROT_ENTRY) 118711bcba0SDavid C Somayajulu 119711bcba0SDavid C Somayajulu #define Q81_MAX_SEMAPHORE_FUNCTIONS 5 120711bcba0SDavid C Somayajulu 121711bcba0SDavid C Somayajulu #define Q81_WQC_WORD_SIZE 6 122711bcba0SDavid C Somayajulu #define Q81_NUMBER_OF_WQCS 128 123711bcba0SDavid C Somayajulu #define Q81_WQ_SIZE (Q81_WQC_WORD_SIZE * Q81_NUMBER_OF_WQCS) 124711bcba0SDavid C Somayajulu 125711bcba0SDavid C Somayajulu #define Q81_CQC_WORD_SIZE 13 126711bcba0SDavid C Somayajulu #define Q81_NUMBER_OF_CQCS 128 127711bcba0SDavid C Somayajulu #define Q81_CQ_SIZE (Q81_CQC_WORD_SIZE * Q81_NUMBER_OF_CQCS) 128711bcba0SDavid C Somayajulu 129711bcba0SDavid C Somayajulu struct qls_mpi_coredump { 130711bcba0SDavid C Somayajulu qls_mpid_glbl_hdr_t mpi_global_header; 131711bcba0SDavid C Somayajulu 132711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t core_regs_seg_hdr; 133711bcba0SDavid C Somayajulu uint32_t mpi_core_regs[Q81_MPI_CORE_REGS_CNT]; 134711bcba0SDavid C Somayajulu uint32_t mpi_core_sh_regs[Q81_MPI_CORE_SH_REGS_CNT]; 135711bcba0SDavid C Somayajulu 136711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t test_logic_regs_seg_hdr; 137711bcba0SDavid C Somayajulu uint32_t test_logic_regs[Q81_TEST_REGS_CNT]; 138711bcba0SDavid C Somayajulu 139711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t rmii_regs_seg_hdr; 140711bcba0SDavid C Somayajulu uint32_t rmii_regs[Q81_RMII_REGS_CNT]; 141711bcba0SDavid C Somayajulu 142711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t fcmac1_regs_seg_hdr; 143711bcba0SDavid C Somayajulu uint32_t fcmac1_regs[Q81_FCMAC_REGS_CNT]; 144711bcba0SDavid C Somayajulu 145711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t fcmac2_regs_seg_hdr; 146711bcba0SDavid C Somayajulu uint32_t fcmac2_regs[Q81_FCMAC_REGS_CNT]; 147711bcba0SDavid C Somayajulu 148711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t fc1_mbx_regs_seg_hdr; 149711bcba0SDavid C Somayajulu uint32_t fc1_mbx_regs[Q81_FC_MBX_REGS_CNT]; 150711bcba0SDavid C Somayajulu 151711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t ide_regs_seg_hdr; 152711bcba0SDavid C Somayajulu uint32_t ide_regs[Q81_IDE_REGS_CNT]; 153711bcba0SDavid C Somayajulu 154711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t nic1_mbx_regs_seg_hdr; 155711bcba0SDavid C Somayajulu uint32_t nic1_mbx_regs[Q81_NIC_MBX_REGS_CNT]; 156711bcba0SDavid C Somayajulu 157711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t smbus_regs_seg_hdr; 158711bcba0SDavid C Somayajulu uint32_t smbus_regs[Q81_SMBUS_REGS_CNT]; 159711bcba0SDavid C Somayajulu 160711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t fc2_mbx_regs_seg_hdr; 161711bcba0SDavid C Somayajulu uint32_t fc2_mbx_regs[Q81_FC_MBX_REGS_CNT]; 162711bcba0SDavid C Somayajulu 163711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t nic2_mbx_regs_seg_hdr; 164711bcba0SDavid C Somayajulu uint32_t nic2_mbx_regs[Q81_NIC_MBX_REGS_CNT]; 165711bcba0SDavid C Somayajulu 166711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t i2c_regs_seg_hdr; 167711bcba0SDavid C Somayajulu uint32_t i2c_regs[Q81_I2C_REGS_CNT]; 168711bcba0SDavid C Somayajulu 169711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t memc_regs_seg_hdr; 170711bcba0SDavid C Somayajulu uint32_t memc_regs[Q81_MEMC_REGS_CNT]; 171711bcba0SDavid C Somayajulu 172711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t pbus_regs_seg_hdr; 173711bcba0SDavid C Somayajulu uint32_t pbus_regs[Q81_PBUS_REGS_CNT]; 174711bcba0SDavid C Somayajulu 175711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t mde_regs_seg_hdr; 176711bcba0SDavid C Somayajulu uint32_t mde_regs[Q81_MDE_REGS_CNT]; 177711bcba0SDavid C Somayajulu 178711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xaui1_an_hdr; 179711bcba0SDavid C Somayajulu uint32_t serdes1_xaui_an[14]; 180711bcba0SDavid C Somayajulu 181711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xaui1_hss_pcs_hdr; 182711bcba0SDavid C Somayajulu uint32_t serdes1_xaui_hss_pcs[33]; 183711bcba0SDavid C Somayajulu 184711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi1_an_hdr; 185711bcba0SDavid C Somayajulu uint32_t serdes1_xfi_an[14]; 186711bcba0SDavid C Somayajulu 187711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi1_train_hdr; 188711bcba0SDavid C Somayajulu uint32_t serdes1_xfi_train[12]; 189711bcba0SDavid C Somayajulu 190711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi1_hss_pcs_hdr; 191711bcba0SDavid C Somayajulu uint32_t serdes1_xfi_hss_pcs[15]; 192711bcba0SDavid C Somayajulu 193711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi1_hss_tx_hdr; 194711bcba0SDavid C Somayajulu uint32_t serdes1_xfi_hss_tx[32]; 195711bcba0SDavid C Somayajulu 196711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi1_hss_rx_hdr; 197711bcba0SDavid C Somayajulu uint32_t serdes1_xfi_hss_rx[32]; 198711bcba0SDavid C Somayajulu 199711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi1_hss_pll_hdr; 200711bcba0SDavid C Somayajulu uint32_t serdes1_xfi_hss_pll[32]; 201711bcba0SDavid C Somayajulu 202711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xaui2_an_hdr; 203711bcba0SDavid C Somayajulu uint32_t serdes2_xaui_an[14]; 204711bcba0SDavid C Somayajulu 205711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xaui2_hss_pcs_hdr; 206711bcba0SDavid C Somayajulu uint32_t serdes2_xaui_hss_pcs[33]; 207711bcba0SDavid C Somayajulu 208711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi2_an_hdr; 209711bcba0SDavid C Somayajulu uint32_t serdes2_xfi_an[14]; 210711bcba0SDavid C Somayajulu 211711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi2_train_hdr; 212711bcba0SDavid C Somayajulu uint32_t serdes2_xfi_train[12]; 213711bcba0SDavid C Somayajulu 214711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi2_hss_pcs_hdr; 215711bcba0SDavid C Somayajulu uint32_t serdes2_xfi_hss_pcs[15]; 216711bcba0SDavid C Somayajulu 217711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi2_hss_tx_hdr; 218711bcba0SDavid C Somayajulu uint32_t serdes2_xfi_hss_tx[32]; 219711bcba0SDavid C Somayajulu 220711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi2_hss_rx_hdr; 221711bcba0SDavid C Somayajulu uint32_t serdes2_xfi_hss_rx[32]; 222711bcba0SDavid C Somayajulu 223711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xfi2_hss_pll_hdr; 224711bcba0SDavid C Somayajulu uint32_t serdes2_xfi_hss_pll[32]; 225711bcba0SDavid C Somayajulu 226711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t nic1_regs_seg_hdr; 227711bcba0SDavid C Somayajulu uint32_t nic1_regs[64]; 228711bcba0SDavid C Somayajulu 229711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t nic2_regs_seg_hdr; 230711bcba0SDavid C Somayajulu uint32_t nic2_regs[64]; 231711bcba0SDavid C Somayajulu 232711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t intr_states_seg_hdr; 233711bcba0SDavid C Somayajulu uint32_t intr_states[MAX_RX_RINGS]; 234711bcba0SDavid C Somayajulu 235711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xgmac1_seg_hdr; 236711bcba0SDavid C Somayajulu uint32_t xgmac1[Q81_XGMAC_REGISTER_END]; 237711bcba0SDavid C Somayajulu 238711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t xgmac2_seg_hdr; 239711bcba0SDavid C Somayajulu uint32_t xgmac2[Q81_XGMAC_REGISTER_END]; 240711bcba0SDavid C Somayajulu 241711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t probe_dump_seg_hdr; 242711bcba0SDavid C Somayajulu uint32_t probe_dump[Q81_PROBE_SIZE]; 243711bcba0SDavid C Somayajulu 244711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t routing_reg_seg_hdr; 245711bcba0SDavid C Somayajulu uint32_t routing_regs[Q81_ROUT_REG_SIZE]; 246711bcba0SDavid C Somayajulu 247711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t mac_prot_reg_seg_hdr; 248711bcba0SDavid C Somayajulu uint32_t mac_prot_regs[Q81_MAC_REG_SIZE]; 249711bcba0SDavid C Somayajulu 250711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t sem_regs_seg_hdr; 251711bcba0SDavid C Somayajulu uint32_t sem_regs[Q81_MAX_SEMAPHORE_FUNCTIONS]; 252711bcba0SDavid C Somayajulu 253711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t ets_seg_hdr; 254711bcba0SDavid C Somayajulu uint32_t ets[8+2]; 255711bcba0SDavid C Somayajulu 256711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t wqc1_seg_hdr; 257711bcba0SDavid C Somayajulu uint32_t wqc1[Q81_WQ_SIZE]; 258711bcba0SDavid C Somayajulu 259711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t cqc1_seg_hdr; 260711bcba0SDavid C Somayajulu uint32_t cqc1[Q81_CQ_SIZE]; 261711bcba0SDavid C Somayajulu 262711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t wqc2_seg_hdr; 263711bcba0SDavid C Somayajulu uint32_t wqc2[Q81_WQ_SIZE]; 264711bcba0SDavid C Somayajulu 265711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t cqc2_seg_hdr; 266711bcba0SDavid C Somayajulu uint32_t cqc2[Q81_CQ_SIZE]; 267711bcba0SDavid C Somayajulu 268711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t code_ram_seg_hdr; 269711bcba0SDavid C Somayajulu uint32_t code_ram[Q81_CODE_RAM_CNT]; 270711bcba0SDavid C Somayajulu 271711bcba0SDavid C Somayajulu qls_mpid_seg_hdr_t memc_ram_seg_hdr; 272711bcba0SDavid C Somayajulu uint32_t memc_ram[Q81_MEMC_RAM_CNT]; 273711bcba0SDavid C Somayajulu }; 274711bcba0SDavid C Somayajulu typedef struct qls_mpi_coredump qls_mpi_coredump_t; 275711bcba0SDavid C Somayajulu 276711bcba0SDavid C Somayajulu #define Q81_BAD_DATA 0xDEADBEEF 277711bcba0SDavid C Somayajulu 278711bcba0SDavid C Somayajulu #endif /* #ifndef _QLS_DUMP_H_ */ 279711bcba0SDavid C Somayajulu 280