1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013-2014 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * File: qls_dump.c 32 */ 33 #include <sys/cdefs.h> 34 #include "qls_os.h" 35 #include "qls_hw.h" 36 #include "qls_def.h" 37 #include "qls_glbl.h" 38 #include "qls_dump.h" 39 40 qls_mpi_coredump_t ql_mpi_coredump; 41 42 #define Q81_CORE_SEG_NUM 1 43 #define Q81_TEST_LOGIC_SEG_NUM 2 44 #define Q81_RMII_SEG_NUM 3 45 #define Q81_FCMAC1_SEG_NUM 4 46 #define Q81_FCMAC2_SEG_NUM 5 47 #define Q81_FC1_MBOX_SEG_NUM 6 48 #define Q81_IDE_SEG_NUM 7 49 #define Q81_NIC1_MBOX_SEG_NUM 8 50 #define Q81_SMBUS_SEG_NUM 9 51 #define Q81_FC2_MBOX_SEG_NUM 10 52 #define Q81_NIC2_MBOX_SEG_NUM 11 53 #define Q81_I2C_SEG_NUM 12 54 #define Q81_MEMC_SEG_NUM 13 55 #define Q81_PBUS_SEG_NUM 14 56 #define Q81_MDE_SEG_NUM 15 57 #define Q81_NIC1_CONTROL_SEG_NUM 16 58 #define Q81_NIC2_CONTROL_SEG_NUM 17 59 #define Q81_NIC1_XGMAC_SEG_NUM 18 60 #define Q81_NIC2_XGMAC_SEG_NUM 19 61 #define Q81_WCS_RAM_SEG_NUM 20 62 #define Q81_MEMC_RAM_SEG_NUM 21 63 #define Q81_XAUI1_AN_SEG_NUM 22 64 #define Q81_XAUI1_HSS_PCS_SEG_NUM 23 65 #define Q81_XFI1_AN_SEG_NUM 24 66 #define Q81_XFI1_TRAIN_SEG_NUM 25 67 #define Q81_XFI1_HSS_PCS_SEG_NUM 26 68 #define Q81_XFI1_HSS_TX_SEG_NUM 27 69 #define Q81_XFI1_HSS_RX_SEG_NUM 28 70 #define Q81_XFI1_HSS_PLL_SEG_NUM 29 71 #define Q81_INTR_STATES_SEG_NUM 31 72 #define Q81_ETS_SEG_NUM 34 73 #define Q81_PROBE_DUMP_SEG_NUM 35 74 #define Q81_ROUTING_INDEX_SEG_NUM 36 75 #define Q81_MAC_PROTOCOL_SEG_NUM 37 76 #define Q81_XAUI2_AN_SEG_NUM 38 77 #define Q81_XAUI2_HSS_PCS_SEG_NUM 39 78 #define Q81_XFI2_AN_SEG_NUM 40 79 #define Q81_XFI2_TRAIN_SEG_NUM 41 80 #define Q81_XFI2_HSS_PCS_SEG_NUM 42 81 #define Q81_XFI2_HSS_TX_SEG_NUM 43 82 #define Q81_XFI2_HSS_RX_SEG_NUM 44 83 #define Q81_XFI2_HSS_PLL_SEG_NUM 45 84 #define Q81_WQC1_SEG_NUM 46 85 #define Q81_CQC1_SEG_NUM 47 86 #define Q81_WQC2_SEG_NUM 48 87 #define Q81_CQC2_SEG_NUM 49 88 #define Q81_SEM_REGS_SEG_NUM 50 89 90 enum 91 { 92 Q81_PAUSE_SRC_LO = 0x00000100, 93 Q81_PAUSE_SRC_HI = 0x00000104, 94 Q81_GLOBAL_CFG = 0x00000108, 95 Q81_GLOBAL_CFG_RESET = (1 << 0), /*Control*/ 96 Q81_GLOBAL_CFG_JUMBO = (1 << 6), /*Control*/ 97 Q81_GLOBAL_CFG_TX_STAT_EN = (1 << 10), /*Control*/ 98 Q81_GLOBAL_CFG_RX_STAT_EN = (1 << 11), /*Control*/ 99 Q81_TX_CFG = 0x0000010c, 100 Q81_TX_CFG_RESET = (1 << 0), /*Control*/ 101 Q81_TX_CFG_EN = (1 << 1), /*Control*/ 102 Q81_TX_CFG_PREAM = (1 << 2), /*Control*/ 103 Q81_RX_CFG = 0x00000110, 104 Q81_RX_CFG_RESET = (1 << 0), /*Control*/ 105 Q81_RX_CFG_EN = (1 << 1), /*Control*/ 106 Q81_RX_CFG_PREAM = (1 << 2), /*Control*/ 107 Q81_FLOW_CTL = 0x0000011c, 108 Q81_PAUSE_OPCODE = 0x00000120, 109 Q81_PAUSE_TIMER = 0x00000124, 110 Q81_PAUSE_FRM_DEST_LO = 0x00000128, 111 Q81_PAUSE_FRM_DEST_HI = 0x0000012c, 112 Q81_MAC_TX_PARAMS = 0x00000134, 113 Q81_MAC_TX_PARAMS_JUMBO = (1U << 31), /*Control*/ 114 Q81_MAC_TX_PARAMS_SIZE_SHIFT = 16, /*Control*/ 115 Q81_MAC_RX_PARAMS = 0x00000138, 116 Q81_MAC_SYS_INT = 0x00000144, 117 Q81_MAC_SYS_INT_MASK = 0x00000148, 118 Q81_MAC_MGMT_INT = 0x0000014c, 119 Q81_MAC_MGMT_IN_MASK = 0x00000150, 120 Q81_EXT_ARB_MODE = 0x000001fc, 121 Q81_TX_PKTS = 0x00000200, 122 Q81_TX_PKTS_LO = 0x00000204, 123 Q81_TX_BYTES = 0x00000208, 124 Q81_TX_BYTES_LO = 0x0000020C, 125 Q81_TX_MCAST_PKTS = 0x00000210, 126 Q81_TX_MCAST_PKTS_LO = 0x00000214, 127 Q81_TX_BCAST_PKTS = 0x00000218, 128 Q81_TX_BCAST_PKTS_LO = 0x0000021C, 129 Q81_TX_UCAST_PKTS = 0x00000220, 130 Q81_TX_UCAST_PKTS_LO = 0x00000224, 131 Q81_TX_CTL_PKTS = 0x00000228, 132 Q81_TX_CTL_PKTS_LO = 0x0000022c, 133 Q81_TX_PAUSE_PKTS = 0x00000230, 134 Q81_TX_PAUSE_PKTS_LO = 0x00000234, 135 Q81_TX_64_PKT = 0x00000238, 136 Q81_TX_64_PKT_LO = 0x0000023c, 137 Q81_TX_65_TO_127_PKT = 0x00000240, 138 Q81_TX_65_TO_127_PKT_LO = 0x00000244, 139 Q81_TX_128_TO_255_PKT = 0x00000248, 140 Q81_TX_128_TO_255_PKT_LO = 0x0000024c, 141 Q81_TX_256_511_PKT = 0x00000250, 142 Q81_TX_256_511_PKT_LO = 0x00000254, 143 Q81_TX_512_TO_1023_PKT = 0x00000258, 144 Q81_TX_512_TO_1023_PKT_LO = 0x0000025c, 145 Q81_TX_1024_TO_1518_PKT = 0x00000260, 146 Q81_TX_1024_TO_1518_PKT_LO = 0x00000264, 147 Q81_TX_1519_TO_MAX_PKT = 0x00000268, 148 Q81_TX_1519_TO_MAX_PKT_LO = 0x0000026c, 149 Q81_TX_UNDERSIZE_PKT = 0x00000270, 150 Q81_TX_UNDERSIZE_PKT_LO = 0x00000274, 151 Q81_TX_OVERSIZE_PKT = 0x00000278, 152 Q81_TX_OVERSIZE_PKT_LO = 0x0000027c, 153 Q81_RX_HALF_FULL_DET = 0x000002a0, 154 Q81_TX_HALF_FULL_DET_LO = 0x000002a4, 155 Q81_RX_OVERFLOW_DET = 0x000002a8, 156 Q81_TX_OVERFLOW_DET_LO = 0x000002ac, 157 Q81_RX_HALF_FULL_MASK = 0x000002b0, 158 Q81_TX_HALF_FULL_MASK_LO = 0x000002b4, 159 Q81_RX_OVERFLOW_MASK = 0x000002b8, 160 Q81_TX_OVERFLOW_MASK_LO = 0x000002bc, 161 Q81_STAT_CNT_CTL = 0x000002c0, 162 Q81_STAT_CNT_CTL_CLEAR_TX = (1 << 0), /*Control*/ 163 Q81_STAT_CNT_CTL_CLEAR_RX = (1 << 1), /*Control*/ 164 Q81_AUX_RX_HALF_FULL_DET = 0x000002d0, 165 Q81_AUX_TX_HALF_FULL_DET = 0x000002d4, 166 Q81_AUX_RX_OVERFLOW_DET = 0x000002d8, 167 Q81_AUX_TX_OVERFLOW_DET = 0x000002dc, 168 Q81_AUX_RX_HALF_FULL_MASK = 0x000002f0, 169 Q81_AUX_TX_HALF_FULL_MASK = 0x000002f4, 170 Q81_AUX_RX_OVERFLOW_MASK = 0x000002f8, 171 Q81_AUX_TX_OVERFLOW_MASK = 0x000002fc, 172 Q81_RX_BYTES = 0x00000300, 173 Q81_RX_BYTES_LO = 0x00000304, 174 Q81_RX_BYTES_OK = 0x00000308, 175 Q81_RX_BYTES_OK_LO = 0x0000030c, 176 Q81_RX_PKTS = 0x00000310, 177 Q81_RX_PKTS_LO = 0x00000314, 178 Q81_RX_PKTS_OK = 0x00000318, 179 Q81_RX_PKTS_OK_LO = 0x0000031c, 180 Q81_RX_BCAST_PKTS = 0x00000320, 181 Q81_RX_BCAST_PKTS_LO = 0x00000324, 182 Q81_RX_MCAST_PKTS = 0x00000328, 183 Q81_RX_MCAST_PKTS_LO = 0x0000032c, 184 Q81_RX_UCAST_PKTS = 0x00000330, 185 Q81_RX_UCAST_PKTS_LO = 0x00000334, 186 Q81_RX_UNDERSIZE_PKTS = 0x00000338, 187 Q81_RX_UNDERSIZE_PKTS_LO = 0x0000033c, 188 Q81_RX_OVERSIZE_PKTS = 0x00000340, 189 Q81_RX_OVERSIZE_PKTS_LO = 0x00000344, 190 Q81_RX_JABBER_PKTS = 0x00000348, 191 Q81_RX_JABBER_PKTS_LO = 0x0000034c, 192 Q81_RX_UNDERSIZE_FCERR_PKTS = 0x00000350, 193 Q81_RX_UNDERSIZE_FCERR_PKTS_LO = 0x00000354, 194 Q81_RX_DROP_EVENTS = 0x00000358, 195 Q81_RX_DROP_EVENTS_LO = 0x0000035c, 196 Q81_RX_FCERR_PKTS = 0x00000360, 197 Q81_RX_FCERR_PKTS_LO = 0x00000364, 198 Q81_RX_ALIGN_ERR = 0x00000368, 199 Q81_RX_ALIGN_ERR_LO = 0x0000036c, 200 Q81_RX_SYMBOL_ERR = 0x00000370, 201 Q81_RX_SYMBOL_ERR_LO = 0x00000374, 202 Q81_RX_MAC_ERR = 0x00000378, 203 Q81_RX_MAC_ERR_LO = 0x0000037c, 204 Q81_RX_CTL_PKTS = 0x00000380, 205 Q81_RX_CTL_PKTS_LO = 0x00000384, 206 Q81_RX_PAUSE_PKTS = 0x00000388, 207 Q81_RX_PAUSE_PKTS_LO = 0x0000038c, 208 Q81_RX_64_PKTS = 0x00000390, 209 Q81_RX_64_PKTS_LO = 0x00000394, 210 Q81_RX_65_TO_127_PKTS = 0x00000398, 211 Q81_RX_65_TO_127_PKTS_LO = 0x0000039c, 212 Q81_RX_128_255_PKTS = 0x000003a0, 213 Q81_RX_128_255_PKTS_LO = 0x000003a4, 214 Q81_RX_256_511_PKTS = 0x000003a8, 215 Q81_RX_256_511_PKTS_LO = 0x000003ac, 216 Q81_RX_512_TO_1023_PKTS = 0x000003b0, 217 Q81_RX_512_TO_1023_PKTS_LO = 0x000003b4, 218 Q81_RX_1024_TO_1518_PKTS = 0x000003b8, 219 Q81_RX_1024_TO_1518_PKTS_LO = 0x000003bc, 220 Q81_RX_1519_TO_MAX_PKTS = 0x000003c0, 221 Q81_RX_1519_TO_MAX_PKTS_LO = 0x000003c4, 222 Q81_RX_LEN_ERR_PKTS = 0x000003c8, 223 Q81_RX_LEN_ERR_PKTS_LO = 0x000003cc, 224 Q81_MDIO_TX_DATA = 0x00000400, 225 Q81_MDIO_RX_DATA = 0x00000410, 226 Q81_MDIO_CMD = 0x00000420, 227 Q81_MDIO_PHY_ADDR = 0x00000430, 228 Q81_MDIO_PORT = 0x00000440, 229 Q81_MDIO_STATUS = 0x00000450, 230 Q81_TX_CBFC_PAUSE_FRAMES0 = 0x00000500, 231 Q81_TX_CBFC_PAUSE_FRAMES0_LO = 0x00000504, 232 Q81_TX_CBFC_PAUSE_FRAMES1 = 0x00000508, 233 Q81_TX_CBFC_PAUSE_FRAMES1_LO = 0x0000050C, 234 Q81_TX_CBFC_PAUSE_FRAMES2 = 0x00000510, 235 Q81_TX_CBFC_PAUSE_FRAMES2_LO = 0x00000514, 236 Q81_TX_CBFC_PAUSE_FRAMES3 = 0x00000518, 237 Q81_TX_CBFC_PAUSE_FRAMES3_LO = 0x0000051C, 238 Q81_TX_CBFC_PAUSE_FRAMES4 = 0x00000520, 239 Q81_TX_CBFC_PAUSE_FRAMES4_LO = 0x00000524, 240 Q81_TX_CBFC_PAUSE_FRAMES5 = 0x00000528, 241 Q81_TX_CBFC_PAUSE_FRAMES5_LO = 0x0000052C, 242 Q81_TX_CBFC_PAUSE_FRAMES6 = 0x00000530, 243 Q81_TX_CBFC_PAUSE_FRAMES6_LO = 0x00000534, 244 Q81_TX_CBFC_PAUSE_FRAMES7 = 0x00000538, 245 Q81_TX_CBFC_PAUSE_FRAMES7_LO = 0x0000053C, 246 Q81_TX_FCOE_PKTS = 0x00000540, 247 Q81_TX_FCOE_PKTS_LO = 0x00000544, 248 Q81_TX_MGMT_PKTS = 0x00000548, 249 Q81_TX_MGMT_PKTS_LO = 0x0000054C, 250 Q81_RX_CBFC_PAUSE_FRAMES0 = 0x00000568, 251 Q81_RX_CBFC_PAUSE_FRAMES0_LO = 0x0000056C, 252 Q81_RX_CBFC_PAUSE_FRAMES1 = 0x00000570, 253 Q81_RX_CBFC_PAUSE_FRAMES1_LO = 0x00000574, 254 Q81_RX_CBFC_PAUSE_FRAMES2 = 0x00000578, 255 Q81_RX_CBFC_PAUSE_FRAMES2_LO = 0x0000057C, 256 Q81_RX_CBFC_PAUSE_FRAMES3 = 0x00000580, 257 Q81_RX_CBFC_PAUSE_FRAMES3_LO = 0x00000584, 258 Q81_RX_CBFC_PAUSE_FRAMES4 = 0x00000588, 259 Q81_RX_CBFC_PAUSE_FRAMES4_LO = 0x0000058C, 260 Q81_RX_CBFC_PAUSE_FRAMES5 = 0x00000590, 261 Q81_RX_CBFC_PAUSE_FRAMES5_LO = 0x00000594, 262 Q81_RX_CBFC_PAUSE_FRAMES6 = 0x00000598, 263 Q81_RX_CBFC_PAUSE_FRAMES6_LO = 0x0000059C, 264 Q81_RX_CBFC_PAUSE_FRAMES7 = 0x000005A0, 265 Q81_RX_CBFC_PAUSE_FRAMES7_LO = 0x000005A4, 266 Q81_RX_FCOE_PKTS = 0x000005A8, 267 Q81_RX_FCOE_PKTS_LO = 0x000005AC, 268 Q81_RX_MGMT_PKTS = 0x000005B0, 269 Q81_RX_MGMT_PKTS_LO = 0x000005B4, 270 Q81_RX_NIC_FIFO_DROP = 0x000005B8, 271 Q81_RX_NIC_FIFO_DROP_LO = 0x000005BC, 272 Q81_RX_FCOE_FIFO_DROP = 0x000005C0, 273 Q81_RX_FCOE_FIFO_DROP_LO = 0x000005C4, 274 Q81_RX_MGMT_FIFO_DROP = 0x000005C8, 275 Q81_RX_MGMT_FIFO_DROP_LO = 0x000005CC, 276 Q81_RX_PKTS_PRIORITY0 = 0x00000600, 277 Q81_RX_PKTS_PRIORITY0_LO = 0x00000604, 278 Q81_RX_PKTS_PRIORITY1 = 0x00000608, 279 Q81_RX_PKTS_PRIORITY1_LO = 0x0000060C, 280 Q81_RX_PKTS_PRIORITY2 = 0x00000610, 281 Q81_RX_PKTS_PRIORITY2_LO = 0x00000614, 282 Q81_RX_PKTS_PRIORITY3 = 0x00000618, 283 Q81_RX_PKTS_PRIORITY3_LO = 0x0000061C, 284 Q81_RX_PKTS_PRIORITY4 = 0x00000620, 285 Q81_RX_PKTS_PRIORITY4_LO = 0x00000624, 286 Q81_RX_PKTS_PRIORITY5 = 0x00000628, 287 Q81_RX_PKTS_PRIORITY5_LO = 0x0000062C, 288 Q81_RX_PKTS_PRIORITY6 = 0x00000630, 289 Q81_RX_PKTS_PRIORITY6_LO = 0x00000634, 290 Q81_RX_PKTS_PRIORITY7 = 0x00000638, 291 Q81_RX_PKTS_PRIORITY7_LO = 0x0000063C, 292 Q81_RX_OCTETS_PRIORITY0 = 0x00000640, 293 Q81_RX_OCTETS_PRIORITY0_LO = 0x00000644, 294 Q81_RX_OCTETS_PRIORITY1 = 0x00000648, 295 Q81_RX_OCTETS_PRIORITY1_LO = 0x0000064C, 296 Q81_RX_OCTETS_PRIORITY2 = 0x00000650, 297 Q81_RX_OCTETS_PRIORITY2_LO = 0x00000654, 298 Q81_RX_OCTETS_PRIORITY3 = 0x00000658, 299 Q81_RX_OCTETS_PRIORITY3_LO = 0x0000065C, 300 Q81_RX_OCTETS_PRIORITY4 = 0x00000660, 301 Q81_RX_OCTETS_PRIORITY4_LO = 0x00000664, 302 Q81_RX_OCTETS_PRIORITY5 = 0x00000668, 303 Q81_RX_OCTETS_PRIORITY5_LO = 0x0000066C, 304 Q81_RX_OCTETS_PRIORITY6 = 0x00000670, 305 Q81_RX_OCTETS_PRIORITY6_LO = 0x00000674, 306 Q81_RX_OCTETS_PRIORITY7 = 0x00000678, 307 Q81_RX_OCTETS_PRIORITY7_LO = 0x0000067C, 308 Q81_TX_PKTS_PRIORITY0 = 0x00000680, 309 Q81_TX_PKTS_PRIORITY0_LO = 0x00000684, 310 Q81_TX_PKTS_PRIORITY1 = 0x00000688, 311 Q81_TX_PKTS_PRIORITY1_LO = 0x0000068C, 312 Q81_TX_PKTS_PRIORITY2 = 0x00000690, 313 Q81_TX_PKTS_PRIORITY2_LO = 0x00000694, 314 Q81_TX_PKTS_PRIORITY3 = 0x00000698, 315 Q81_TX_PKTS_PRIORITY3_LO = 0x0000069C, 316 Q81_TX_PKTS_PRIORITY4 = 0x000006A0, 317 Q81_TX_PKTS_PRIORITY4_LO = 0x000006A4, 318 Q81_TX_PKTS_PRIORITY5 = 0x000006A8, 319 Q81_TX_PKTS_PRIORITY5_LO = 0x000006AC, 320 Q81_TX_PKTS_PRIORITY6 = 0x000006B0, 321 Q81_TX_PKTS_PRIORITY6_LO = 0x000006B4, 322 Q81_TX_PKTS_PRIORITY7 = 0x000006B8, 323 Q81_TX_PKTS_PRIORITY7_LO = 0x000006BC, 324 Q81_TX_OCTETS_PRIORITY0 = 0x000006C0, 325 Q81_TX_OCTETS_PRIORITY0_LO = 0x000006C4, 326 Q81_TX_OCTETS_PRIORITY1 = 0x000006C8, 327 Q81_TX_OCTETS_PRIORITY1_LO = 0x000006CC, 328 Q81_TX_OCTETS_PRIORITY2 = 0x000006D0, 329 Q81_TX_OCTETS_PRIORITY2_LO = 0x000006D4, 330 Q81_TX_OCTETS_PRIORITY3 = 0x000006D8, 331 Q81_TX_OCTETS_PRIORITY3_LO = 0x000006DC, 332 Q81_TX_OCTETS_PRIORITY4 = 0x000006E0, 333 Q81_TX_OCTETS_PRIORITY4_LO = 0x000006E4, 334 Q81_TX_OCTETS_PRIORITY5 = 0x000006E8, 335 Q81_TX_OCTETS_PRIORITY5_LO = 0x000006EC, 336 Q81_TX_OCTETS_PRIORITY6 = 0x000006F0, 337 Q81_TX_OCTETS_PRIORITY6_LO = 0x000006F4, 338 Q81_TX_OCTETS_PRIORITY7 = 0x000006F8, 339 Q81_TX_OCTETS_PRIORITY7_LO = 0x000006FC, 340 Q81_RX_DISCARD_PRIORITY0 = 0x00000700, 341 Q81_RX_DISCARD_PRIORITY0_LO = 0x00000704, 342 Q81_RX_DISCARD_PRIORITY1 = 0x00000708, 343 Q81_RX_DISCARD_PRIORITY1_LO = 0x0000070C, 344 Q81_RX_DISCARD_PRIORITY2 = 0x00000710, 345 Q81_RX_DISCARD_PRIORITY2_LO = 0x00000714, 346 Q81_RX_DISCARD_PRIORITY3 = 0x00000718, 347 Q81_RX_DISCARD_PRIORITY3_LO = 0x0000071C, 348 Q81_RX_DISCARD_PRIORITY4 = 0x00000720, 349 Q81_RX_DISCARD_PRIORITY4_LO = 0x00000724, 350 Q81_RX_DISCARD_PRIORITY5 = 0x00000728, 351 Q81_RX_DISCARD_PRIORITY5_LO = 0x0000072C, 352 Q81_RX_DISCARD_PRIORITY6 = 0x00000730, 353 Q81_RX_DISCARD_PRIORITY6_LO = 0x00000734, 354 Q81_RX_DISCARD_PRIORITY7 = 0x00000738, 355 Q81_RX_DISCARD_PRIORITY7_LO = 0x0000073C 356 }; 357 358 static void 359 qls_mpid_seg_hdr(qls_mpid_seg_hdr_t *seg_hdr, uint32_t seg_num, 360 uint32_t seg_size, unsigned char *desc) 361 { 362 memset(seg_hdr, 0, sizeof(qls_mpid_seg_hdr_t)); 363 364 seg_hdr->cookie = Q81_MPID_COOKIE; 365 seg_hdr->seg_num = seg_num; 366 seg_hdr->seg_size = seg_size; 367 368 memcpy(seg_hdr->desc, desc, (sizeof(seg_hdr->desc))-1); 369 370 return; 371 } 372 373 static int 374 qls_wait_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, uint32_t err_bit) 375 { 376 uint32_t data; 377 int count = 10; 378 379 while (count) { 380 data = READ_REG32(ha, reg); 381 382 if (data & err_bit) 383 return (-1); 384 else if (data & bit) 385 return (0); 386 387 qls_mdelay(__func__, 10); 388 count--; 389 } 390 return (-1); 391 } 392 393 static int 394 qls_rd_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 395 { 396 int ret; 397 398 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 399 Q81_CTL_PROC_ADDR_ERR); 400 401 if (ret) 402 goto exit_qls_rd_mpi_reg; 403 404 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ); 405 406 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 407 Q81_CTL_PROC_ADDR_ERR); 408 409 if (ret) 410 goto exit_qls_rd_mpi_reg; 411 412 *data = READ_REG32(ha, Q81_CTL_PROC_DATA); 413 414 exit_qls_rd_mpi_reg: 415 return (ret); 416 } 417 418 static int 419 qls_wr_mpi_reg(qla_host_t *ha, uint32_t reg, uint32_t data) 420 { 421 int ret = 0; 422 423 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 424 Q81_CTL_PROC_ADDR_ERR); 425 if (ret) 426 goto exit_qls_wr_mpi_reg; 427 428 WRITE_REG32(ha, Q81_CTL_PROC_DATA, data); 429 430 WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg); 431 432 ret = qls_wait_reg_rdy(ha, Q81_CTL_PROC_ADDR, Q81_CTL_PROC_ADDR_RDY, 433 Q81_CTL_PROC_ADDR_ERR); 434 exit_qls_wr_mpi_reg: 435 return (ret); 436 } 437 438 #define Q81_TEST_LOGIC_FUNC_PORT_CONFIG 0x1002 439 #define Q81_INVALID_NUM 0xFFFFFFFF 440 441 #define Q81_NIC1_FUNC_ENABLE 0x00000001 442 #define Q81_NIC1_FUNC_MASK 0x0000000e 443 #define Q81_NIC1_FUNC_SHIFT 1 444 #define Q81_NIC2_FUNC_ENABLE 0x00000010 445 #define Q81_NIC2_FUNC_MASK 0x000000e0 446 #define Q81_NIC2_FUNC_SHIFT 5 447 #define Q81_FUNCTION_SHIFT 6 448 449 static uint32_t 450 qls_get_other_fnum(qla_host_t *ha) 451 { 452 int ret; 453 uint32_t o_func; 454 uint32_t test_logic; 455 uint32_t nic1_fnum = Q81_INVALID_NUM; 456 uint32_t nic2_fnum = Q81_INVALID_NUM; 457 458 ret = qls_rd_mpi_reg(ha, Q81_TEST_LOGIC_FUNC_PORT_CONFIG, &test_logic); 459 if (ret) 460 return(Q81_INVALID_NUM); 461 462 if (test_logic & Q81_NIC1_FUNC_ENABLE) 463 nic1_fnum = (test_logic & Q81_NIC1_FUNC_MASK) >> 464 Q81_NIC1_FUNC_SHIFT; 465 466 if (test_logic & Q81_NIC2_FUNC_ENABLE) 467 nic2_fnum = (test_logic & Q81_NIC2_FUNC_MASK) >> 468 Q81_NIC2_FUNC_SHIFT; 469 470 if (ha->pci_func == 0) 471 o_func = nic2_fnum; 472 else 473 o_func = nic1_fnum; 474 475 return(o_func); 476 } 477 478 static uint32_t 479 qls_rd_ofunc_reg(qla_host_t *ha, uint32_t reg) 480 { 481 uint32_t ofunc; 482 uint32_t data; 483 int ret = 0; 484 485 ofunc = qls_get_other_fnum(ha); 486 487 if (ofunc == Q81_INVALID_NUM) 488 return(Q81_INVALID_NUM); 489 490 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg; 491 492 ret = qls_rd_mpi_reg(ha, reg, &data); 493 494 if (ret != 0) 495 return(Q81_INVALID_NUM); 496 497 return(data); 498 } 499 500 static void 501 qls_wr_ofunc_reg(qla_host_t *ha, uint32_t reg, uint32_t value) 502 { 503 uint32_t ofunc; 504 505 ofunc = qls_get_other_fnum(ha); 506 507 if (ofunc == Q81_INVALID_NUM) 508 return; 509 510 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (ofunc << Q81_FUNCTION_SHIFT) | reg; 511 512 qls_wr_mpi_reg(ha, reg, value); 513 514 return; 515 } 516 517 static int 518 qls_wait_ofunc_reg_rdy(qla_host_t *ha , uint32_t reg, uint32_t bit, 519 uint32_t err_bit) 520 { 521 uint32_t data; 522 int count = 10; 523 524 while (count) { 525 data = qls_rd_ofunc_reg(ha, reg); 526 527 if (data & err_bit) 528 return (-1); 529 else if (data & bit) 530 return (0); 531 532 qls_mdelay(__func__, 10); 533 count--; 534 } 535 return (-1); 536 } 537 538 #define Q81_XG_SERDES_ADDR_RDY BIT_31 539 #define Q81_XG_SERDES_ADDR_READ BIT_30 540 541 static int 542 qls_rd_ofunc_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 543 { 544 int ret; 545 546 /* wait for reg to come ready */ 547 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 548 Q81_XG_SERDES_ADDR_RDY, 0); 549 if (ret) 550 goto exit_qls_rd_ofunc_serdes_reg; 551 552 /* set up for reg read */ 553 qls_wr_ofunc_reg(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 554 (reg | Q81_XG_SERDES_ADDR_READ)); 555 556 /* wait for reg to come ready */ 557 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XG_SERDES_ADDR >> 2), 558 Q81_XG_SERDES_ADDR_RDY, 0); 559 if (ret) 560 goto exit_qls_rd_ofunc_serdes_reg; 561 562 /* get the data */ 563 *data = qls_rd_ofunc_reg(ha, (Q81_CTL_XG_SERDES_DATA >> 2)); 564 565 exit_qls_rd_ofunc_serdes_reg: 566 return ret; 567 } 568 569 #define Q81_XGMAC_ADDR_RDY BIT_31 570 #define Q81_XGMAC_ADDR_R BIT_30 571 #define Q81_XGMAC_ADDR_XME BIT_29 572 573 static int 574 qls_rd_ofunc_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 575 { 576 int ret = 0; 577 578 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2), 579 Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME); 580 581 if (ret) 582 goto exit_qls_rd_ofunc_xgmac_reg; 583 584 qls_wr_ofunc_reg(ha, (Q81_XGMAC_ADDR_RDY >> 2), 585 (reg | Q81_XGMAC_ADDR_R)); 586 587 ret = qls_wait_ofunc_reg_rdy(ha, (Q81_CTL_XGMAC_ADDR >> 2), 588 Q81_XGMAC_ADDR_RDY, Q81_XGMAC_ADDR_XME); 589 if (ret) 590 goto exit_qls_rd_ofunc_xgmac_reg; 591 592 *data = qls_rd_ofunc_reg(ha, Q81_CTL_XGMAC_DATA); 593 594 exit_qls_rd_ofunc_xgmac_reg: 595 return ret; 596 } 597 598 static int 599 qls_rd_serdes_reg(qla_host_t *ha, uint32_t reg, uint32_t *data) 600 { 601 int ret; 602 603 ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR, 604 Q81_XG_SERDES_ADDR_RDY, 0); 605 606 if (ret) 607 goto exit_qls_rd_serdes_reg; 608 609 WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \ 610 (reg | Q81_XG_SERDES_ADDR_READ)); 611 612 ret = qls_wait_reg_rdy(ha, Q81_CTL_XG_SERDES_ADDR, 613 Q81_XG_SERDES_ADDR_RDY, 0); 614 615 if (ret) 616 goto exit_qls_rd_serdes_reg; 617 618 *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA); 619 620 exit_qls_rd_serdes_reg: 621 622 return ret; 623 } 624 625 static void 626 qls_get_both_serdes(qla_host_t *ha, uint32_t addr, uint32_t *dptr, 627 uint32_t *ind_ptr, uint32_t dvalid, uint32_t ind_valid) 628 { 629 int ret = -1; 630 631 if (dvalid) 632 ret = qls_rd_serdes_reg(ha, addr, dptr); 633 634 if (ret) 635 *dptr = Q81_BAD_DATA; 636 637 ret = -1; 638 639 if(ind_valid) 640 ret = qls_rd_ofunc_serdes_reg(ha, addr, ind_ptr); 641 642 if (ret) 643 *ind_ptr = Q81_BAD_DATA; 644 } 645 646 #define Q81_XFI1_POWERED_UP 0x00000005 647 #define Q81_XFI2_POWERED_UP 0x0000000A 648 #define Q81_XAUI_POWERED_UP 0x00000001 649 650 static int 651 qls_rd_serdes_regs(qla_host_t *ha, qls_mpi_coredump_t *mpi_dump) 652 { 653 int ret; 654 uint32_t xfi_d_valid, xfi_ind_valid, xaui_d_valid, xaui_ind_valid; 655 uint32_t temp, xaui_reg, i; 656 uint32_t *dptr, *indptr; 657 658 xfi_d_valid = xfi_ind_valid = xaui_d_valid = xaui_ind_valid = 0; 659 660 xaui_reg = 0x800; 661 662 ret = qls_rd_ofunc_serdes_reg(ha, xaui_reg, &temp); 663 if (ret) 664 temp = 0; 665 666 if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP) 667 xaui_ind_valid = 1; 668 669 ret = qls_rd_serdes_reg(ha, xaui_reg, &temp); 670 if (ret) 671 temp = 0; 672 673 if ((temp & Q81_XAUI_POWERED_UP) == Q81_XAUI_POWERED_UP) 674 xaui_d_valid = 1; 675 676 ret = qls_rd_serdes_reg(ha, 0x1E06, &temp); 677 if (ret) 678 temp = 0; 679 680 if ((temp & Q81_XFI1_POWERED_UP) == Q81_XFI1_POWERED_UP) { 681 if (ha->pci_func & 1) 682 xfi_ind_valid = 1; /* NIC 2, so the indirect 683 (NIC1) xfi is up*/ 684 else 685 xfi_d_valid = 1; 686 } 687 688 if((temp & Q81_XFI2_POWERED_UP) == Q81_XFI2_POWERED_UP) { 689 if(ha->pci_func & 1) 690 xfi_d_valid = 1; /* NIC 2, so the indirect (NIC1) 691 xfi is up */ 692 else 693 xfi_ind_valid = 1; 694 } 695 696 if (ha->pci_func & 1) { 697 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an); 698 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an); 699 } else { 700 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_an); 701 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_an); 702 } 703 704 for (i = 0; i <= 0x000000034; i += 4, dptr ++, indptr ++) { 705 qls_get_both_serdes(ha, i, dptr, indptr, 706 xaui_d_valid, xaui_ind_valid); 707 } 708 709 if (ha->pci_func & 1) { 710 dptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs); 711 indptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs); 712 } else { 713 dptr = (uint32_t *)(&mpi_dump->serdes1_xaui_hss_pcs); 714 indptr = (uint32_t *)(&mpi_dump->serdes2_xaui_hss_pcs); 715 } 716 717 for (i = 0x800; i <= 0x880; i += 4, dptr ++, indptr ++) { 718 qls_get_both_serdes(ha, i, dptr, indptr, 719 xaui_d_valid, xaui_ind_valid); 720 } 721 722 if (ha->pci_func & 1) { 723 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an); 724 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an); 725 } else { 726 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_an); 727 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_an); 728 } 729 730 for (i = 0x1000; i <= 0x1034; i += 4, dptr ++, indptr ++) { 731 qls_get_both_serdes(ha, i, dptr, indptr, 732 xfi_d_valid, xfi_ind_valid); 733 } 734 735 if (ha->pci_func & 1) { 736 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train); 737 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train); 738 } else { 739 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_train); 740 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_train); 741 } 742 743 for (i = 0x1050; i <= 0x107c; i += 4, dptr ++, indptr ++) { 744 qls_get_both_serdes(ha, i, dptr, indptr, 745 xfi_d_valid, xfi_ind_valid); 746 } 747 748 if (ha->pci_func & 1) { 749 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs); 750 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs); 751 } else { 752 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pcs); 753 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pcs); 754 } 755 756 for (i = 0x1800; i <= 0x1838; i += 4, dptr++, indptr ++) { 757 qls_get_both_serdes(ha, i, dptr, indptr, 758 xfi_d_valid, xfi_ind_valid); 759 } 760 761 if (ha->pci_func & 1) { 762 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx); 763 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx); 764 } else { 765 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_tx); 766 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_tx); 767 } 768 769 for (i = 0x1c00; i <= 0x1c1f; i++, dptr ++, indptr ++) { 770 qls_get_both_serdes(ha, i, dptr, indptr, 771 xfi_d_valid, xfi_ind_valid); 772 } 773 774 if (ha->pci_func & 1) { 775 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx); 776 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx); 777 } else { 778 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_rx); 779 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_rx); 780 } 781 782 for (i = 0x1c40; i <= 0x1c5f; i++, dptr ++, indptr ++) { 783 qls_get_both_serdes(ha, i, dptr, indptr, 784 xfi_d_valid, xfi_ind_valid); 785 } 786 787 if (ha->pci_func & 1) { 788 dptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll); 789 indptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll); 790 } else { 791 dptr = (uint32_t *)(&mpi_dump->serdes1_xfi_hss_pll); 792 indptr = (uint32_t *)(&mpi_dump->serdes2_xfi_hss_pll); 793 } 794 795 for (i = 0x1e00; i <= 0x1e1f; i++, dptr ++, indptr ++) { 796 qls_get_both_serdes(ha, i, dptr, indptr, 797 xfi_d_valid, xfi_ind_valid); 798 } 799 800 return(0); 801 } 802 803 static int 804 qls_unpause_mpi_risc(qla_host_t *ha) 805 { 806 uint32_t data; 807 808 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 809 810 if (!(data & Q81_CTL_HCS_RISC_PAUSED)) 811 return -1; 812 813 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 814 Q81_CTL_HCS_CMD_CLR_RISC_PAUSE); 815 816 return 0; 817 } 818 819 static int 820 qls_pause_mpi_risc(qla_host_t *ha) 821 { 822 uint32_t data; 823 int count = 10; 824 825 WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \ 826 Q81_CTL_HCS_CMD_SET_RISC_PAUSE); 827 828 do { 829 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS); 830 831 if (data & Q81_CTL_HCS_RISC_PAUSED) 832 break; 833 834 qls_mdelay(__func__, 10); 835 836 count--; 837 838 } while (count); 839 840 return ((count == 0) ? -1 : 0); 841 } 842 843 static void 844 qls_get_intr_states(qla_host_t *ha, uint32_t *buf) 845 { 846 int i; 847 848 for (i = 0; i < MAX_RX_RINGS; i++, buf++) { 849 WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i)); 850 851 *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE); 852 } 853 } 854 855 static int 856 qls_rd_xgmac_reg(qla_host_t *ha, uint32_t reg, uint32_t*data) 857 { 858 int ret = 0; 859 860 ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY, 861 Q81_XGMAC_ADDR_XME); 862 if (ret) 863 goto exit_qls_rd_xgmac_reg; 864 865 WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R)); 866 867 ret = qls_wait_reg_rdy(ha, Q81_CTL_XGMAC_ADDR, Q81_XGMAC_ADDR_RDY, 868 Q81_XGMAC_ADDR_XME); 869 if (ret) 870 goto exit_qls_rd_xgmac_reg; 871 872 *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA); 873 874 exit_qls_rd_xgmac_reg: 875 return ret; 876 } 877 878 static int 879 qls_rd_xgmac_regs(qla_host_t *ha, uint32_t *buf, uint32_t o_func) 880 { 881 int ret = 0; 882 int i; 883 884 for (i = 0; i < Q81_XGMAC_REGISTER_END; i += 4, buf ++) { 885 switch (i) { 886 case Q81_PAUSE_SRC_LO : 887 case Q81_PAUSE_SRC_HI : 888 case Q81_GLOBAL_CFG : 889 case Q81_TX_CFG : 890 case Q81_RX_CFG : 891 case Q81_FLOW_CTL : 892 case Q81_PAUSE_OPCODE : 893 case Q81_PAUSE_TIMER : 894 case Q81_PAUSE_FRM_DEST_LO : 895 case Q81_PAUSE_FRM_DEST_HI : 896 case Q81_MAC_TX_PARAMS : 897 case Q81_MAC_RX_PARAMS : 898 case Q81_MAC_SYS_INT : 899 case Q81_MAC_SYS_INT_MASK : 900 case Q81_MAC_MGMT_INT : 901 case Q81_MAC_MGMT_IN_MASK : 902 case Q81_EXT_ARB_MODE : 903 case Q81_TX_PKTS : 904 case Q81_TX_PKTS_LO : 905 case Q81_TX_BYTES : 906 case Q81_TX_BYTES_LO : 907 case Q81_TX_MCAST_PKTS : 908 case Q81_TX_MCAST_PKTS_LO : 909 case Q81_TX_BCAST_PKTS : 910 case Q81_TX_BCAST_PKTS_LO : 911 case Q81_TX_UCAST_PKTS : 912 case Q81_TX_UCAST_PKTS_LO : 913 case Q81_TX_CTL_PKTS : 914 case Q81_TX_CTL_PKTS_LO : 915 case Q81_TX_PAUSE_PKTS : 916 case Q81_TX_PAUSE_PKTS_LO : 917 case Q81_TX_64_PKT : 918 case Q81_TX_64_PKT_LO : 919 case Q81_TX_65_TO_127_PKT : 920 case Q81_TX_65_TO_127_PKT_LO : 921 case Q81_TX_128_TO_255_PKT : 922 case Q81_TX_128_TO_255_PKT_LO : 923 case Q81_TX_256_511_PKT : 924 case Q81_TX_256_511_PKT_LO : 925 case Q81_TX_512_TO_1023_PKT : 926 case Q81_TX_512_TO_1023_PKT_LO : 927 case Q81_TX_1024_TO_1518_PKT : 928 case Q81_TX_1024_TO_1518_PKT_LO : 929 case Q81_TX_1519_TO_MAX_PKT : 930 case Q81_TX_1519_TO_MAX_PKT_LO : 931 case Q81_TX_UNDERSIZE_PKT : 932 case Q81_TX_UNDERSIZE_PKT_LO : 933 case Q81_TX_OVERSIZE_PKT : 934 case Q81_TX_OVERSIZE_PKT_LO : 935 case Q81_RX_HALF_FULL_DET : 936 case Q81_TX_HALF_FULL_DET_LO : 937 case Q81_RX_OVERFLOW_DET : 938 case Q81_TX_OVERFLOW_DET_LO : 939 case Q81_RX_HALF_FULL_MASK : 940 case Q81_TX_HALF_FULL_MASK_LO : 941 case Q81_RX_OVERFLOW_MASK : 942 case Q81_TX_OVERFLOW_MASK_LO : 943 case Q81_STAT_CNT_CTL : 944 case Q81_AUX_RX_HALF_FULL_DET : 945 case Q81_AUX_TX_HALF_FULL_DET : 946 case Q81_AUX_RX_OVERFLOW_DET : 947 case Q81_AUX_TX_OVERFLOW_DET : 948 case Q81_AUX_RX_HALF_FULL_MASK : 949 case Q81_AUX_TX_HALF_FULL_MASK : 950 case Q81_AUX_RX_OVERFLOW_MASK : 951 case Q81_AUX_TX_OVERFLOW_MASK : 952 case Q81_RX_BYTES : 953 case Q81_RX_BYTES_LO : 954 case Q81_RX_BYTES_OK : 955 case Q81_RX_BYTES_OK_LO : 956 case Q81_RX_PKTS : 957 case Q81_RX_PKTS_LO : 958 case Q81_RX_PKTS_OK : 959 case Q81_RX_PKTS_OK_LO : 960 case Q81_RX_BCAST_PKTS : 961 case Q81_RX_BCAST_PKTS_LO : 962 case Q81_RX_MCAST_PKTS : 963 case Q81_RX_MCAST_PKTS_LO : 964 case Q81_RX_UCAST_PKTS : 965 case Q81_RX_UCAST_PKTS_LO : 966 case Q81_RX_UNDERSIZE_PKTS : 967 case Q81_RX_UNDERSIZE_PKTS_LO : 968 case Q81_RX_OVERSIZE_PKTS : 969 case Q81_RX_OVERSIZE_PKTS_LO : 970 case Q81_RX_JABBER_PKTS : 971 case Q81_RX_JABBER_PKTS_LO : 972 case Q81_RX_UNDERSIZE_FCERR_PKTS : 973 case Q81_RX_UNDERSIZE_FCERR_PKTS_LO : 974 case Q81_RX_DROP_EVENTS : 975 case Q81_RX_DROP_EVENTS_LO : 976 case Q81_RX_FCERR_PKTS : 977 case Q81_RX_FCERR_PKTS_LO : 978 case Q81_RX_ALIGN_ERR : 979 case Q81_RX_ALIGN_ERR_LO : 980 case Q81_RX_SYMBOL_ERR : 981 case Q81_RX_SYMBOL_ERR_LO : 982 case Q81_RX_MAC_ERR : 983 case Q81_RX_MAC_ERR_LO : 984 case Q81_RX_CTL_PKTS : 985 case Q81_RX_CTL_PKTS_LO : 986 case Q81_RX_PAUSE_PKTS : 987 case Q81_RX_PAUSE_PKTS_LO : 988 case Q81_RX_64_PKTS : 989 case Q81_RX_64_PKTS_LO : 990 case Q81_RX_65_TO_127_PKTS : 991 case Q81_RX_65_TO_127_PKTS_LO : 992 case Q81_RX_128_255_PKTS : 993 case Q81_RX_128_255_PKTS_LO : 994 case Q81_RX_256_511_PKTS : 995 case Q81_RX_256_511_PKTS_LO : 996 case Q81_RX_512_TO_1023_PKTS : 997 case Q81_RX_512_TO_1023_PKTS_LO : 998 case Q81_RX_1024_TO_1518_PKTS : 999 case Q81_RX_1024_TO_1518_PKTS_LO : 1000 case Q81_RX_1519_TO_MAX_PKTS : 1001 case Q81_RX_1519_TO_MAX_PKTS_LO : 1002 case Q81_RX_LEN_ERR_PKTS : 1003 case Q81_RX_LEN_ERR_PKTS_LO : 1004 case Q81_MDIO_TX_DATA : 1005 case Q81_MDIO_RX_DATA : 1006 case Q81_MDIO_CMD : 1007 case Q81_MDIO_PHY_ADDR : 1008 case Q81_MDIO_PORT : 1009 case Q81_MDIO_STATUS : 1010 case Q81_TX_CBFC_PAUSE_FRAMES0 : 1011 case Q81_TX_CBFC_PAUSE_FRAMES0_LO : 1012 case Q81_TX_CBFC_PAUSE_FRAMES1 : 1013 case Q81_TX_CBFC_PAUSE_FRAMES1_LO : 1014 case Q81_TX_CBFC_PAUSE_FRAMES2 : 1015 case Q81_TX_CBFC_PAUSE_FRAMES2_LO : 1016 case Q81_TX_CBFC_PAUSE_FRAMES3 : 1017 case Q81_TX_CBFC_PAUSE_FRAMES3_LO : 1018 case Q81_TX_CBFC_PAUSE_FRAMES4 : 1019 case Q81_TX_CBFC_PAUSE_FRAMES4_LO : 1020 case Q81_TX_CBFC_PAUSE_FRAMES5 : 1021 case Q81_TX_CBFC_PAUSE_FRAMES5_LO : 1022 case Q81_TX_CBFC_PAUSE_FRAMES6 : 1023 case Q81_TX_CBFC_PAUSE_FRAMES6_LO : 1024 case Q81_TX_CBFC_PAUSE_FRAMES7 : 1025 case Q81_TX_CBFC_PAUSE_FRAMES7_LO : 1026 case Q81_TX_FCOE_PKTS : 1027 case Q81_TX_FCOE_PKTS_LO : 1028 case Q81_TX_MGMT_PKTS : 1029 case Q81_TX_MGMT_PKTS_LO : 1030 case Q81_RX_CBFC_PAUSE_FRAMES0 : 1031 case Q81_RX_CBFC_PAUSE_FRAMES0_LO : 1032 case Q81_RX_CBFC_PAUSE_FRAMES1 : 1033 case Q81_RX_CBFC_PAUSE_FRAMES1_LO : 1034 case Q81_RX_CBFC_PAUSE_FRAMES2 : 1035 case Q81_RX_CBFC_PAUSE_FRAMES2_LO : 1036 case Q81_RX_CBFC_PAUSE_FRAMES3 : 1037 case Q81_RX_CBFC_PAUSE_FRAMES3_LO : 1038 case Q81_RX_CBFC_PAUSE_FRAMES4 : 1039 case Q81_RX_CBFC_PAUSE_FRAMES4_LO : 1040 case Q81_RX_CBFC_PAUSE_FRAMES5 : 1041 case Q81_RX_CBFC_PAUSE_FRAMES5_LO : 1042 case Q81_RX_CBFC_PAUSE_FRAMES6 : 1043 case Q81_RX_CBFC_PAUSE_FRAMES6_LO : 1044 case Q81_RX_CBFC_PAUSE_FRAMES7 : 1045 case Q81_RX_CBFC_PAUSE_FRAMES7_LO : 1046 case Q81_RX_FCOE_PKTS : 1047 case Q81_RX_FCOE_PKTS_LO : 1048 case Q81_RX_MGMT_PKTS : 1049 case Q81_RX_MGMT_PKTS_LO : 1050 case Q81_RX_NIC_FIFO_DROP : 1051 case Q81_RX_NIC_FIFO_DROP_LO : 1052 case Q81_RX_FCOE_FIFO_DROP : 1053 case Q81_RX_FCOE_FIFO_DROP_LO : 1054 case Q81_RX_MGMT_FIFO_DROP : 1055 case Q81_RX_MGMT_FIFO_DROP_LO : 1056 case Q81_RX_PKTS_PRIORITY0 : 1057 case Q81_RX_PKTS_PRIORITY0_LO : 1058 case Q81_RX_PKTS_PRIORITY1 : 1059 case Q81_RX_PKTS_PRIORITY1_LO : 1060 case Q81_RX_PKTS_PRIORITY2 : 1061 case Q81_RX_PKTS_PRIORITY2_LO : 1062 case Q81_RX_PKTS_PRIORITY3 : 1063 case Q81_RX_PKTS_PRIORITY3_LO : 1064 case Q81_RX_PKTS_PRIORITY4 : 1065 case Q81_RX_PKTS_PRIORITY4_LO : 1066 case Q81_RX_PKTS_PRIORITY5 : 1067 case Q81_RX_PKTS_PRIORITY5_LO : 1068 case Q81_RX_PKTS_PRIORITY6 : 1069 case Q81_RX_PKTS_PRIORITY6_LO : 1070 case Q81_RX_PKTS_PRIORITY7 : 1071 case Q81_RX_PKTS_PRIORITY7_LO : 1072 case Q81_RX_OCTETS_PRIORITY0 : 1073 case Q81_RX_OCTETS_PRIORITY0_LO : 1074 case Q81_RX_OCTETS_PRIORITY1 : 1075 case Q81_RX_OCTETS_PRIORITY1_LO : 1076 case Q81_RX_OCTETS_PRIORITY2 : 1077 case Q81_RX_OCTETS_PRIORITY2_LO : 1078 case Q81_RX_OCTETS_PRIORITY3 : 1079 case Q81_RX_OCTETS_PRIORITY3_LO : 1080 case Q81_RX_OCTETS_PRIORITY4 : 1081 case Q81_RX_OCTETS_PRIORITY4_LO : 1082 case Q81_RX_OCTETS_PRIORITY5 : 1083 case Q81_RX_OCTETS_PRIORITY5_LO : 1084 case Q81_RX_OCTETS_PRIORITY6 : 1085 case Q81_RX_OCTETS_PRIORITY6_LO : 1086 case Q81_RX_OCTETS_PRIORITY7 : 1087 case Q81_RX_OCTETS_PRIORITY7_LO : 1088 case Q81_TX_PKTS_PRIORITY0 : 1089 case Q81_TX_PKTS_PRIORITY0_LO : 1090 case Q81_TX_PKTS_PRIORITY1 : 1091 case Q81_TX_PKTS_PRIORITY1_LO : 1092 case Q81_TX_PKTS_PRIORITY2 : 1093 case Q81_TX_PKTS_PRIORITY2_LO : 1094 case Q81_TX_PKTS_PRIORITY3 : 1095 case Q81_TX_PKTS_PRIORITY3_LO : 1096 case Q81_TX_PKTS_PRIORITY4 : 1097 case Q81_TX_PKTS_PRIORITY4_LO : 1098 case Q81_TX_PKTS_PRIORITY5 : 1099 case Q81_TX_PKTS_PRIORITY5_LO : 1100 case Q81_TX_PKTS_PRIORITY6 : 1101 case Q81_TX_PKTS_PRIORITY6_LO : 1102 case Q81_TX_PKTS_PRIORITY7 : 1103 case Q81_TX_PKTS_PRIORITY7_LO : 1104 case Q81_TX_OCTETS_PRIORITY0 : 1105 case Q81_TX_OCTETS_PRIORITY0_LO : 1106 case Q81_TX_OCTETS_PRIORITY1 : 1107 case Q81_TX_OCTETS_PRIORITY1_LO : 1108 case Q81_TX_OCTETS_PRIORITY2 : 1109 case Q81_TX_OCTETS_PRIORITY2_LO : 1110 case Q81_TX_OCTETS_PRIORITY3 : 1111 case Q81_TX_OCTETS_PRIORITY3_LO : 1112 case Q81_TX_OCTETS_PRIORITY4 : 1113 case Q81_TX_OCTETS_PRIORITY4_LO : 1114 case Q81_TX_OCTETS_PRIORITY5 : 1115 case Q81_TX_OCTETS_PRIORITY5_LO : 1116 case Q81_TX_OCTETS_PRIORITY6 : 1117 case Q81_TX_OCTETS_PRIORITY6_LO : 1118 case Q81_TX_OCTETS_PRIORITY7 : 1119 case Q81_TX_OCTETS_PRIORITY7_LO : 1120 case Q81_RX_DISCARD_PRIORITY0 : 1121 case Q81_RX_DISCARD_PRIORITY0_LO : 1122 case Q81_RX_DISCARD_PRIORITY1 : 1123 case Q81_RX_DISCARD_PRIORITY1_LO : 1124 case Q81_RX_DISCARD_PRIORITY2 : 1125 case Q81_RX_DISCARD_PRIORITY2_LO : 1126 case Q81_RX_DISCARD_PRIORITY3 : 1127 case Q81_RX_DISCARD_PRIORITY3_LO : 1128 case Q81_RX_DISCARD_PRIORITY4 : 1129 case Q81_RX_DISCARD_PRIORITY4_LO : 1130 case Q81_RX_DISCARD_PRIORITY5 : 1131 case Q81_RX_DISCARD_PRIORITY5_LO : 1132 case Q81_RX_DISCARD_PRIORITY6 : 1133 case Q81_RX_DISCARD_PRIORITY6_LO : 1134 case Q81_RX_DISCARD_PRIORITY7 : 1135 case Q81_RX_DISCARD_PRIORITY7_LO : 1136 1137 if (o_func) 1138 ret = qls_rd_ofunc_xgmac_reg(ha, 1139 i, buf); 1140 else 1141 ret = qls_rd_xgmac_reg(ha, i, buf); 1142 1143 if (ret) 1144 *buf = Q81_BAD_DATA; 1145 1146 break; 1147 1148 default: 1149 break; 1150 } 1151 } 1152 return 0; 1153 } 1154 1155 static int 1156 qls_get_mpi_regs(qla_host_t *ha, uint32_t *buf, uint32_t offset, uint32_t count) 1157 { 1158 int i, ret = 0; 1159 1160 for (i = 0; i < count; i++, buf++) { 1161 ret = qls_rd_mpi_reg(ha, (offset + i), buf); 1162 1163 if (ret) 1164 return ret; 1165 } 1166 1167 return (ret); 1168 } 1169 1170 static int 1171 qls_get_mpi_shadow_regs(qla_host_t *ha, uint32_t *buf) 1172 { 1173 uint32_t i; 1174 int ret; 1175 1176 #define Q81_RISC_124 0x0000007c 1177 #define Q81_RISC_127 0x0000007f 1178 #define Q81_SHADOW_OFFSET 0xb0000000 1179 1180 for (i = 0; i < Q81_MPI_CORE_SH_REGS_CNT; i++, buf++) { 1181 ret = qls_wr_mpi_reg(ha, 1182 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_124), 1183 (Q81_SHADOW_OFFSET | i << 20)); 1184 if (ret) 1185 goto exit_qls_get_mpi_shadow_regs; 1186 1187 ret = qls_mpi_risc_rd_reg(ha, 1188 (Q81_CTL_PROC_ADDR_RISC_INT_REG | Q81_RISC_127), 1189 buf); 1190 if (ret) 1191 goto exit_qls_get_mpi_shadow_regs; 1192 } 1193 1194 exit_qls_get_mpi_shadow_regs: 1195 return ret; 1196 } 1197 1198 #define SYS_CLOCK (0x00) 1199 #define PCI_CLOCK (0x80) 1200 #define FC_CLOCK (0x140) 1201 #define XGM_CLOCK (0x180) 1202 1203 #define Q81_ADDRESS_REGISTER_ENABLE 0x00010000 1204 #define Q81_UP 0x00008000 1205 #define Q81_MAX_MUX 0x40 1206 #define Q81_MAX_MODULES 0x1F 1207 1208 static uint32_t * 1209 qls_get_probe(qla_host_t *ha, uint32_t clock, uint8_t *valid, uint32_t *buf) 1210 { 1211 uint32_t module, mux_sel, probe, lo_val, hi_val; 1212 1213 for (module = 0; module < Q81_MAX_MODULES; module ++) { 1214 if (valid[module]) { 1215 for (mux_sel = 0; mux_sel < Q81_MAX_MUX; mux_sel++) { 1216 probe = clock | Q81_ADDRESS_REGISTER_ENABLE | 1217 mux_sel | (module << 9); 1218 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1219 probe); 1220 1221 lo_val = READ_REG32(ha,\ 1222 Q81_CTL_XG_PROBE_MUX_DATA); 1223 1224 if (mux_sel == 0) { 1225 *buf = probe; 1226 buf ++; 1227 } 1228 1229 probe |= Q81_UP; 1230 1231 WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\ 1232 probe); 1233 hi_val = READ_REG32(ha,\ 1234 Q81_CTL_XG_PROBE_MUX_DATA); 1235 1236 *buf = lo_val; 1237 buf++; 1238 *buf = hi_val; 1239 buf++; 1240 } 1241 } 1242 } 1243 1244 return(buf); 1245 } 1246 1247 static int 1248 qls_get_probe_dump(qla_host_t *ha, uint32_t *buf) 1249 { 1250 1251 uint8_t sys_clock_valid_modules[0x20] = { 1252 1, // 0x00 1253 1, // 0x01 1254 1, // 0x02 1255 0, // 0x03 1256 1, // 0x04 1257 1, // 0x05 1258 1, // 0x06 1259 1, // 0x07 1260 1, // 0x08 1261 1, // 0x09 1262 1, // 0x0A 1263 1, // 0x0B 1264 1, // 0x0C 1265 1, // 0x0D 1266 1, // 0x0E 1267 0, // 0x0F 1268 1, // 0x10 1269 1, // 0x11 1270 1, // 0x12 1271 1, // 0x13 1272 0, // 0x14 1273 0, // 0x15 1274 0, // 0x16 1275 0, // 0x17 1276 0, // 0x18 1277 0, // 0x19 1278 0, // 0x1A 1279 0, // 0x1B 1280 0, // 0x1C 1281 0, // 0x1D 1282 0, // 0x1E 1283 0 // 0x1F 1284 }; 1285 1286 uint8_t pci_clock_valid_modules[0x20] = { 1287 1, // 0x00 1288 0, // 0x01 1289 0, // 0x02 1290 0, // 0x03 1291 0, // 0x04 1292 0, // 0x05 1293 1, // 0x06 1294 1, // 0x07 1295 0, // 0x08 1296 0, // 0x09 1297 0, // 0x0A 1298 0, // 0x0B 1299 0, // 0x0C 1300 0, // 0x0D 1301 1, // 0x0E 1302 0, // 0x0F 1303 0, // 0x10 1304 0, // 0x11 1305 0, // 0x12 1306 0, // 0x13 1307 0, // 0x14 1308 0, // 0x15 1309 0, // 0x16 1310 0, // 0x17 1311 0, // 0x18 1312 0, // 0x19 1313 0, // 0x1A 1314 0, // 0x1B 1315 0, // 0x1C 1316 0, // 0x1D 1317 0, // 0x1E 1318 0 // 0x1F 1319 }; 1320 1321 uint8_t xgm_clock_valid_modules[0x20] = { 1322 1, // 0x00 1323 0, // 0x01 1324 0, // 0x02 1325 1, // 0x03 1326 0, // 0x04 1327 0, // 0x05 1328 0, // 0x06 1329 0, // 0x07 1330 1, // 0x08 1331 1, // 0x09 1332 0, // 0x0A 1333 0, // 0x0B 1334 1, // 0x0C 1335 1, // 0x0D 1336 1, // 0x0E 1337 0, // 0x0F 1338 1, // 0x10 1339 1, // 0x11 1340 0, // 0x12 1341 0, // 0x13 1342 0, // 0x14 1343 0, // 0x15 1344 0, // 0x16 1345 0, // 0x17 1346 0, // 0x18 1347 0, // 0x19 1348 0, // 0x1A 1349 0, // 0x1B 1350 0, // 0x1C 1351 0, // 0x1D 1352 0, // 0x1E 1353 0 // 0x1F 1354 }; 1355 1356 uint8_t fc_clock_valid_modules[0x20] = { 1357 1, // 0x00 1358 0, // 0x01 1359 0, // 0x02 1360 0, // 0x03 1361 0, // 0x04 1362 0, // 0x05 1363 0, // 0x06 1364 0, // 0x07 1365 0, // 0x08 1366 0, // 0x09 1367 0, // 0x0A 1368 0, // 0x0B 1369 1, // 0x0C 1370 1, // 0x0D 1371 0, // 0x0E 1372 0, // 0x0F 1373 0, // 0x10 1374 0, // 0x11 1375 0, // 0x12 1376 0, // 0x13 1377 0, // 0x14 1378 0, // 0x15 1379 0, // 0x16 1380 0, // 0x17 1381 0, // 0x18 1382 0, // 0x19 1383 0, // 0x1A 1384 0, // 0x1B 1385 0, // 0x1C 1386 0, // 0x1D 1387 0, // 0x1E 1388 0 // 0x1F 1389 }; 1390 1391 qls_wr_mpi_reg(ha, 0x100e, 0x18a20000); 1392 1393 buf = qls_get_probe(ha, SYS_CLOCK, sys_clock_valid_modules, buf); 1394 1395 buf = qls_get_probe(ha, PCI_CLOCK, pci_clock_valid_modules, buf); 1396 1397 buf = qls_get_probe(ha, XGM_CLOCK, xgm_clock_valid_modules, buf); 1398 1399 buf = qls_get_probe(ha, FC_CLOCK, fc_clock_valid_modules, buf); 1400 1401 return(0); 1402 } 1403 1404 static void 1405 qls_get_ridx_registers(qla_host_t *ha, uint32_t *buf) 1406 { 1407 uint32_t type, idx, idx_max; 1408 uint32_t r_idx; 1409 uint32_t r_data; 1410 uint32_t val; 1411 1412 for (type = 0; type < 4; type ++) { 1413 if (type < 2) 1414 idx_max = 8; 1415 else 1416 idx_max = 16; 1417 1418 for (idx = 0; idx < idx_max; idx ++) { 1419 val = 0x04000000 | (type << 16) | (idx << 8); 1420 WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val); 1421 1422 r_idx = 0; 1423 while ((r_idx & 0x40000000) == 0) 1424 r_idx = READ_REG32(ha, Q81_CTL_ROUTING_INDEX); 1425 1426 r_data = READ_REG32(ha, Q81_CTL_ROUTING_DATA); 1427 1428 *buf = type; 1429 buf ++; 1430 *buf = idx; 1431 buf ++; 1432 *buf = r_idx; 1433 buf ++; 1434 *buf = r_data; 1435 buf ++; 1436 } 1437 } 1438 } 1439 1440 static void 1441 qls_get_mac_proto_regs(qla_host_t *ha, uint32_t* buf) 1442 { 1443 1444 #define Q81_RS_AND_ADR 0x06000000 1445 #define Q81_RS_ONLY 0x04000000 1446 #define Q81_NUM_TYPES 10 1447 1448 uint32_t result_index, result_data; 1449 uint32_t type; 1450 uint32_t index; 1451 uint32_t offset; 1452 uint32_t val; 1453 uint32_t initial_val; 1454 uint32_t max_index; 1455 uint32_t max_offset; 1456 1457 for (type = 0; type < Q81_NUM_TYPES; type ++) { 1458 switch (type) { 1459 case 0: // CAM 1460 initial_val = Q81_RS_AND_ADR; 1461 max_index = 512; 1462 max_offset = 3; 1463 break; 1464 1465 case 1: // Multicast MAC Address 1466 initial_val = Q81_RS_ONLY; 1467 max_index = 32; 1468 max_offset = 2; 1469 break; 1470 1471 case 2: // VLAN filter mask 1472 case 3: // MC filter mask 1473 initial_val = Q81_RS_ONLY; 1474 max_index = 4096; 1475 max_offset = 1; 1476 break; 1477 1478 case 4: // FC MAC addresses 1479 initial_val = Q81_RS_ONLY; 1480 max_index = 4; 1481 max_offset = 2; 1482 break; 1483 1484 case 5: // Mgmt MAC addresses 1485 initial_val = Q81_RS_ONLY; 1486 max_index = 8; 1487 max_offset = 2; 1488 break; 1489 1490 case 6: // Mgmt VLAN addresses 1491 initial_val = Q81_RS_ONLY; 1492 max_index = 16; 1493 max_offset = 1; 1494 break; 1495 1496 case 7: // Mgmt IPv4 address 1497 initial_val = Q81_RS_ONLY; 1498 max_index = 4; 1499 max_offset = 1; 1500 break; 1501 1502 case 8: // Mgmt IPv6 address 1503 initial_val = Q81_RS_ONLY; 1504 max_index = 4; 1505 max_offset = 4; 1506 break; 1507 1508 case 9: // Mgmt TCP/UDP Dest port 1509 initial_val = Q81_RS_ONLY; 1510 max_index = 4; 1511 max_offset = 1; 1512 break; 1513 1514 default: 1515 printf("Bad type!!! 0x%08x\n", type); 1516 max_index = 0; 1517 max_offset = 0; 1518 break; 1519 } 1520 1521 for (index = 0; index < max_index; index ++) { 1522 for (offset = 0; offset < max_offset; offset ++) { 1523 val = initial_val | (type << 16) | 1524 (index << 4) | (offset); 1525 1526 WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX,\ 1527 val); 1528 1529 result_index = 0; 1530 1531 while ((result_index & 0x40000000) == 0) 1532 result_index = 1533 READ_REG32(ha, \ 1534 Q81_CTL_MAC_PROTO_ADDR_INDEX); 1535 1536 result_data = READ_REG32(ha,\ 1537 Q81_CTL_MAC_PROTO_ADDR_DATA); 1538 1539 *buf = result_index; 1540 buf ++; 1541 1542 *buf = result_data; 1543 buf ++; 1544 } 1545 } 1546 } 1547 } 1548 1549 static int 1550 qls_get_ets_regs(qla_host_t *ha, uint32_t *buf) 1551 { 1552 int ret = 0; 1553 int i; 1554 1555 for(i = 0; i < 8; i ++, buf ++) { 1556 WRITE_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD, \ 1557 ((i << 29) | 0x08000000)); 1558 *buf = READ_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD); 1559 } 1560 1561 for(i = 0; i < 2; i ++, buf ++) { 1562 WRITE_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD, \ 1563 ((i << 29) | 0x08000000)); 1564 *buf = READ_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD); 1565 } 1566 1567 return ret; 1568 } 1569 1570 int 1571 qls_mpi_core_dump(qla_host_t *ha) 1572 { 1573 int ret; 1574 int i; 1575 uint32_t reg, reg_val; 1576 1577 qls_mpi_coredump_t *mpi_dump = &ql_mpi_coredump; 1578 1579 ret = qls_pause_mpi_risc(ha); 1580 if (ret) { 1581 printf("Failed RISC pause. Status = 0x%.08x\n",ret); 1582 return(-1); 1583 } 1584 1585 memset(&(mpi_dump->mpi_global_header), 0, 1586 sizeof(qls_mpid_glbl_hdr_t)); 1587 1588 mpi_dump->mpi_global_header.cookie = Q81_MPID_COOKIE; 1589 mpi_dump->mpi_global_header.hdr_size = 1590 sizeof(qls_mpid_glbl_hdr_t); 1591 mpi_dump->mpi_global_header.img_size = 1592 sizeof(qls_mpi_coredump_t); 1593 1594 memcpy(mpi_dump->mpi_global_header.id, "MPI Coredump", 1595 sizeof(mpi_dump->mpi_global_header.id)); 1596 1597 qls_mpid_seg_hdr(&mpi_dump->nic1_regs_seg_hdr, 1598 Q81_NIC1_CONTROL_SEG_NUM, 1599 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_regs)), 1600 "NIC1 Registers"); 1601 1602 qls_mpid_seg_hdr(&mpi_dump->nic2_regs_seg_hdr, 1603 Q81_NIC2_CONTROL_SEG_NUM, 1604 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_regs)), 1605 "NIC2 Registers"); 1606 1607 qls_mpid_seg_hdr(&mpi_dump->xgmac1_seg_hdr, 1608 Q81_NIC1_XGMAC_SEG_NUM, 1609 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac1)), 1610 "NIC1 XGMac Registers"); 1611 1612 qls_mpid_seg_hdr(&mpi_dump->xgmac2_seg_hdr, 1613 Q81_NIC2_XGMAC_SEG_NUM, 1614 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->xgmac2)), 1615 "NIC2 XGMac Registers"); 1616 1617 if (ha->pci_func & 1) { 1618 for (i = 0; i < 64; i++) 1619 mpi_dump->nic2_regs[i] = 1620 READ_REG32(ha, i * sizeof(uint32_t)); 1621 1622 for (i = 0; i < 64; i++) 1623 mpi_dump->nic1_regs[i] = 1624 qls_rd_ofunc_reg(ha, 1625 (i * sizeof(uint32_t)) / 4); 1626 1627 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 0); 1628 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 1); 1629 } else { 1630 for (i = 0; i < 64; i++) 1631 mpi_dump->nic1_regs[i] = 1632 READ_REG32(ha, i * sizeof(uint32_t)); 1633 1634 for (i = 0; i < 64; i++) 1635 mpi_dump->nic2_regs[i] = 1636 qls_rd_ofunc_reg(ha, 1637 (i * sizeof(uint32_t)) / 4); 1638 1639 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac1[0], 0); 1640 qls_rd_xgmac_regs(ha, &mpi_dump->xgmac2[0], 1); 1641 } 1642 1643 qls_mpid_seg_hdr(&mpi_dump->xaui1_an_hdr, 1644 Q81_XAUI1_AN_SEG_NUM, 1645 (sizeof(qls_mpid_seg_hdr_t) + 1646 sizeof(mpi_dump->serdes1_xaui_an)), 1647 "XAUI1 AN Registers"); 1648 1649 qls_mpid_seg_hdr(&mpi_dump->xaui1_hss_pcs_hdr, 1650 Q81_XAUI1_HSS_PCS_SEG_NUM, 1651 (sizeof(qls_mpid_seg_hdr_t) + 1652 sizeof(mpi_dump->serdes1_xaui_hss_pcs)), 1653 "XAUI1 HSS PCS Registers"); 1654 1655 qls_mpid_seg_hdr(&mpi_dump->xfi1_an_hdr, 1656 Q81_XFI1_AN_SEG_NUM, 1657 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes1_xfi_an)), 1658 "XFI1 AN Registers"); 1659 1660 qls_mpid_seg_hdr(&mpi_dump->xfi1_train_hdr, 1661 Q81_XFI1_TRAIN_SEG_NUM, 1662 (sizeof(qls_mpid_seg_hdr_t) + 1663 sizeof(mpi_dump->serdes1_xfi_train)), 1664 "XFI1 TRAIN Registers"); 1665 1666 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pcs_hdr, 1667 Q81_XFI1_HSS_PCS_SEG_NUM, 1668 (sizeof(qls_mpid_seg_hdr_t) + 1669 sizeof(mpi_dump->serdes1_xfi_hss_pcs)), 1670 "XFI1 HSS PCS Registers"); 1671 1672 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_tx_hdr, 1673 Q81_XFI1_HSS_TX_SEG_NUM, 1674 (sizeof(qls_mpid_seg_hdr_t) + 1675 sizeof(mpi_dump->serdes1_xfi_hss_tx)), 1676 "XFI1 HSS TX Registers"); 1677 1678 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_rx_hdr, 1679 Q81_XFI1_HSS_RX_SEG_NUM, 1680 (sizeof(qls_mpid_seg_hdr_t) + 1681 sizeof(mpi_dump->serdes1_xfi_hss_rx)), 1682 "XFI1 HSS RX Registers"); 1683 1684 qls_mpid_seg_hdr(&mpi_dump->xfi1_hss_pll_hdr, 1685 Q81_XFI1_HSS_PLL_SEG_NUM, 1686 (sizeof(qls_mpid_seg_hdr_t) + 1687 sizeof(mpi_dump->serdes1_xfi_hss_pll)), 1688 "XFI1 HSS PLL Registers"); 1689 1690 qls_mpid_seg_hdr(&mpi_dump->xaui2_an_hdr, 1691 Q81_XAUI2_AN_SEG_NUM, 1692 (sizeof(qls_mpid_seg_hdr_t) + 1693 sizeof(mpi_dump->serdes2_xaui_an)), 1694 "XAUI2 AN Registers"); 1695 1696 qls_mpid_seg_hdr(&mpi_dump->xaui2_hss_pcs_hdr, 1697 Q81_XAUI2_HSS_PCS_SEG_NUM, 1698 (sizeof(qls_mpid_seg_hdr_t) + 1699 sizeof(mpi_dump->serdes2_xaui_hss_pcs)), 1700 "XAUI2 HSS PCS Registers"); 1701 1702 qls_mpid_seg_hdr(&mpi_dump->xfi2_an_hdr, 1703 Q81_XFI2_AN_SEG_NUM, 1704 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->serdes2_xfi_an)), 1705 "XFI2 AN Registers"); 1706 1707 qls_mpid_seg_hdr(&mpi_dump->xfi2_train_hdr, 1708 Q81_XFI2_TRAIN_SEG_NUM, 1709 (sizeof(qls_mpid_seg_hdr_t) + 1710 sizeof(mpi_dump->serdes2_xfi_train)), 1711 "XFI2 TRAIN Registers"); 1712 1713 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pcs_hdr, 1714 Q81_XFI2_HSS_PCS_SEG_NUM, 1715 (sizeof(qls_mpid_seg_hdr_t) + 1716 sizeof(mpi_dump->serdes2_xfi_hss_pcs)), 1717 "XFI2 HSS PCS Registers"); 1718 1719 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_tx_hdr, 1720 Q81_XFI2_HSS_TX_SEG_NUM, 1721 (sizeof(qls_mpid_seg_hdr_t) + 1722 sizeof(mpi_dump->serdes2_xfi_hss_tx)), 1723 "XFI2 HSS TX Registers"); 1724 1725 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_rx_hdr, 1726 Q81_XFI2_HSS_RX_SEG_NUM, 1727 (sizeof(qls_mpid_seg_hdr_t) + 1728 sizeof(mpi_dump->serdes2_xfi_hss_rx)), 1729 "XFI2 HSS RX Registers"); 1730 1731 qls_mpid_seg_hdr(&mpi_dump->xfi2_hss_pll_hdr, 1732 Q81_XFI2_HSS_PLL_SEG_NUM, 1733 (sizeof(qls_mpid_seg_hdr_t) + 1734 sizeof(mpi_dump->serdes2_xfi_hss_pll)), 1735 "XFI2 HSS PLL Registers"); 1736 1737 qls_rd_serdes_regs(ha, mpi_dump); 1738 1739 qls_mpid_seg_hdr(&mpi_dump->core_regs_seg_hdr, 1740 Q81_CORE_SEG_NUM, 1741 (sizeof(mpi_dump->core_regs_seg_hdr) + 1742 sizeof(mpi_dump->mpi_core_regs) + 1743 sizeof(mpi_dump->mpi_core_sh_regs)), 1744 "Core Registers"); 1745 1746 ret = qls_get_mpi_regs(ha, &mpi_dump->mpi_core_regs[0], 1747 Q81_MPI_CORE_REGS_ADDR, Q81_MPI_CORE_REGS_CNT); 1748 1749 ret = qls_get_mpi_shadow_regs(ha, 1750 &mpi_dump->mpi_core_sh_regs[0]); 1751 1752 qls_mpid_seg_hdr(&mpi_dump->test_logic_regs_seg_hdr, 1753 Q81_TEST_LOGIC_SEG_NUM, 1754 (sizeof(qls_mpid_seg_hdr_t) + 1755 sizeof(mpi_dump->test_logic_regs)), 1756 "Test Logic Regs"); 1757 1758 ret = qls_get_mpi_regs(ha, &mpi_dump->test_logic_regs[0], 1759 Q81_TEST_REGS_ADDR, Q81_TEST_REGS_CNT); 1760 1761 qls_mpid_seg_hdr(&mpi_dump->rmii_regs_seg_hdr, 1762 Q81_RMII_SEG_NUM, 1763 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->rmii_regs)), 1764 "RMII Registers"); 1765 1766 ret = qls_get_mpi_regs(ha, &mpi_dump->rmii_regs[0], 1767 Q81_RMII_REGS_ADDR, Q81_RMII_REGS_CNT); 1768 1769 qls_mpid_seg_hdr(&mpi_dump->fcmac1_regs_seg_hdr, 1770 Q81_FCMAC1_SEG_NUM, 1771 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac1_regs)), 1772 "FCMAC1 Registers"); 1773 1774 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac1_regs[0], 1775 Q81_FCMAC1_REGS_ADDR, Q81_FCMAC_REGS_CNT); 1776 1777 qls_mpid_seg_hdr(&mpi_dump->fcmac2_regs_seg_hdr, 1778 Q81_FCMAC2_SEG_NUM, 1779 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fcmac2_regs)), 1780 "FCMAC2 Registers"); 1781 1782 ret = qls_get_mpi_regs(ha, &mpi_dump->fcmac2_regs[0], 1783 Q81_FCMAC2_REGS_ADDR, Q81_FCMAC_REGS_CNT); 1784 1785 qls_mpid_seg_hdr(&mpi_dump->fc1_mbx_regs_seg_hdr, 1786 Q81_FC1_MBOX_SEG_NUM, 1787 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc1_mbx_regs)), 1788 "FC1 MBox Regs"); 1789 1790 ret = qls_get_mpi_regs(ha, &mpi_dump->fc1_mbx_regs[0], 1791 Q81_FC1_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT); 1792 1793 qls_mpid_seg_hdr(&mpi_dump->ide_regs_seg_hdr, 1794 Q81_IDE_SEG_NUM, 1795 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ide_regs)), 1796 "IDE Registers"); 1797 1798 ret = qls_get_mpi_regs(ha, &mpi_dump->ide_regs[0], 1799 Q81_IDE_REGS_ADDR, Q81_IDE_REGS_CNT); 1800 1801 qls_mpid_seg_hdr(&mpi_dump->nic1_mbx_regs_seg_hdr, 1802 Q81_NIC1_MBOX_SEG_NUM, 1803 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic1_mbx_regs)), 1804 "NIC1 MBox Regs"); 1805 1806 ret = qls_get_mpi_regs(ha, &mpi_dump->nic1_mbx_regs[0], 1807 Q81_NIC1_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT); 1808 1809 qls_mpid_seg_hdr(&mpi_dump->smbus_regs_seg_hdr, 1810 Q81_SMBUS_SEG_NUM, 1811 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->smbus_regs)), 1812 "SMBus Registers"); 1813 1814 ret = qls_get_mpi_regs(ha, &mpi_dump->smbus_regs[0], 1815 Q81_SMBUS_REGS_ADDR, Q81_SMBUS_REGS_CNT); 1816 1817 qls_mpid_seg_hdr(&mpi_dump->fc2_mbx_regs_seg_hdr, 1818 Q81_FC2_MBOX_SEG_NUM, 1819 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->fc2_mbx_regs)), 1820 "FC2 MBox Regs"); 1821 1822 ret = qls_get_mpi_regs(ha, &mpi_dump->fc2_mbx_regs[0], 1823 Q81_FC2_MBX_REGS_ADDR, Q81_FC_MBX_REGS_CNT); 1824 1825 qls_mpid_seg_hdr(&mpi_dump->nic2_mbx_regs_seg_hdr, 1826 Q81_NIC2_MBOX_SEG_NUM, 1827 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->nic2_mbx_regs)), 1828 "NIC2 MBox Regs"); 1829 1830 ret = qls_get_mpi_regs(ha, &mpi_dump->nic2_mbx_regs[0], 1831 Q81_NIC2_MBX_REGS_ADDR, Q81_NIC_MBX_REGS_CNT); 1832 1833 qls_mpid_seg_hdr(&mpi_dump->i2c_regs_seg_hdr, 1834 Q81_I2C_SEG_NUM, 1835 (sizeof(qls_mpid_seg_hdr_t) + 1836 sizeof(mpi_dump->i2c_regs)), 1837 "I2C Registers"); 1838 1839 ret = qls_get_mpi_regs(ha, &mpi_dump->i2c_regs[0], 1840 Q81_I2C_REGS_ADDR, Q81_I2C_REGS_CNT); 1841 1842 qls_mpid_seg_hdr(&mpi_dump->memc_regs_seg_hdr, 1843 Q81_MEMC_SEG_NUM, 1844 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_regs)), 1845 "MEMC Registers"); 1846 1847 ret = qls_get_mpi_regs(ha, &mpi_dump->memc_regs[0], 1848 Q81_MEMC_REGS_ADDR, Q81_MEMC_REGS_CNT); 1849 1850 qls_mpid_seg_hdr(&mpi_dump->pbus_regs_seg_hdr, 1851 Q81_PBUS_SEG_NUM, 1852 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->pbus_regs)), 1853 "PBUS Registers"); 1854 1855 ret = qls_get_mpi_regs(ha, &mpi_dump->pbus_regs[0], 1856 Q81_PBUS_REGS_ADDR, Q81_PBUS_REGS_CNT); 1857 1858 qls_mpid_seg_hdr(&mpi_dump->mde_regs_seg_hdr, 1859 Q81_MDE_SEG_NUM, 1860 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mde_regs)), 1861 "MDE Registers"); 1862 1863 ret = qls_get_mpi_regs(ha, &mpi_dump->mde_regs[0], 1864 Q81_MDE_REGS_ADDR, Q81_MDE_REGS_CNT); 1865 1866 qls_mpid_seg_hdr(&mpi_dump->intr_states_seg_hdr, 1867 Q81_INTR_STATES_SEG_NUM, 1868 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->intr_states)), 1869 "INTR States"); 1870 1871 qls_get_intr_states(ha, &mpi_dump->intr_states[0]); 1872 1873 qls_mpid_seg_hdr(&mpi_dump->probe_dump_seg_hdr, 1874 Q81_PROBE_DUMP_SEG_NUM, 1875 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->probe_dump)), 1876 "Probe Dump"); 1877 1878 qls_get_probe_dump(ha, &mpi_dump->probe_dump[0]); 1879 1880 qls_mpid_seg_hdr(&mpi_dump->routing_reg_seg_hdr, 1881 Q81_ROUTING_INDEX_SEG_NUM, 1882 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->routing_regs)), 1883 "Routing Regs"); 1884 1885 qls_get_ridx_registers(ha, &mpi_dump->routing_regs[0]); 1886 1887 qls_mpid_seg_hdr(&mpi_dump->mac_prot_reg_seg_hdr, 1888 Q81_MAC_PROTOCOL_SEG_NUM, 1889 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->mac_prot_regs)), 1890 "MAC Prot Regs"); 1891 1892 qls_get_mac_proto_regs(ha, &mpi_dump->mac_prot_regs[0]); 1893 1894 qls_mpid_seg_hdr(&mpi_dump->ets_seg_hdr, 1895 Q81_ETS_SEG_NUM, 1896 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->ets)), 1897 "ETS Registers"); 1898 1899 ret = qls_get_ets_regs(ha, &mpi_dump->ets[0]); 1900 1901 qls_mpid_seg_hdr(&mpi_dump->sem_regs_seg_hdr, 1902 Q81_SEM_REGS_SEG_NUM, 1903 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->sem_regs)), 1904 "Sem Registers"); 1905 1906 for(i = 0; i < Q81_MAX_SEMAPHORE_FUNCTIONS ; i ++) { 1907 reg = Q81_CTL_PROC_ADDR_REG_BLOCK | (i << Q81_FUNCTION_SHIFT) | 1908 (Q81_CTL_SEMAPHORE >> 2); 1909 1910 ret = qls_mpi_risc_rd_reg(ha, reg, ®_val); 1911 mpi_dump->sem_regs[i] = reg_val; 1912 1913 if (ret != 0) 1914 mpi_dump->sem_regs[i] = Q81_BAD_DATA; 1915 } 1916 1917 ret = qls_unpause_mpi_risc(ha); 1918 if (ret) 1919 printf("Failed RISC unpause. Status = 0x%.08x\n",ret); 1920 1921 ret = qls_mpi_reset(ha); 1922 if (ret) 1923 printf("Failed RISC reset. Status = 0x%.08x\n",ret); 1924 1925 WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, 0x80008000); 1926 1927 qls_mpid_seg_hdr(&mpi_dump->memc_ram_seg_hdr, 1928 Q81_MEMC_RAM_SEG_NUM, 1929 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->memc_ram)), 1930 "MEMC RAM"); 1931 1932 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], 1933 Q81_MEMC_RAM_ADDR, Q81_MEMC_RAM_CNT); 1934 if (ret) 1935 printf("Failed Dump of MEMC RAM. Status = 0x%.08x\n",ret); 1936 1937 qls_mpid_seg_hdr(&mpi_dump->code_ram_seg_hdr, 1938 Q81_WCS_RAM_SEG_NUM, 1939 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->code_ram)), 1940 "WCS RAM"); 1941 1942 ret = qls_mbx_dump_risc_ram(ha, &mpi_dump->memc_ram[0], 1943 Q81_CODE_RAM_ADDR, Q81_CODE_RAM_CNT); 1944 if (ret) 1945 printf("Failed Dump of CODE RAM. Status = 0x%.08x\n",ret); 1946 1947 qls_mpid_seg_hdr(&mpi_dump->wqc1_seg_hdr, 1948 Q81_WQC1_SEG_NUM, 1949 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc1)), 1950 "WQC 1"); 1951 1952 qls_mpid_seg_hdr(&mpi_dump->wqc2_seg_hdr, 1953 Q81_WQC2_SEG_NUM, 1954 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->wqc2)), 1955 "WQC 2"); 1956 1957 qls_mpid_seg_hdr(&mpi_dump->cqc1_seg_hdr, 1958 Q81_CQC1_SEG_NUM, 1959 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc1)), 1960 "CQC 1"); 1961 1962 qls_mpid_seg_hdr(&mpi_dump->cqc2_seg_hdr, 1963 Q81_CQC2_SEG_NUM, 1964 (sizeof(qls_mpid_seg_hdr_t) + sizeof(mpi_dump->cqc2)), 1965 "CQC 2"); 1966 1967 return 0; 1968 } 1969