1 /* 2 * Copyright (c) 2013-2016 Qlogic Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * File: ql_minidump.h 30 * 31 * $FreeBSD$ 32 */ 33 #ifndef _QL_MINIDUMP_H_ 34 #define _QL_MINIDUMP_H_ 35 36 #define QL_DBG_STATE_ARRAY_LEN 16 37 #define QL_DBG_CAP_SIZE_ARRAY_LEN 8 38 #define QL_NO_OF_OCM_WINDOWS 16 39 40 typedef struct ql_mdump_tmplt_hdr { 41 uint32_t entry_type ; 42 uint32_t first_entry_offset ; 43 uint32_t size_of_template ; 44 uint32_t recommended_capture_mask; 45 46 uint32_t num_of_entries ; 47 uint32_t version ; 48 uint32_t driver_timestamp ; 49 uint32_t checksum ; 50 51 uint32_t driver_capture_mask ; 52 uint32_t driver_info_word2 ; 53 uint32_t driver_info_word3 ; 54 uint32_t driver_info_word4 ; 55 56 uint32_t saved_state_array[QL_DBG_STATE_ARRAY_LEN] ; 57 uint32_t capture_size_array[QL_DBG_CAP_SIZE_ARRAY_LEN] ; 58 59 uint32_t ocm_window_array[QL_NO_OF_OCM_WINDOWS] ; 60 } ql_minidump_template_hdr_t ; 61 62 /* 63 * MIU AGENT ADDRESSES. 64 */ 65 66 #define MD_TA_CTL_ENABLE 0x2 67 #define MD_TA_CTL_START 0x1 68 #define MD_TA_CTL_BUSY 0x8 69 #define MD_TA_CTL_CHECK 1000 70 71 #define MD_MIU_TEST_AGT_CTRL 0x41000090 72 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094 73 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098 74 75 #define MD_MIU_TEST_AGT_RDDATA_0_31 0x410000A8 76 #define MD_MIU_TEST_AGT_RDDATA_32_63 0x410000AC 77 #define MD_MIU_TEST_AGT_RDDATA_64_95 0x410000B8 78 #define MD_MIU_TEST_AGT_RDDATA_96_127 0x410000BC 79 80 #define MD_MIU_TEST_AGT_WRDATA_0_31 0x410000A0 81 #define MD_MIU_TEST_AGT_WRDATA_32_63 0x410000A4 82 #define MD_MIU_TEST_AGT_WRDATA_64_95 0x410000B0 83 #define MD_MIU_TEST_AGT_WRDATA_96_127 0x410000B4 84 85 /* 86 * ROM Read Address 87 */ 88 89 #define MD_DIRECT_ROM_WINDOW 0x42110030 90 #define MD_DIRECT_ROM_READ_BASE 0x42150000 91 92 /* 93 * Entry Type Defines 94 */ 95 96 #define RDNOP 0 97 #define RDCRB 1 98 #define RDMUX 2 99 #define QUEUE 3 100 #define BOARD 4 101 #define RDOCM 6 102 #define L1DAT 11 103 #define L1INS 12 104 #define L2DTG 21 105 #define L2ITG 22 106 #define L2DAT 23 107 #define L2INS 24 108 #define POLLRD 35 109 #define RDMUX2 36 110 #define POLLRDMWR 37 111 #define RDROM 71 112 #define RDMEM 72 113 #define CNTRL 98 114 #define TLHDR 99 115 #define RDEND 255 116 117 /* 118 * Index of State Table. The Template header maintains 119 * an array of 8 (0..7) words that is used to store some 120 * "State Information" from the board. 121 */ 122 123 #define QL_PCIE_FUNC_INDX 0 124 #define QL_CLK_STATE_INDX 1 125 #define QL_SRE_STATE_INDX 2 126 #define QL_OCM0_ADDR_INDX 3 127 128 #define QL_REVID_STATE_INDX 4 129 #define QL_MAJVER_STATE_INDX 5 130 #define QL_MINVER_STATE_INDX 6 131 #define QL_SUBVER_STATE_INDX 7 132 133 /* 134 * Opcodes for Control Entries. 135 * These Flags are bit fields. 136 */ 137 138 #define QL_DBG_OPCODE_WR 0x01 139 #define QL_DBG_OPCODE_RW 0x02 140 #define QL_DBG_OPCODE_AND 0x04 141 #define QL_DBG_OPCODE_OR 0x08 142 #define QL_DBG_OPCODE_POLL 0x10 143 #define QL_DBG_OPCODE_RDSTATE 0x20 144 #define QL_DBG_OPCODE_WRSTATE 0x40 145 #define QL_DBG_OPCODE_MDSTATE 0x80 146 147 typedef struct ql_minidump_entry_hdr_s { 148 uint32_t entry_type ; 149 uint32_t entry_size ; 150 uint32_t entry_capture_size ; 151 union { 152 struct { 153 uint8_t entry_capture_mask ; 154 uint8_t entry_code ; 155 uint8_t driver_code ; 156 uint8_t driver_flags ; 157 }; 158 uint32_t entry_ctrl_word ; 159 }; 160 } ql_minidump_entry_hdr_t ; 161 162 /* 163 * Driver Flags 164 */ 165 #define QL_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */ 166 #define QL_DBG_SIZE_ERR_FLAG 0x40 /* entry size vs capture size mismatch*/ 167 168 /* 169 * Generic Entry Including Header 170 */ 171 172 typedef struct ql_minidump_entry_s { 173 ql_minidump_entry_hdr_t hdr ; 174 175 uint32_t entry_data00 ; 176 uint32_t entry_data01 ; 177 uint32_t entry_data02 ; 178 uint32_t entry_data03 ; 179 180 uint32_t entry_data04 ; 181 uint32_t entry_data05 ; 182 uint32_t entry_data06 ; 183 uint32_t entry_data07 ; 184 } ql_minidump_entry_t; 185 186 /* 187 * Read CRB Entry Header 188 */ 189 190 typedef struct ql_minidump_entry_rdcrb_s { 191 ql_minidump_entry_hdr_t h; 192 193 uint32_t addr ; 194 union { 195 struct { 196 uint8_t addr_stride ; 197 uint8_t rsvd_0; 198 uint16_t rsvd_1 ; 199 } ; 200 uint32_t addr_cntrl ; 201 } ; 202 203 uint32_t data_size ; 204 uint32_t op_count; 205 206 uint32_t rsvd_2 ; 207 uint32_t rsvd_3 ; 208 uint32_t rsvd_4 ; 209 uint32_t rsvd_5 ; 210 211 } ql_minidump_entry_rdcrb_t ; 212 213 /* 214 * Cache Entry Header 215 */ 216 217 typedef struct ql_minidump_entry_cache_s { 218 ql_minidump_entry_hdr_t h; 219 220 uint32_t tag_reg_addr ; 221 union { 222 struct { 223 uint16_t tag_value_stride ; 224 uint16_t init_tag_value ; 225 } ; 226 uint32_t select_addr_cntrl ; 227 } ; 228 229 uint32_t data_size ; 230 uint32_t op_count; 231 232 uint32_t control_addr ; 233 union { 234 struct { 235 uint16_t write_value ; 236 uint8_t poll_mask ; 237 uint8_t poll_wait ; 238 }; 239 uint32_t control_value ; 240 } ; 241 242 uint32_t read_addr ; 243 union { 244 struct { 245 uint8_t read_addr_stride ; 246 uint8_t read_addr_cnt ; 247 uint16_t rsvd_1 ; 248 } ; 249 uint32_t read_addr_cntrl ; 250 } ; 251 } ql_minidump_entry_cache_t ; 252 253 /* 254 * Read OCM Entry Header 255 */ 256 257 typedef struct ql_minidump_entry_rdocm_s { 258 ql_minidump_entry_hdr_t h; 259 260 uint32_t rsvd_0 ; 261 uint32_t rsvd_1 ; 262 263 uint32_t data_size ; 264 uint32_t op_count; 265 266 uint32_t rsvd_2 ; 267 uint32_t rsvd_3 ; 268 269 uint32_t read_addr ; 270 uint32_t read_addr_stride ; 271 272 } ql_minidump_entry_rdocm_t ; 273 274 /* 275 * Read MEM Entry Header 276 */ 277 278 typedef struct ql_minidump_entry_rdmem_s { 279 ql_minidump_entry_hdr_t h; 280 281 uint32_t rsvd_0[6] ; 282 283 uint32_t read_addr ; 284 uint32_t read_data_size ; 285 286 } ql_minidump_entry_rdmem_t ; 287 288 /* 289 * Read ROM Entry Header 290 */ 291 292 typedef struct ql_minidump_entry_rdrom_s { 293 ql_minidump_entry_hdr_t h; 294 295 uint32_t rsvd_0[6] ; 296 297 uint32_t read_addr ; 298 uint32_t read_data_size ; 299 300 } ql_minidump_entry_rdrom_t ; 301 302 /* 303 * Read MUX Entry Header 304 */ 305 306 typedef struct ql_minidump_entry_mux_s { 307 ql_minidump_entry_hdr_t h; 308 309 uint32_t select_addr ; 310 union { 311 struct { 312 uint32_t rsvd_0 ; 313 } ; 314 uint32_t select_addr_cntrl ; 315 } ; 316 317 uint32_t data_size ; 318 uint32_t op_count; 319 320 uint32_t select_value ; 321 uint32_t select_value_stride ; 322 323 uint32_t read_addr ; 324 uint32_t rsvd_1 ; 325 326 } ql_minidump_entry_mux_t ; 327 328 /* 329 * Read MUX2 Entry Header 330 */ 331 332 typedef struct ql_minidump_entry_mux2_s { 333 ql_minidump_entry_hdr_t h; 334 335 uint32_t select_addr_1; 336 uint32_t select_addr_2; 337 uint32_t select_value_1; 338 uint32_t select_value_2; 339 uint32_t select_value_count; 340 uint32_t select_value_mask; 341 uint32_t read_addr; 342 union { 343 struct { 344 uint8_t select_value_stride; 345 uint8_t data_size; 346 uint8_t reserved_0; 347 uint8_t reserved_1; 348 }; 349 uint32_t select_addr_value_cntrl; 350 }; 351 352 } ql_minidump_entry_mux2_t; 353 354 /* 355 * Read QUEUE Entry Header 356 */ 357 358 typedef struct ql_minidump_entry_queue_s { 359 ql_minidump_entry_hdr_t h; 360 361 uint32_t select_addr ; 362 union { 363 struct { 364 uint16_t queue_id_stride ; 365 uint16_t rsvd_0 ; 366 } ; 367 uint32_t select_addr_cntrl ; 368 } ; 369 370 uint32_t data_size ; 371 uint32_t op_count ; 372 373 uint32_t rsvd_1 ; 374 uint32_t rsvd_2 ; 375 376 uint32_t read_addr ; 377 union { 378 struct { 379 uint8_t read_addr_stride ; 380 uint8_t read_addr_cnt ; 381 uint16_t rsvd_3 ; 382 } ; 383 uint32_t read_addr_cntrl ; 384 } ; 385 386 } ql_minidump_entry_queue_t ; 387 388 /* 389 * Control Entry Header 390 */ 391 392 typedef struct ql_minidump_entry_cntrl_s { 393 ql_minidump_entry_hdr_t h; 394 395 uint32_t addr ; 396 union { 397 struct { 398 uint8_t addr_stride ; 399 uint8_t state_index_a ; 400 uint16_t poll_timeout ; 401 } ; 402 uint32_t addr_cntrl ; 403 } ; 404 405 uint32_t data_size ; 406 uint32_t op_count; 407 408 union { 409 struct { 410 uint8_t opcode ; 411 uint8_t state_index_v ; 412 uint8_t shl ; 413 uint8_t shr ; 414 } ; 415 uint32_t control_value ; 416 } ; 417 418 uint32_t value_1 ; 419 uint32_t value_2 ; 420 uint32_t value_3 ; 421 } ql_minidump_entry_cntrl_t ; 422 423 /* 424 * Read with poll. 425 */ 426 427 typedef struct ql_minidump_entry_rdcrb_with_poll_s { 428 ql_minidump_entry_hdr_t h; 429 430 uint32_t select_addr; 431 uint32_t read_addr; 432 uint32_t select_value; 433 union { 434 struct { 435 uint16_t select_value_stride; 436 uint16_t op_count; 437 }; 438 uint32_t select_value_cntrl; 439 }; 440 441 uint32_t poll; 442 uint32_t mask; 443 444 uint32_t data_size; 445 uint32_t rsvd_0; 446 447 } ql_minidump_entry_pollrd_t; 448 449 /* 450 * Read_Modify_Write with poll. 451 */ 452 453 typedef struct ql_minidump_entry_rd_modify_wr_with_poll_s { 454 ql_minidump_entry_hdr_t h; 455 456 uint32_t addr_1; 457 uint32_t addr_2; 458 uint32_t value_1; 459 uint32_t value_2; 460 uint32_t poll; 461 uint32_t mask; 462 uint32_t modify_mask; 463 uint32_t data_size; 464 465 } ql_minidump_entry_rd_modify_wr_with_poll_t; 466 467 #endif /* #ifndef _QL_MINIDUMP_H_ */ 468