1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2016 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * File: ql_isr.c 32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 39 #include "ql_os.h" 40 #include "ql_hw.h" 41 #include "ql_def.h" 42 #include "ql_inline.h" 43 #include "ql_ver.h" 44 #include "ql_glbl.h" 45 #include "ql_dbg.h" 46 47 static void qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp, 48 uint32_t r_idx); 49 50 static void 51 qla_rcv_error(qla_host_t *ha) 52 { 53 ha->stop_rcv = 1; 54 ha->qla_initiate_recovery = 1; 55 } 56 57 58 /* 59 * Name: qla_rx_intr 60 * Function: Handles normal ethernet frames received 61 */ 62 static void 63 qla_rx_intr(qla_host_t *ha, qla_sgl_rcv_t *sgc, uint32_t sds_idx) 64 { 65 qla_rx_buf_t *rxb; 66 struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL; 67 struct ifnet *ifp = ha->ifp; 68 qla_sds_t *sdsp; 69 struct ether_vlan_header *eh; 70 uint32_t i, rem_len = 0; 71 uint32_t r_idx = 0; 72 qla_rx_ring_t *rx_ring; 73 struct lro_ctrl *lro; 74 75 lro = &ha->hw.sds[sds_idx].lro; 76 77 if (ha->hw.num_rds_rings > 1) 78 r_idx = sds_idx; 79 80 ha->hw.rds[r_idx].count++; 81 82 sdsp = &ha->hw.sds[sds_idx]; 83 rx_ring = &ha->rx_ring[r_idx]; 84 85 for (i = 0; i < sgc->num_handles; i++) { 86 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF]; 87 88 QL_ASSERT(ha, (rxb != NULL), 89 ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\ 90 sds_idx)); 91 92 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_RX_RXB_INVAL)) { 93 /* log the error */ 94 device_printf(ha->pci_dev, 95 "%s invalid rxb[%d, %d, 0x%04x]\n", 96 __func__, sds_idx, i, sgc->handle[i]); 97 qla_rcv_error(ha); 98 return; 99 } 100 101 mp = rxb->m_head; 102 if (i == 0) 103 mpf = mp; 104 105 QL_ASSERT(ha, (mp != NULL), 106 ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\ 107 sds_idx)); 108 109 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD); 110 111 rxb->m_head = NULL; 112 rxb->next = sdsp->rxb_free; 113 sdsp->rxb_free = rxb; 114 sdsp->rx_free++; 115 116 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_RX_MP_NULL)) { 117 /* log the error */ 118 device_printf(ha->pci_dev, 119 "%s mp == NULL [%d, %d, 0x%04x]\n", 120 __func__, sds_idx, i, sgc->handle[i]); 121 qla_rcv_error(ha); 122 return; 123 } 124 125 if (i == 0) { 126 mpl = mpf = mp; 127 mp->m_flags |= M_PKTHDR; 128 mp->m_pkthdr.len = sgc->pkt_length; 129 mp->m_pkthdr.rcvif = ifp; 130 rem_len = mp->m_pkthdr.len; 131 } else { 132 mp->m_flags &= ~M_PKTHDR; 133 mpl->m_next = mp; 134 mpl = mp; 135 rem_len = rem_len - mp->m_len; 136 } 137 } 138 139 mpl->m_len = rem_len; 140 141 eh = mtod(mpf, struct ether_vlan_header *); 142 143 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 144 uint32_t *data = (uint32_t *)eh; 145 146 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag); 147 mpf->m_flags |= M_VLANTAG; 148 149 *(data + 3) = *(data + 2); 150 *(data + 2) = *(data + 1); 151 *(data + 1) = *data; 152 153 m_adj(mpf, ETHER_VLAN_ENCAP_LEN); 154 } 155 156 if (sgc->chksum_status == Q8_STAT_DESC_STATUS_CHKSUM_OK) { 157 mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID | 158 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 159 mpf->m_pkthdr.csum_data = 0xFFFF; 160 } else { 161 mpf->m_pkthdr.csum_flags = 0; 162 } 163 164 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 165 166 mpf->m_pkthdr.flowid = sgc->rss_hash; 167 168 #if __FreeBSD_version >= 1100000 169 M_HASHTYPE_SET(mpf, M_HASHTYPE_OPAQUE_HASH); 170 #else 171 #if (__FreeBSD_version >= 903511 && __FreeBSD_version < 1100000) 172 M_HASHTYPE_SET(mpf, M_HASHTYPE_OPAQUE); 173 #else 174 M_HASHTYPE_SET(mpf, M_HASHTYPE_NONE); 175 #endif 176 #endif /* #if __FreeBSD_version >= 1100000 */ 177 178 if (ha->hw.enable_soft_lro) { 179 180 #if (__FreeBSD_version >= 1100101) 181 182 tcp_lro_queue_mbuf(lro, mpf); 183 184 #else 185 if (tcp_lro_rx(lro, mpf, 0)) 186 (*ifp->if_input)(ifp, mpf); 187 188 #endif /* #if (__FreeBSD_version >= 1100101) */ 189 190 191 } else { 192 (*ifp->if_input)(ifp, mpf); 193 } 194 195 if (sdsp->rx_free > ha->std_replenish) 196 qla_replenish_normal_rx(ha, sdsp, r_idx); 197 198 return; 199 } 200 201 #define QLA_TCP_HDR_SIZE 20 202 #define QLA_TCP_TS_OPTION_SIZE 12 203 204 /* 205 * Name: qla_lro_intr 206 * Function: Handles normal ethernet frames received 207 */ 208 static int 209 qla_lro_intr(qla_host_t *ha, qla_sgl_lro_t *sgc, uint32_t sds_idx) 210 { 211 qla_rx_buf_t *rxb; 212 struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL; 213 struct ifnet *ifp = ha->ifp; 214 qla_sds_t *sdsp; 215 struct ether_vlan_header *eh; 216 uint32_t i, rem_len = 0, pkt_length, iplen; 217 struct tcphdr *th; 218 struct ip *ip = NULL; 219 struct ip6_hdr *ip6 = NULL; 220 uint16_t etype; 221 uint32_t r_idx = 0; 222 qla_rx_ring_t *rx_ring; 223 224 if (ha->hw.num_rds_rings > 1) 225 r_idx = sds_idx; 226 227 ha->hw.rds[r_idx].count++; 228 229 rx_ring = &ha->rx_ring[r_idx]; 230 231 ha->hw.rds[r_idx].lro_pkt_count++; 232 233 sdsp = &ha->hw.sds[sds_idx]; 234 235 pkt_length = sgc->payload_length + sgc->l4_offset; 236 237 if (sgc->flags & Q8_LRO_COMP_TS) { 238 pkt_length += QLA_TCP_HDR_SIZE + QLA_TCP_TS_OPTION_SIZE; 239 } else { 240 pkt_length += QLA_TCP_HDR_SIZE; 241 } 242 ha->hw.rds[r_idx].lro_bytes += pkt_length; 243 244 for (i = 0; i < sgc->num_handles; i++) { 245 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF]; 246 247 QL_ASSERT(ha, (rxb != NULL), 248 ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\ 249 sds_idx)); 250 251 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_RXB_INVAL)) { 252 /* log the error */ 253 device_printf(ha->pci_dev, 254 "%s invalid rxb[%d, %d, 0x%04x]\n", 255 __func__, sds_idx, i, sgc->handle[i]); 256 qla_rcv_error(ha); 257 return (0); 258 } 259 260 mp = rxb->m_head; 261 if (i == 0) 262 mpf = mp; 263 264 QL_ASSERT(ha, (mp != NULL), 265 ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\ 266 sds_idx)); 267 268 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD); 269 270 rxb->m_head = NULL; 271 rxb->next = sdsp->rxb_free; 272 sdsp->rxb_free = rxb; 273 sdsp->rx_free++; 274 275 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_MP_NULL)) { 276 /* log the error */ 277 device_printf(ha->pci_dev, 278 "%s mp == NULL [%d, %d, 0x%04x]\n", 279 __func__, sds_idx, i, sgc->handle[i]); 280 qla_rcv_error(ha); 281 return (0); 282 } 283 284 if (i == 0) { 285 mpl = mpf = mp; 286 mp->m_flags |= M_PKTHDR; 287 mp->m_pkthdr.len = pkt_length; 288 mp->m_pkthdr.rcvif = ifp; 289 rem_len = mp->m_pkthdr.len; 290 } else { 291 mp->m_flags &= ~M_PKTHDR; 292 mpl->m_next = mp; 293 mpl = mp; 294 rem_len = rem_len - mp->m_len; 295 } 296 } 297 298 mpl->m_len = rem_len; 299 300 th = (struct tcphdr *)(mpf->m_data + sgc->l4_offset); 301 302 if (sgc->flags & Q8_LRO_COMP_PUSH_BIT) 303 th->th_flags |= TH_PUSH; 304 305 m_adj(mpf, sgc->l2_offset); 306 307 eh = mtod(mpf, struct ether_vlan_header *); 308 309 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 310 uint32_t *data = (uint32_t *)eh; 311 312 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag); 313 mpf->m_flags |= M_VLANTAG; 314 315 *(data + 3) = *(data + 2); 316 *(data + 2) = *(data + 1); 317 *(data + 1) = *data; 318 319 m_adj(mpf, ETHER_VLAN_ENCAP_LEN); 320 321 etype = ntohs(eh->evl_proto); 322 } else { 323 etype = ntohs(eh->evl_encap_proto); 324 } 325 326 if (etype == ETHERTYPE_IP) { 327 ip = (struct ip *)(mpf->m_data + ETHER_HDR_LEN); 328 329 iplen = (ip->ip_hl << 2) + (th->th_off << 2) + 330 sgc->payload_length; 331 332 ip->ip_len = htons(iplen); 333 334 ha->ipv4_lro++; 335 336 M_HASHTYPE_SET(mpf, M_HASHTYPE_RSS_TCP_IPV4); 337 338 } else if (etype == ETHERTYPE_IPV6) { 339 ip6 = (struct ip6_hdr *)(mpf->m_data + ETHER_HDR_LEN); 340 341 iplen = (th->th_off << 2) + sgc->payload_length; 342 343 ip6->ip6_plen = htons(iplen); 344 345 ha->ipv6_lro++; 346 347 M_HASHTYPE_SET(mpf, M_HASHTYPE_RSS_TCP_IPV6); 348 349 } else { 350 m_freem(mpf); 351 352 if (sdsp->rx_free > ha->std_replenish) 353 qla_replenish_normal_rx(ha, sdsp, r_idx); 354 return 0; 355 } 356 357 mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID | 358 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 359 mpf->m_pkthdr.csum_data = 0xFFFF; 360 361 mpf->m_pkthdr.flowid = sgc->rss_hash; 362 363 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 364 365 (*ifp->if_input)(ifp, mpf); 366 367 if (sdsp->rx_free > ha->std_replenish) 368 qla_replenish_normal_rx(ha, sdsp, r_idx); 369 370 return (0); 371 } 372 373 static int 374 qla_rcv_cont_sds(qla_host_t *ha, uint32_t sds_idx, uint32_t comp_idx, 375 uint32_t dcount, uint16_t *handle, uint16_t *nhandles) 376 { 377 uint32_t i; 378 uint16_t num_handles; 379 q80_stat_desc_t *sdesc; 380 uint32_t opcode; 381 382 *nhandles = 0; 383 dcount--; 384 385 for (i = 0; i < dcount; i++) { 386 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1); 387 sdesc = (q80_stat_desc_t *) 388 &ha->hw.sds[sds_idx].sds_ring_base[comp_idx]; 389 390 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1])); 391 392 if (!opcode) { 393 device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n", 394 __func__, (void *)sdesc->data[0], 395 (void *)sdesc->data[1]); 396 return -1; 397 } 398 399 num_handles = Q8_SGL_STAT_DESC_NUM_HANDLES((sdesc->data[1])); 400 if (!num_handles) { 401 device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n", 402 __func__, (void *)sdesc->data[0], 403 (void *)sdesc->data[1]); 404 return -1; 405 } 406 407 if (QL_ERR_INJECT(ha, INJCT_NUM_HNDLE_INVALID)) 408 num_handles = -1; 409 410 switch (num_handles) { 411 412 case 1: 413 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0])); 414 break; 415 416 case 2: 417 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0])); 418 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0])); 419 break; 420 421 case 3: 422 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0])); 423 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0])); 424 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0])); 425 break; 426 427 case 4: 428 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0])); 429 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0])); 430 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0])); 431 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0])); 432 break; 433 434 case 5: 435 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0])); 436 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0])); 437 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0])); 438 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0])); 439 *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1])); 440 break; 441 442 case 6: 443 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0])); 444 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0])); 445 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0])); 446 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0])); 447 *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1])); 448 *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1])); 449 break; 450 451 case 7: 452 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0])); 453 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0])); 454 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0])); 455 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0])); 456 *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1])); 457 *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1])); 458 *handle++ = Q8_SGL_STAT_DESC_HANDLE7((sdesc->data[1])); 459 break; 460 461 default: 462 device_printf(ha->pci_dev, 463 "%s: invalid num handles %p %p\n", 464 __func__, (void *)sdesc->data[0], 465 (void *)sdesc->data[1]); 466 467 QL_ASSERT(ha, (0),\ 468 ("%s: %s [nh, sds, d0, d1]=[%d, %d, %p, %p]\n", 469 __func__, "invalid num handles", sds_idx, num_handles, 470 (void *)sdesc->data[0],(void *)sdesc->data[1])); 471 472 qla_rcv_error(ha); 473 return 0; 474 } 475 *nhandles = *nhandles + num_handles; 476 } 477 return 0; 478 } 479 480 /* 481 * Name: ql_rcv_isr 482 * Function: Main Interrupt Service Routine 483 */ 484 uint32_t 485 ql_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count) 486 { 487 device_t dev; 488 qla_hw_t *hw; 489 uint32_t comp_idx, c_idx = 0, desc_count = 0, opcode; 490 volatile q80_stat_desc_t *sdesc, *sdesc0 = NULL; 491 uint32_t ret = 0; 492 qla_sgl_comp_t sgc; 493 uint16_t nhandles; 494 uint32_t sds_replenish_threshold = 0; 495 uint32_t r_idx = 0; 496 qla_sds_t *sdsp; 497 498 dev = ha->pci_dev; 499 hw = &ha->hw; 500 501 hw->sds[sds_idx].rcv_active = 1; 502 if (ha->stop_rcv) { 503 hw->sds[sds_idx].rcv_active = 0; 504 return 0; 505 } 506 507 QL_DPRINT2(ha, (dev, "%s: [%d]enter\n", __func__, sds_idx)); 508 509 /* 510 * receive interrupts 511 */ 512 comp_idx = hw->sds[sds_idx].sdsr_next; 513 514 while (count-- && !ha->stop_rcv) { 515 516 sdesc = (q80_stat_desc_t *) 517 &hw->sds[sds_idx].sds_ring_base[comp_idx]; 518 519 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1])); 520 521 if (!opcode) 522 break; 523 524 switch (opcode) { 525 526 case Q8_STAT_DESC_OPCODE_RCV_PKT: 527 528 desc_count = 1; 529 530 bzero(&sgc, sizeof(qla_sgl_comp_t)); 531 532 sgc.rcv.pkt_length = 533 Q8_STAT_DESC_TOTAL_LENGTH((sdesc->data[0])); 534 sgc.rcv.num_handles = 1; 535 sgc.rcv.handle[0] = 536 Q8_STAT_DESC_HANDLE((sdesc->data[0])); 537 sgc.rcv.chksum_status = 538 Q8_STAT_DESC_STATUS((sdesc->data[1])); 539 540 sgc.rcv.rss_hash = 541 Q8_STAT_DESC_RSS_HASH((sdesc->data[0])); 542 543 if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) { 544 sgc.rcv.vlan_tag = 545 Q8_STAT_DESC_VLAN_ID((sdesc->data[1])); 546 } 547 qla_rx_intr(ha, &sgc.rcv, sds_idx); 548 break; 549 550 case Q8_STAT_DESC_OPCODE_SGL_RCV: 551 552 desc_count = 553 Q8_STAT_DESC_COUNT_SGL_RCV((sdesc->data[1])); 554 555 if (desc_count > 1) { 556 c_idx = (comp_idx + desc_count -1) & 557 (NUM_STATUS_DESCRIPTORS-1); 558 sdesc0 = (q80_stat_desc_t *) 559 &hw->sds[sds_idx].sds_ring_base[c_idx]; 560 561 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) != 562 Q8_STAT_DESC_OPCODE_CONT) { 563 desc_count = 0; 564 break; 565 } 566 } 567 568 bzero(&sgc, sizeof(qla_sgl_comp_t)); 569 570 sgc.rcv.pkt_length = 571 Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(\ 572 (sdesc->data[0])); 573 sgc.rcv.chksum_status = 574 Q8_STAT_DESC_STATUS((sdesc->data[1])); 575 576 sgc.rcv.rss_hash = 577 Q8_STAT_DESC_RSS_HASH((sdesc->data[0])); 578 579 if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) { 580 sgc.rcv.vlan_tag = 581 Q8_STAT_DESC_VLAN_ID((sdesc->data[1])); 582 } 583 584 QL_ASSERT(ha, (desc_count <= 2) ,\ 585 ("%s: [sds_idx, data0, data1]="\ 586 "%d, %p, %p]\n", __func__, sds_idx,\ 587 (void *)sdesc->data[0],\ 588 (void *)sdesc->data[1])); 589 590 sgc.rcv.num_handles = 1; 591 sgc.rcv.handle[0] = 592 Q8_STAT_DESC_HANDLE((sdesc->data[0])); 593 594 if (qla_rcv_cont_sds(ha, sds_idx, comp_idx, desc_count, 595 &sgc.rcv.handle[1], &nhandles)) { 596 device_printf(dev, 597 "%s: [sds_idx, dcount, data0, data1]=" 598 "[%d, %d, 0x%llx, 0x%llx]\n", 599 __func__, sds_idx, desc_count, 600 (long long unsigned int)sdesc->data[0], 601 (long long unsigned int)sdesc->data[1]); 602 desc_count = 0; 603 break; 604 } 605 606 sgc.rcv.num_handles += nhandles; 607 608 qla_rx_intr(ha, &sgc.rcv, sds_idx); 609 610 break; 611 612 case Q8_STAT_DESC_OPCODE_SGL_LRO: 613 614 desc_count = 615 Q8_STAT_DESC_COUNT_SGL_LRO((sdesc->data[1])); 616 617 if (desc_count > 1) { 618 c_idx = (comp_idx + desc_count -1) & 619 (NUM_STATUS_DESCRIPTORS-1); 620 sdesc0 = (q80_stat_desc_t *) 621 &hw->sds[sds_idx].sds_ring_base[c_idx]; 622 623 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) != 624 Q8_STAT_DESC_OPCODE_CONT) { 625 desc_count = 0; 626 break; 627 } 628 } 629 bzero(&sgc, sizeof(qla_sgl_comp_t)); 630 631 sgc.lro.payload_length = 632 Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV((sdesc->data[0])); 633 634 sgc.lro.rss_hash = 635 Q8_STAT_DESC_RSS_HASH((sdesc->data[0])); 636 637 sgc.lro.num_handles = 1; 638 sgc.lro.handle[0] = 639 Q8_STAT_DESC_HANDLE((sdesc->data[0])); 640 641 if (Q8_SGL_LRO_STAT_TS((sdesc->data[1]))) 642 sgc.lro.flags |= Q8_LRO_COMP_TS; 643 644 if (Q8_SGL_LRO_STAT_PUSH_BIT((sdesc->data[1]))) 645 sgc.lro.flags |= Q8_LRO_COMP_PUSH_BIT; 646 647 sgc.lro.l2_offset = 648 Q8_SGL_LRO_STAT_L2_OFFSET((sdesc->data[1])); 649 sgc.lro.l4_offset = 650 Q8_SGL_LRO_STAT_L4_OFFSET((sdesc->data[1])); 651 652 if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) { 653 sgc.lro.vlan_tag = 654 Q8_STAT_DESC_VLAN_ID((sdesc->data[1])); 655 } 656 657 QL_ASSERT(ha, (desc_count <= 7) ,\ 658 ("%s: [sds_idx, data0, data1]="\ 659 "[%d, 0x%llx, 0x%llx]\n",\ 660 __func__, sds_idx,\ 661 (long long unsigned int)sdesc->data[0],\ 662 (long long unsigned int)sdesc->data[1])); 663 664 if (qla_rcv_cont_sds(ha, sds_idx, comp_idx, 665 desc_count, &sgc.lro.handle[1], &nhandles)) { 666 device_printf(dev, 667 "%s: [sds_idx, data0, data1]="\ 668 "[%d, 0x%llx, 0x%llx]\n",\ 669 __func__, sds_idx,\ 670 (long long unsigned int)sdesc->data[0],\ 671 (long long unsigned int)sdesc->data[1]); 672 673 desc_count = 0; 674 break; 675 } 676 677 sgc.lro.num_handles += nhandles; 678 679 if (qla_lro_intr(ha, &sgc.lro, sds_idx)) { 680 device_printf(dev, 681 "%s: [sds_idx, data0, data1]="\ 682 "[%d, 0x%llx, 0x%llx]\n",\ 683 __func__, sds_idx,\ 684 (long long unsigned int)sdesc->data[0],\ 685 (long long unsigned int)sdesc->data[1]); 686 device_printf(dev, 687 "%s: [comp_idx, c_idx, dcount, nhndls]="\ 688 "[%d, %d, %d, %d]\n",\ 689 __func__, comp_idx, c_idx, desc_count, 690 sgc.lro.num_handles); 691 if (desc_count > 1) { 692 device_printf(dev, 693 "%s: [sds_idx, data0, data1]="\ 694 "[%d, 0x%llx, 0x%llx]\n",\ 695 __func__, sds_idx,\ 696 (long long unsigned int)sdesc0->data[0],\ 697 (long long unsigned int)sdesc0->data[1]); 698 } 699 } 700 701 break; 702 703 default: 704 device_printf(dev, "%s: default 0x%llx!\n", __func__, 705 (long long unsigned int)sdesc->data[0]); 706 break; 707 } 708 709 if (desc_count == 0) 710 break; 711 712 sds_replenish_threshold += desc_count; 713 714 715 while (desc_count--) { 716 sdesc->data[0] = 0ULL; 717 sdesc->data[1] = 0ULL; 718 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1); 719 sdesc = (q80_stat_desc_t *) 720 &hw->sds[sds_idx].sds_ring_base[comp_idx]; 721 } 722 723 if (sds_replenish_threshold > ha->hw.sds_cidx_thres) { 724 sds_replenish_threshold = 0; 725 if (hw->sds[sds_idx].sdsr_next != comp_idx) { 726 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx,\ 727 comp_idx); 728 } 729 hw->sds[sds_idx].sdsr_next = comp_idx; 730 } 731 } 732 733 if (ha->hw.enable_soft_lro) { 734 struct lro_ctrl *lro; 735 736 lro = &ha->hw.sds[sds_idx].lro; 737 738 #if (__FreeBSD_version >= 1100101) 739 740 tcp_lro_flush_all(lro); 741 742 #else 743 struct lro_entry *queued; 744 745 while ((!SLIST_EMPTY(&lro->lro_active))) { 746 queued = SLIST_FIRST(&lro->lro_active); 747 SLIST_REMOVE_HEAD(&lro->lro_active, next); 748 tcp_lro_flush(lro, queued); 749 } 750 751 #endif /* #if (__FreeBSD_version >= 1100101) */ 752 753 } 754 755 if (ha->stop_rcv) 756 goto ql_rcv_isr_exit; 757 758 if (hw->sds[sds_idx].sdsr_next != comp_idx) { 759 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx); 760 hw->sds[sds_idx].sdsr_next = comp_idx; 761 } else { 762 if (ha->hw.num_rds_rings > 1) 763 r_idx = sds_idx; 764 765 sdsp = &ha->hw.sds[sds_idx]; 766 767 if (sdsp->rx_free > ha->std_replenish) 768 qla_replenish_normal_rx(ha, sdsp, r_idx); 769 } 770 771 sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx]; 772 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1])); 773 774 if (opcode) 775 ret = -1; 776 777 ql_rcv_isr_exit: 778 hw->sds[sds_idx].rcv_active = 0; 779 780 return (ret); 781 } 782 783 void 784 ql_mbx_isr(void *arg) 785 { 786 qla_host_t *ha; 787 uint32_t data; 788 uint32_t prev_link_state; 789 790 ha = arg; 791 792 if (ha == NULL) { 793 device_printf(ha->pci_dev, "%s: arg == NULL\n", __func__); 794 return; 795 } 796 797 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL); 798 if ((data & 0x3) != 0x1) { 799 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0); 800 return; 801 } 802 803 data = READ_REG32(ha, Q8_FW_MBOX0); 804 805 if ((data & 0xF000) != 0x8000) 806 return; 807 808 data = data & 0xFFFF; 809 810 switch (data) { 811 812 case 0x8001: /* It's an AEN */ 813 814 ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); 815 816 data = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); 817 ha->hw.cable_length = data & 0xFFFF; 818 819 data = data >> 16; 820 ha->hw.link_speed = data & 0xFFF; 821 822 data = READ_REG32(ha, (Q8_FW_MBOX0 + 12)); 823 824 prev_link_state = ha->hw.link_up; 825 ha->hw.link_up = (((data & 0xFF) == 0) ? 0 : 1); 826 827 if (prev_link_state != ha->hw.link_up) { 828 if (ha->hw.link_up) 829 if_link_state_change(ha->ifp, LINK_STATE_UP); 830 else 831 if_link_state_change(ha->ifp, LINK_STATE_DOWN); 832 } 833 834 835 ha->hw.module_type = ((data >> 8) & 0xFF); 836 ha->hw.flags.fduplex = (((data & 0xFF0000) == 0) ? 0 : 1); 837 ha->hw.flags.autoneg = (((data & 0xFF000000) == 0) ? 0 : 1); 838 839 data = READ_REG32(ha, (Q8_FW_MBOX0 + 16)); 840 ha->hw.flags.loopback_mode = data & 0x03; 841 842 ha->hw.link_faults = (data >> 3) & 0xFF; 843 844 break; 845 846 case 0x8100: 847 ha->hw.imd_compl=1; 848 break; 849 850 case 0x8101: 851 ha->async_event = 1; 852 ha->hw.aen_mb0 = 0x8101; 853 ha->hw.aen_mb1 = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); 854 ha->hw.aen_mb2 = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); 855 ha->hw.aen_mb3 = READ_REG32(ha, (Q8_FW_MBOX0 + 12)); 856 ha->hw.aen_mb4 = READ_REG32(ha, (Q8_FW_MBOX0 + 16)); 857 break; 858 859 case 0x8110: 860 /* for now just dump the registers */ 861 { 862 uint32_t ombx[5]; 863 864 ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); 865 ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); 866 ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12)); 867 ombx[3] = READ_REG32(ha, (Q8_FW_MBOX0 + 16)); 868 ombx[4] = READ_REG32(ha, (Q8_FW_MBOX0 + 20)); 869 870 device_printf(ha->pci_dev, "%s: " 871 "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 872 __func__, data, ombx[0], ombx[1], ombx[2], 873 ombx[3], ombx[4]); 874 } 875 876 break; 877 878 case 0x8130: 879 /* sfp insertion aen */ 880 device_printf(ha->pci_dev, "%s: sfp inserted [0x%08x]\n", 881 __func__, READ_REG32(ha, (Q8_FW_MBOX0 + 4))); 882 break; 883 884 case 0x8131: 885 /* sfp removal aen */ 886 device_printf(ha->pci_dev, "%s: sfp removed]\n", __func__); 887 break; 888 889 case 0x8140: 890 { 891 uint32_t ombx[3]; 892 893 ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4)); 894 ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8)); 895 ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12)); 896 897 device_printf(ha->pci_dev, "%s: " 898 "0x%08x 0x%08x 0x%08x 0x%08x \n", 899 __func__, data, ombx[0], ombx[1], ombx[2]); 900 } 901 break; 902 903 default: 904 device_printf(ha->pci_dev, "%s: AEN[0x%08x]\n", __func__, data); 905 break; 906 } 907 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); 908 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 909 return; 910 } 911 912 913 static void 914 qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp, uint32_t r_idx) 915 { 916 qla_rx_buf_t *rxb; 917 int count = sdsp->rx_free; 918 uint32_t rx_next; 919 qla_rdesc_t *rdesc; 920 921 /* we can play with this value via a sysctl */ 922 uint32_t replenish_thresh = ha->hw.rds_pidx_thres; 923 924 rdesc = &ha->hw.rds[r_idx]; 925 926 rx_next = rdesc->rx_next; 927 928 while (count--) { 929 rxb = sdsp->rxb_free; 930 931 if (rxb == NULL) 932 break; 933 934 sdsp->rxb_free = rxb->next; 935 sdsp->rx_free--; 936 937 if (ql_get_mbuf(ha, rxb, NULL) == 0) { 938 qla_set_hw_rcv_desc(ha, r_idx, rdesc->rx_in, 939 rxb->handle, 940 rxb->paddr, (rxb->m_head)->m_pkthdr.len); 941 rdesc->rx_in++; 942 if (rdesc->rx_in == NUM_RX_DESCRIPTORS) 943 rdesc->rx_in = 0; 944 rdesc->rx_next++; 945 if (rdesc->rx_next == NUM_RX_DESCRIPTORS) 946 rdesc->rx_next = 0; 947 } else { 948 device_printf(ha->pci_dev, 949 "%s: qla_get_mbuf [(%d),(%d),(%d)] failed\n", 950 __func__, r_idx, rdesc->rx_in, rxb->handle); 951 952 rxb->m_head = NULL; 953 rxb->next = sdsp->rxb_free; 954 sdsp->rxb_free = rxb; 955 sdsp->rx_free++; 956 957 break; 958 } 959 if (replenish_thresh-- == 0) { 960 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std, 961 rdesc->rx_next); 962 rx_next = rdesc->rx_next; 963 replenish_thresh = ha->hw.rds_pidx_thres; 964 } 965 } 966 967 if (rx_next != rdesc->rx_next) { 968 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std, 969 rdesc->rx_next); 970 } 971 } 972 973 void 974 ql_isr(void *arg) 975 { 976 qla_ivec_t *ivec = arg; 977 qla_host_t *ha ; 978 int idx; 979 qla_hw_t *hw; 980 struct ifnet *ifp; 981 qla_tx_fp_t *fp; 982 983 ha = ivec->ha; 984 hw = &ha->hw; 985 ifp = ha->ifp; 986 987 if ((idx = ivec->sds_idx) >= ha->hw.num_sds_rings) 988 return; 989 990 fp = &ha->tx_fp[idx]; 991 hw->sds[idx].intr_count++; 992 993 if ((fp->fp_taskqueue != NULL) && 994 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 995 taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task); 996 997 return; 998 } 999 1000