1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2016 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 /* 32 * File: ql_ioctl.h 33 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 34 */ 35 36 #ifndef _QL_IOCTL_H_ 37 #define _QL_IOCTL_H_ 38 39 #include <sys/ioccom.h> 40 41 struct qla_reg_val { 42 uint16_t rd; 43 uint16_t direct; 44 uint32_t reg; 45 uint32_t val; 46 }; 47 typedef struct qla_reg_val qla_reg_val_t; 48 49 struct qla_rd_flash { 50 uint32_t off; 51 uint32_t data; 52 }; 53 typedef struct qla_rd_flash qla_rd_flash_t; 54 55 struct qla_wr_flash { 56 uint32_t off; 57 uint32_t size; 58 void *buffer; 59 uint32_t pattern; 60 }; 61 typedef struct qla_wr_flash qla_wr_flash_t; 62 63 struct qla_erase_flash { 64 uint32_t off; 65 uint32_t size; 66 }; 67 typedef struct qla_erase_flash qla_erase_flash_t; 68 69 struct qla_rd_pci_ids { 70 uint16_t ven_id; 71 uint16_t dev_id; 72 uint16_t subsys_ven_id; 73 uint16_t subsys_dev_id; 74 uint8_t rev_id; 75 }; 76 typedef struct qla_rd_pci_ids qla_rd_pci_ids_t; 77 78 /* 79 * structure encapsulating the value to read/write from/to offchip (MS) memory 80 */ 81 struct qla_offchip_mem_val { 82 uint16_t rd; 83 uint64_t off; 84 uint32_t data_lo; 85 uint32_t data_hi; 86 uint32_t data_ulo; 87 uint32_t data_uhi; 88 }; 89 typedef struct qla_offchip_mem_val qla_offchip_mem_val_t; 90 91 struct qla_rd_fw_dump { 92 uint16_t pci_func; 93 uint32_t minidump_size; 94 void *minidump; 95 }; 96 typedef struct qla_rd_fw_dump qla_rd_fw_dump_t; 97 98 struct qla_drvr_state_tx { 99 uint64_t base_p_addr; 100 uint64_t cons_p_addr; 101 uint32_t tx_prod_reg; 102 uint32_t tx_cntxt_id; 103 uint32_t txr_free; 104 uint32_t txr_next; 105 uint32_t txr_comp; 106 }; 107 typedef struct qla_drvr_state_tx qla_drvr_state_tx_t; 108 109 struct qla_drvr_state_sds { 110 uint32_t sdsr_next; /* next entry in SDS ring to process */ 111 uint32_t sds_consumer; 112 }; 113 typedef struct qla_drvr_state_sds qla_drvr_state_sds_t; 114 115 struct qla_drvr_state_rx { 116 uint32_t prod_std; 117 uint32_t rx_next; /* next standard rcv ring to arm fw */; 118 }; 119 typedef struct qla_drvr_state_rx qla_drvr_state_rx_t; 120 121 struct qla_drvr_state_hdr { 122 uint32_t drvr_version_major; 123 uint32_t drvr_version_minor; 124 uint32_t drvr_version_build; 125 126 uint8_t mac_addr[ETHER_ADDR_LEN]; 127 uint16_t link_speed; 128 uint16_t cable_length; 129 uint32_t cable_oui; 130 uint8_t link_up; 131 uint8_t module_type; 132 uint8_t link_faults; 133 uint32_t rcv_intr_coalesce; 134 uint32_t xmt_intr_coalesce; 135 136 uint32_t tx_state_offset;/* size = sizeof (qla_drvr_state_tx_t) * num_tx_rings */ 137 uint32_t rx_state_offset;/* size = sizeof (qla_drvr_state_rx_t) * num_rx_rings */ 138 uint32_t sds_state_offset;/* size = sizeof (qla_drvr_state_sds_t) * num_sds_rings */ 139 140 uint32_t num_tx_rings; /* number of tx rings */ 141 uint32_t txr_size; /* size of each tx ring in bytes */ 142 uint32_t txr_entries; /* number of descriptors in each tx ring */ 143 uint32_t txr_offset; /* start of tx ring [0 - #rings] content */ 144 145 uint32_t num_rx_rings; /* number of rx rings */ 146 uint32_t rxr_size; /* size of each rx ring in bytes */ 147 uint32_t rxr_entries; /* number of descriptors in each rx ring */ 148 uint32_t rxr_offset; /* start of rx ring [0 - #rings] content */ 149 150 uint32_t num_sds_rings; /* number of sds rings */ 151 uint32_t sds_ring_size; /* size of each sds ring in bytes */ 152 uint32_t sds_entries; /* number of descriptors in each sds ring */ 153 uint32_t sds_offset; /* start of sds ring [0 - #rings] content */ 154 }; 155 156 typedef struct qla_drvr_state_hdr qla_drvr_state_hdr_t; 157 158 struct qla_driver_state { 159 uint32_t size; 160 void *buffer; 161 }; 162 typedef struct qla_driver_state qla_driver_state_t; 163 164 /* 165 * Read/Write Register 166 */ 167 #define QLA_RDWR_REG _IOWR('q', 1, qla_reg_val_t) 168 169 /* 170 * Read Flash 171 */ 172 #define QLA_RD_FLASH _IOWR('q', 2, qla_rd_flash_t) 173 174 /* 175 * Write Flash 176 */ 177 #define QLA_WR_FLASH _IOWR('q', 3, qla_wr_flash_t) 178 179 /* 180 * Read Offchip (MS) Memory 181 */ 182 #define QLA_RDWR_MS_MEM _IOWR('q', 4, qla_offchip_mem_val_t) 183 184 /* 185 * Erase Flash 186 */ 187 #define QLA_ERASE_FLASH _IOWR('q', 5, qla_erase_flash_t) 188 189 /* 190 * Read PCI IDs 191 */ 192 #define QLA_RD_PCI_IDS _IOWR('q', 6, qla_rd_pci_ids_t) 193 194 /* 195 * Read Minidump Template Size 196 */ 197 #define QLA_RD_FW_DUMP_SIZE _IOWR('q', 7, qla_rd_fw_dump_t) 198 199 /* 200 * Read Minidump Template 201 */ 202 #define QLA_RD_FW_DUMP _IOWR('q', 8, qla_rd_fw_dump_t) 203 204 /* 205 * Read Driver State 206 */ 207 #define QLA_RD_DRVR_STATE _IOWR('q', 9, qla_driver_state_t) 208 209 210 #endif /* #ifndef _QL_IOCTL_H_ */ 211