1 /* 2 * Copyright (c) 2013-2016 Qlogic Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 /* 30 * File: ql_ioctl.h 31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32 */ 33 34 #ifndef _QL_IOCTL_H_ 35 #define _QL_IOCTL_H_ 36 37 #include <sys/ioccom.h> 38 39 struct qla_reg_val { 40 uint16_t rd; 41 uint16_t direct; 42 uint32_t reg; 43 uint32_t val; 44 }; 45 typedef struct qla_reg_val qla_reg_val_t; 46 47 struct qla_rd_flash { 48 uint32_t off; 49 uint32_t data; 50 }; 51 typedef struct qla_rd_flash qla_rd_flash_t; 52 53 struct qla_wr_flash { 54 uint32_t off; 55 uint32_t size; 56 void *buffer; 57 uint32_t pattern; 58 }; 59 typedef struct qla_wr_flash qla_wr_flash_t; 60 61 struct qla_erase_flash { 62 uint32_t off; 63 uint32_t size; 64 }; 65 typedef struct qla_erase_flash qla_erase_flash_t; 66 67 struct qla_rd_pci_ids { 68 uint16_t ven_id; 69 uint16_t dev_id; 70 uint16_t subsys_ven_id; 71 uint16_t subsys_dev_id; 72 uint8_t rev_id; 73 }; 74 typedef struct qla_rd_pci_ids qla_rd_pci_ids_t; 75 76 /* 77 * structure encapsulating the value to read/write from/to offchip (MS) memory 78 */ 79 struct qla_offchip_mem_val { 80 uint16_t rd; 81 uint64_t off; 82 uint32_t data_lo; 83 uint32_t data_hi; 84 uint32_t data_ulo; 85 uint32_t data_uhi; 86 }; 87 typedef struct qla_offchip_mem_val qla_offchip_mem_val_t; 88 89 struct qla_rd_fw_dump { 90 uint16_t pci_func; 91 uint32_t minidump_size; 92 void *minidump; 93 }; 94 typedef struct qla_rd_fw_dump qla_rd_fw_dump_t; 95 96 struct qla_drvr_state_tx { 97 uint64_t base_p_addr; 98 uint64_t cons_p_addr; 99 uint32_t tx_prod_reg; 100 uint32_t tx_cntxt_id; 101 uint32_t txr_free; 102 uint32_t txr_next; 103 uint32_t txr_comp; 104 }; 105 typedef struct qla_drvr_state_tx qla_drvr_state_tx_t; 106 107 struct qla_drvr_state_sds { 108 uint32_t sdsr_next; /* next entry in SDS ring to process */ 109 uint32_t sds_consumer; 110 }; 111 typedef struct qla_drvr_state_sds qla_drvr_state_sds_t; 112 113 struct qla_drvr_state_rx { 114 uint32_t prod_std; 115 uint32_t rx_next; /* next standard rcv ring to arm fw */; 116 }; 117 typedef struct qla_drvr_state_rx qla_drvr_state_rx_t; 118 119 struct qla_drvr_state_hdr { 120 uint32_t drvr_version_major; 121 uint32_t drvr_version_minor; 122 uint32_t drvr_version_build; 123 124 uint8_t mac_addr[ETHER_ADDR_LEN]; 125 uint16_t link_speed; 126 uint16_t cable_length; 127 uint32_t cable_oui; 128 uint8_t link_up; 129 uint8_t module_type; 130 uint8_t link_faults; 131 uint32_t rcv_intr_coalesce; 132 uint32_t xmt_intr_coalesce; 133 134 uint32_t tx_state_offset;/* size = sizeof (qla_drvr_state_tx_t) * num_tx_rings */ 135 uint32_t rx_state_offset;/* size = sizeof (qla_drvr_state_rx_t) * num_rx_rings */ 136 uint32_t sds_state_offset;/* size = sizeof (qla_drvr_state_sds_t) * num_sds_rings */ 137 138 uint32_t num_tx_rings; /* number of tx rings */ 139 uint32_t txr_size; /* size of each tx ring in bytes */ 140 uint32_t txr_entries; /* number of descriptors in each tx ring */ 141 uint32_t txr_offset; /* start of tx ring [0 - #rings] content */ 142 143 uint32_t num_rx_rings; /* number of rx rings */ 144 uint32_t rxr_size; /* size of each rx ring in bytes */ 145 uint32_t rxr_entries; /* number of descriptors in each rx ring */ 146 uint32_t rxr_offset; /* start of rx ring [0 - #rings] content */ 147 148 uint32_t num_sds_rings; /* number of sds rings */ 149 uint32_t sds_ring_size; /* size of each sds ring in bytes */ 150 uint32_t sds_entries; /* number of descriptors in each sds ring */ 151 uint32_t sds_offset; /* start of sds ring [0 - #rings] content */ 152 }; 153 154 typedef struct qla_drvr_state_hdr qla_drvr_state_hdr_t; 155 156 struct qla_driver_state { 157 uint32_t size; 158 void *buffer; 159 }; 160 typedef struct qla_driver_state qla_driver_state_t; 161 162 /* 163 * Read/Write Register 164 */ 165 #define QLA_RDWR_REG _IOWR('q', 1, qla_reg_val_t) 166 167 /* 168 * Read Flash 169 */ 170 #define QLA_RD_FLASH _IOWR('q', 2, qla_rd_flash_t) 171 172 /* 173 * Write Flash 174 */ 175 #define QLA_WR_FLASH _IOWR('q', 3, qla_wr_flash_t) 176 177 /* 178 * Read Offchip (MS) Memory 179 */ 180 #define QLA_RDWR_MS_MEM _IOWR('q', 4, qla_offchip_mem_val_t) 181 182 /* 183 * Erase Flash 184 */ 185 #define QLA_ERASE_FLASH _IOWR('q', 5, qla_erase_flash_t) 186 187 /* 188 * Read PCI IDs 189 */ 190 #define QLA_RD_PCI_IDS _IOWR('q', 6, qla_rd_pci_ids_t) 191 192 /* 193 * Read Minidump Template Size 194 */ 195 #define QLA_RD_FW_DUMP_SIZE _IOWR('q', 7, qla_rd_fw_dump_t) 196 197 /* 198 * Read Minidump Template 199 */ 200 #define QLA_RD_FW_DUMP _IOWR('q', 8, qla_rd_fw_dump_t) 201 202 /* 203 * Read Driver State 204 */ 205 #define QLA_RD_DRVR_STATE _IOWR('q', 9, qla_driver_state_t) 206 207 208 #endif /* #ifndef _QL_IOCTL_H_ */ 209