1 /* 2 * Copyright (c) 2013-2016 Qlogic Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 /* 30 * File: ql_hw.h 31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32 */ 33 #ifndef _QL_HW_H_ 34 #define _QL_HW_H_ 35 36 /* 37 * PCIe Registers; Direct Mapped; Offsets from BAR0 38 */ 39 40 /* 41 * Register offsets for QLE8030 42 */ 43 44 /* 45 * Firmware Mailbox Registers 46 * 0 thru 511; offsets 0x800 thru 0xFFC; 32bits each 47 */ 48 #define Q8_FW_MBOX0 0x00000800 49 #define Q8_FW_MBOX511 0x00000FFC 50 51 /* 52 * Host Mailbox Registers 53 * 0 thru 511; offsets 0x000 thru 0x7FC; 32bits each 54 */ 55 #define Q8_HOST_MBOX0 0x00000000 56 #define Q8_HOST_MBOX511 0x000007FC 57 58 #define Q8_MBOX_INT_ENABLE 0x00001000 59 #define Q8_MBOX_INT_MASK_MSIX 0x00001200 60 #define Q8_MBOX_INT_LEGACY 0x00003010 61 62 #define Q8_HOST_MBOX_CNTRL 0x00003038 63 #define Q8_FW_MBOX_CNTRL 0x0000303C 64 65 #define Q8_PEG_HALT_STATUS1 0x000034A8 66 #define Q8_PEG_HALT_STATUS2 0x000034AC 67 #define Q8_FIRMWARE_HEARTBEAT 0x000034B0 68 69 #define Q8_FLASH_LOCK_ID 0x00003500 70 #define Q8_DRIVER_LOCK_ID 0x00003504 71 #define Q8_FW_CAPABILITIES 0x00003528 72 73 #define Q8_FW_VER_MAJOR 0x00003550 74 #define Q8_FW_VER_MINOR 0x00003554 75 #define Q8_FW_VER_SUB 0x00003558 76 77 #define Q8_BOOTLD_ADDR 0x0000355C 78 #define Q8_BOOTLD_SIZE 0x00003560 79 80 #define Q8_FW_IMAGE_ADDR 0x00003564 81 #define Q8_FW_BUILD_NUMBER 0x00003568 82 #define Q8_FW_IMAGE_VALID 0x000035FC 83 84 #define Q8_CMDPEG_STATE 0x00003650 85 86 #define Q8_LINK_STATE 0x00003698 87 #define Q8_LINK_STATE_2 0x0000369C 88 89 #define Q8_LINK_SPEED_0 0x000036E0 90 #define Q8_LINK_SPEED_1 0x000036E4 91 #define Q8_LINK_SPEED_2 0x000036E8 92 #define Q8_LINK_SPEED_3 0x000036EC 93 94 #define Q8_MAX_LINK_SPEED_0 0x000036F0 95 #define Q8_MAX_LINK_SPEED_1 0x000036F4 96 #define Q8_MAX_LINK_SPEED_2 0x000036F8 97 #define Q8_MAX_LINK_SPEED_3 0x000036FC 98 99 #define Q8_ASIC_TEMPERATURE 0x000037B4 100 101 /* 102 * CRB Window Registers 103 * 0 thru 15; offsets 0x3800 thru 0x383C; 32bits each 104 */ 105 #define Q8_CRB_WINDOW_PF0 0x00003800 106 #define Q8_CRB_WINDOW_PF15 0x0000383C 107 108 #define Q8_FLASH_LOCK 0x00003850 109 #define Q8_FLASH_UNLOCK 0x00003854 110 111 #define Q8_DRIVER_LOCK 0x00003868 112 #define Q8_DRIVER_UNLOCK 0x0000386C 113 114 #define Q8_LEGACY_INT_PTR 0x000038C0 115 #define Q8_LEGACY_INT_TRIG 0x000038C4 116 #define Q8_LEGACY_INT_MASK 0x000038C8 117 118 #define Q8_WILD_CARD 0x000038F0 119 #define Q8_INFORMANT 0x000038FC 120 121 /* 122 * Ethernet Interface Specific Registers 123 */ 124 #define Q8_DRIVER_OP_MODE 0x00003570 125 #define Q8_API_VERSION 0x0000356C 126 #define Q8_NPAR_STATE 0x0000359C 127 128 /* 129 * End of PCIe Registers; Direct Mapped; Offsets from BAR0 130 */ 131 132 /* 133 * Indirect Registers 134 */ 135 #define Q8_LED_DUAL_0 0x28084C80 136 #define Q8_LED_SINGLE_0 0x28084C90 137 138 #define Q8_LED_DUAL_1 0x28084CA0 139 #define Q8_LED_SINGLE_1 0x28084CB0 140 141 #define Q8_LED_DUAL_2 0x28084CC0 142 #define Q8_LED_SINGLE_2 0x28084CD0 143 144 #define Q8_LED_DUAL_3 0x28084CE0 145 #define Q8_LED_SINGLE_3 0x28084CF0 146 147 #define Q8_GPIO_1 0x28084D00 148 #define Q8_GPIO_2 0x28084D10 149 #define Q8_GPIO_3 0x28084D20 150 #define Q8_GPIO_4 0x28084D40 151 #define Q8_GPIO_5 0x28084D50 152 #define Q8_GPIO_6 0x28084D60 153 #define Q8_GPIO_7 0x42100060 154 #define Q8_GPIO_8 0x42100064 155 156 #define Q8_FLASH_SPI_STATUS 0x2808E010 157 #define Q8_FLASH_SPI_CONTROL 0x2808E014 158 159 #define Q8_FLASH_STATUS 0x42100004 160 #define Q8_FLASH_CONTROL 0x42110004 161 #define Q8_FLASH_ADDRESS 0x42110008 162 #define Q8_FLASH_WR_DATA 0x4211000C 163 #define Q8_FLASH_RD_DATA 0x42110018 164 165 #define Q8_FLASH_DIRECT_WINDOW 0x42110030 166 #define Q8_FLASH_DIRECT_DATA 0x42150000 167 168 #define Q8_MS_CNTRL 0x41000090 169 170 #define Q8_MS_ADDR_LO 0x41000094 171 #define Q8_MS_ADDR_HI 0x41000098 172 173 #define Q8_MS_WR_DATA_0_31 0x410000A0 174 #define Q8_MS_WR_DATA_32_63 0x410000A4 175 #define Q8_MS_WR_DATA_64_95 0x410000B0 176 #define Q8_MS_WR_DATA_96_127 0x410000B4 177 178 #define Q8_MS_RD_DATA_0_31 0x410000A8 179 #define Q8_MS_RD_DATA_32_63 0x410000AC 180 #define Q8_MS_RD_DATA_64_95 0x410000B8 181 #define Q8_MS_RD_DATA_96_127 0x410000BC 182 183 #define Q8_CRB_PEG_0 0x3400003c 184 #define Q8_CRB_PEG_1 0x3410003c 185 #define Q8_CRB_PEG_2 0x3420003c 186 #define Q8_CRB_PEG_3 0x3430003c 187 #define Q8_CRB_PEG_4 0x34B0003c 188 189 /* 190 * Macros for reading and writing registers 191 */ 192 193 #if defined(__i386__) || defined(__amd64__) 194 #define Q8_MB() __asm volatile("mfence" ::: "memory") 195 #define Q8_WMB() __asm volatile("sfence" ::: "memory") 196 #define Q8_RMB() __asm volatile("lfence" ::: "memory") 197 #else 198 #define Q8_MB() 199 #define Q8_WMB() 200 #define Q8_RMB() 201 #endif 202 203 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 204 205 #define WRITE_REG32(ha, reg, val) \ 206 {\ 207 bus_write_4((ha->pci_reg), reg, val);\ 208 bus_read_4((ha->pci_reg), reg);\ 209 } 210 211 #define Q8_NUM_MBOX 512 212 213 #define Q8_MAX_NUM_MULTICAST_ADDRS 1023 214 #define Q8_MAC_ADDR_LEN 6 215 216 /* 217 * Firmware Interface 218 */ 219 220 /* 221 * Command Response Interface - Commands 222 */ 223 224 #define Q8_MBX_CONFIG_IP_ADDRESS 0x0001 225 #define Q8_MBX_CONFIG_INTR 0x0002 226 #define Q8_MBX_MAP_INTR_SRC 0x0003 227 #define Q8_MBX_MAP_SDS_TO_RDS 0x0006 228 #define Q8_MBX_CREATE_RX_CNTXT 0x0007 229 #define Q8_MBX_DESTROY_RX_CNTXT 0x0008 230 #define Q8_MBX_CREATE_TX_CNTXT 0x0009 231 #define Q8_MBX_DESTROY_TX_CNTXT 0x000A 232 #define Q8_MBX_ADD_RX_RINGS 0x000B 233 #define Q8_MBX_CONFIG_LRO_FLOW 0x000C 234 #define Q8_MBX_CONFIG_MAC_LEARNING 0x000D 235 #define Q8_MBX_GET_STATS 0x000F 236 #define Q8_MBX_GENERATE_INTR 0x0011 237 #define Q8_MBX_SET_MAX_MTU 0x0012 238 #define Q8_MBX_MAC_ADDR_CNTRL 0x001F 239 #define Q8_MBX_GET_PCI_CONFIG 0x0020 240 #define Q8_MBX_GET_NIC_PARTITION 0x0021 241 #define Q8_MBX_SET_NIC_PARTITION 0x0022 242 #define Q8_MBX_QUERY_WOL_CAP 0x002C 243 #define Q8_MBX_SET_WOL_CONFIG 0x002D 244 #define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE 0x002F 245 #define Q8_MBX_GET_MINIDUMP_TMPLT 0x0030 246 #define Q8_MBX_GET_FW_DCBX_CAPS 0x0034 247 #define Q8_MBX_QUERY_DCBX_SETTINGS 0x0035 248 #define Q8_MBX_CONFIG_RSS 0x0041 249 #define Q8_MBX_CONFIG_RSS_TABLE 0x0042 250 #define Q8_MBX_CONFIG_INTR_COALESCE 0x0043 251 #define Q8_MBX_CONFIG_LED 0x0044 252 #define Q8_MBX_CONFIG_MAC_ADDR 0x0045 253 #define Q8_MBX_CONFIG_STATISTICS 0x0046 254 #define Q8_MBX_CONFIG_LOOPBACK 0x0047 255 #define Q8_MBX_LINK_EVENT_REQ 0x0048 256 #define Q8_MBX_CONFIG_MAC_RX_MODE 0x0049 257 #define Q8_MBX_CONFIG_FW_LRO 0x004A 258 #define Q8_MBX_INIT_NIC_FUNC 0x0060 259 #define Q8_MBX_STOP_NIC_FUNC 0x0061 260 #define Q8_MBX_IDC_REQ 0x0062 261 #define Q8_MBX_IDC_ACK 0x0063 262 #define Q8_MBX_SET_PORT_CONFIG 0x0066 263 #define Q8_MBX_GET_PORT_CONFIG 0x0067 264 #define Q8_MBX_GET_LINK_STATUS 0x0068 265 266 267 268 /* 269 * Mailbox Command Response 270 */ 271 #define Q8_MBX_RSP_SUCCESS 0x0001 272 #define Q8_MBX_RSP_RESPONSE_FAILURE 0x0002 273 #define Q8_MBX_RSP_NO_CARD_CRB 0x0003 274 #define Q8_MBX_RSP_NO_CARD_MEM 0x0004 275 #define Q8_MBX_RSP_NO_CARD_RSRC 0x0005 276 #define Q8_MBX_RSP_INVALID_ARGS 0x0006 277 #define Q8_MBX_RSP_INVALID_ACTION 0x0007 278 #define Q8_MBX_RSP_INVALID_STATE 0x0008 279 #define Q8_MBX_RSP_NOT_SUPPORTED 0x0009 280 #define Q8_MBX_RSP_NOT_PERMITTED 0x000A 281 #define Q8_MBX_RSP_NOT_READY 0x000B 282 #define Q8_MBX_RSP_DOES_NOT_EXIST 0x000C 283 #define Q8_MBX_RSP_ALREADY_EXISTS 0x000D 284 #define Q8_MBX_RSP_BAD_SIGNATURE 0x000E 285 #define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED 0x000F 286 #define Q8_MBX_RSP_CMD_INVALID 0x0010 287 #define Q8_MBX_RSP_TIMEOUT 0x0011 288 #define Q8_MBX_RSP_CMD_FAILED 0x0012 289 #define Q8_MBX_RSP_FATAL_TEMP 0x0013 290 #define Q8_MBX_RSP_MAX_EXCEEDED 0x0014 291 #define Q8_MBX_RSP_UNSPECIFIED 0x0015 292 #define Q8_MBX_RSP_INTR_CREATE_FAILED 0x0017 293 #define Q8_MBX_RSP_INTR_DELETE_FAILED 0x0018 294 #define Q8_MBX_RSP_INTR_INVALID_OP 0x0019 295 #define Q8_MBX_RSP_IDC_INTRMD_RSP 0x001A 296 297 #define Q8_MBX_CMD_VERSION (0x2 << 13) 298 #define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9)) 299 /* 300 * Configure IP Address 301 */ 302 typedef struct _q80_config_ip_addr { 303 uint16_t opcode; 304 uint16_t count_version; 305 306 uint8_t cmd; 307 #define Q8_MBX_CONFIG_IP_ADD_IP 0x1 308 #define Q8_MBX_CONFIG_IP_DEL_IP 0x2 309 310 uint8_t ip_type; 311 #define Q8_MBX_CONFIG_IP_V4 0x0 312 #define Q8_MBX_CONFIG_IP_V6 0x1 313 314 uint16_t rsrvd; 315 union { 316 struct { 317 uint32_t addr; 318 uint32_t rsrvd[3]; 319 } ipv4; 320 uint8_t ipv6_addr[16]; 321 } u; 322 } __packed q80_config_ip_addr_t; 323 324 typedef struct _q80_config_ip_addr_rsp { 325 uint16_t opcode; 326 uint16_t regcnt_status; 327 } __packed q80_config_ip_addr_rsp_t; 328 329 /* 330 * Configure Interrupt Command 331 */ 332 typedef struct _q80_intr { 333 uint8_t cmd_type; 334 #define Q8_MBX_CONFIG_INTR_CREATE 0x1 335 #define Q8_MBX_CONFIG_INTR_DELETE 0x2 336 #define Q8_MBX_CONFIG_INTR_TYPE_LINE (0x1 << 4) 337 #define Q8_MBX_CONFIG_INTR_TYPE_MSI_X (0x3 << 4) 338 339 uint8_t rsrvd; 340 uint16_t msix_index; 341 } __packed q80_intr_t; 342 343 #define Q8_MAX_INTR_VECTORS 16 344 typedef struct _q80_config_intr { 345 uint16_t opcode; 346 uint16_t count_version; 347 uint8_t nentries; 348 uint8_t rsrvd[3]; 349 q80_intr_t intr[Q8_MAX_INTR_VECTORS]; 350 } __packed q80_config_intr_t; 351 352 typedef struct _q80_intr_rsp { 353 uint8_t status; 354 uint8_t cmd; 355 uint16_t intr_id; 356 uint32_t intr_src; 357 } q80_intr_rsp_t; 358 359 typedef struct _q80_config_intr_rsp { 360 uint16_t opcode; 361 uint16_t regcnt_status; 362 uint8_t nentries; 363 uint8_t rsrvd[3]; 364 q80_intr_rsp_t intr[Q8_MAX_INTR_VECTORS]; 365 } __packed q80_config_intr_rsp_t; 366 367 /* 368 * Configure LRO Flow Command 369 */ 370 typedef struct _q80_config_lro_flow { 371 uint16_t opcode; 372 uint16_t count_version; 373 374 uint8_t cmd; 375 #define Q8_MBX_CONFIG_LRO_FLOW_ADD 0x01 376 #define Q8_MBX_CONFIG_LRO_FLOW_DELETE 0x02 377 378 uint8_t type_ts; 379 #define Q8_MBX_CONFIG_LRO_FLOW_IPV4 0x00 380 #define Q8_MBX_CONFIG_LRO_FLOW_IPV6 0x01 381 #define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT 0x00 382 #define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT 0x02 383 384 uint16_t rsrvd; 385 union { 386 struct { 387 uint32_t addr; 388 uint32_t rsrvd[3]; 389 } ipv4; 390 uint8_t ipv6_addr[16]; 391 } dst; 392 union { 393 struct { 394 uint32_t addr; 395 uint32_t rsrvd[3]; 396 } ipv4; 397 uint8_t ipv6_addr[16]; 398 } src; 399 uint16_t dst_port; 400 uint16_t src_port; 401 } __packed q80_config_lro_flow_t; 402 403 typedef struct _q80_config_lro_flow_rsp { 404 uint16_t opcode; 405 uint16_t regcnt_status; 406 } __packed q80_config_lro_flow_rsp_t; 407 408 typedef struct _q80_set_max_mtu { 409 uint16_t opcode; 410 uint16_t count_version; 411 uint32_t cntxt_id; 412 uint32_t mtu; 413 } __packed q80_set_max_mtu_t; 414 415 typedef struct _q80_set_max_mtu_rsp { 416 uint16_t opcode; 417 uint16_t regcnt_status; 418 } __packed q80_set_max_mtu_rsp_t; 419 420 /* 421 * Configure RSS 422 */ 423 typedef struct _q80_config_rss { 424 uint16_t opcode; 425 uint16_t count_version; 426 427 uint16_t cntxt_id; 428 uint16_t rsrvd; 429 430 uint8_t hash_type; 431 #define Q8_MBX_RSS_HASH_TYPE_IPV4_IP (0x1 << 4) 432 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP (0x2 << 4) 433 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4) 434 #define Q8_MBX_RSS_HASH_TYPE_IPV6_IP (0x1 << 6) 435 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP (0x2 << 6) 436 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6) 437 438 uint8_t flags; 439 #define Q8_MBX_RSS_FLAGS_ENABLE_RSS (0x1) 440 #define Q8_MBX_RSS_FLAGS_USE_IND_TABLE (0x2) 441 #define Q8_MBX_RSS_FLAGS_TYPE_CRSS (0x4) 442 443 uint16_t indtbl_mask; 444 #define Q8_MBX_RSS_INDTBL_MASK 0x7F 445 #define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID 0x8000 446 447 uint32_t multi_rss; 448 #define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN BIT_30 449 #define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES BIT_31 450 451 uint64_t rss_key[5]; 452 } __packed q80_config_rss_t; 453 454 typedef struct _q80_config_rss_rsp { 455 uint16_t opcode; 456 uint16_t regcnt_status; 457 } __packed q80_config_rss_rsp_t; 458 459 /* 460 * Configure RSS Indirection Table 461 */ 462 #define Q8_RSS_IND_TBL_SIZE 40 463 #define Q8_RSS_IND_TBL_MIN_IDX 0 464 #define Q8_RSS_IND_TBL_MAX_IDX 127 465 466 typedef struct _q80_config_rss_ind_table { 467 uint16_t opcode; 468 uint16_t count_version; 469 uint8_t start_idx; 470 uint8_t end_idx; 471 uint16_t cntxt_id; 472 uint8_t ind_table[Q8_RSS_IND_TBL_SIZE]; 473 } __packed q80_config_rss_ind_table_t; 474 475 typedef struct _q80_config_rss_ind_table_rsp { 476 uint16_t opcode; 477 uint16_t regcnt_status; 478 } __packed q80_config_rss_ind_table_rsp_t; 479 480 /* 481 * Configure Interrupt Coalescing and Generation 482 */ 483 typedef struct _q80_config_intr_coalesc { 484 uint16_t opcode; 485 uint16_t count_version; 486 uint16_t flags; 487 #define Q8_MBX_INTRC_FLAGS_RCV 1 488 #define Q8_MBX_INTRC_FLAGS_XMT 2 489 #define Q8_MBX_INTRC_FLAGS_PERIODIC (1 << 3) 490 491 uint16_t cntxt_id; 492 uint16_t max_pkts; 493 uint16_t max_mswait; 494 uint8_t timer_type; 495 #define Q8_MBX_INTRC_TIMER_NONE 0 496 #define Q8_MBX_INTRC_TIMER_SINGLE 1 497 #define Q8_MBX_INTRC_TIMER_PERIODIC 2 498 499 uint16_t sds_ring_mask; 500 501 uint8_t rsrvd; 502 uint32_t ms_timeout; 503 } __packed q80_config_intr_coalesc_t; 504 505 typedef struct _q80_config_intr_coalesc_rsp { 506 uint16_t opcode; 507 uint16_t regcnt_status; 508 } __packed q80_config_intr_coalesc_rsp_t; 509 510 /* 511 * Configure MAC Address 512 */ 513 typedef struct _q80_mac_addr { 514 uint8_t addr[6]; 515 uint16_t vlan_tci; 516 } __packed q80_mac_addr_t; 517 518 #define Q8_MAX_MAC_ADDRS 64 519 520 typedef struct _q80_config_mac_addr { 521 uint16_t opcode; 522 uint16_t count_version; 523 uint8_t cmd; 524 #define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR 1 525 #define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR 2 526 527 #define Q8_MBX_CMAC_CMD_CAM_BOTH (0x0 << 6) 528 #define Q8_MBX_CMAC_CMD_CAM_INGRESS (0x1 << 6) 529 #define Q8_MBX_CMAC_CMD_CAM_EGRESS (0x2 << 6) 530 531 uint8_t nmac_entries; 532 uint16_t cntxt_id; 533 q80_mac_addr_t mac_addr[Q8_MAX_MAC_ADDRS]; 534 } __packed q80_config_mac_addr_t; 535 536 typedef struct _q80_config_mac_addr_rsp { 537 uint16_t opcode; 538 uint16_t regcnt_status; 539 uint8_t cmd; 540 uint8_t nmac_entries; 541 uint16_t cntxt_id; 542 uint32_t status[Q8_MAX_MAC_ADDRS]; 543 } __packed q80_config_mac_addr_rsp_t; 544 545 /* 546 * Configure MAC Receive Mode 547 */ 548 typedef struct _q80_config_mac_rcv_mode { 549 uint16_t opcode; 550 uint16_t count_version; 551 552 uint8_t mode; 553 #define Q8_MBX_MAC_RCV_PROMISC_ENABLE 0x1 554 #define Q8_MBX_MAC_ALL_MULTI_ENABLE 0x2 555 556 uint8_t rsrvd; 557 uint16_t cntxt_id; 558 } __packed q80_config_mac_rcv_mode_t; 559 560 typedef struct _q80_config_mac_rcv_mode_rsp { 561 uint16_t opcode; 562 uint16_t regcnt_status; 563 } __packed q80_config_mac_rcv_mode_rsp_t; 564 565 /* 566 * Configure Firmware Controlled LRO 567 */ 568 typedef struct _q80_config_fw_lro { 569 uint16_t opcode; 570 uint16_t count_version; 571 572 uint8_t flags; 573 #define Q8_MBX_FW_LRO_IPV4 0x1 574 #define Q8_MBX_FW_LRO_IPV6 0x2 575 #define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK 0x4 576 #define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK 0x8 577 #define Q8_MBX_FW_LRO_LOW_THRESHOLD 0x10 578 579 uint8_t rsrvd; 580 uint16_t cntxt_id; 581 582 uint16_t low_threshold; 583 uint16_t rsrvd0; 584 } __packed q80_config_fw_lro_t; 585 586 typedef struct _q80_config_fw_lro_rsp { 587 uint16_t opcode; 588 uint16_t regcnt_status; 589 } __packed q80_config_fw_lro_rsp_t; 590 591 /* 592 * Minidump mailbox commands 593 */ 594 typedef struct _q80_config_md_templ_size { 595 uint16_t opcode; 596 uint16_t count_version; 597 } __packed q80_config_md_templ_size_t; 598 599 typedef struct _q80_config_md_templ_size_rsp { 600 uint16_t opcode; 601 uint16_t regcnt_status; 602 uint32_t rsrvd; 603 uint32_t templ_size; 604 uint32_t templ_version; 605 } __packed q80_config_md_templ_size_rsp_t; 606 607 typedef struct _q80_config_md_templ_cmd { 608 uint16_t opcode; 609 uint16_t count_version; 610 uint64_t buf_addr; /* physical address of buffer */ 611 uint32_t buff_size; 612 uint32_t offset; 613 } __packed q80_config_md_templ_cmd_t; 614 615 typedef struct _q80_config_md_templ_cmd_rsp { 616 uint16_t opcode; 617 uint16_t regcnt_status; 618 uint32_t rsrvd; 619 uint32_t templ_size; 620 uint32_t buff_size; 621 uint32_t offset; 622 } __packed q80_config_md_templ_cmd_rsp_t; 623 624 /* 625 * Link Event Request Command 626 */ 627 typedef struct _q80_link_event { 628 uint16_t opcode; 629 uint16_t count_version; 630 uint8_t cmd; 631 #define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0 632 #define Q8_LINK_EVENT_CMD_ENABLE_ASYNC 1 633 634 uint8_t flags; 635 #define Q8_LINK_EVENT_FLAGS_SEND_RSP 1 636 637 uint16_t cntxt_id; 638 } __packed q80_link_event_t; 639 640 typedef struct _q80_link_event_rsp { 641 uint16_t opcode; 642 uint16_t regcnt_status; 643 } __packed q80_link_event_rsp_t; 644 645 /* 646 * Get Statistics Command 647 */ 648 typedef struct _q80_rcv_stats { 649 uint64_t total_bytes; 650 uint64_t total_pkts; 651 uint64_t lro_pkt_count; 652 uint64_t sw_pkt_count; 653 uint64_t ip_chksum_err; 654 uint64_t pkts_wo_acntxts; 655 uint64_t pkts_dropped_no_sds_card; 656 uint64_t pkts_dropped_no_sds_host; 657 uint64_t oversized_pkts; 658 uint64_t pkts_dropped_no_rds; 659 uint64_t unxpctd_mcast_pkts; 660 uint64_t re1_fbq_error; 661 uint64_t invalid_mac_addr; 662 uint64_t rds_prime_trys; 663 uint64_t rds_prime_success; 664 uint64_t lro_flows_added; 665 uint64_t lro_flows_deleted; 666 uint64_t lro_flows_active; 667 uint64_t pkts_droped_unknown; 668 } __packed q80_rcv_stats_t; 669 670 typedef struct _q80_xmt_stats { 671 uint64_t total_bytes; 672 uint64_t total_pkts; 673 uint64_t errors; 674 uint64_t pkts_dropped; 675 uint64_t switch_pkts; 676 uint64_t num_buffers; 677 } __packed q80_xmt_stats_t; 678 679 typedef struct _q80_mac_stats { 680 uint64_t xmt_frames; 681 uint64_t xmt_bytes; 682 uint64_t xmt_mcast_pkts; 683 uint64_t xmt_bcast_pkts; 684 uint64_t xmt_pause_frames; 685 uint64_t xmt_cntrl_pkts; 686 uint64_t xmt_pkt_lt_64bytes; 687 uint64_t xmt_pkt_lt_127bytes; 688 uint64_t xmt_pkt_lt_255bytes; 689 uint64_t xmt_pkt_lt_511bytes; 690 uint64_t xmt_pkt_lt_1023bytes; 691 uint64_t xmt_pkt_lt_1518bytes; 692 uint64_t xmt_pkt_gt_1518bytes; 693 uint64_t rsrvd0[3]; 694 uint64_t rcv_frames; 695 uint64_t rcv_bytes; 696 uint64_t rcv_mcast_pkts; 697 uint64_t rcv_bcast_pkts; 698 uint64_t rcv_pause_frames; 699 uint64_t rcv_cntrl_pkts; 700 uint64_t rcv_pkt_lt_64bytes; 701 uint64_t rcv_pkt_lt_127bytes; 702 uint64_t rcv_pkt_lt_255bytes; 703 uint64_t rcv_pkt_lt_511bytes; 704 uint64_t rcv_pkt_lt_1023bytes; 705 uint64_t rcv_pkt_lt_1518bytes; 706 uint64_t rcv_pkt_gt_1518bytes; 707 uint64_t rsrvd1[3]; 708 uint64_t rcv_len_error; 709 uint64_t rcv_len_small; 710 uint64_t rcv_len_large; 711 uint64_t rcv_jabber; 712 uint64_t rcv_dropped; 713 uint64_t fcs_error; 714 uint64_t align_error; 715 uint64_t eswitched_frames; 716 uint64_t eswitched_bytes; 717 uint64_t eswitched_mcast_frames; 718 uint64_t eswitched_bcast_frames; 719 uint64_t eswitched_ucast_frames; 720 uint64_t eswitched_err_free_frames; 721 uint64_t eswitched_err_free_bytes; 722 } __packed q80_mac_stats_t; 723 724 typedef struct _q80_get_stats { 725 uint16_t opcode; 726 uint16_t count_version; 727 728 uint32_t cmd; 729 #define Q8_GET_STATS_CMD_CLEAR 0x01 730 #define Q8_GET_STATS_CMD_RCV 0x00 731 #define Q8_GET_STATS_CMD_XMT 0x02 732 #define Q8_GET_STATS_CMD_TYPE_CNTXT 0x00 733 #define Q8_GET_STATS_CMD_TYPE_MAC 0x04 734 #define Q8_GET_STATS_CMD_TYPE_FUNC 0x08 735 #define Q8_GET_STATS_CMD_TYPE_VPORT 0x0C 736 #define Q8_GET_STATS_CMD_TYPE_ALL (0x7 << 2) 737 738 } __packed q80_get_stats_t; 739 740 typedef struct _q80_get_stats_rsp { 741 uint16_t opcode; 742 uint16_t regcnt_status; 743 uint32_t cmd; 744 union { 745 q80_rcv_stats_t rcv; 746 q80_xmt_stats_t xmt; 747 q80_mac_stats_t mac; 748 } u; 749 } __packed q80_get_stats_rsp_t; 750 751 typedef struct _q80_get_mac_rcv_xmt_stats_rsp { 752 uint16_t opcode; 753 uint16_t regcnt_status; 754 uint32_t cmd; 755 q80_mac_stats_t mac; 756 q80_rcv_stats_t rcv; 757 q80_xmt_stats_t xmt; 758 } __packed q80_get_mac_rcv_xmt_stats_rsp_t; 759 760 /* 761 * Init NIC Function 762 * Used to Register DCBX Configuration Change AEN 763 */ 764 typedef struct _q80_init_nic_func { 765 uint16_t opcode; 766 uint16_t count_version; 767 768 uint32_t options; 769 #define Q8_INIT_NIC_REG_IDC_AEN 0x01 770 #define Q8_INIT_NIC_REG_DCBX_CHNG_AEN 0x02 771 #define Q8_INIT_NIC_REG_SFP_CHNG_AEN 0x04 772 773 } __packed q80_init_nic_func_t; 774 775 typedef struct _q80_init_nic_func_rsp { 776 uint16_t opcode; 777 uint16_t regcnt_status; 778 } __packed q80_init_nic_func_rsp_t; 779 780 /* 781 * Stop NIC Function 782 * Used to DeRegister DCBX Configuration Change AEN 783 */ 784 typedef struct _q80_stop_nic_func { 785 uint16_t opcode; 786 uint16_t count_version; 787 788 uint32_t options; 789 #define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02 790 #define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN 0x04 791 792 } __packed q80_stop_nic_func_t; 793 794 typedef struct _q80_stop_nic_func_rsp { 795 uint16_t opcode; 796 uint16_t regcnt_status; 797 } __packed q80_stop_nic_func_rsp_t; 798 799 /* 800 * Query Firmware DCBX Capabilities 801 */ 802 typedef struct _q80_query_fw_dcbx_caps { 803 uint16_t opcode; 804 uint16_t count_version; 805 } __packed q80_query_fw_dcbx_caps_t; 806 807 typedef struct _q80_query_fw_dcbx_caps_rsp { 808 uint16_t opcode; 809 uint16_t regcnt_status; 810 811 uint32_t dcbx_caps; 812 #define Q8_QUERY_FW_DCBX_CAPS_TSA 0x00000001 813 #define Q8_QUERY_FW_DCBX_CAPS_ETS 0x00000002 814 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01 0x00000004 815 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0 0x00000008 816 #define Q8_QUERY_FW_DCBX_MAX_TC_MASK 0x00F00000 817 #define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK 0x0F000000 818 #define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK 0xF0000000 819 820 } __packed q80_query_fw_dcbx_caps_rsp_t; 821 822 /* 823 * IDC Ack Cmd 824 */ 825 826 typedef struct _q80_idc_ack { 827 uint16_t opcode; 828 uint16_t count_version; 829 830 uint32_t aen_mb1; 831 uint32_t aen_mb2; 832 uint32_t aen_mb3; 833 uint32_t aen_mb4; 834 835 } __packed q80_idc_ack_t; 836 837 typedef struct _q80_idc_ack_rsp { 838 uint16_t opcode; 839 uint16_t regcnt_status; 840 } __packed q80_idc_ack_rsp_t; 841 842 843 /* 844 * Set Port Configuration command 845 * Used to set Ethernet Standard Pause values 846 */ 847 848 typedef struct _q80_set_port_cfg { 849 uint16_t opcode; 850 uint16_t count_version; 851 852 uint32_t cfg_bits; 853 854 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK (0x7 << 1) 855 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE (0x0 << 1) 856 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS (0x2 << 1) 857 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY (0x3 << 1) 858 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT (0x4 << 1) 859 860 #define Q8_VALID_LOOPBACK_MODE(mode) \ 861 (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \ 862 (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \ 863 ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT))) 864 865 #define Q8_PORT_CFG_BITS_DCBX_ENABLE BIT_4 866 867 #define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 5) 868 #define Q8_PORT_CFG_BITS_PAUSE_DISABLED (0x0 << 5) 869 #define Q8_PORT_CFG_BITS_PAUSE_STD (0x1 << 5) 870 #define Q8_PORT_CFG_BITS_PAUSE_PPM (0x2 << 5) 871 872 #define Q8_PORT_CFG_BITS_LNKCAP_10MB BIT_8 873 #define Q8_PORT_CFG_BITS_LNKCAP_100MB BIT_9 874 #define Q8_PORT_CFG_BITS_LNKCAP_1GB BIT_10 875 #define Q8_PORT_CFG_BITS_LNKCAP_10GB BIT_11 876 877 #define Q8_PORT_CFG_BITS_AUTONEG BIT_15 878 #define Q8_PORT_CFG_BITS_XMT_DISABLE BIT_17 879 #define Q8_PORT_CFG_BITS_FEC_RQSTD BIT_18 880 #define Q8_PORT_CFG_BITS_EEE_RQSTD BIT_19 881 882 #define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) 883 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV (0x0 << 20) 884 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) 885 #define Q8_PORT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) 886 887 } __packed q80_set_port_cfg_t; 888 889 typedef struct _q80_set_port_cfg_rsp { 890 uint16_t opcode; 891 uint16_t regcnt_status; 892 } __packed q80_set_port_cfg_rsp_t; 893 894 /* 895 * Get Port Configuration Command 896 */ 897 898 typedef struct _q80_get_port_cfg { 899 uint16_t opcode; 900 uint16_t count_version; 901 } __packed q80_get_port_cfg_t; 902 903 typedef struct _q80_get_port_cfg_rsp { 904 uint16_t opcode; 905 uint16_t regcnt_status; 906 907 uint32_t cfg_bits; /* same as in q80_set_port_cfg_t */ 908 909 uint8_t phys_port_type; 910 uint8_t rsvd[3]; 911 } __packed q80_get_port_cfg_rsp_t; 912 913 /* 914 * Get Link Status Command 915 * Used to get current PAUSE values for the port 916 */ 917 918 typedef struct _q80_get_link_status { 919 uint16_t opcode; 920 uint16_t count_version; 921 } __packed q80_get_link_status_t; 922 923 typedef struct _q80_get_link_status_rsp { 924 uint16_t opcode; 925 uint16_t regcnt_status; 926 927 uint32_t cfg_bits; 928 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP BIT_0 929 930 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK (0x7 << 3) 931 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN (0x0 << 3) 932 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB (0x1 << 3) 933 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB (0x2 << 3) 934 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB (0x3 << 3) 935 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB (0x4 << 3) 936 937 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 6) 938 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE (0x0 << 6) 939 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD (0x1 << 6) 940 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM (0x2 << 6) 941 942 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK (0x7 << 8) 943 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE (0x0 << 6) 944 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS (0x2 << 6) 945 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY (0x3 << 6) 946 947 #define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED BIT_12 948 #define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED BIT_13 949 950 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) 951 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE (0x0 << 20) 952 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) 953 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) 954 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV (0x3 << 20) 955 956 uint32_t link_state; 957 #define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL BIT_0 958 #define Q8_GET_LINK_STAT_PORT_RST_DONE BIT_3 959 #define Q8_GET_LINK_STAT_PHY_LINK_DOWN BIT_4 960 #define Q8_GET_LINK_STAT_PCS_LINK_DOWN BIT_5 961 #define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT BIT_6 962 #define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT BIT_7 963 #define Q8_GET_LINK_STAT_XMT_DISABLED BIT_9 964 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 965 966 uint32_t sfp_info; 967 #define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK 0x3 968 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED 0x0 969 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE 0x1 970 #define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID 0x2 971 #define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID 0x3 972 973 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK (0x3 << 2) 974 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR (0x0 << 2) 975 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC (0x1 << 2) 976 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED (0x2 << 2) 977 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR (0x3 << 2) 978 979 #define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK (0x1F << 4) 980 #define Q8_GET_LINK_STAT_SFP_MOD_NONE (0x00 << 4) 981 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM (0x01 << 4) 982 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLR (0x02 << 4) 983 #define Q8_GET_LINK_STAT_SFP_MOD_10GBSR (0x03 << 4) 984 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P (0x04 << 4) 985 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL (0x05 << 4) 986 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL (0x06 << 4) 987 #define Q8_GET_LINK_STAT_SFP_MOD_1GBSX (0x07 << 4) 988 #define Q8_GET_LINK_STAT_SFP_MOD_1GBLX (0x08 << 4) 989 #define Q8_GET_LINK_STAT_SFP_MOD_1GBCX (0x09 << 4) 990 #define Q8_GET_LINK_STAT_SFP_MOD_1GBT (0x0A << 4) 991 #define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL (0x0B << 4) 992 #define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN (0x0F << 4) 993 994 #define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD BIT_9 995 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 996 #define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK (0xFF << 16) 997 998 } __packed q80_get_link_status_rsp_t; 999 1000 1001 /* 1002 * Transmit Related Definitions 1003 */ 1004 /* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/ 1005 #define MAX_TCNTXT_RINGS 8 1006 1007 /* 1008 * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data 1009 */ 1010 1011 typedef struct _q80_rq_tx_ring { 1012 uint64_t paddr; 1013 uint64_t tx_consumer; 1014 uint16_t nentries; 1015 uint16_t intr_id; 1016 uint8_t intr_src_bit; 1017 uint8_t rsrvd[3]; 1018 } __packed q80_rq_tx_ring_t; 1019 1020 typedef struct _q80_rq_tx_cntxt { 1021 uint16_t opcode; 1022 uint16_t count_version; 1023 1024 uint32_t cap0; 1025 #define Q8_TX_CNTXT_CAP0_BASEFW (1 << 0) 1026 #define Q8_TX_CNTXT_CAP0_LSO (1 << 6) 1027 #define Q8_TX_CNTXT_CAP0_TC (1 << 25) 1028 1029 uint32_t cap1; 1030 uint32_t cap2; 1031 uint32_t cap3; 1032 uint8_t ntx_rings; 1033 uint8_t traffic_class; /* bits 8-10; others reserved */ 1034 uint16_t tx_vpid; 1035 q80_rq_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; 1036 } __packed q80_rq_tx_cntxt_t; 1037 1038 typedef struct _q80_rsp_tx_ring { 1039 uint32_t prod_index; 1040 uint16_t cntxt_id; 1041 uint8_t state; 1042 uint8_t rsrvd; 1043 } q80_rsp_tx_ring_t; 1044 1045 typedef struct _q80_rsp_tx_cntxt { 1046 uint16_t opcode; 1047 uint16_t regcnt_status; 1048 uint8_t ntx_rings; 1049 uint8_t phy_port; 1050 uint8_t virt_port; 1051 uint8_t rsrvd; 1052 q80_rsp_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; 1053 } __packed q80_rsp_tx_cntxt_t; 1054 1055 typedef struct _q80_tx_cntxt_destroy { 1056 uint16_t opcode; 1057 uint16_t count_version; 1058 uint32_t cntxt_id; 1059 } __packed q80_tx_cntxt_destroy_t; 1060 1061 typedef struct _q80_tx_cntxt_destroy_rsp { 1062 uint16_t opcode; 1063 uint16_t regcnt_status; 1064 } __packed q80_tx_cntxt_destroy_rsp_t; 1065 1066 /* 1067 * Transmit Command Descriptor 1068 * These commands are issued on the Transmit Ring associated with a Transmit 1069 * context 1070 */ 1071 typedef struct _q80_tx_cmd { 1072 uint8_t tcp_hdr_off; /* TCP Header Offset */ 1073 uint8_t ip_hdr_off; /* IP Header Offset */ 1074 uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */ 1075 1076 /* flags field */ 1077 #define Q8_TX_CMD_FLAGS_MULTICAST 0x01 1078 #define Q8_TX_CMD_FLAGS_LSO_TSO 0x02 1079 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10 1080 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40 1081 1082 /* opcode field */ 1083 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7) 1084 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7) 1085 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7) 1086 #define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7) 1087 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7) 1088 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7) 1089 #define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7) 1090 1091 uint8_t n_bufs; /* # of data segs in data buffer */ 1092 uint8_t data_len_lo; /* data length lower 8 bits */ 1093 uint16_t data_len_hi; /* data length upper 16 bits */ 1094 1095 uint64_t buf2_addr; /* buffer 2 address */ 1096 1097 uint16_t rsrvd0; 1098 uint16_t mss; /* MSS for this packet */ 1099 uint8_t cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */ 1100 1101 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4) 1102 1103 uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */ 1104 uint16_t rsrvd1; 1105 1106 uint64_t buf3_addr; /* buffer 3 address */ 1107 uint64_t buf1_addr; /* buffer 1 address */ 1108 1109 uint16_t buf1_len; /* length of buffer 1 */ 1110 uint16_t buf2_len; /* length of buffer 2 */ 1111 uint16_t buf3_len; /* length of buffer 3 */ 1112 uint16_t buf4_len; /* length of buffer 4 */ 1113 1114 uint64_t buf4_addr; /* buffer 4 address */ 1115 1116 uint32_t rsrvd2; 1117 uint16_t rsrvd3; 1118 uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/ 1119 1120 } __packed q80_tx_cmd_t; /* 64 bytes */ 1121 1122 #define Q8_TX_CMD_MAX_SEGMENTS 4 1123 #define Q8_TX_CMD_TSO_ALIGN 2 1124 #define Q8_TX_MAX_NON_TSO_SEGS 62 1125 1126 1127 /* 1128 * Receive Related Definitions 1129 */ 1130 #define MAX_RDS_RING_SETS 8 /* Max# of Receive Descriptor Rings */ 1131 1132 #ifdef QL_ENABLE_ISCSI_TLV 1133 #define MAX_SDS_RINGS 32 /* Max# of Status Descriptor Rings */ 1134 #define NUM_TX_RINGS (MAX_SDS_RINGS * 2) 1135 #else 1136 #define MAX_SDS_RINGS 4 /* Max# of Status Descriptor Rings */ 1137 #define NUM_TX_RINGS MAX_SDS_RINGS 1138 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */ 1139 #define MAX_RDS_RINGS MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */ 1140 1141 1142 typedef struct _q80_rq_sds_ring { 1143 uint64_t paddr; /* physical addr of status ring in system memory */ 1144 uint64_t hdr_split1; 1145 uint64_t hdr_split2; 1146 uint16_t size; /* number of entries in status ring */ 1147 uint16_t hdr_split1_size; 1148 uint16_t hdr_split2_size; 1149 uint16_t hdr_split_count; 1150 uint16_t intr_id; 1151 uint8_t intr_src_bit; 1152 uint8_t rsrvd[5]; 1153 } __packed q80_rq_sds_ring_t; /* 10 32bit words */ 1154 1155 typedef struct _q80_rq_rds_ring { 1156 uint64_t paddr_std; /* physical addr of rcv ring in system memory */ 1157 uint64_t paddr_jumbo; /* physical addr of rcv ring in system memory */ 1158 uint16_t std_bsize; 1159 uint16_t std_nentries; 1160 uint16_t jumbo_bsize; 1161 uint16_t jumbo_nentries; 1162 } __packed q80_rq_rds_ring_t; /* 6 32bit words */ 1163 1164 #define MAX_RCNTXT_SDS_RINGS 8 1165 1166 typedef struct _q80_rq_rcv_cntxt { 1167 uint16_t opcode; 1168 uint16_t count_version; 1169 uint32_t cap0; 1170 #define Q8_RCV_CNTXT_CAP0_BASEFW (1 << 0) 1171 #define Q8_RCV_CNTXT_CAP0_MULTI_RDS (1 << 1) 1172 #define Q8_RCV_CNTXT_CAP0_LRO (1 << 5) 1173 #define Q8_RCV_CNTXT_CAP0_HW_LRO (1 << 10) 1174 #define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN (1 << 14) 1175 #define Q8_RCV_CNTXT_CAP0_RSS (1 << 15) 1176 #define Q8_RCV_CNTXT_CAP0_MSFT_RSS (1 << 16) 1177 #define Q8_RCV_CNTXT_CAP0_SGL_JUMBO (1 << 18) 1178 #define Q8_RCV_CNTXT_CAP0_SGL_LRO (1 << 19) 1179 #define Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO (1 << 26) 1180 1181 uint32_t cap1; 1182 uint32_t cap2; 1183 uint32_t cap3; 1184 uint8_t nrds_sets_rings; 1185 uint8_t nsds_rings; 1186 uint16_t rds_producer_mode; 1187 #define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE 0 1188 #define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED 1 1189 1190 uint16_t rcv_vpid; 1191 uint16_t rsrvd0; 1192 uint32_t rsrvd1; 1193 q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; 1194 q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; 1195 } __packed q80_rq_rcv_cntxt_t; 1196 1197 typedef struct _q80_rsp_rds_ring { 1198 uint32_t prod_std; 1199 uint32_t prod_jumbo; 1200 } __packed q80_rsp_rds_ring_t; /* 8 bytes */ 1201 1202 typedef struct _q80_rsp_rcv_cntxt { 1203 uint16_t opcode; 1204 uint16_t regcnt_status; 1205 uint8_t nrds_sets_rings; 1206 uint8_t nsds_rings; 1207 uint16_t cntxt_id; 1208 uint8_t state; 1209 uint8_t num_funcs; 1210 uint8_t phy_port; 1211 uint8_t virt_port; 1212 uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; 1213 q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; 1214 } __packed q80_rsp_rcv_cntxt_t; 1215 1216 typedef struct _q80_rcv_cntxt_destroy { 1217 uint16_t opcode; 1218 uint16_t count_version; 1219 uint32_t cntxt_id; 1220 } __packed q80_rcv_cntxt_destroy_t; 1221 1222 typedef struct _q80_rcv_cntxt_destroy_rsp { 1223 uint16_t opcode; 1224 uint16_t regcnt_status; 1225 } __packed q80_rcv_cntxt_destroy_rsp_t; 1226 1227 1228 /* 1229 * Add Receive Rings 1230 */ 1231 typedef struct _q80_rq_add_rcv_rings { 1232 uint16_t opcode; 1233 uint16_t count_version; 1234 uint8_t nrds_sets_rings; 1235 uint8_t nsds_rings; 1236 uint16_t cntxt_id; 1237 q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; 1238 q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; 1239 } __packed q80_rq_add_rcv_rings_t; 1240 1241 typedef struct _q80_rsp_add_rcv_rings { 1242 uint16_t opcode; 1243 uint16_t regcnt_status; 1244 uint8_t nrds_sets_rings; 1245 uint8_t nsds_rings; 1246 uint16_t cntxt_id; 1247 uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; 1248 q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; 1249 } __packed q80_rsp_add_rcv_rings_t; 1250 1251 /* 1252 * Map Status Ring to Receive Descriptor Set 1253 */ 1254 1255 #define MAX_SDS_TO_RDS_MAP 16 1256 1257 typedef struct _q80_sds_rds_map_e { 1258 uint8_t sds_ring; 1259 uint8_t rsrvd0; 1260 uint8_t rds_ring; 1261 uint8_t rsrvd1; 1262 } __packed q80_sds_rds_map_e_t; 1263 1264 typedef struct _q80_rq_map_sds_to_rds { 1265 uint16_t opcode; 1266 uint16_t count_version; 1267 uint16_t cntxt_id; 1268 uint16_t num_rings; 1269 q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; 1270 } __packed q80_rq_map_sds_to_rds_t; 1271 1272 1273 typedef struct _q80_rsp_map_sds_to_rds { 1274 uint16_t opcode; 1275 uint16_t regcnt_status; 1276 uint16_t cntxt_id; 1277 uint16_t num_rings; 1278 q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; 1279 } __packed q80_rsp_map_sds_to_rds_t; 1280 1281 1282 /* 1283 * Receive Descriptor corresponding to each entry in the receive ring 1284 */ 1285 typedef struct _q80_rcv_desc { 1286 uint16_t handle; 1287 uint16_t rsrvd; 1288 uint32_t buf_size; /* buffer size in bytes */ 1289 uint64_t buf_addr; /* physical address of buffer */ 1290 } __packed q80_recv_desc_t; 1291 1292 /* 1293 * Status Descriptor corresponding to each entry in the Status ring 1294 */ 1295 typedef struct _q80_stat_desc { 1296 uint64_t data[2]; 1297 } __packed q80_stat_desc_t; 1298 1299 /* 1300 * definitions for data[0] field of Status Descriptor 1301 */ 1302 #define Q8_STAT_DESC_RSS_HASH(data) (data & 0xFFFFFFFF) 1303 #define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 32) & 0x3FFF) 1304 #define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF) 1305 #define Q8_STAT_DESC_HANDLE(data) ((data >> 48) & 0xFFFF) 1306 /* 1307 * definitions for data[1] field of Status Descriptor 1308 */ 1309 1310 #define Q8_STAT_DESC_OPCODE(data) ((data >> 42) & 0xF) 1311 #define Q8_STAT_DESC_OPCODE_RCV_PKT 0x01 1312 #define Q8_STAT_DESC_OPCODE_LRO_PKT 0x02 1313 #define Q8_STAT_DESC_OPCODE_SGL_LRO 0x04 1314 #define Q8_STAT_DESC_OPCODE_SGL_RCV 0x05 1315 #define Q8_STAT_DESC_OPCODE_CONT 0x06 1316 1317 /* 1318 * definitions for data[1] field of Status Descriptor for standard frames 1319 * status descriptor opcode equals 0x04 1320 */ 1321 #define Q8_STAT_DESC_STATUS(data) ((data >> 39) & 0x0007) 1322 #define Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE 0x00 1323 #define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01 1324 #define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02 1325 #define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03 1326 1327 #define Q8_STAT_DESC_VLAN(data) ((data >> 47) & 1) 1328 #define Q8_STAT_DESC_VLAN_ID(data) ((data >> 48) & 0xFFFF) 1329 1330 #define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F) 1331 #define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F) 1332 #define Q8_STAT_DESC_COUNT(data) ((data >> 37) & 0x0007) 1333 1334 /* 1335 * definitions for data[0-1] fields of Status Descriptor for LRO 1336 * status descriptor opcode equals 0x04 1337 */ 1338 1339 /* definitions for data[1] field */ 1340 #define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data) 1341 1342 /* 1343 * definitions specific to opcode 0x04 data[1] 1344 */ 1345 #define Q8_STAT_DESC_COUNT_SGL_LRO(data) ((data >> 13) & 0x0007) 1346 #define Q8_SGL_LRO_STAT_L2_OFFSET(data) ((data >> 16) & 0xFF) 1347 #define Q8_SGL_LRO_STAT_L4_OFFSET(data) ((data >> 24) & 0xFF) 1348 #define Q8_SGL_LRO_STAT_TS(data) ((data >> 40) & 0x1) 1349 #define Q8_SGL_LRO_STAT_PUSH_BIT(data) ((data >> 41) & 0x1) 1350 1351 1352 /* 1353 * definitions specific to opcode 0x05 data[1] 1354 */ 1355 #define Q8_STAT_DESC_COUNT_SGL_RCV(data) ((data >> 37) & 0x0003) 1356 1357 /* 1358 * definitions for opcode 0x06 1359 */ 1360 /* definitions for data[0] field */ 1361 #define Q8_SGL_STAT_DESC_HANDLE1(data) (data & 0xFFFF) 1362 #define Q8_SGL_STAT_DESC_HANDLE2(data) ((data >> 16) & 0xFFFF) 1363 #define Q8_SGL_STAT_DESC_HANDLE3(data) ((data >> 32) & 0xFFFF) 1364 #define Q8_SGL_STAT_DESC_HANDLE4(data) ((data >> 48) & 0xFFFF) 1365 1366 /* definitions for data[1] field */ 1367 #define Q8_SGL_STAT_DESC_HANDLE5(data) (data & 0xFFFF) 1368 #define Q8_SGL_STAT_DESC_HANDLE6(data) ((data >> 16) & 0xFFFF) 1369 #define Q8_SGL_STAT_DESC_NUM_HANDLES(data) ((data >> 32) & 0x7) 1370 #define Q8_SGL_STAT_DESC_HANDLE7(data) ((data >> 48) & 0xFFFF) 1371 1372 /** Driver Related Definitions Begin **/ 1373 1374 #define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */ 1375 1376 /* The number of descriptors should be a power of 2 */ 1377 #define NUM_TX_DESCRIPTORS 1024 1378 #define NUM_STATUS_DESCRIPTORS 1024 1379 1380 1381 #define NUM_RX_DESCRIPTORS 2048 1382 1383 /* 1384 * structure describing various dma buffers 1385 */ 1386 1387 typedef struct qla_dmabuf { 1388 volatile struct { 1389 uint32_t tx_ring :1, 1390 rds_ring :1, 1391 sds_ring :1, 1392 minidump :1; 1393 } flags; 1394 1395 qla_dma_t tx_ring; 1396 qla_dma_t rds_ring[MAX_RDS_RINGS]; 1397 qla_dma_t sds_ring[MAX_SDS_RINGS]; 1398 qla_dma_t minidump; 1399 } qla_dmabuf_t; 1400 1401 typedef struct _qla_sds { 1402 q80_stat_desc_t *sds_ring_base; /* start of sds ring */ 1403 uint32_t sdsr_next; /* next entry in SDS ring to process */ 1404 struct lro_ctrl lro; 1405 void *rxb_free; 1406 uint32_t rx_free; 1407 volatile uint32_t rcv_active; 1408 uint32_t sds_consumer; 1409 uint64_t intr_count; 1410 } qla_sds_t; 1411 1412 #define Q8_MAX_LRO_CONT_DESC 7 1413 #define Q8_MAX_HANDLES_LRO (1 + (Q8_MAX_LRO_CONT_DESC * 7)) 1414 #define Q8_MAX_HANDLES_NON_LRO 8 1415 1416 typedef struct _qla_sgl_rcv { 1417 uint16_t pkt_length; 1418 uint16_t num_handles; 1419 uint16_t chksum_status; 1420 uint32_t rss_hash; 1421 uint16_t rss_hash_flags; 1422 uint16_t vlan_tag; 1423 uint16_t handle[Q8_MAX_HANDLES_NON_LRO]; 1424 } qla_sgl_rcv_t; 1425 1426 typedef struct _qla_sgl_lro { 1427 uint16_t flags; 1428 #define Q8_LRO_COMP_TS 0x1 1429 #define Q8_LRO_COMP_PUSH_BIT 0x2 1430 uint16_t l2_offset; 1431 uint16_t l4_offset; 1432 1433 uint16_t payload_length; 1434 uint16_t num_handles; 1435 uint32_t rss_hash; 1436 uint16_t rss_hash_flags; 1437 uint16_t vlan_tag; 1438 uint16_t handle[Q8_MAX_HANDLES_LRO]; 1439 } qla_sgl_lro_t; 1440 1441 typedef union { 1442 qla_sgl_rcv_t rcv; 1443 qla_sgl_lro_t lro; 1444 } qla_sgl_comp_t; 1445 1446 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\ 1447 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16) 1448 1449 typedef struct _qla_hw_tx_cntxt { 1450 q80_tx_cmd_t *tx_ring_base; 1451 bus_addr_t tx_ring_paddr; 1452 1453 volatile uint32_t *tx_cons; /* tx consumer shadow reg */ 1454 bus_addr_t tx_cons_paddr; 1455 1456 volatile uint32_t txr_free; /* # of free entries in tx ring */ 1457 volatile uint32_t txr_next; /* # next available tx ring entry */ 1458 volatile uint32_t txr_comp; /* index of last tx entry completed */ 1459 1460 uint32_t tx_prod_reg; 1461 uint16_t tx_cntxt_id; 1462 uint8_t frame_hdr[QL_FRAME_HDR_SIZE]; 1463 1464 } qla_hw_tx_cntxt_t; 1465 1466 typedef struct _qla_mcast { 1467 uint16_t rsrvd; 1468 uint8_t addr[6]; 1469 } __packed qla_mcast_t; 1470 1471 typedef struct _qla_rdesc { 1472 volatile uint32_t prod_std; 1473 volatile uint32_t prod_jumbo; 1474 volatile uint32_t rx_next; /* next standard rcv ring to arm fw */ 1475 volatile int32_t rx_in; /* next standard rcv ring to add mbufs */ 1476 volatile uint64_t count; 1477 } qla_rdesc_t; 1478 1479 typedef struct _qla_flash_desc_table { 1480 uint32_t flash_valid; 1481 uint16_t flash_ver; 1482 uint16_t flash_len; 1483 uint16_t flash_cksum; 1484 uint16_t flash_unused; 1485 uint8_t flash_model[16]; 1486 uint16_t flash_manuf; 1487 uint16_t flash_id; 1488 uint8_t flash_flag; 1489 uint8_t erase_cmd; 1490 uint8_t alt_erase_cmd; 1491 uint8_t write_enable_cmd; 1492 uint8_t write_enable_bits; 1493 uint8_t write_statusreg_cmd; 1494 uint8_t unprotected_sec_cmd; 1495 uint8_t read_manuf_cmd; 1496 uint32_t block_size; 1497 uint32_t alt_block_size; 1498 uint32_t flash_size; 1499 uint32_t write_enable_data; 1500 uint8_t readid_addr_len; 1501 uint8_t write_disable_bits; 1502 uint8_t read_dev_id_len; 1503 uint8_t chip_erase_cmd; 1504 uint16_t read_timeo; 1505 uint8_t protected_sec_cmd; 1506 uint8_t resvd[65]; 1507 } __packed qla_flash_desc_table_t; 1508 1509 /* 1510 * struct for storing hardware specific information for a given interface 1511 */ 1512 typedef struct _qla_hw { 1513 struct { 1514 uint32_t 1515 unicast_mac :1, 1516 bcast_mac :1, 1517 loopback_mode :2, 1518 init_tx_cnxt :1, 1519 init_rx_cnxt :1, 1520 init_intr_cnxt :1, 1521 fduplex :1, 1522 autoneg :1, 1523 fdt_valid :1; 1524 } flags; 1525 1526 1527 uint16_t link_speed; 1528 uint16_t cable_length; 1529 uint32_t cable_oui; 1530 uint8_t link_up; 1531 uint8_t module_type; 1532 uint8_t link_faults; 1533 1534 uint8_t mac_rcv_mode; 1535 1536 uint32_t max_mtu; 1537 1538 uint8_t mac_addr[ETHER_ADDR_LEN]; 1539 1540 uint32_t num_sds_rings; 1541 uint32_t num_rds_rings; 1542 uint32_t num_tx_rings; 1543 1544 qla_dmabuf_t dma_buf; 1545 1546 /* Transmit Side */ 1547 1548 qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS]; 1549 1550 /* Receive Side */ 1551 1552 uint16_t rcv_cntxt_id; 1553 1554 uint32_t mbx_intr_mask_offset; 1555 1556 uint16_t intr_id[MAX_SDS_RINGS]; 1557 uint32_t intr_src[MAX_SDS_RINGS]; 1558 1559 qla_sds_t sds[MAX_SDS_RINGS]; 1560 uint32_t mbox[Q8_NUM_MBOX]; 1561 qla_rdesc_t rds[MAX_RDS_RINGS]; 1562 1563 uint32_t rds_pidx_thres; 1564 uint32_t sds_cidx_thres; 1565 1566 uint32_t rcv_intr_coalesce; 1567 uint32_t xmt_intr_coalesce; 1568 1569 /* Immediate Completion */ 1570 volatile uint32_t imd_compl; 1571 volatile uint32_t aen_mb0; 1572 volatile uint32_t aen_mb1; 1573 volatile uint32_t aen_mb2; 1574 volatile uint32_t aen_mb3; 1575 volatile uint32_t aen_mb4; 1576 1577 /* multicast address list */ 1578 uint32_t nmcast; 1579 qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS]; 1580 1581 /* reset sequence */ 1582 #define Q8_MAX_RESET_SEQ_IDX 16 1583 uint32_t rst_seq[Q8_MAX_RESET_SEQ_IDX]; 1584 uint32_t rst_seq_idx; 1585 1586 /* heart beat register value */ 1587 uint32_t hbeat_value; 1588 uint32_t health_count; 1589 1590 uint32_t max_tx_segs; 1591 uint32_t min_lro_pkt_size; 1592 1593 uint32_t enable_9kb; 1594 1595 uint32_t user_pri_nic; 1596 uint32_t user_pri_iscsi; 1597 uint64_t iscsi_pkt_count; 1598 1599 /* Flash Descriptor Table */ 1600 qla_flash_desc_table_t fdt; 1601 1602 /* Minidump Related */ 1603 uint32_t mdump_init; 1604 uint32_t mdump_start; 1605 uint32_t mdump_active; 1606 uint32_t mdump_start_seq_index; 1607 } qla_hw_t; 1608 1609 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \ 1610 bus_write_4((ha->pci_reg), prod_reg, val); 1611 1612 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \ 1613 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val) 1614 1615 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \ 1616 bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val); 1617 1618 #define QL_ENABLE_INTERRUPTS(ha, i) \ 1619 bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0); 1620 1621 #define QL_BUFFER_ALIGN 16 1622 1623 1624 /* 1625 * Flash Configuration 1626 */ 1627 #define Q8_BOARD_CONFIG_OFFSET 0x370000 1628 #define Q8_BOARD_CONFIG_LENGTH 0x2000 1629 1630 #define Q8_BOARD_CONFIG_MAC0_LO 0x400 1631 1632 #define Q8_FDT_LOCK_MAGIC_ID 0x00FD00FD 1633 #define Q8_FDT_FLASH_ADDR_VAL 0xFD009F 1634 #define Q8_FDT_FLASH_CTRL_VAL 0x3F 1635 #define Q8_FDT_MASK_VAL 0xFF 1636 1637 #define Q8_WR_ENABLE_FL_ADDR 0xFD0100 1638 #define Q8_WR_ENABLE_FL_CTRL 0x5 1639 1640 #define Q8_ERASE_LOCK_MAGIC_ID 0x00EF00EF 1641 #define Q8_ERASE_FL_ADDR_MASK 0xFD0300 1642 #define Q8_ERASE_FL_CTRL_MASK 0x3D 1643 1644 #define Q8_WR_FL_LOCK_MAGIC_ID 0xABCDABCD 1645 #define Q8_WR_FL_ADDR_MASK 0x800000 1646 #define Q8_WR_FL_CTRL_MASK 0x3D 1647 1648 #define QL_FDT_OFFSET 0x3F0000 1649 #define Q8_FLASH_SECTOR_SIZE 0x10000 1650 1651 /* 1652 * Off Chip Memory Access 1653 */ 1654 1655 typedef struct _q80_offchip_mem_val { 1656 uint32_t data_lo; 1657 uint32_t data_hi; 1658 uint32_t data_ulo; 1659 uint32_t data_uhi; 1660 } q80_offchip_mem_val_t; 1661 1662 #endif /* #ifndef _QL_HW_H_ */ 1663