1 /* 2 * Copyright (c) 2013-2016 Qlogic Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * File: ql_hw.c 30 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 31 * Content: Contains Hardware dependent functions 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "ql_os.h" 38 #include "ql_hw.h" 39 #include "ql_def.h" 40 #include "ql_inline.h" 41 #include "ql_ver.h" 42 #include "ql_glbl.h" 43 #include "ql_dbg.h" 44 #include "ql_minidump.h" 45 46 /* 47 * Static Functions 48 */ 49 50 static void qla_del_rcv_cntxt(qla_host_t *ha); 51 static int qla_init_rcv_cntxt(qla_host_t *ha); 52 static void qla_del_xmt_cntxt(qla_host_t *ha); 53 static int qla_init_xmt_cntxt(qla_host_t *ha); 54 static int qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox, 55 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause); 56 static int qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, 57 uint32_t num_intrs, uint32_t create); 58 static int qla_config_rss(qla_host_t *ha, uint16_t cntxt_id); 59 static int qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, 60 int tenable, int rcv); 61 static int qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode); 62 static int qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id); 63 64 static int qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, 65 uint8_t *hdr); 66 static int qla_hw_add_all_mcast(qla_host_t *ha); 67 static int qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds); 68 69 static int qla_init_nic_func(qla_host_t *ha); 70 static int qla_stop_nic_func(qla_host_t *ha); 71 static int qla_query_fw_dcbx_caps(qla_host_t *ha); 72 static int qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits); 73 static int qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits); 74 static int qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode); 75 static int qla_get_cam_search_mode(qla_host_t *ha); 76 77 static void ql_minidump_free(qla_host_t *ha); 78 79 #ifdef QL_DBG 80 81 static void 82 qla_stop_pegs(qla_host_t *ha) 83 { 84 uint32_t val = 1; 85 86 ql_rdwr_indreg32(ha, Q8_CRB_PEG_0, &val, 0); 87 ql_rdwr_indreg32(ha, Q8_CRB_PEG_1, &val, 0); 88 ql_rdwr_indreg32(ha, Q8_CRB_PEG_2, &val, 0); 89 ql_rdwr_indreg32(ha, Q8_CRB_PEG_3, &val, 0); 90 ql_rdwr_indreg32(ha, Q8_CRB_PEG_4, &val, 0); 91 device_printf(ha->pci_dev, "%s PEGS HALTED!!!!!\n", __func__); 92 } 93 94 static int 95 qla_sysctl_stop_pegs(SYSCTL_HANDLER_ARGS) 96 { 97 int err, ret = 0; 98 qla_host_t *ha; 99 100 err = sysctl_handle_int(oidp, &ret, 0, req); 101 102 103 if (err || !req->newptr) 104 return (err); 105 106 if (ret == 1) { 107 ha = (qla_host_t *)arg1; 108 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 109 qla_stop_pegs(ha); 110 QLA_UNLOCK(ha, __func__); 111 } 112 } 113 114 return err; 115 } 116 #endif /* #ifdef QL_DBG */ 117 118 static int 119 qla_validate_set_port_cfg_bit(uint32_t bits) 120 { 121 if ((bits & 0xF) > 1) 122 return (-1); 123 124 if (((bits >> 4) & 0xF) > 2) 125 return (-1); 126 127 if (((bits >> 8) & 0xF) > 2) 128 return (-1); 129 130 return (0); 131 } 132 133 static int 134 qla_sysctl_port_cfg(SYSCTL_HANDLER_ARGS) 135 { 136 int err, ret = 0; 137 qla_host_t *ha; 138 uint32_t cfg_bits; 139 140 err = sysctl_handle_int(oidp, &ret, 0, req); 141 142 if (err || !req->newptr) 143 return (err); 144 145 ha = (qla_host_t *)arg1; 146 147 if ((qla_validate_set_port_cfg_bit((uint32_t)ret) == 0)) { 148 149 err = qla_get_port_config(ha, &cfg_bits); 150 151 if (err) 152 goto qla_sysctl_set_port_cfg_exit; 153 154 if (ret & 0x1) { 155 cfg_bits |= Q8_PORT_CFG_BITS_DCBX_ENABLE; 156 } else { 157 cfg_bits &= ~Q8_PORT_CFG_BITS_DCBX_ENABLE; 158 } 159 160 ret = ret >> 4; 161 cfg_bits &= ~Q8_PORT_CFG_BITS_PAUSE_CFG_MASK; 162 163 if ((ret & 0xF) == 0) { 164 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_DISABLED; 165 } else if ((ret & 0xF) == 1){ 166 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_STD; 167 } else { 168 cfg_bits |= Q8_PORT_CFG_BITS_PAUSE_PPM; 169 } 170 171 ret = ret >> 4; 172 cfg_bits &= ~Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK; 173 174 if (ret == 0) { 175 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV; 176 } else if (ret == 1){ 177 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_XMT; 178 } else { 179 cfg_bits |= Q8_PORT_CFG_BITS_STDPAUSE_RCV; 180 } 181 182 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 183 err = qla_set_port_config(ha, cfg_bits); 184 QLA_UNLOCK(ha, __func__); 185 } else { 186 device_printf(ha->pci_dev, "%s: failed\n", __func__); 187 } 188 } else { 189 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 190 err = qla_get_port_config(ha, &cfg_bits); 191 QLA_UNLOCK(ha, __func__); 192 } else { 193 device_printf(ha->pci_dev, "%s: failed\n", __func__); 194 } 195 } 196 197 qla_sysctl_set_port_cfg_exit: 198 return err; 199 } 200 201 static int 202 qla_sysctl_set_cam_search_mode(SYSCTL_HANDLER_ARGS) 203 { 204 int err, ret = 0; 205 qla_host_t *ha; 206 207 err = sysctl_handle_int(oidp, &ret, 0, req); 208 209 if (err || !req->newptr) 210 return (err); 211 212 ha = (qla_host_t *)arg1; 213 214 if ((ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL) || 215 (ret == Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO)) { 216 217 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 218 err = qla_set_cam_search_mode(ha, (uint32_t)ret); 219 QLA_UNLOCK(ha, __func__); 220 } else { 221 device_printf(ha->pci_dev, "%s: failed\n", __func__); 222 } 223 224 } else { 225 device_printf(ha->pci_dev, "%s: ret = %d\n", __func__, ret); 226 } 227 228 return (err); 229 } 230 231 static int 232 qla_sysctl_get_cam_search_mode(SYSCTL_HANDLER_ARGS) 233 { 234 int err, ret = 0; 235 qla_host_t *ha; 236 237 err = sysctl_handle_int(oidp, &ret, 0, req); 238 239 if (err || !req->newptr) 240 return (err); 241 242 ha = (qla_host_t *)arg1; 243 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { 244 err = qla_get_cam_search_mode(ha); 245 QLA_UNLOCK(ha, __func__); 246 } else { 247 device_printf(ha->pci_dev, "%s: failed\n", __func__); 248 } 249 250 return (err); 251 } 252 253 static void 254 qlnx_add_hw_mac_stats_sysctls(qla_host_t *ha) 255 { 256 struct sysctl_ctx_list *ctx; 257 struct sysctl_oid_list *children; 258 struct sysctl_oid *ctx_oid; 259 260 ctx = device_get_sysctl_ctx(ha->pci_dev); 261 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 262 263 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_mac", 264 CTLFLAG_RD, NULL, "stats_hw_mac"); 265 children = SYSCTL_CHILDREN(ctx_oid); 266 267 SYSCTL_ADD_QUAD(ctx, children, 268 OID_AUTO, "xmt_frames", 269 CTLFLAG_RD, &ha->hw.mac.xmt_frames, 270 "xmt_frames"); 271 272 SYSCTL_ADD_QUAD(ctx, children, 273 OID_AUTO, "xmt_bytes", 274 CTLFLAG_RD, &ha->hw.mac.xmt_bytes, 275 "xmt_frames"); 276 277 SYSCTL_ADD_QUAD(ctx, children, 278 OID_AUTO, "xmt_mcast_pkts", 279 CTLFLAG_RD, &ha->hw.mac.xmt_mcast_pkts, 280 "xmt_mcast_pkts"); 281 282 SYSCTL_ADD_QUAD(ctx, children, 283 OID_AUTO, "xmt_bcast_pkts", 284 CTLFLAG_RD, &ha->hw.mac.xmt_bcast_pkts, 285 "xmt_bcast_pkts"); 286 287 SYSCTL_ADD_QUAD(ctx, children, 288 OID_AUTO, "xmt_pause_frames", 289 CTLFLAG_RD, &ha->hw.mac.xmt_pause_frames, 290 "xmt_pause_frames"); 291 292 SYSCTL_ADD_QUAD(ctx, children, 293 OID_AUTO, "xmt_cntrl_pkts", 294 CTLFLAG_RD, &ha->hw.mac.xmt_cntrl_pkts, 295 "xmt_cntrl_pkts"); 296 297 SYSCTL_ADD_QUAD(ctx, children, 298 OID_AUTO, "xmt_pkt_lt_64bytes", 299 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_64bytes, 300 "xmt_pkt_lt_64bytes"); 301 302 SYSCTL_ADD_QUAD(ctx, children, 303 OID_AUTO, "xmt_pkt_lt_127bytes", 304 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_127bytes, 305 "xmt_pkt_lt_127bytes"); 306 307 SYSCTL_ADD_QUAD(ctx, children, 308 OID_AUTO, "xmt_pkt_lt_255bytes", 309 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_255bytes, 310 "xmt_pkt_lt_255bytes"); 311 312 SYSCTL_ADD_QUAD(ctx, children, 313 OID_AUTO, "xmt_pkt_lt_511bytes", 314 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_511bytes, 315 "xmt_pkt_lt_511bytes"); 316 317 SYSCTL_ADD_QUAD(ctx, children, 318 OID_AUTO, "xmt_pkt_lt_1023bytes", 319 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1023bytes, 320 "xmt_pkt_lt_1023bytes"); 321 322 SYSCTL_ADD_QUAD(ctx, children, 323 OID_AUTO, "xmt_pkt_lt_1518bytes", 324 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_lt_1518bytes, 325 "xmt_pkt_lt_1518bytes"); 326 327 SYSCTL_ADD_QUAD(ctx, children, 328 OID_AUTO, "xmt_pkt_gt_1518bytes", 329 CTLFLAG_RD, &ha->hw.mac.xmt_pkt_gt_1518bytes, 330 "xmt_pkt_gt_1518bytes"); 331 332 SYSCTL_ADD_QUAD(ctx, children, 333 OID_AUTO, "rcv_frames", 334 CTLFLAG_RD, &ha->hw.mac.rcv_frames, 335 "rcv_frames"); 336 337 SYSCTL_ADD_QUAD(ctx, children, 338 OID_AUTO, "rcv_bytes", 339 CTLFLAG_RD, &ha->hw.mac.rcv_bytes, 340 "rcv_bytes"); 341 342 SYSCTL_ADD_QUAD(ctx, children, 343 OID_AUTO, "rcv_mcast_pkts", 344 CTLFLAG_RD, &ha->hw.mac.rcv_mcast_pkts, 345 "rcv_mcast_pkts"); 346 347 SYSCTL_ADD_QUAD(ctx, children, 348 OID_AUTO, "rcv_bcast_pkts", 349 CTLFLAG_RD, &ha->hw.mac.rcv_bcast_pkts, 350 "rcv_bcast_pkts"); 351 352 SYSCTL_ADD_QUAD(ctx, children, 353 OID_AUTO, "rcv_pause_frames", 354 CTLFLAG_RD, &ha->hw.mac.rcv_pause_frames, 355 "rcv_pause_frames"); 356 357 SYSCTL_ADD_QUAD(ctx, children, 358 OID_AUTO, "rcv_cntrl_pkts", 359 CTLFLAG_RD, &ha->hw.mac.rcv_cntrl_pkts, 360 "rcv_cntrl_pkts"); 361 362 SYSCTL_ADD_QUAD(ctx, children, 363 OID_AUTO, "rcv_pkt_lt_64bytes", 364 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_64bytes, 365 "rcv_pkt_lt_64bytes"); 366 367 SYSCTL_ADD_QUAD(ctx, children, 368 OID_AUTO, "rcv_pkt_lt_127bytes", 369 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_127bytes, 370 "rcv_pkt_lt_127bytes"); 371 372 SYSCTL_ADD_QUAD(ctx, children, 373 OID_AUTO, "rcv_pkt_lt_255bytes", 374 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_255bytes, 375 "rcv_pkt_lt_255bytes"); 376 377 SYSCTL_ADD_QUAD(ctx, children, 378 OID_AUTO, "rcv_pkt_lt_511bytes", 379 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_511bytes, 380 "rcv_pkt_lt_511bytes"); 381 382 SYSCTL_ADD_QUAD(ctx, children, 383 OID_AUTO, "rcv_pkt_lt_1023bytes", 384 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1023bytes, 385 "rcv_pkt_lt_1023bytes"); 386 387 SYSCTL_ADD_QUAD(ctx, children, 388 OID_AUTO, "rcv_pkt_lt_1518bytes", 389 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_lt_1518bytes, 390 "rcv_pkt_lt_1518bytes"); 391 392 SYSCTL_ADD_QUAD(ctx, children, 393 OID_AUTO, "rcv_pkt_gt_1518bytes", 394 CTLFLAG_RD, &ha->hw.mac.rcv_pkt_gt_1518bytes, 395 "rcv_pkt_gt_1518bytes"); 396 397 SYSCTL_ADD_QUAD(ctx, children, 398 OID_AUTO, "rcv_len_error", 399 CTLFLAG_RD, &ha->hw.mac.rcv_len_error, 400 "rcv_len_error"); 401 402 SYSCTL_ADD_QUAD(ctx, children, 403 OID_AUTO, "rcv_len_small", 404 CTLFLAG_RD, &ha->hw.mac.rcv_len_small, 405 "rcv_len_small"); 406 407 SYSCTL_ADD_QUAD(ctx, children, 408 OID_AUTO, "rcv_len_large", 409 CTLFLAG_RD, &ha->hw.mac.rcv_len_large, 410 "rcv_len_large"); 411 412 SYSCTL_ADD_QUAD(ctx, children, 413 OID_AUTO, "rcv_jabber", 414 CTLFLAG_RD, &ha->hw.mac.rcv_jabber, 415 "rcv_jabber"); 416 417 SYSCTL_ADD_QUAD(ctx, children, 418 OID_AUTO, "rcv_dropped", 419 CTLFLAG_RD, &ha->hw.mac.rcv_dropped, 420 "rcv_dropped"); 421 422 SYSCTL_ADD_QUAD(ctx, children, 423 OID_AUTO, "fcs_error", 424 CTLFLAG_RD, &ha->hw.mac.fcs_error, 425 "fcs_error"); 426 427 SYSCTL_ADD_QUAD(ctx, children, 428 OID_AUTO, "align_error", 429 CTLFLAG_RD, &ha->hw.mac.align_error, 430 "align_error"); 431 432 SYSCTL_ADD_QUAD(ctx, children, 433 OID_AUTO, "eswitched_frames", 434 CTLFLAG_RD, &ha->hw.mac.eswitched_frames, 435 "eswitched_frames"); 436 437 SYSCTL_ADD_QUAD(ctx, children, 438 OID_AUTO, "eswitched_bytes", 439 CTLFLAG_RD, &ha->hw.mac.eswitched_bytes, 440 "eswitched_bytes"); 441 442 SYSCTL_ADD_QUAD(ctx, children, 443 OID_AUTO, "eswitched_mcast_frames", 444 CTLFLAG_RD, &ha->hw.mac.eswitched_mcast_frames, 445 "eswitched_mcast_frames"); 446 447 SYSCTL_ADD_QUAD(ctx, children, 448 OID_AUTO, "eswitched_bcast_frames", 449 CTLFLAG_RD, &ha->hw.mac.eswitched_bcast_frames, 450 "eswitched_bcast_frames"); 451 452 SYSCTL_ADD_QUAD(ctx, children, 453 OID_AUTO, "eswitched_ucast_frames", 454 CTLFLAG_RD, &ha->hw.mac.eswitched_ucast_frames, 455 "eswitched_ucast_frames"); 456 457 SYSCTL_ADD_QUAD(ctx, children, 458 OID_AUTO, "eswitched_err_free_frames", 459 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_frames, 460 "eswitched_err_free_frames"); 461 462 SYSCTL_ADD_QUAD(ctx, children, 463 OID_AUTO, "eswitched_err_free_bytes", 464 CTLFLAG_RD, &ha->hw.mac.eswitched_err_free_bytes, 465 "eswitched_err_free_bytes"); 466 467 return; 468 } 469 470 static void 471 qlnx_add_hw_rcv_stats_sysctls(qla_host_t *ha) 472 { 473 struct sysctl_ctx_list *ctx; 474 struct sysctl_oid_list *children; 475 struct sysctl_oid *ctx_oid; 476 477 ctx = device_get_sysctl_ctx(ha->pci_dev); 478 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 479 480 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_rcv", 481 CTLFLAG_RD, NULL, "stats_hw_rcv"); 482 children = SYSCTL_CHILDREN(ctx_oid); 483 484 SYSCTL_ADD_QUAD(ctx, children, 485 OID_AUTO, "total_bytes", 486 CTLFLAG_RD, &ha->hw.rcv.total_bytes, 487 "total_bytes"); 488 489 SYSCTL_ADD_QUAD(ctx, children, 490 OID_AUTO, "total_pkts", 491 CTLFLAG_RD, &ha->hw.rcv.total_pkts, 492 "total_pkts"); 493 494 SYSCTL_ADD_QUAD(ctx, children, 495 OID_AUTO, "lro_pkt_count", 496 CTLFLAG_RD, &ha->hw.rcv.lro_pkt_count, 497 "lro_pkt_count"); 498 499 SYSCTL_ADD_QUAD(ctx, children, 500 OID_AUTO, "sw_pkt_count", 501 CTLFLAG_RD, &ha->hw.rcv.sw_pkt_count, 502 "sw_pkt_count"); 503 504 SYSCTL_ADD_QUAD(ctx, children, 505 OID_AUTO, "ip_chksum_err", 506 CTLFLAG_RD, &ha->hw.rcv.ip_chksum_err, 507 "ip_chksum_err"); 508 509 SYSCTL_ADD_QUAD(ctx, children, 510 OID_AUTO, "pkts_wo_acntxts", 511 CTLFLAG_RD, &ha->hw.rcv.pkts_wo_acntxts, 512 "pkts_wo_acntxts"); 513 514 SYSCTL_ADD_QUAD(ctx, children, 515 OID_AUTO, "pkts_dropped_no_sds_card", 516 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_card, 517 "pkts_dropped_no_sds_card"); 518 519 SYSCTL_ADD_QUAD(ctx, children, 520 OID_AUTO, "pkts_dropped_no_sds_host", 521 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_sds_host, 522 "pkts_dropped_no_sds_host"); 523 524 SYSCTL_ADD_QUAD(ctx, children, 525 OID_AUTO, "oversized_pkts", 526 CTLFLAG_RD, &ha->hw.rcv.oversized_pkts, 527 "oversized_pkts"); 528 529 SYSCTL_ADD_QUAD(ctx, children, 530 OID_AUTO, "pkts_dropped_no_rds", 531 CTLFLAG_RD, &ha->hw.rcv.pkts_dropped_no_rds, 532 "pkts_dropped_no_rds"); 533 534 SYSCTL_ADD_QUAD(ctx, children, 535 OID_AUTO, "unxpctd_mcast_pkts", 536 CTLFLAG_RD, &ha->hw.rcv.unxpctd_mcast_pkts, 537 "unxpctd_mcast_pkts"); 538 539 SYSCTL_ADD_QUAD(ctx, children, 540 OID_AUTO, "re1_fbq_error", 541 CTLFLAG_RD, &ha->hw.rcv.re1_fbq_error, 542 "re1_fbq_error"); 543 544 SYSCTL_ADD_QUAD(ctx, children, 545 OID_AUTO, "invalid_mac_addr", 546 CTLFLAG_RD, &ha->hw.rcv.invalid_mac_addr, 547 "invalid_mac_addr"); 548 549 SYSCTL_ADD_QUAD(ctx, children, 550 OID_AUTO, "rds_prime_trys", 551 CTLFLAG_RD, &ha->hw.rcv.rds_prime_trys, 552 "rds_prime_trys"); 553 554 SYSCTL_ADD_QUAD(ctx, children, 555 OID_AUTO, "rds_prime_success", 556 CTLFLAG_RD, &ha->hw.rcv.rds_prime_success, 557 "rds_prime_success"); 558 559 SYSCTL_ADD_QUAD(ctx, children, 560 OID_AUTO, "lro_flows_added", 561 CTLFLAG_RD, &ha->hw.rcv.lro_flows_added, 562 "lro_flows_added"); 563 564 SYSCTL_ADD_QUAD(ctx, children, 565 OID_AUTO, "lro_flows_deleted", 566 CTLFLAG_RD, &ha->hw.rcv.lro_flows_deleted, 567 "lro_flows_deleted"); 568 569 SYSCTL_ADD_QUAD(ctx, children, 570 OID_AUTO, "lro_flows_active", 571 CTLFLAG_RD, &ha->hw.rcv.lro_flows_active, 572 "lro_flows_active"); 573 574 SYSCTL_ADD_QUAD(ctx, children, 575 OID_AUTO, "pkts_droped_unknown", 576 CTLFLAG_RD, &ha->hw.rcv.pkts_droped_unknown, 577 "pkts_droped_unknown"); 578 579 SYSCTL_ADD_QUAD(ctx, children, 580 OID_AUTO, "pkts_cnt_oversized", 581 CTLFLAG_RD, &ha->hw.rcv.pkts_cnt_oversized, 582 "pkts_cnt_oversized"); 583 584 return; 585 } 586 587 static void 588 qlnx_add_hw_xmt_stats_sysctls(qla_host_t *ha) 589 { 590 struct sysctl_ctx_list *ctx; 591 struct sysctl_oid_list *children; 592 struct sysctl_oid_list *node_children; 593 struct sysctl_oid *ctx_oid; 594 int i; 595 uint8_t name_str[16]; 596 597 ctx = device_get_sysctl_ctx(ha->pci_dev); 598 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 599 600 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_hw_xmt", 601 CTLFLAG_RD, NULL, "stats_hw_xmt"); 602 children = SYSCTL_CHILDREN(ctx_oid); 603 604 for (i = 0; i < ha->hw.num_tx_rings; i++) { 605 606 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 607 snprintf(name_str, sizeof(name_str), "%d", i); 608 609 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 610 CTLFLAG_RD, NULL, name_str); 611 node_children = SYSCTL_CHILDREN(ctx_oid); 612 613 /* Tx Related */ 614 615 SYSCTL_ADD_QUAD(ctx, node_children, 616 OID_AUTO, "total_bytes", 617 CTLFLAG_RD, &ha->hw.xmt[i].total_bytes, 618 "total_bytes"); 619 620 SYSCTL_ADD_QUAD(ctx, node_children, 621 OID_AUTO, "total_pkts", 622 CTLFLAG_RD, &ha->hw.xmt[i].total_pkts, 623 "total_pkts"); 624 625 SYSCTL_ADD_QUAD(ctx, node_children, 626 OID_AUTO, "errors", 627 CTLFLAG_RD, &ha->hw.xmt[i].errors, 628 "errors"); 629 630 SYSCTL_ADD_QUAD(ctx, node_children, 631 OID_AUTO, "pkts_dropped", 632 CTLFLAG_RD, &ha->hw.xmt[i].pkts_dropped, 633 "pkts_dropped"); 634 635 SYSCTL_ADD_QUAD(ctx, node_children, 636 OID_AUTO, "switch_pkts", 637 CTLFLAG_RD, &ha->hw.xmt[i].switch_pkts, 638 "switch_pkts"); 639 640 SYSCTL_ADD_QUAD(ctx, node_children, 641 OID_AUTO, "num_buffers", 642 CTLFLAG_RD, &ha->hw.xmt[i].num_buffers, 643 "num_buffers"); 644 } 645 646 return; 647 } 648 649 static void 650 qlnx_add_hw_stats_sysctls(qla_host_t *ha) 651 { 652 qlnx_add_hw_mac_stats_sysctls(ha); 653 qlnx_add_hw_rcv_stats_sysctls(ha); 654 qlnx_add_hw_xmt_stats_sysctls(ha); 655 656 return; 657 } 658 659 static void 660 qlnx_add_drvr_sds_stats(qla_host_t *ha) 661 { 662 struct sysctl_ctx_list *ctx; 663 struct sysctl_oid_list *children; 664 struct sysctl_oid_list *node_children; 665 struct sysctl_oid *ctx_oid; 666 int i; 667 uint8_t name_str[16]; 668 669 ctx = device_get_sysctl_ctx(ha->pci_dev); 670 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 671 672 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_sds", 673 CTLFLAG_RD, NULL, "stats_drvr_sds"); 674 children = SYSCTL_CHILDREN(ctx_oid); 675 676 for (i = 0; i < ha->hw.num_sds_rings; i++) { 677 678 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 679 snprintf(name_str, sizeof(name_str), "%d", i); 680 681 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 682 CTLFLAG_RD, NULL, name_str); 683 node_children = SYSCTL_CHILDREN(ctx_oid); 684 685 SYSCTL_ADD_QUAD(ctx, node_children, 686 OID_AUTO, "intr_count", 687 CTLFLAG_RD, &ha->hw.sds[i].intr_count, 688 "intr_count"); 689 690 SYSCTL_ADD_UINT(ctx, node_children, 691 OID_AUTO, "rx_free", 692 CTLFLAG_RD, &ha->hw.sds[i].rx_free, 693 ha->hw.sds[i].rx_free, "rx_free"); 694 } 695 696 return; 697 } 698 static void 699 qlnx_add_drvr_rds_stats(qla_host_t *ha) 700 { 701 struct sysctl_ctx_list *ctx; 702 struct sysctl_oid_list *children; 703 struct sysctl_oid_list *node_children; 704 struct sysctl_oid *ctx_oid; 705 int i; 706 uint8_t name_str[16]; 707 708 ctx = device_get_sysctl_ctx(ha->pci_dev); 709 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 710 711 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_rds", 712 CTLFLAG_RD, NULL, "stats_drvr_rds"); 713 children = SYSCTL_CHILDREN(ctx_oid); 714 715 for (i = 0; i < ha->hw.num_rds_rings; i++) { 716 717 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 718 snprintf(name_str, sizeof(name_str), "%d", i); 719 720 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 721 CTLFLAG_RD, NULL, name_str); 722 node_children = SYSCTL_CHILDREN(ctx_oid); 723 724 SYSCTL_ADD_QUAD(ctx, node_children, 725 OID_AUTO, "count", 726 CTLFLAG_RD, &ha->hw.rds[i].count, 727 "count"); 728 729 SYSCTL_ADD_QUAD(ctx, node_children, 730 OID_AUTO, "lro_pkt_count", 731 CTLFLAG_RD, &ha->hw.rds[i].lro_pkt_count, 732 "lro_pkt_count"); 733 734 SYSCTL_ADD_QUAD(ctx, node_children, 735 OID_AUTO, "lro_bytes", 736 CTLFLAG_RD, &ha->hw.rds[i].lro_bytes, 737 "lro_bytes"); 738 } 739 740 return; 741 } 742 743 static void 744 qlnx_add_drvr_tx_stats(qla_host_t *ha) 745 { 746 struct sysctl_ctx_list *ctx; 747 struct sysctl_oid_list *children; 748 struct sysctl_oid_list *node_children; 749 struct sysctl_oid *ctx_oid; 750 int i; 751 uint8_t name_str[16]; 752 753 ctx = device_get_sysctl_ctx(ha->pci_dev); 754 children = SYSCTL_CHILDREN(device_get_sysctl_tree(ha->pci_dev)); 755 756 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats_drvr_xmt", 757 CTLFLAG_RD, NULL, "stats_drvr_xmt"); 758 children = SYSCTL_CHILDREN(ctx_oid); 759 760 for (i = 0; i < ha->hw.num_tx_rings; i++) { 761 762 bzero(name_str, (sizeof(uint8_t) * sizeof(name_str))); 763 snprintf(name_str, sizeof(name_str), "%d", i); 764 765 ctx_oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name_str, 766 CTLFLAG_RD, NULL, name_str); 767 node_children = SYSCTL_CHILDREN(ctx_oid); 768 769 SYSCTL_ADD_QUAD(ctx, node_children, 770 OID_AUTO, "count", 771 CTLFLAG_RD, &ha->tx_ring[i].count, 772 "count"); 773 774 #ifdef QL_ENABLE_ISCSI_TLV 775 SYSCTL_ADD_QUAD(ctx, node_children, 776 OID_AUTO, "iscsi_pkt_count", 777 CTLFLAG_RD, &ha->tx_ring[i].iscsi_pkt_count, 778 "iscsi_pkt_count"); 779 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */ 780 } 781 782 return; 783 } 784 785 static void 786 qlnx_add_drvr_stats_sysctls(qla_host_t *ha) 787 { 788 qlnx_add_drvr_sds_stats(ha); 789 qlnx_add_drvr_rds_stats(ha); 790 qlnx_add_drvr_tx_stats(ha); 791 return; 792 } 793 794 /* 795 * Name: ql_hw_add_sysctls 796 * Function: Add P3Plus specific sysctls 797 */ 798 void 799 ql_hw_add_sysctls(qla_host_t *ha) 800 { 801 device_t dev; 802 803 dev = ha->pci_dev; 804 805 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 806 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 807 OID_AUTO, "num_rds_rings", CTLFLAG_RD, &ha->hw.num_rds_rings, 808 ha->hw.num_rds_rings, "Number of Rcv Descriptor Rings"); 809 810 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 811 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 812 OID_AUTO, "num_sds_rings", CTLFLAG_RD, &ha->hw.num_sds_rings, 813 ha->hw.num_sds_rings, "Number of Status Descriptor Rings"); 814 815 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 817 OID_AUTO, "num_tx_rings", CTLFLAG_RD, &ha->hw.num_tx_rings, 818 ha->hw.num_tx_rings, "Number of Transmit Rings"); 819 820 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 821 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 822 OID_AUTO, "tx_ring_index", CTLFLAG_RW, &ha->txr_idx, 823 ha->txr_idx, "Tx Ring Used"); 824 825 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 826 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 827 OID_AUTO, "max_tx_segs", CTLFLAG_RD, &ha->hw.max_tx_segs, 828 ha->hw.max_tx_segs, "Max # of Segments in a non-TSO pkt"); 829 830 ha->hw.sds_cidx_thres = 32; 831 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 832 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 833 OID_AUTO, "sds_cidx_thres", CTLFLAG_RW, &ha->hw.sds_cidx_thres, 834 ha->hw.sds_cidx_thres, 835 "Number of SDS entries to process before updating" 836 " SDS Ring Consumer Index"); 837 838 ha->hw.rds_pidx_thres = 32; 839 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 840 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 841 OID_AUTO, "rds_pidx_thres", CTLFLAG_RW, &ha->hw.rds_pidx_thres, 842 ha->hw.rds_pidx_thres, 843 "Number of Rcv Rings Entries to post before updating" 844 " RDS Ring Producer Index"); 845 846 ha->hw.rcv_intr_coalesce = (3 << 16) | 256; 847 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 848 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 849 OID_AUTO, "rcv_intr_coalesce", CTLFLAG_RW, 850 &ha->hw.rcv_intr_coalesce, 851 ha->hw.rcv_intr_coalesce, 852 "Rcv Intr Coalescing Parameters\n" 853 "\tbits 15:0 max packets\n" 854 "\tbits 31:16 max micro-seconds to wait\n" 855 "\tplease run\n" 856 "\tifconfig <if> down && ifconfig <if> up\n" 857 "\tto take effect \n"); 858 859 ha->hw.xmt_intr_coalesce = (64 << 16) | 64; 860 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 861 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 862 OID_AUTO, "xmt_intr_coalesce", CTLFLAG_RW, 863 &ha->hw.xmt_intr_coalesce, 864 ha->hw.xmt_intr_coalesce, 865 "Xmt Intr Coalescing Parameters\n" 866 "\tbits 15:0 max packets\n" 867 "\tbits 31:16 max micro-seconds to wait\n" 868 "\tplease run\n" 869 "\tifconfig <if> down && ifconfig <if> up\n" 870 "\tto take effect \n"); 871 872 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 873 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 874 OID_AUTO, "port_cfg", CTLTYPE_INT | CTLFLAG_RW, 875 (void *)ha, 0, 876 qla_sysctl_port_cfg, "I", 877 "Set Port Configuration if values below " 878 "otherwise Get Port Configuration\n" 879 "\tBits 0-3 ; 1 = DCBX Enable; 0 = DCBX Disable\n" 880 "\tBits 4-7 : 0 = no pause; 1 = std ; 2 = ppm \n" 881 "\tBits 8-11: std pause cfg; 0 = xmt and rcv;" 882 " 1 = xmt only; 2 = rcv only;\n" 883 ); 884 885 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 886 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 887 OID_AUTO, "set_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW, 888 (void *)ha, 0, 889 qla_sysctl_set_cam_search_mode, "I", 890 "Set CAM Search Mode" 891 "\t 1 = search mode internal\n" 892 "\t 2 = search mode auto\n"); 893 894 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 895 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 896 OID_AUTO, "get_cam_search_mode", CTLTYPE_INT | CTLFLAG_RW, 897 (void *)ha, 0, 898 qla_sysctl_get_cam_search_mode, "I", 899 "Get CAM Search Mode" 900 "\t 1 = search mode internal\n" 901 "\t 2 = search mode auto\n"); 902 903 ha->hw.enable_9kb = 1; 904 905 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 906 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 907 OID_AUTO, "enable_9kb", CTLFLAG_RW, &ha->hw.enable_9kb, 908 ha->hw.enable_9kb, "Enable 9Kbyte Buffers when MTU = 9000"); 909 910 ha->hw.enable_hw_lro = 1; 911 912 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 913 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 914 OID_AUTO, "enable_hw_lro", CTLFLAG_RW, &ha->hw.enable_hw_lro, 915 ha->hw.enable_hw_lro, "Enable Hardware LRO; Default is true \n" 916 "\t 1 : Hardware LRO if LRO is enabled\n" 917 "\t 0 : Software LRO if LRO is enabled\n" 918 "\t Any change requires ifconfig down/up to take effect\n" 919 "\t Note that LRO may be turned off/on via ifconfig\n"); 920 921 ha->hw.mdump_active = 0; 922 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 923 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 924 OID_AUTO, "minidump_active", CTLFLAG_RW, &ha->hw.mdump_active, 925 ha->hw.mdump_active, 926 "Minidump retrieval is Active"); 927 928 ha->hw.mdump_done = 0; 929 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 930 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 931 OID_AUTO, "mdump_done", CTLFLAG_RW, 932 &ha->hw.mdump_done, ha->hw.mdump_done, 933 "Minidump has been done and available for retrieval"); 934 935 ha->hw.mdump_capture_mask = 0xF; 936 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 937 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 938 OID_AUTO, "minidump_capture_mask", CTLFLAG_RW, 939 &ha->hw.mdump_capture_mask, ha->hw.mdump_capture_mask, 940 "Minidump capture mask"); 941 #ifdef QL_DBG 942 943 ha->err_inject = 0; 944 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 945 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 946 OID_AUTO, "err_inject", 947 CTLFLAG_RW, &ha->err_inject, ha->err_inject, 948 "Error to be injected\n" 949 "\t\t\t 0: No Errors\n" 950 "\t\t\t 1: rcv: rxb struct invalid\n" 951 "\t\t\t 2: rcv: mp == NULL\n" 952 "\t\t\t 3: lro: rxb struct invalid\n" 953 "\t\t\t 4: lro: mp == NULL\n" 954 "\t\t\t 5: rcv: num handles invalid\n" 955 "\t\t\t 6: reg: indirect reg rd_wr failure\n" 956 "\t\t\t 7: ocm: offchip memory rd_wr failure\n" 957 "\t\t\t 8: mbx: mailbox command failure\n" 958 "\t\t\t 9: heartbeat failure\n" 959 "\t\t\t A: temperature failure\n" 960 "\t\t\t 11: m_getcl or m_getjcl failure\n" ); 961 962 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 963 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 964 OID_AUTO, "peg_stop", CTLTYPE_INT | CTLFLAG_RW, 965 (void *)ha, 0, 966 qla_sysctl_stop_pegs, "I", "Peg Stop"); 967 968 #endif /* #ifdef QL_DBG */ 969 970 ha->hw.user_pri_nic = 0; 971 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 972 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 973 OID_AUTO, "user_pri_nic", CTLFLAG_RW, &ha->hw.user_pri_nic, 974 ha->hw.user_pri_nic, 975 "VLAN Tag User Priority for Normal Ethernet Packets"); 976 977 ha->hw.user_pri_iscsi = 4; 978 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 979 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 980 OID_AUTO, "user_pri_iscsi", CTLFLAG_RW, &ha->hw.user_pri_iscsi, 981 ha->hw.user_pri_iscsi, 982 "VLAN Tag User Priority for iSCSI Packets"); 983 984 qlnx_add_hw_stats_sysctls(ha); 985 qlnx_add_drvr_stats_sysctls(ha); 986 987 return; 988 } 989 990 void 991 ql_hw_link_status(qla_host_t *ha) 992 { 993 device_printf(ha->pci_dev, "cable_oui\t\t 0x%08x\n", ha->hw.cable_oui); 994 995 if (ha->hw.link_up) { 996 device_printf(ha->pci_dev, "link Up\n"); 997 } else { 998 device_printf(ha->pci_dev, "link Down\n"); 999 } 1000 1001 if (ha->hw.flags.fduplex) { 1002 device_printf(ha->pci_dev, "Full Duplex\n"); 1003 } else { 1004 device_printf(ha->pci_dev, "Half Duplex\n"); 1005 } 1006 1007 if (ha->hw.flags.autoneg) { 1008 device_printf(ha->pci_dev, "Auto Negotiation Enabled\n"); 1009 } else { 1010 device_printf(ha->pci_dev, "Auto Negotiation Disabled\n"); 1011 } 1012 1013 switch (ha->hw.link_speed) { 1014 case 0x710: 1015 device_printf(ha->pci_dev, "link speed\t\t 10Gps\n"); 1016 break; 1017 1018 case 0x3E8: 1019 device_printf(ha->pci_dev, "link speed\t\t 1Gps\n"); 1020 break; 1021 1022 case 0x64: 1023 device_printf(ha->pci_dev, "link speed\t\t 100Mbps\n"); 1024 break; 1025 1026 default: 1027 device_printf(ha->pci_dev, "link speed\t\t Unknown\n"); 1028 break; 1029 } 1030 1031 switch (ha->hw.module_type) { 1032 1033 case 0x01: 1034 device_printf(ha->pci_dev, "Module Type 10GBase-LRM\n"); 1035 break; 1036 1037 case 0x02: 1038 device_printf(ha->pci_dev, "Module Type 10GBase-LR\n"); 1039 break; 1040 1041 case 0x03: 1042 device_printf(ha->pci_dev, "Module Type 10GBase-SR\n"); 1043 break; 1044 1045 case 0x04: 1046 device_printf(ha->pci_dev, 1047 "Module Type 10GE Passive Copper(Compliant)[%d m]\n", 1048 ha->hw.cable_length); 1049 break; 1050 1051 case 0x05: 1052 device_printf(ha->pci_dev, "Module Type 10GE Active" 1053 " Limiting Copper(Compliant)[%d m]\n", 1054 ha->hw.cable_length); 1055 break; 1056 1057 case 0x06: 1058 device_printf(ha->pci_dev, 1059 "Module Type 10GE Passive Copper" 1060 " (Legacy, Best Effort)[%d m]\n", 1061 ha->hw.cable_length); 1062 break; 1063 1064 case 0x07: 1065 device_printf(ha->pci_dev, "Module Type 1000Base-SX\n"); 1066 break; 1067 1068 case 0x08: 1069 device_printf(ha->pci_dev, "Module Type 1000Base-LX\n"); 1070 break; 1071 1072 case 0x09: 1073 device_printf(ha->pci_dev, "Module Type 1000Base-CX\n"); 1074 break; 1075 1076 case 0x0A: 1077 device_printf(ha->pci_dev, "Module Type 1000Base-T\n"); 1078 break; 1079 1080 case 0x0B: 1081 device_printf(ha->pci_dev, "Module Type 1GE Passive Copper" 1082 "(Legacy, Best Effort)\n"); 1083 break; 1084 1085 default: 1086 device_printf(ha->pci_dev, "Unknown Module Type 0x%x\n", 1087 ha->hw.module_type); 1088 break; 1089 } 1090 1091 if (ha->hw.link_faults == 1) 1092 device_printf(ha->pci_dev, "SFP Power Fault\n"); 1093 } 1094 1095 /* 1096 * Name: ql_free_dma 1097 * Function: Frees the DMA'able memory allocated in ql_alloc_dma() 1098 */ 1099 void 1100 ql_free_dma(qla_host_t *ha) 1101 { 1102 uint32_t i; 1103 1104 if (ha->hw.dma_buf.flags.sds_ring) { 1105 for (i = 0; i < ha->hw.num_sds_rings; i++) { 1106 ql_free_dmabuf(ha, &ha->hw.dma_buf.sds_ring[i]); 1107 } 1108 ha->hw.dma_buf.flags.sds_ring = 0; 1109 } 1110 1111 if (ha->hw.dma_buf.flags.rds_ring) { 1112 for (i = 0; i < ha->hw.num_rds_rings; i++) { 1113 ql_free_dmabuf(ha, &ha->hw.dma_buf.rds_ring[i]); 1114 } 1115 ha->hw.dma_buf.flags.rds_ring = 0; 1116 } 1117 1118 if (ha->hw.dma_buf.flags.tx_ring) { 1119 ql_free_dmabuf(ha, &ha->hw.dma_buf.tx_ring); 1120 ha->hw.dma_buf.flags.tx_ring = 0; 1121 } 1122 ql_minidump_free(ha); 1123 } 1124 1125 /* 1126 * Name: ql_alloc_dma 1127 * Function: Allocates DMA'able memory for Tx/Rx Rings, Tx/Rx Contexts. 1128 */ 1129 int 1130 ql_alloc_dma(qla_host_t *ha) 1131 { 1132 device_t dev; 1133 uint32_t i, j, size, tx_ring_size; 1134 qla_hw_t *hw; 1135 qla_hw_tx_cntxt_t *tx_cntxt; 1136 uint8_t *vaddr; 1137 bus_addr_t paddr; 1138 1139 dev = ha->pci_dev; 1140 1141 QL_DPRINT2(ha, (dev, "%s: enter\n", __func__)); 1142 1143 hw = &ha->hw; 1144 /* 1145 * Allocate Transmit Ring 1146 */ 1147 tx_ring_size = (sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS); 1148 size = (tx_ring_size * ha->hw.num_tx_rings); 1149 1150 hw->dma_buf.tx_ring.alignment = 8; 1151 hw->dma_buf.tx_ring.size = size + PAGE_SIZE; 1152 1153 if (ql_alloc_dmabuf(ha, &hw->dma_buf.tx_ring)) { 1154 device_printf(dev, "%s: tx ring alloc failed\n", __func__); 1155 goto ql_alloc_dma_exit; 1156 } 1157 1158 vaddr = (uint8_t *)hw->dma_buf.tx_ring.dma_b; 1159 paddr = hw->dma_buf.tx_ring.dma_addr; 1160 1161 for (i = 0; i < ha->hw.num_tx_rings; i++) { 1162 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i]; 1163 1164 tx_cntxt->tx_ring_base = (q80_tx_cmd_t *)vaddr; 1165 tx_cntxt->tx_ring_paddr = paddr; 1166 1167 vaddr += tx_ring_size; 1168 paddr += tx_ring_size; 1169 } 1170 1171 for (i = 0; i < ha->hw.num_tx_rings; i++) { 1172 tx_cntxt = (qla_hw_tx_cntxt_t *)&hw->tx_cntxt[i]; 1173 1174 tx_cntxt->tx_cons = (uint32_t *)vaddr; 1175 tx_cntxt->tx_cons_paddr = paddr; 1176 1177 vaddr += sizeof (uint32_t); 1178 paddr += sizeof (uint32_t); 1179 } 1180 1181 ha->hw.dma_buf.flags.tx_ring = 1; 1182 1183 QL_DPRINT2(ha, (dev, "%s: tx_ring phys %p virt %p\n", 1184 __func__, (void *)(hw->dma_buf.tx_ring.dma_addr), 1185 hw->dma_buf.tx_ring.dma_b)); 1186 /* 1187 * Allocate Receive Descriptor Rings 1188 */ 1189 1190 for (i = 0; i < hw->num_rds_rings; i++) { 1191 1192 hw->dma_buf.rds_ring[i].alignment = 8; 1193 hw->dma_buf.rds_ring[i].size = 1194 (sizeof(q80_recv_desc_t)) * NUM_RX_DESCRIPTORS; 1195 1196 if (ql_alloc_dmabuf(ha, &hw->dma_buf.rds_ring[i])) { 1197 device_printf(dev, "%s: rds ring[%d] alloc failed\n", 1198 __func__, i); 1199 1200 for (j = 0; j < i; j++) 1201 ql_free_dmabuf(ha, &hw->dma_buf.rds_ring[j]); 1202 1203 goto ql_alloc_dma_exit; 1204 } 1205 QL_DPRINT4(ha, (dev, "%s: rx_ring[%d] phys %p virt %p\n", 1206 __func__, i, (void *)(hw->dma_buf.rds_ring[i].dma_addr), 1207 hw->dma_buf.rds_ring[i].dma_b)); 1208 } 1209 1210 hw->dma_buf.flags.rds_ring = 1; 1211 1212 /* 1213 * Allocate Status Descriptor Rings 1214 */ 1215 1216 for (i = 0; i < hw->num_sds_rings; i++) { 1217 hw->dma_buf.sds_ring[i].alignment = 8; 1218 hw->dma_buf.sds_ring[i].size = 1219 (sizeof(q80_stat_desc_t)) * NUM_STATUS_DESCRIPTORS; 1220 1221 if (ql_alloc_dmabuf(ha, &hw->dma_buf.sds_ring[i])) { 1222 device_printf(dev, "%s: sds ring alloc failed\n", 1223 __func__); 1224 1225 for (j = 0; j < i; j++) 1226 ql_free_dmabuf(ha, &hw->dma_buf.sds_ring[j]); 1227 1228 goto ql_alloc_dma_exit; 1229 } 1230 QL_DPRINT4(ha, (dev, "%s: sds_ring[%d] phys %p virt %p\n", 1231 __func__, i, 1232 (void *)(hw->dma_buf.sds_ring[i].dma_addr), 1233 hw->dma_buf.sds_ring[i].dma_b)); 1234 } 1235 for (i = 0; i < hw->num_sds_rings; i++) { 1236 hw->sds[i].sds_ring_base = 1237 (q80_stat_desc_t *)hw->dma_buf.sds_ring[i].dma_b; 1238 } 1239 1240 hw->dma_buf.flags.sds_ring = 1; 1241 1242 return 0; 1243 1244 ql_alloc_dma_exit: 1245 ql_free_dma(ha); 1246 return -1; 1247 } 1248 1249 #define Q8_MBX_MSEC_DELAY 5000 1250 1251 static int 1252 qla_mbx_cmd(qla_host_t *ha, uint32_t *h_mbox, uint32_t n_hmbox, 1253 uint32_t *fw_mbox, uint32_t n_fwmbox, uint32_t no_pause) 1254 { 1255 uint32_t i; 1256 uint32_t data; 1257 int ret = 0; 1258 1259 if (QL_ERR_INJECT(ha, INJCT_MBX_CMD_FAILURE)) { 1260 ret = -3; 1261 ha->qla_initiate_recovery = 1; 1262 goto exit_qla_mbx_cmd; 1263 } 1264 1265 if (no_pause) 1266 i = 1000; 1267 else 1268 i = Q8_MBX_MSEC_DELAY; 1269 1270 while (i) { 1271 data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL); 1272 if (data == 0) 1273 break; 1274 if (no_pause) { 1275 DELAY(1000); 1276 } else { 1277 qla_mdelay(__func__, 1); 1278 } 1279 i--; 1280 } 1281 1282 if (i == 0) { 1283 device_printf(ha->pci_dev, "%s: host_mbx_cntrl 0x%08x\n", 1284 __func__, data); 1285 ret = -1; 1286 ha->qla_initiate_recovery = 1; 1287 goto exit_qla_mbx_cmd; 1288 } 1289 1290 for (i = 0; i < n_hmbox; i++) { 1291 WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox); 1292 h_mbox++; 1293 } 1294 1295 WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1); 1296 1297 1298 i = Q8_MBX_MSEC_DELAY; 1299 while (i) { 1300 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL); 1301 1302 if ((data & 0x3) == 1) { 1303 data = READ_REG32(ha, Q8_FW_MBOX0); 1304 if ((data & 0xF000) != 0x8000) 1305 break; 1306 } 1307 if (no_pause) { 1308 DELAY(1000); 1309 } else { 1310 qla_mdelay(__func__, 1); 1311 } 1312 i--; 1313 } 1314 if (i == 0) { 1315 device_printf(ha->pci_dev, "%s: fw_mbx_cntrl 0x%08x\n", 1316 __func__, data); 1317 ret = -2; 1318 ha->qla_initiate_recovery = 1; 1319 goto exit_qla_mbx_cmd; 1320 } 1321 1322 for (i = 0; i < n_fwmbox; i++) { 1323 *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2))); 1324 } 1325 1326 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0); 1327 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 1328 1329 exit_qla_mbx_cmd: 1330 return (ret); 1331 } 1332 1333 int 1334 qla_get_nic_partition(qla_host_t *ha, uint32_t *supports_9kb, 1335 uint32_t *num_rcvq) 1336 { 1337 uint32_t *mbox, err; 1338 device_t dev = ha->pci_dev; 1339 1340 bzero(ha->hw.mbox, (sizeof (uint32_t) * Q8_NUM_MBOX)); 1341 1342 mbox = ha->hw.mbox; 1343 1344 mbox[0] = Q8_MBX_GET_NIC_PARTITION | (0x2 << 16) | (0x2 << 29); 1345 1346 if (qla_mbx_cmd(ha, mbox, 2, mbox, 19, 0)) { 1347 device_printf(dev, "%s: failed0\n", __func__); 1348 return (-1); 1349 } 1350 err = mbox[0] >> 25; 1351 1352 if (supports_9kb != NULL) { 1353 if (mbox[16] & 0x80) /* bit 7 of mbox 16 */ 1354 *supports_9kb = 1; 1355 else 1356 *supports_9kb = 0; 1357 } 1358 1359 if (num_rcvq != NULL) 1360 *num_rcvq = ((mbox[6] >> 16) & 0xFFFF); 1361 1362 if ((err != 1) && (err != 0)) { 1363 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1364 return (-1); 1365 } 1366 return 0; 1367 } 1368 1369 static int 1370 qla_config_intr_cntxt(qla_host_t *ha, uint32_t start_idx, uint32_t num_intrs, 1371 uint32_t create) 1372 { 1373 uint32_t i, err; 1374 device_t dev = ha->pci_dev; 1375 q80_config_intr_t *c_intr; 1376 q80_config_intr_rsp_t *c_intr_rsp; 1377 1378 c_intr = (q80_config_intr_t *)ha->hw.mbox; 1379 bzero(c_intr, (sizeof (q80_config_intr_t))); 1380 1381 c_intr->opcode = Q8_MBX_CONFIG_INTR; 1382 1383 c_intr->count_version = (sizeof (q80_config_intr_t) >> 2); 1384 c_intr->count_version |= Q8_MBX_CMD_VERSION; 1385 1386 c_intr->nentries = num_intrs; 1387 1388 for (i = 0; i < num_intrs; i++) { 1389 if (create) { 1390 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_CREATE; 1391 c_intr->intr[i].msix_index = start_idx + 1 + i; 1392 } else { 1393 c_intr->intr[i].cmd_type = Q8_MBX_CONFIG_INTR_DELETE; 1394 c_intr->intr[i].msix_index = 1395 ha->hw.intr_id[(start_idx + i)]; 1396 } 1397 1398 c_intr->intr[i].cmd_type |= Q8_MBX_CONFIG_INTR_TYPE_MSI_X; 1399 } 1400 1401 if (qla_mbx_cmd(ha, (uint32_t *)c_intr, 1402 (sizeof (q80_config_intr_t) >> 2), 1403 ha->hw.mbox, (sizeof (q80_config_intr_rsp_t) >> 2), 0)) { 1404 device_printf(dev, "%s: failed0\n", __func__); 1405 return (-1); 1406 } 1407 1408 c_intr_rsp = (q80_config_intr_rsp_t *)ha->hw.mbox; 1409 1410 err = Q8_MBX_RSP_STATUS(c_intr_rsp->regcnt_status); 1411 1412 if (err) { 1413 device_printf(dev, "%s: failed1 [0x%08x, %d]\n", __func__, err, 1414 c_intr_rsp->nentries); 1415 1416 for (i = 0; i < c_intr_rsp->nentries; i++) { 1417 device_printf(dev, "%s: [%d]:[0x%x 0x%x 0x%x]\n", 1418 __func__, i, 1419 c_intr_rsp->intr[i].status, 1420 c_intr_rsp->intr[i].intr_id, 1421 c_intr_rsp->intr[i].intr_src); 1422 } 1423 1424 return (-1); 1425 } 1426 1427 for (i = 0; ((i < num_intrs) && create); i++) { 1428 if (!c_intr_rsp->intr[i].status) { 1429 ha->hw.intr_id[(start_idx + i)] = 1430 c_intr_rsp->intr[i].intr_id; 1431 ha->hw.intr_src[(start_idx + i)] = 1432 c_intr_rsp->intr[i].intr_src; 1433 } 1434 } 1435 1436 return (0); 1437 } 1438 1439 /* 1440 * Name: qla_config_rss 1441 * Function: Configure RSS for the context/interface. 1442 */ 1443 static const uint64_t rss_key[] = { 0xbeac01fa6a42b73bULL, 1444 0x8030f20c77cb2da3ULL, 1445 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL, 1446 0x255b0ec26d5a56daULL }; 1447 1448 static int 1449 qla_config_rss(qla_host_t *ha, uint16_t cntxt_id) 1450 { 1451 q80_config_rss_t *c_rss; 1452 q80_config_rss_rsp_t *c_rss_rsp; 1453 uint32_t err, i; 1454 device_t dev = ha->pci_dev; 1455 1456 c_rss = (q80_config_rss_t *)ha->hw.mbox; 1457 bzero(c_rss, (sizeof (q80_config_rss_t))); 1458 1459 c_rss->opcode = Q8_MBX_CONFIG_RSS; 1460 1461 c_rss->count_version = (sizeof (q80_config_rss_t) >> 2); 1462 c_rss->count_version |= Q8_MBX_CMD_VERSION; 1463 1464 c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP | 1465 Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP); 1466 //c_rss->hash_type = (Q8_MBX_RSS_HASH_TYPE_IPV4_TCP | 1467 // Q8_MBX_RSS_HASH_TYPE_IPV6_TCP); 1468 1469 c_rss->flags = Q8_MBX_RSS_FLAGS_ENABLE_RSS; 1470 c_rss->flags |= Q8_MBX_RSS_FLAGS_USE_IND_TABLE; 1471 1472 c_rss->indtbl_mask = Q8_MBX_RSS_INDTBL_MASK; 1473 1474 c_rss->indtbl_mask |= Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID; 1475 c_rss->flags |= Q8_MBX_RSS_FLAGS_TYPE_CRSS; 1476 1477 c_rss->cntxt_id = cntxt_id; 1478 1479 for (i = 0; i < 5; i++) { 1480 c_rss->rss_key[i] = rss_key[i]; 1481 } 1482 1483 if (qla_mbx_cmd(ha, (uint32_t *)c_rss, 1484 (sizeof (q80_config_rss_t) >> 2), 1485 ha->hw.mbox, (sizeof(q80_config_rss_rsp_t) >> 2), 0)) { 1486 device_printf(dev, "%s: failed0\n", __func__); 1487 return (-1); 1488 } 1489 c_rss_rsp = (q80_config_rss_rsp_t *)ha->hw.mbox; 1490 1491 err = Q8_MBX_RSP_STATUS(c_rss_rsp->regcnt_status); 1492 1493 if (err) { 1494 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1495 return (-1); 1496 } 1497 return 0; 1498 } 1499 1500 static int 1501 qla_set_rss_ind_table(qla_host_t *ha, uint32_t start_idx, uint32_t count, 1502 uint16_t cntxt_id, uint8_t *ind_table) 1503 { 1504 q80_config_rss_ind_table_t *c_rss_ind; 1505 q80_config_rss_ind_table_rsp_t *c_rss_ind_rsp; 1506 uint32_t err; 1507 device_t dev = ha->pci_dev; 1508 1509 if ((count > Q8_RSS_IND_TBL_SIZE) || 1510 ((start_idx + count - 1) > Q8_RSS_IND_TBL_MAX_IDX)) { 1511 device_printf(dev, "%s: illegal count [%d, %d]\n", __func__, 1512 start_idx, count); 1513 return (-1); 1514 } 1515 1516 c_rss_ind = (q80_config_rss_ind_table_t *)ha->hw.mbox; 1517 bzero(c_rss_ind, sizeof (q80_config_rss_ind_table_t)); 1518 1519 c_rss_ind->opcode = Q8_MBX_CONFIG_RSS_TABLE; 1520 c_rss_ind->count_version = (sizeof (q80_config_rss_ind_table_t) >> 2); 1521 c_rss_ind->count_version |= Q8_MBX_CMD_VERSION; 1522 1523 c_rss_ind->start_idx = start_idx; 1524 c_rss_ind->end_idx = start_idx + count - 1; 1525 c_rss_ind->cntxt_id = cntxt_id; 1526 bcopy(ind_table, c_rss_ind->ind_table, count); 1527 1528 if (qla_mbx_cmd(ha, (uint32_t *)c_rss_ind, 1529 (sizeof (q80_config_rss_ind_table_t) >> 2), ha->hw.mbox, 1530 (sizeof(q80_config_rss_ind_table_rsp_t) >> 2), 0)) { 1531 device_printf(dev, "%s: failed0\n", __func__); 1532 return (-1); 1533 } 1534 1535 c_rss_ind_rsp = (q80_config_rss_ind_table_rsp_t *)ha->hw.mbox; 1536 err = Q8_MBX_RSP_STATUS(c_rss_ind_rsp->regcnt_status); 1537 1538 if (err) { 1539 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1540 return (-1); 1541 } 1542 return 0; 1543 } 1544 1545 /* 1546 * Name: qla_config_intr_coalesce 1547 * Function: Configure Interrupt Coalescing. 1548 */ 1549 static int 1550 qla_config_intr_coalesce(qla_host_t *ha, uint16_t cntxt_id, int tenable, 1551 int rcv) 1552 { 1553 q80_config_intr_coalesc_t *intrc; 1554 q80_config_intr_coalesc_rsp_t *intrc_rsp; 1555 uint32_t err, i; 1556 device_t dev = ha->pci_dev; 1557 1558 intrc = (q80_config_intr_coalesc_t *)ha->hw.mbox; 1559 bzero(intrc, (sizeof (q80_config_intr_coalesc_t))); 1560 1561 intrc->opcode = Q8_MBX_CONFIG_INTR_COALESCE; 1562 intrc->count_version = (sizeof (q80_config_intr_coalesc_t) >> 2); 1563 intrc->count_version |= Q8_MBX_CMD_VERSION; 1564 1565 if (rcv) { 1566 intrc->flags = Q8_MBX_INTRC_FLAGS_RCV; 1567 intrc->max_pkts = ha->hw.rcv_intr_coalesce & 0xFFFF; 1568 intrc->max_mswait = (ha->hw.rcv_intr_coalesce >> 16) & 0xFFFF; 1569 } else { 1570 intrc->flags = Q8_MBX_INTRC_FLAGS_XMT; 1571 intrc->max_pkts = ha->hw.xmt_intr_coalesce & 0xFFFF; 1572 intrc->max_mswait = (ha->hw.xmt_intr_coalesce >> 16) & 0xFFFF; 1573 } 1574 1575 intrc->cntxt_id = cntxt_id; 1576 1577 if (tenable) { 1578 intrc->flags |= Q8_MBX_INTRC_FLAGS_PERIODIC; 1579 intrc->timer_type = Q8_MBX_INTRC_TIMER_PERIODIC; 1580 1581 for (i = 0; i < ha->hw.num_sds_rings; i++) { 1582 intrc->sds_ring_mask |= (1 << i); 1583 } 1584 intrc->ms_timeout = 1000; 1585 } 1586 1587 if (qla_mbx_cmd(ha, (uint32_t *)intrc, 1588 (sizeof (q80_config_intr_coalesc_t) >> 2), 1589 ha->hw.mbox, (sizeof(q80_config_intr_coalesc_rsp_t) >> 2), 0)) { 1590 device_printf(dev, "%s: failed0\n", __func__); 1591 return (-1); 1592 } 1593 intrc_rsp = (q80_config_intr_coalesc_rsp_t *)ha->hw.mbox; 1594 1595 err = Q8_MBX_RSP_STATUS(intrc_rsp->regcnt_status); 1596 1597 if (err) { 1598 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1599 return (-1); 1600 } 1601 1602 return 0; 1603 } 1604 1605 1606 /* 1607 * Name: qla_config_mac_addr 1608 * Function: binds a MAC address to the context/interface. 1609 * Can be unicast, multicast or broadcast. 1610 */ 1611 static int 1612 qla_config_mac_addr(qla_host_t *ha, uint8_t *mac_addr, uint32_t add_mac, 1613 uint32_t num_mac) 1614 { 1615 q80_config_mac_addr_t *cmac; 1616 q80_config_mac_addr_rsp_t *cmac_rsp; 1617 uint32_t err; 1618 device_t dev = ha->pci_dev; 1619 int i; 1620 uint8_t *mac_cpy = mac_addr; 1621 1622 if (num_mac > Q8_MAX_MAC_ADDRS) { 1623 device_printf(dev, "%s: %s num_mac [0x%x] > Q8_MAX_MAC_ADDRS\n", 1624 __func__, (add_mac ? "Add" : "Del"), num_mac); 1625 return (-1); 1626 } 1627 1628 cmac = (q80_config_mac_addr_t *)ha->hw.mbox; 1629 bzero(cmac, (sizeof (q80_config_mac_addr_t))); 1630 1631 cmac->opcode = Q8_MBX_CONFIG_MAC_ADDR; 1632 cmac->count_version = sizeof (q80_config_mac_addr_t) >> 2; 1633 cmac->count_version |= Q8_MBX_CMD_VERSION; 1634 1635 if (add_mac) 1636 cmac->cmd = Q8_MBX_CMAC_CMD_ADD_MAC_ADDR; 1637 else 1638 cmac->cmd = Q8_MBX_CMAC_CMD_DEL_MAC_ADDR; 1639 1640 cmac->cmd |= Q8_MBX_CMAC_CMD_CAM_INGRESS; 1641 1642 cmac->nmac_entries = num_mac; 1643 cmac->cntxt_id = ha->hw.rcv_cntxt_id; 1644 1645 for (i = 0; i < num_mac; i++) { 1646 bcopy(mac_addr, cmac->mac_addr[i].addr, Q8_ETHER_ADDR_LEN); 1647 mac_addr = mac_addr + ETHER_ADDR_LEN; 1648 } 1649 1650 if (qla_mbx_cmd(ha, (uint32_t *)cmac, 1651 (sizeof (q80_config_mac_addr_t) >> 2), 1652 ha->hw.mbox, (sizeof(q80_config_mac_addr_rsp_t) >> 2), 1)) { 1653 device_printf(dev, "%s: %s failed0\n", __func__, 1654 (add_mac ? "Add" : "Del")); 1655 return (-1); 1656 } 1657 cmac_rsp = (q80_config_mac_addr_rsp_t *)ha->hw.mbox; 1658 1659 err = Q8_MBX_RSP_STATUS(cmac_rsp->regcnt_status); 1660 1661 if (err) { 1662 device_printf(dev, "%s: %s failed1 [0x%08x]\n", __func__, 1663 (add_mac ? "Add" : "Del"), err); 1664 for (i = 0; i < num_mac; i++) { 1665 device_printf(dev, "%s: %02x:%02x:%02x:%02x:%02x:%02x\n", 1666 __func__, mac_cpy[0], mac_cpy[1], mac_cpy[2], 1667 mac_cpy[3], mac_cpy[4], mac_cpy[5]); 1668 mac_cpy += ETHER_ADDR_LEN; 1669 } 1670 return (-1); 1671 } 1672 1673 return 0; 1674 } 1675 1676 1677 /* 1678 * Name: qla_set_mac_rcv_mode 1679 * Function: Enable/Disable AllMulticast and Promiscous Modes. 1680 */ 1681 static int 1682 qla_set_mac_rcv_mode(qla_host_t *ha, uint32_t mode) 1683 { 1684 q80_config_mac_rcv_mode_t *rcv_mode; 1685 uint32_t err; 1686 q80_config_mac_rcv_mode_rsp_t *rcv_mode_rsp; 1687 device_t dev = ha->pci_dev; 1688 1689 rcv_mode = (q80_config_mac_rcv_mode_t *)ha->hw.mbox; 1690 bzero(rcv_mode, (sizeof (q80_config_mac_rcv_mode_t))); 1691 1692 rcv_mode->opcode = Q8_MBX_CONFIG_MAC_RX_MODE; 1693 rcv_mode->count_version = sizeof (q80_config_mac_rcv_mode_t) >> 2; 1694 rcv_mode->count_version |= Q8_MBX_CMD_VERSION; 1695 1696 rcv_mode->mode = mode; 1697 1698 rcv_mode->cntxt_id = ha->hw.rcv_cntxt_id; 1699 1700 if (qla_mbx_cmd(ha, (uint32_t *)rcv_mode, 1701 (sizeof (q80_config_mac_rcv_mode_t) >> 2), 1702 ha->hw.mbox, (sizeof(q80_config_mac_rcv_mode_rsp_t) >> 2), 1)) { 1703 device_printf(dev, "%s: failed0\n", __func__); 1704 return (-1); 1705 } 1706 rcv_mode_rsp = (q80_config_mac_rcv_mode_rsp_t *)ha->hw.mbox; 1707 1708 err = Q8_MBX_RSP_STATUS(rcv_mode_rsp->regcnt_status); 1709 1710 if (err) { 1711 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 1712 return (-1); 1713 } 1714 1715 return 0; 1716 } 1717 1718 int 1719 ql_set_promisc(qla_host_t *ha) 1720 { 1721 int ret; 1722 1723 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_RCV_PROMISC_ENABLE; 1724 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1725 return (ret); 1726 } 1727 1728 void 1729 qla_reset_promisc(qla_host_t *ha) 1730 { 1731 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_RCV_PROMISC_ENABLE; 1732 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1733 } 1734 1735 int 1736 ql_set_allmulti(qla_host_t *ha) 1737 { 1738 int ret; 1739 1740 ha->hw.mac_rcv_mode |= Q8_MBX_MAC_ALL_MULTI_ENABLE; 1741 ret = qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1742 return (ret); 1743 } 1744 1745 void 1746 qla_reset_allmulti(qla_host_t *ha) 1747 { 1748 ha->hw.mac_rcv_mode &= ~Q8_MBX_MAC_ALL_MULTI_ENABLE; 1749 (void)qla_set_mac_rcv_mode(ha, ha->hw.mac_rcv_mode); 1750 } 1751 1752 /* 1753 * Name: ql_set_max_mtu 1754 * Function: 1755 * Sets the maximum transfer unit size for the specified rcv context. 1756 */ 1757 int 1758 ql_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id) 1759 { 1760 device_t dev; 1761 q80_set_max_mtu_t *max_mtu; 1762 q80_set_max_mtu_rsp_t *max_mtu_rsp; 1763 uint32_t err; 1764 1765 dev = ha->pci_dev; 1766 1767 max_mtu = (q80_set_max_mtu_t *)ha->hw.mbox; 1768 bzero(max_mtu, (sizeof (q80_set_max_mtu_t))); 1769 1770 max_mtu->opcode = Q8_MBX_SET_MAX_MTU; 1771 max_mtu->count_version = (sizeof (q80_set_max_mtu_t) >> 2); 1772 max_mtu->count_version |= Q8_MBX_CMD_VERSION; 1773 1774 max_mtu->cntxt_id = cntxt_id; 1775 max_mtu->mtu = mtu; 1776 1777 if (qla_mbx_cmd(ha, (uint32_t *)max_mtu, 1778 (sizeof (q80_set_max_mtu_t) >> 2), 1779 ha->hw.mbox, (sizeof (q80_set_max_mtu_rsp_t) >> 2), 1)) { 1780 device_printf(dev, "%s: failed\n", __func__); 1781 return -1; 1782 } 1783 1784 max_mtu_rsp = (q80_set_max_mtu_rsp_t *)ha->hw.mbox; 1785 1786 err = Q8_MBX_RSP_STATUS(max_mtu_rsp->regcnt_status); 1787 1788 if (err) { 1789 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1790 } 1791 1792 return 0; 1793 } 1794 1795 static int 1796 qla_link_event_req(qla_host_t *ha, uint16_t cntxt_id) 1797 { 1798 device_t dev; 1799 q80_link_event_t *lnk; 1800 q80_link_event_rsp_t *lnk_rsp; 1801 uint32_t err; 1802 1803 dev = ha->pci_dev; 1804 1805 lnk = (q80_link_event_t *)ha->hw.mbox; 1806 bzero(lnk, (sizeof (q80_link_event_t))); 1807 1808 lnk->opcode = Q8_MBX_LINK_EVENT_REQ; 1809 lnk->count_version = (sizeof (q80_link_event_t) >> 2); 1810 lnk->count_version |= Q8_MBX_CMD_VERSION; 1811 1812 lnk->cntxt_id = cntxt_id; 1813 lnk->cmd = Q8_LINK_EVENT_CMD_ENABLE_ASYNC; 1814 1815 if (qla_mbx_cmd(ha, (uint32_t *)lnk, (sizeof (q80_link_event_t) >> 2), 1816 ha->hw.mbox, (sizeof (q80_link_event_rsp_t) >> 2), 0)) { 1817 device_printf(dev, "%s: failed\n", __func__); 1818 return -1; 1819 } 1820 1821 lnk_rsp = (q80_link_event_rsp_t *)ha->hw.mbox; 1822 1823 err = Q8_MBX_RSP_STATUS(lnk_rsp->regcnt_status); 1824 1825 if (err) { 1826 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1827 } 1828 1829 return 0; 1830 } 1831 1832 static int 1833 qla_config_fw_lro(qla_host_t *ha, uint16_t cntxt_id) 1834 { 1835 device_t dev; 1836 q80_config_fw_lro_t *fw_lro; 1837 q80_config_fw_lro_rsp_t *fw_lro_rsp; 1838 uint32_t err; 1839 1840 dev = ha->pci_dev; 1841 1842 fw_lro = (q80_config_fw_lro_t *)ha->hw.mbox; 1843 bzero(fw_lro, sizeof(q80_config_fw_lro_t)); 1844 1845 fw_lro->opcode = Q8_MBX_CONFIG_FW_LRO; 1846 fw_lro->count_version = (sizeof (q80_config_fw_lro_t) >> 2); 1847 fw_lro->count_version |= Q8_MBX_CMD_VERSION; 1848 1849 fw_lro->flags |= Q8_MBX_FW_LRO_IPV4 | Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK; 1850 fw_lro->flags |= Q8_MBX_FW_LRO_IPV6 | Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK; 1851 1852 fw_lro->cntxt_id = cntxt_id; 1853 1854 if (qla_mbx_cmd(ha, (uint32_t *)fw_lro, 1855 (sizeof (q80_config_fw_lro_t) >> 2), 1856 ha->hw.mbox, (sizeof (q80_config_fw_lro_rsp_t) >> 2), 0)) { 1857 device_printf(dev, "%s: failed\n", __func__); 1858 return -1; 1859 } 1860 1861 fw_lro_rsp = (q80_config_fw_lro_rsp_t *)ha->hw.mbox; 1862 1863 err = Q8_MBX_RSP_STATUS(fw_lro_rsp->regcnt_status); 1864 1865 if (err) { 1866 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1867 } 1868 1869 return 0; 1870 } 1871 1872 static int 1873 qla_set_cam_search_mode(qla_host_t *ha, uint32_t search_mode) 1874 { 1875 device_t dev; 1876 q80_hw_config_t *hw_config; 1877 q80_hw_config_rsp_t *hw_config_rsp; 1878 uint32_t err; 1879 1880 dev = ha->pci_dev; 1881 1882 hw_config = (q80_hw_config_t *)ha->hw.mbox; 1883 bzero(hw_config, sizeof (q80_hw_config_t)); 1884 1885 hw_config->opcode = Q8_MBX_HW_CONFIG; 1886 hw_config->count_version = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT; 1887 hw_config->count_version |= Q8_MBX_CMD_VERSION; 1888 1889 hw_config->cmd = Q8_HW_CONFIG_SET_CAM_SEARCH_MODE; 1890 1891 hw_config->u.set_cam_search_mode.mode = search_mode; 1892 1893 if (qla_mbx_cmd(ha, (uint32_t *)hw_config, 1894 (sizeof (q80_hw_config_t) >> 2), 1895 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) { 1896 device_printf(dev, "%s: failed\n", __func__); 1897 return -1; 1898 } 1899 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox; 1900 1901 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status); 1902 1903 if (err) { 1904 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1905 } 1906 1907 return 0; 1908 } 1909 1910 static int 1911 qla_get_cam_search_mode(qla_host_t *ha) 1912 { 1913 device_t dev; 1914 q80_hw_config_t *hw_config; 1915 q80_hw_config_rsp_t *hw_config_rsp; 1916 uint32_t err; 1917 1918 dev = ha->pci_dev; 1919 1920 hw_config = (q80_hw_config_t *)ha->hw.mbox; 1921 bzero(hw_config, sizeof (q80_hw_config_t)); 1922 1923 hw_config->opcode = Q8_MBX_HW_CONFIG; 1924 hw_config->count_version = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT; 1925 hw_config->count_version |= Q8_MBX_CMD_VERSION; 1926 1927 hw_config->cmd = Q8_HW_CONFIG_GET_CAM_SEARCH_MODE; 1928 1929 if (qla_mbx_cmd(ha, (uint32_t *)hw_config, 1930 (sizeof (q80_hw_config_t) >> 2), 1931 ha->hw.mbox, (sizeof (q80_hw_config_rsp_t) >> 2), 0)) { 1932 device_printf(dev, "%s: failed\n", __func__); 1933 return -1; 1934 } 1935 hw_config_rsp = (q80_hw_config_rsp_t *)ha->hw.mbox; 1936 1937 err = Q8_MBX_RSP_STATUS(hw_config_rsp->regcnt_status); 1938 1939 if (err) { 1940 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 1941 } else { 1942 device_printf(dev, "%s: cam search mode [0x%08x]\n", __func__, 1943 hw_config_rsp->u.get_cam_search_mode.mode); 1944 } 1945 1946 return 0; 1947 } 1948 1949 static int 1950 qla_get_hw_stats(qla_host_t *ha, uint32_t cmd, uint32_t rsp_size) 1951 { 1952 device_t dev; 1953 q80_get_stats_t *stat; 1954 q80_get_stats_rsp_t *stat_rsp; 1955 uint32_t err; 1956 1957 dev = ha->pci_dev; 1958 1959 stat = (q80_get_stats_t *)ha->hw.mbox; 1960 bzero(stat, (sizeof (q80_get_stats_t))); 1961 1962 stat->opcode = Q8_MBX_GET_STATS; 1963 stat->count_version = 2; 1964 stat->count_version |= Q8_MBX_CMD_VERSION; 1965 1966 stat->cmd = cmd; 1967 1968 if (qla_mbx_cmd(ha, (uint32_t *)stat, 2, 1969 ha->hw.mbox, (rsp_size >> 2), 0)) { 1970 device_printf(dev, "%s: failed\n", __func__); 1971 return -1; 1972 } 1973 1974 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox; 1975 1976 err = Q8_MBX_RSP_STATUS(stat_rsp->regcnt_status); 1977 1978 if (err) { 1979 return -1; 1980 } 1981 1982 return 0; 1983 } 1984 1985 void 1986 ql_get_stats(qla_host_t *ha) 1987 { 1988 q80_get_stats_rsp_t *stat_rsp; 1989 q80_mac_stats_t *mstat; 1990 q80_xmt_stats_t *xstat; 1991 q80_rcv_stats_t *rstat; 1992 uint32_t cmd; 1993 int i; 1994 struct ifnet *ifp = ha->ifp; 1995 1996 if (ifp == NULL) 1997 return; 1998 1999 if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) != 0) { 2000 device_printf(ha->pci_dev, "%s: failed\n", __func__); 2001 return; 2002 } 2003 2004 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2005 QLA_UNLOCK(ha, __func__); 2006 return; 2007 } 2008 2009 stat_rsp = (q80_get_stats_rsp_t *)ha->hw.mbox; 2010 /* 2011 * Get MAC Statistics 2012 */ 2013 cmd = Q8_GET_STATS_CMD_TYPE_MAC; 2014 // cmd |= Q8_GET_STATS_CMD_CLEAR; 2015 2016 cmd |= ((ha->pci_func & 0x1) << 16); 2017 2018 if (ha->qla_watchdog_pause) 2019 goto ql_get_stats_exit; 2020 2021 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) { 2022 mstat = (q80_mac_stats_t *)&stat_rsp->u.mac; 2023 bcopy(mstat, &ha->hw.mac, sizeof(q80_mac_stats_t)); 2024 } else { 2025 device_printf(ha->pci_dev, "%s: mac failed [0x%08x]\n", 2026 __func__, ha->hw.mbox[0]); 2027 } 2028 /* 2029 * Get RCV Statistics 2030 */ 2031 cmd = Q8_GET_STATS_CMD_RCV | Q8_GET_STATS_CMD_TYPE_CNTXT; 2032 // cmd |= Q8_GET_STATS_CMD_CLEAR; 2033 cmd |= (ha->hw.rcv_cntxt_id << 16); 2034 2035 if (ha->qla_watchdog_pause) 2036 goto ql_get_stats_exit; 2037 2038 if (qla_get_hw_stats(ha, cmd, sizeof (q80_get_stats_rsp_t)) == 0) { 2039 rstat = (q80_rcv_stats_t *)&stat_rsp->u.rcv; 2040 bcopy(rstat, &ha->hw.rcv, sizeof(q80_rcv_stats_t)); 2041 } else { 2042 device_printf(ha->pci_dev, "%s: rcv failed [0x%08x]\n", 2043 __func__, ha->hw.mbox[0]); 2044 } 2045 2046 if (ha->qla_watchdog_pause) 2047 goto ql_get_stats_exit; 2048 /* 2049 * Get XMT Statistics 2050 */ 2051 for (i = 0 ; ((i < ha->hw.num_tx_rings) && (!ha->qla_watchdog_pause)); 2052 i++) { 2053 cmd = Q8_GET_STATS_CMD_XMT | Q8_GET_STATS_CMD_TYPE_CNTXT; 2054 // cmd |= Q8_GET_STATS_CMD_CLEAR; 2055 cmd |= (ha->hw.tx_cntxt[i].tx_cntxt_id << 16); 2056 2057 if (qla_get_hw_stats(ha, cmd, sizeof(q80_get_stats_rsp_t)) 2058 == 0) { 2059 xstat = (q80_xmt_stats_t *)&stat_rsp->u.xmt; 2060 bcopy(xstat, &ha->hw.xmt[i], sizeof(q80_xmt_stats_t)); 2061 } else { 2062 device_printf(ha->pci_dev, "%s: xmt failed [0x%08x]\n", 2063 __func__, ha->hw.mbox[0]); 2064 } 2065 } 2066 2067 ql_get_stats_exit: 2068 QLA_UNLOCK(ha, __func__); 2069 2070 return; 2071 } 2072 2073 /* 2074 * Name: qla_tx_tso 2075 * Function: Checks if the packet to be transmitted is a candidate for 2076 * Large TCP Segment Offload. If yes, the appropriate fields in the Tx 2077 * Ring Structure are plugged in. 2078 */ 2079 static int 2080 qla_tx_tso(qla_host_t *ha, struct mbuf *mp, q80_tx_cmd_t *tx_cmd, uint8_t *hdr) 2081 { 2082 struct ether_vlan_header *eh; 2083 struct ip *ip = NULL; 2084 struct ip6_hdr *ip6 = NULL; 2085 struct tcphdr *th = NULL; 2086 uint32_t ehdrlen, hdrlen, ip_hlen, tcp_hlen, tcp_opt_off; 2087 uint16_t etype, opcode, offload = 1; 2088 device_t dev; 2089 2090 dev = ha->pci_dev; 2091 2092 2093 eh = mtod(mp, struct ether_vlan_header *); 2094 2095 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2096 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2097 etype = ntohs(eh->evl_proto); 2098 } else { 2099 ehdrlen = ETHER_HDR_LEN; 2100 etype = ntohs(eh->evl_encap_proto); 2101 } 2102 2103 hdrlen = 0; 2104 2105 switch (etype) { 2106 case ETHERTYPE_IP: 2107 2108 tcp_opt_off = ehdrlen + sizeof(struct ip) + 2109 sizeof(struct tcphdr); 2110 2111 if (mp->m_len < tcp_opt_off) { 2112 m_copydata(mp, 0, tcp_opt_off, hdr); 2113 ip = (struct ip *)(hdr + ehdrlen); 2114 } else { 2115 ip = (struct ip *)(mp->m_data + ehdrlen); 2116 } 2117 2118 ip_hlen = ip->ip_hl << 2; 2119 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO; 2120 2121 2122 if ((ip->ip_p != IPPROTO_TCP) || 2123 (ip_hlen != sizeof (struct ip))){ 2124 /* IP Options are not supported */ 2125 2126 offload = 0; 2127 } else 2128 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 2129 2130 break; 2131 2132 case ETHERTYPE_IPV6: 2133 2134 tcp_opt_off = ehdrlen + sizeof(struct ip6_hdr) + 2135 sizeof (struct tcphdr); 2136 2137 if (mp->m_len < tcp_opt_off) { 2138 m_copydata(mp, 0, tcp_opt_off, hdr); 2139 ip6 = (struct ip6_hdr *)(hdr + ehdrlen); 2140 } else { 2141 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 2142 } 2143 2144 ip_hlen = sizeof(struct ip6_hdr); 2145 opcode = Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6; 2146 2147 if (ip6->ip6_nxt != IPPROTO_TCP) { 2148 //device_printf(dev, "%s: ipv6\n", __func__); 2149 offload = 0; 2150 } else 2151 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen); 2152 break; 2153 2154 default: 2155 QL_DPRINT8(ha, (dev, "%s: type!=ip\n", __func__)); 2156 offload = 0; 2157 break; 2158 } 2159 2160 if (!offload) 2161 return (-1); 2162 2163 tcp_hlen = th->th_off << 2; 2164 hdrlen = ehdrlen + ip_hlen + tcp_hlen; 2165 2166 if (mp->m_len < hdrlen) { 2167 if (mp->m_len < tcp_opt_off) { 2168 if (tcp_hlen > sizeof(struct tcphdr)) { 2169 m_copydata(mp, tcp_opt_off, 2170 (tcp_hlen - sizeof(struct tcphdr)), 2171 &hdr[tcp_opt_off]); 2172 } 2173 } else { 2174 m_copydata(mp, 0, hdrlen, hdr); 2175 } 2176 } 2177 2178 tx_cmd->mss = mp->m_pkthdr.tso_segsz; 2179 2180 tx_cmd->flags_opcode = opcode ; 2181 tx_cmd->tcp_hdr_off = ip_hlen + ehdrlen; 2182 tx_cmd->total_hdr_len = hdrlen; 2183 2184 /* Check for Multicast least significant bit of MSB == 1 */ 2185 if (eh->evl_dhost[0] & 0x01) { 2186 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_MULTICAST; 2187 } 2188 2189 if (mp->m_len < hdrlen) { 2190 printf("%d\n", hdrlen); 2191 return (1); 2192 } 2193 2194 return (0); 2195 } 2196 2197 /* 2198 * Name: qla_tx_chksum 2199 * Function: Checks if the packet to be transmitted is a candidate for 2200 * TCP/UDP Checksum offload. If yes, the appropriate fields in the Tx 2201 * Ring Structure are plugged in. 2202 */ 2203 static int 2204 qla_tx_chksum(qla_host_t *ha, struct mbuf *mp, uint32_t *op_code, 2205 uint32_t *tcp_hdr_off) 2206 { 2207 struct ether_vlan_header *eh; 2208 struct ip *ip; 2209 struct ip6_hdr *ip6; 2210 uint32_t ehdrlen, ip_hlen; 2211 uint16_t etype, opcode, offload = 1; 2212 device_t dev; 2213 uint8_t buf[sizeof(struct ip6_hdr)]; 2214 2215 dev = ha->pci_dev; 2216 2217 *op_code = 0; 2218 2219 if ((mp->m_pkthdr.csum_flags & 2220 (CSUM_TCP|CSUM_UDP|CSUM_TCP_IPV6 | CSUM_UDP_IPV6)) == 0) 2221 return (-1); 2222 2223 eh = mtod(mp, struct ether_vlan_header *); 2224 2225 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2226 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2227 etype = ntohs(eh->evl_proto); 2228 } else { 2229 ehdrlen = ETHER_HDR_LEN; 2230 etype = ntohs(eh->evl_encap_proto); 2231 } 2232 2233 2234 switch (etype) { 2235 case ETHERTYPE_IP: 2236 ip = (struct ip *)(mp->m_data + ehdrlen); 2237 2238 ip_hlen = sizeof (struct ip); 2239 2240 if (mp->m_len < (ehdrlen + ip_hlen)) { 2241 m_copydata(mp, ehdrlen, sizeof(struct ip), buf); 2242 ip = (struct ip *)buf; 2243 } 2244 2245 if (ip->ip_p == IPPROTO_TCP) 2246 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM; 2247 else if (ip->ip_p == IPPROTO_UDP) 2248 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM; 2249 else { 2250 //device_printf(dev, "%s: ipv4\n", __func__); 2251 offload = 0; 2252 } 2253 break; 2254 2255 case ETHERTYPE_IPV6: 2256 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 2257 2258 ip_hlen = sizeof(struct ip6_hdr); 2259 2260 if (mp->m_len < (ehdrlen + ip_hlen)) { 2261 m_copydata(mp, ehdrlen, sizeof (struct ip6_hdr), 2262 buf); 2263 ip6 = (struct ip6_hdr *)buf; 2264 } 2265 2266 if (ip6->ip6_nxt == IPPROTO_TCP) 2267 opcode = Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6; 2268 else if (ip6->ip6_nxt == IPPROTO_UDP) 2269 opcode = Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6; 2270 else { 2271 //device_printf(dev, "%s: ipv6\n", __func__); 2272 offload = 0; 2273 } 2274 break; 2275 2276 default: 2277 offload = 0; 2278 break; 2279 } 2280 if (!offload) 2281 return (-1); 2282 2283 *op_code = opcode; 2284 *tcp_hdr_off = (ip_hlen + ehdrlen); 2285 2286 return (0); 2287 } 2288 2289 #define QLA_TX_MIN_FREE 2 2290 /* 2291 * Name: ql_hw_send 2292 * Function: Transmits a packet. It first checks if the packet is a 2293 * candidate for Large TCP Segment Offload and then for UDP/TCP checksum 2294 * offload. If either of these creteria are not met, it is transmitted 2295 * as a regular ethernet frame. 2296 */ 2297 int 2298 ql_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs, 2299 uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx, uint32_t iscsi_pdu) 2300 { 2301 struct ether_vlan_header *eh; 2302 qla_hw_t *hw = &ha->hw; 2303 q80_tx_cmd_t *tx_cmd, tso_cmd; 2304 bus_dma_segment_t *c_seg; 2305 uint32_t num_tx_cmds, hdr_len = 0; 2306 uint32_t total_length = 0, bytes, tx_cmd_count = 0, txr_next; 2307 device_t dev; 2308 int i, ret; 2309 uint8_t *src = NULL, *dst = NULL; 2310 uint8_t frame_hdr[QL_FRAME_HDR_SIZE]; 2311 uint32_t op_code = 0; 2312 uint32_t tcp_hdr_off = 0; 2313 2314 dev = ha->pci_dev; 2315 2316 /* 2317 * Always make sure there is atleast one empty slot in the tx_ring 2318 * tx_ring is considered full when there only one entry available 2319 */ 2320 num_tx_cmds = (nsegs + (Q8_TX_CMD_MAX_SEGMENTS - 1)) >> 2; 2321 2322 total_length = mp->m_pkthdr.len; 2323 if (total_length > QLA_MAX_TSO_FRAME_SIZE) { 2324 device_printf(dev, "%s: total length exceeds maxlen(%d)\n", 2325 __func__, total_length); 2326 return (EINVAL); 2327 } 2328 eh = mtod(mp, struct ether_vlan_header *); 2329 2330 if (mp->m_pkthdr.csum_flags & CSUM_TSO) { 2331 2332 bzero((void *)&tso_cmd, sizeof(q80_tx_cmd_t)); 2333 2334 src = frame_hdr; 2335 ret = qla_tx_tso(ha, mp, &tso_cmd, src); 2336 2337 if (!(ret & ~1)) { 2338 /* find the additional tx_cmd descriptors required */ 2339 2340 if (mp->m_flags & M_VLANTAG) 2341 tso_cmd.total_hdr_len += ETHER_VLAN_ENCAP_LEN; 2342 2343 hdr_len = tso_cmd.total_hdr_len; 2344 2345 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN; 2346 bytes = QL_MIN(bytes, hdr_len); 2347 2348 num_tx_cmds++; 2349 hdr_len -= bytes; 2350 2351 while (hdr_len) { 2352 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len); 2353 hdr_len -= bytes; 2354 num_tx_cmds++; 2355 } 2356 hdr_len = tso_cmd.total_hdr_len; 2357 2358 if (ret == 0) 2359 src = (uint8_t *)eh; 2360 } else 2361 return (EINVAL); 2362 } else { 2363 (void)qla_tx_chksum(ha, mp, &op_code, &tcp_hdr_off); 2364 } 2365 2366 if (hw->tx_cntxt[txr_idx].txr_free <= (num_tx_cmds + QLA_TX_MIN_FREE)) { 2367 ql_hw_tx_done_locked(ha, txr_idx); 2368 if (hw->tx_cntxt[txr_idx].txr_free <= 2369 (num_tx_cmds + QLA_TX_MIN_FREE)) { 2370 QL_DPRINT8(ha, (dev, "%s: (hw->txr_free <= " 2371 "(num_tx_cmds + QLA_TX_MIN_FREE))\n", 2372 __func__)); 2373 return (-1); 2374 } 2375 } 2376 2377 for (i = 0; i < num_tx_cmds; i++) { 2378 if (NULL != ha->tx_ring[txr_idx].tx_buf[(tx_idx+i)].m_head) { 2379 QL_ASSERT(ha, 0, \ 2380 ("%s: txr_idx = %d tx_idx = %d mbuf = %p\n",\ 2381 __func__, txr_idx, (tx_idx+i),\ 2382 ha->tx_ring[txr_idx].tx_buf[(tx_idx+i)].m_head)); 2383 return (EINVAL); 2384 } 2385 } 2386 2387 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[tx_idx]; 2388 2389 if (!(mp->m_pkthdr.csum_flags & CSUM_TSO)) { 2390 2391 if (nsegs > ha->hw.max_tx_segs) 2392 ha->hw.max_tx_segs = nsegs; 2393 2394 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2395 2396 if (op_code) { 2397 tx_cmd->flags_opcode = op_code; 2398 tx_cmd->tcp_hdr_off = tcp_hdr_off; 2399 2400 } else { 2401 tx_cmd->flags_opcode = Q8_TX_CMD_OP_XMT_ETHER; 2402 } 2403 } else { 2404 bcopy(&tso_cmd, tx_cmd, sizeof(q80_tx_cmd_t)); 2405 ha->tx_tso_frames++; 2406 } 2407 2408 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 2409 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_VLAN_TAGGED; 2410 2411 if (iscsi_pdu) 2412 eh->evl_tag |= ha->hw.user_pri_iscsi << 13; 2413 2414 } else if (mp->m_flags & M_VLANTAG) { 2415 2416 if (hdr_len) { /* TSO */ 2417 tx_cmd->flags_opcode |= (Q8_TX_CMD_FLAGS_VLAN_TAGGED | 2418 Q8_TX_CMD_FLAGS_HW_VLAN_ID); 2419 tx_cmd->tcp_hdr_off += ETHER_VLAN_ENCAP_LEN; 2420 } else 2421 tx_cmd->flags_opcode |= Q8_TX_CMD_FLAGS_HW_VLAN_ID; 2422 2423 ha->hw_vlan_tx_frames++; 2424 tx_cmd->vlan_tci = mp->m_pkthdr.ether_vtag; 2425 2426 if (iscsi_pdu) { 2427 tx_cmd->vlan_tci |= ha->hw.user_pri_iscsi << 13; 2428 mp->m_pkthdr.ether_vtag = tx_cmd->vlan_tci; 2429 } 2430 } 2431 2432 2433 tx_cmd->n_bufs = (uint8_t)nsegs; 2434 tx_cmd->data_len_lo = (uint8_t)(total_length & 0xFF); 2435 tx_cmd->data_len_hi = qla_host_to_le16(((uint16_t)(total_length >> 8))); 2436 tx_cmd->cntxtid = Q8_TX_CMD_PORT_CNXTID(ha->pci_func); 2437 2438 c_seg = segs; 2439 2440 while (1) { 2441 for (i = 0; ((i < Q8_TX_CMD_MAX_SEGMENTS) && nsegs); i++) { 2442 2443 switch (i) { 2444 case 0: 2445 tx_cmd->buf1_addr = c_seg->ds_addr; 2446 tx_cmd->buf1_len = c_seg->ds_len; 2447 break; 2448 2449 case 1: 2450 tx_cmd->buf2_addr = c_seg->ds_addr; 2451 tx_cmd->buf2_len = c_seg->ds_len; 2452 break; 2453 2454 case 2: 2455 tx_cmd->buf3_addr = c_seg->ds_addr; 2456 tx_cmd->buf3_len = c_seg->ds_len; 2457 break; 2458 2459 case 3: 2460 tx_cmd->buf4_addr = c_seg->ds_addr; 2461 tx_cmd->buf4_len = c_seg->ds_len; 2462 break; 2463 } 2464 2465 c_seg++; 2466 nsegs--; 2467 } 2468 2469 txr_next = hw->tx_cntxt[txr_idx].txr_next = 2470 (hw->tx_cntxt[txr_idx].txr_next + 1) & 2471 (NUM_TX_DESCRIPTORS - 1); 2472 tx_cmd_count++; 2473 2474 if (!nsegs) 2475 break; 2476 2477 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next]; 2478 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2479 } 2480 2481 if (mp->m_pkthdr.csum_flags & CSUM_TSO) { 2482 2483 /* TSO : Copy the header in the following tx cmd descriptors */ 2484 2485 txr_next = hw->tx_cntxt[txr_idx].txr_next; 2486 2487 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next]; 2488 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2489 2490 bytes = sizeof(q80_tx_cmd_t) - Q8_TX_CMD_TSO_ALIGN; 2491 bytes = QL_MIN(bytes, hdr_len); 2492 2493 dst = (uint8_t *)tx_cmd + Q8_TX_CMD_TSO_ALIGN; 2494 2495 if (mp->m_flags & M_VLANTAG) { 2496 /* first copy the src/dst MAC addresses */ 2497 bcopy(src, dst, (ETHER_ADDR_LEN * 2)); 2498 dst += (ETHER_ADDR_LEN * 2); 2499 src += (ETHER_ADDR_LEN * 2); 2500 2501 *((uint16_t *)dst) = htons(ETHERTYPE_VLAN); 2502 dst += 2; 2503 *((uint16_t *)dst) = htons(mp->m_pkthdr.ether_vtag); 2504 dst += 2; 2505 2506 /* bytes left in src header */ 2507 hdr_len -= ((ETHER_ADDR_LEN * 2) + 2508 ETHER_VLAN_ENCAP_LEN); 2509 2510 /* bytes left in TxCmd Entry */ 2511 bytes -= ((ETHER_ADDR_LEN * 2) + ETHER_VLAN_ENCAP_LEN); 2512 2513 2514 bcopy(src, dst, bytes); 2515 src += bytes; 2516 hdr_len -= bytes; 2517 } else { 2518 bcopy(src, dst, bytes); 2519 src += bytes; 2520 hdr_len -= bytes; 2521 } 2522 2523 txr_next = hw->tx_cntxt[txr_idx].txr_next = 2524 (hw->tx_cntxt[txr_idx].txr_next + 1) & 2525 (NUM_TX_DESCRIPTORS - 1); 2526 tx_cmd_count++; 2527 2528 while (hdr_len) { 2529 tx_cmd = &hw->tx_cntxt[txr_idx].tx_ring_base[txr_next]; 2530 bzero((void *)tx_cmd, sizeof(q80_tx_cmd_t)); 2531 2532 bytes = QL_MIN((sizeof(q80_tx_cmd_t)), hdr_len); 2533 2534 bcopy(src, tx_cmd, bytes); 2535 src += bytes; 2536 hdr_len -= bytes; 2537 2538 txr_next = hw->tx_cntxt[txr_idx].txr_next = 2539 (hw->tx_cntxt[txr_idx].txr_next + 1) & 2540 (NUM_TX_DESCRIPTORS - 1); 2541 tx_cmd_count++; 2542 } 2543 } 2544 2545 hw->tx_cntxt[txr_idx].txr_free = 2546 hw->tx_cntxt[txr_idx].txr_free - tx_cmd_count; 2547 2548 QL_UPDATE_TX_PRODUCER_INDEX(ha, hw->tx_cntxt[txr_idx].txr_next,\ 2549 txr_idx); 2550 QL_DPRINT8(ha, (dev, "%s: return\n", __func__)); 2551 2552 return (0); 2553 } 2554 2555 2556 2557 #define Q8_CONFIG_IND_TBL_SIZE 32 /* < Q8_RSS_IND_TBL_SIZE and power of 2 */ 2558 static int 2559 qla_config_rss_ind_table(qla_host_t *ha) 2560 { 2561 uint32_t i, count; 2562 uint8_t rss_ind_tbl[Q8_CONFIG_IND_TBL_SIZE]; 2563 2564 2565 for (i = 0; i < Q8_CONFIG_IND_TBL_SIZE; i++) { 2566 rss_ind_tbl[i] = i % ha->hw.num_sds_rings; 2567 } 2568 2569 for (i = 0; i <= Q8_RSS_IND_TBL_MAX_IDX ; 2570 i = i + Q8_CONFIG_IND_TBL_SIZE) { 2571 2572 if ((i + Q8_CONFIG_IND_TBL_SIZE) > Q8_RSS_IND_TBL_MAX_IDX) { 2573 count = Q8_RSS_IND_TBL_MAX_IDX - i + 1; 2574 } else { 2575 count = Q8_CONFIG_IND_TBL_SIZE; 2576 } 2577 2578 if (qla_set_rss_ind_table(ha, i, count, ha->hw.rcv_cntxt_id, 2579 rss_ind_tbl)) 2580 return (-1); 2581 } 2582 2583 return (0); 2584 } 2585 2586 static int 2587 qla_config_soft_lro(qla_host_t *ha) 2588 { 2589 int i; 2590 qla_hw_t *hw = &ha->hw; 2591 struct lro_ctrl *lro; 2592 2593 for (i = 0; i < hw->num_sds_rings; i++) { 2594 lro = &hw->sds[i].lro; 2595 2596 bzero(lro, sizeof(struct lro_ctrl)); 2597 2598 #if (__FreeBSD_version >= 1100101) 2599 if (tcp_lro_init_args(lro, ha->ifp, 0, NUM_RX_DESCRIPTORS)) { 2600 device_printf(ha->pci_dev, 2601 "%s: tcp_lro_init_args [%d] failed\n", 2602 __func__, i); 2603 return (-1); 2604 } 2605 #else 2606 if (tcp_lro_init(lro)) { 2607 device_printf(ha->pci_dev, 2608 "%s: tcp_lro_init [%d] failed\n", 2609 __func__, i); 2610 return (-1); 2611 } 2612 #endif /* #if (__FreeBSD_version >= 1100101) */ 2613 2614 lro->ifp = ha->ifp; 2615 } 2616 2617 QL_DPRINT2(ha, (ha->pci_dev, "%s: LRO initialized\n", __func__)); 2618 return (0); 2619 } 2620 2621 static void 2622 qla_drain_soft_lro(qla_host_t *ha) 2623 { 2624 int i; 2625 qla_hw_t *hw = &ha->hw; 2626 struct lro_ctrl *lro; 2627 2628 for (i = 0; i < hw->num_sds_rings; i++) { 2629 lro = &hw->sds[i].lro; 2630 2631 #if (__FreeBSD_version >= 1100101) 2632 tcp_lro_flush_all(lro); 2633 #else 2634 struct lro_entry *queued; 2635 2636 while ((!SLIST_EMPTY(&lro->lro_active))) { 2637 queued = SLIST_FIRST(&lro->lro_active); 2638 SLIST_REMOVE_HEAD(&lro->lro_active, next); 2639 tcp_lro_flush(lro, queued); 2640 } 2641 #endif /* #if (__FreeBSD_version >= 1100101) */ 2642 } 2643 2644 return; 2645 } 2646 2647 static void 2648 qla_free_soft_lro(qla_host_t *ha) 2649 { 2650 int i; 2651 qla_hw_t *hw = &ha->hw; 2652 struct lro_ctrl *lro; 2653 2654 for (i = 0; i < hw->num_sds_rings; i++) { 2655 lro = &hw->sds[i].lro; 2656 tcp_lro_free(lro); 2657 } 2658 2659 return; 2660 } 2661 2662 2663 /* 2664 * Name: ql_del_hw_if 2665 * Function: Destroys the hardware specific entities corresponding to an 2666 * Ethernet Interface 2667 */ 2668 void 2669 ql_del_hw_if(qla_host_t *ha) 2670 { 2671 uint32_t i; 2672 uint32_t num_msix; 2673 2674 (void)qla_stop_nic_func(ha); 2675 2676 qla_del_rcv_cntxt(ha); 2677 2678 qla_del_xmt_cntxt(ha); 2679 2680 if (ha->hw.flags.init_intr_cnxt) { 2681 for (i = 0; i < ha->hw.num_sds_rings; ) { 2682 2683 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings) 2684 num_msix = Q8_MAX_INTR_VECTORS; 2685 else 2686 num_msix = ha->hw.num_sds_rings - i; 2687 qla_config_intr_cntxt(ha, i, num_msix, 0); 2688 2689 i += num_msix; 2690 } 2691 2692 ha->hw.flags.init_intr_cnxt = 0; 2693 } 2694 2695 if (ha->hw.enable_soft_lro) { 2696 qla_drain_soft_lro(ha); 2697 qla_free_soft_lro(ha); 2698 } 2699 2700 return; 2701 } 2702 2703 void 2704 qla_confirm_9kb_enable(qla_host_t *ha) 2705 { 2706 uint32_t supports_9kb = 0; 2707 2708 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX); 2709 2710 /* Use MSI-X vector 0; Enable Firmware Mailbox Interrupt */ 2711 WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2); 2712 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0); 2713 2714 qla_get_nic_partition(ha, &supports_9kb, NULL); 2715 2716 if (!supports_9kb) 2717 ha->hw.enable_9kb = 0; 2718 2719 return; 2720 } 2721 2722 /* 2723 * Name: ql_init_hw_if 2724 * Function: Creates the hardware specific entities corresponding to an 2725 * Ethernet Interface - Transmit and Receive Contexts. Sets the MAC Address 2726 * corresponding to the interface. Enables LRO if allowed. 2727 */ 2728 int 2729 ql_init_hw_if(qla_host_t *ha) 2730 { 2731 device_t dev; 2732 uint32_t i; 2733 uint8_t bcast_mac[6]; 2734 qla_rdesc_t *rdesc; 2735 uint32_t num_msix; 2736 2737 dev = ha->pci_dev; 2738 2739 for (i = 0; i < ha->hw.num_sds_rings; i++) { 2740 bzero(ha->hw.dma_buf.sds_ring[i].dma_b, 2741 ha->hw.dma_buf.sds_ring[i].size); 2742 } 2743 2744 for (i = 0; i < ha->hw.num_sds_rings; ) { 2745 2746 if ((i + Q8_MAX_INTR_VECTORS) < ha->hw.num_sds_rings) 2747 num_msix = Q8_MAX_INTR_VECTORS; 2748 else 2749 num_msix = ha->hw.num_sds_rings - i; 2750 2751 if (qla_config_intr_cntxt(ha, i, num_msix, 1)) { 2752 2753 if (i > 0) { 2754 2755 num_msix = i; 2756 2757 for (i = 0; i < num_msix; ) { 2758 qla_config_intr_cntxt(ha, i, 2759 Q8_MAX_INTR_VECTORS, 0); 2760 i += Q8_MAX_INTR_VECTORS; 2761 } 2762 } 2763 return (-1); 2764 } 2765 2766 i = i + num_msix; 2767 } 2768 2769 ha->hw.flags.init_intr_cnxt = 1; 2770 2771 /* 2772 * Create Receive Context 2773 */ 2774 if (qla_init_rcv_cntxt(ha)) { 2775 return (-1); 2776 } 2777 2778 for (i = 0; i < ha->hw.num_rds_rings; i++) { 2779 rdesc = &ha->hw.rds[i]; 2780 rdesc->rx_next = NUM_RX_DESCRIPTORS - 2; 2781 rdesc->rx_in = 0; 2782 /* Update the RDS Producer Indices */ 2783 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,\ 2784 rdesc->rx_next); 2785 } 2786 2787 /* 2788 * Create Transmit Context 2789 */ 2790 if (qla_init_xmt_cntxt(ha)) { 2791 qla_del_rcv_cntxt(ha); 2792 return (-1); 2793 } 2794 ha->hw.max_tx_segs = 0; 2795 2796 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 1, 1)) 2797 return(-1); 2798 2799 ha->hw.flags.unicast_mac = 1; 2800 2801 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF; 2802 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF; 2803 2804 if (qla_config_mac_addr(ha, bcast_mac, 1, 1)) 2805 return (-1); 2806 2807 ha->hw.flags.bcast_mac = 1; 2808 2809 /* 2810 * program any cached multicast addresses 2811 */ 2812 if (qla_hw_add_all_mcast(ha)) 2813 return (-1); 2814 2815 if (ql_set_max_mtu(ha, ha->max_frame_size, ha->hw.rcv_cntxt_id)) 2816 return (-1); 2817 2818 if (qla_config_rss(ha, ha->hw.rcv_cntxt_id)) 2819 return (-1); 2820 2821 if (qla_config_rss_ind_table(ha)) 2822 return (-1); 2823 2824 if (qla_config_intr_coalesce(ha, ha->hw.rcv_cntxt_id, 0, 1)) 2825 return (-1); 2826 2827 if (qla_link_event_req(ha, ha->hw.rcv_cntxt_id)) 2828 return (-1); 2829 2830 if (ha->ifp->if_capenable & IFCAP_LRO) { 2831 if (ha->hw.enable_hw_lro) { 2832 ha->hw.enable_soft_lro = 0; 2833 2834 if (qla_config_fw_lro(ha, ha->hw.rcv_cntxt_id)) 2835 return (-1); 2836 } else { 2837 ha->hw.enable_soft_lro = 1; 2838 2839 if (qla_config_soft_lro(ha)) 2840 return (-1); 2841 } 2842 } 2843 2844 if (qla_init_nic_func(ha)) 2845 return (-1); 2846 2847 if (qla_query_fw_dcbx_caps(ha)) 2848 return (-1); 2849 2850 for (i = 0; i < ha->hw.num_sds_rings; i++) 2851 QL_ENABLE_INTERRUPTS(ha, i); 2852 2853 return (0); 2854 } 2855 2856 static int 2857 qla_map_sds_to_rds(qla_host_t *ha, uint32_t start_idx, uint32_t num_idx) 2858 { 2859 device_t dev = ha->pci_dev; 2860 q80_rq_map_sds_to_rds_t *map_rings; 2861 q80_rsp_map_sds_to_rds_t *map_rings_rsp; 2862 uint32_t i, err; 2863 qla_hw_t *hw = &ha->hw; 2864 2865 map_rings = (q80_rq_map_sds_to_rds_t *)ha->hw.mbox; 2866 bzero(map_rings, sizeof(q80_rq_map_sds_to_rds_t)); 2867 2868 map_rings->opcode = Q8_MBX_MAP_SDS_TO_RDS; 2869 map_rings->count_version = (sizeof (q80_rq_map_sds_to_rds_t) >> 2); 2870 map_rings->count_version |= Q8_MBX_CMD_VERSION; 2871 2872 map_rings->cntxt_id = hw->rcv_cntxt_id; 2873 map_rings->num_rings = num_idx; 2874 2875 for (i = 0; i < num_idx; i++) { 2876 map_rings->sds_rds[i].sds_ring = i + start_idx; 2877 map_rings->sds_rds[i].rds_ring = i + start_idx; 2878 } 2879 2880 if (qla_mbx_cmd(ha, (uint32_t *)map_rings, 2881 (sizeof (q80_rq_map_sds_to_rds_t) >> 2), 2882 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) { 2883 device_printf(dev, "%s: failed0\n", __func__); 2884 return (-1); 2885 } 2886 2887 map_rings_rsp = (q80_rsp_map_sds_to_rds_t *)ha->hw.mbox; 2888 2889 err = Q8_MBX_RSP_STATUS(map_rings_rsp->regcnt_status); 2890 2891 if (err) { 2892 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 2893 return (-1); 2894 } 2895 2896 return (0); 2897 } 2898 2899 /* 2900 * Name: qla_init_rcv_cntxt 2901 * Function: Creates the Receive Context. 2902 */ 2903 static int 2904 qla_init_rcv_cntxt(qla_host_t *ha) 2905 { 2906 q80_rq_rcv_cntxt_t *rcntxt; 2907 q80_rsp_rcv_cntxt_t *rcntxt_rsp; 2908 q80_stat_desc_t *sdesc; 2909 int i, j; 2910 qla_hw_t *hw = &ha->hw; 2911 device_t dev; 2912 uint32_t err; 2913 uint32_t rcntxt_sds_rings; 2914 uint32_t rcntxt_rds_rings; 2915 uint32_t max_idx; 2916 2917 dev = ha->pci_dev; 2918 2919 /* 2920 * Create Receive Context 2921 */ 2922 2923 for (i = 0; i < hw->num_sds_rings; i++) { 2924 sdesc = (q80_stat_desc_t *)&hw->sds[i].sds_ring_base[0]; 2925 2926 for (j = 0; j < NUM_STATUS_DESCRIPTORS; j++) { 2927 sdesc->data[0] = 1ULL; 2928 sdesc->data[1] = 1ULL; 2929 } 2930 } 2931 2932 rcntxt_sds_rings = hw->num_sds_rings; 2933 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) 2934 rcntxt_sds_rings = MAX_RCNTXT_SDS_RINGS; 2935 2936 rcntxt_rds_rings = hw->num_rds_rings; 2937 2938 if (hw->num_rds_rings > MAX_RDS_RING_SETS) 2939 rcntxt_rds_rings = MAX_RDS_RING_SETS; 2940 2941 rcntxt = (q80_rq_rcv_cntxt_t *)ha->hw.mbox; 2942 bzero(rcntxt, (sizeof (q80_rq_rcv_cntxt_t))); 2943 2944 rcntxt->opcode = Q8_MBX_CREATE_RX_CNTXT; 2945 rcntxt->count_version = (sizeof (q80_rq_rcv_cntxt_t) >> 2); 2946 rcntxt->count_version |= Q8_MBX_CMD_VERSION; 2947 2948 rcntxt->cap0 = Q8_RCV_CNTXT_CAP0_BASEFW | 2949 Q8_RCV_CNTXT_CAP0_LRO | 2950 Q8_RCV_CNTXT_CAP0_HW_LRO | 2951 Q8_RCV_CNTXT_CAP0_RSS | 2952 Q8_RCV_CNTXT_CAP0_SGL_LRO; 2953 2954 if (ha->hw.enable_9kb) 2955 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO; 2956 else 2957 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_SGL_JUMBO; 2958 2959 if (ha->hw.num_rds_rings > 1) { 2960 rcntxt->nrds_sets_rings = rcntxt_rds_rings | (1 << 5); 2961 rcntxt->cap0 |= Q8_RCV_CNTXT_CAP0_MULTI_RDS; 2962 } else 2963 rcntxt->nrds_sets_rings = 0x1 | (1 << 5); 2964 2965 rcntxt->nsds_rings = rcntxt_sds_rings; 2966 2967 rcntxt->rds_producer_mode = Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE; 2968 2969 rcntxt->rcv_vpid = 0; 2970 2971 for (i = 0; i < rcntxt_sds_rings; i++) { 2972 rcntxt->sds[i].paddr = 2973 qla_host_to_le64(hw->dma_buf.sds_ring[i].dma_addr); 2974 rcntxt->sds[i].size = 2975 qla_host_to_le32(NUM_STATUS_DESCRIPTORS); 2976 rcntxt->sds[i].intr_id = qla_host_to_le16(hw->intr_id[i]); 2977 rcntxt->sds[i].intr_src_bit = qla_host_to_le16(0); 2978 } 2979 2980 for (i = 0; i < rcntxt_rds_rings; i++) { 2981 rcntxt->rds[i].paddr_std = 2982 qla_host_to_le64(hw->dma_buf.rds_ring[i].dma_addr); 2983 2984 if (ha->hw.enable_9kb) 2985 rcntxt->rds[i].std_bsize = 2986 qla_host_to_le64(MJUM9BYTES); 2987 else 2988 rcntxt->rds[i].std_bsize = qla_host_to_le64(MCLBYTES); 2989 2990 rcntxt->rds[i].std_nentries = 2991 qla_host_to_le32(NUM_RX_DESCRIPTORS); 2992 } 2993 2994 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt, 2995 (sizeof (q80_rq_rcv_cntxt_t) >> 2), 2996 ha->hw.mbox, (sizeof(q80_rsp_rcv_cntxt_t) >> 2), 0)) { 2997 device_printf(dev, "%s: failed0\n", __func__); 2998 return (-1); 2999 } 3000 3001 rcntxt_rsp = (q80_rsp_rcv_cntxt_t *)ha->hw.mbox; 3002 3003 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status); 3004 3005 if (err) { 3006 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3007 return (-1); 3008 } 3009 3010 for (i = 0; i < rcntxt_sds_rings; i++) { 3011 hw->sds[i].sds_consumer = rcntxt_rsp->sds_cons[i]; 3012 } 3013 3014 for (i = 0; i < rcntxt_rds_rings; i++) { 3015 hw->rds[i].prod_std = rcntxt_rsp->rds[i].prod_std; 3016 } 3017 3018 hw->rcv_cntxt_id = rcntxt_rsp->cntxt_id; 3019 3020 ha->hw.flags.init_rx_cnxt = 1; 3021 3022 if (hw->num_sds_rings > MAX_RCNTXT_SDS_RINGS) { 3023 3024 for (i = MAX_RCNTXT_SDS_RINGS; i < hw->num_sds_rings;) { 3025 3026 if ((i + MAX_RCNTXT_SDS_RINGS) < hw->num_sds_rings) 3027 max_idx = MAX_RCNTXT_SDS_RINGS; 3028 else 3029 max_idx = hw->num_sds_rings - i; 3030 3031 err = qla_add_rcv_rings(ha, i, max_idx); 3032 if (err) 3033 return -1; 3034 3035 i += max_idx; 3036 } 3037 } 3038 3039 if (hw->num_rds_rings > 1) { 3040 3041 for (i = 0; i < hw->num_rds_rings; ) { 3042 3043 if ((i + MAX_SDS_TO_RDS_MAP) < hw->num_rds_rings) 3044 max_idx = MAX_SDS_TO_RDS_MAP; 3045 else 3046 max_idx = hw->num_rds_rings - i; 3047 3048 err = qla_map_sds_to_rds(ha, i, max_idx); 3049 if (err) 3050 return -1; 3051 3052 i += max_idx; 3053 } 3054 } 3055 3056 return (0); 3057 } 3058 3059 static int 3060 qla_add_rcv_rings(qla_host_t *ha, uint32_t sds_idx, uint32_t nsds) 3061 { 3062 device_t dev = ha->pci_dev; 3063 q80_rq_add_rcv_rings_t *add_rcv; 3064 q80_rsp_add_rcv_rings_t *add_rcv_rsp; 3065 uint32_t i,j, err; 3066 qla_hw_t *hw = &ha->hw; 3067 3068 add_rcv = (q80_rq_add_rcv_rings_t *)ha->hw.mbox; 3069 bzero(add_rcv, sizeof (q80_rq_add_rcv_rings_t)); 3070 3071 add_rcv->opcode = Q8_MBX_ADD_RX_RINGS; 3072 add_rcv->count_version = (sizeof (q80_rq_add_rcv_rings_t) >> 2); 3073 add_rcv->count_version |= Q8_MBX_CMD_VERSION; 3074 3075 add_rcv->nrds_sets_rings = nsds | (1 << 5); 3076 add_rcv->nsds_rings = nsds; 3077 add_rcv->cntxt_id = hw->rcv_cntxt_id; 3078 3079 for (i = 0; i < nsds; i++) { 3080 3081 j = i + sds_idx; 3082 3083 add_rcv->sds[i].paddr = 3084 qla_host_to_le64(hw->dma_buf.sds_ring[j].dma_addr); 3085 3086 add_rcv->sds[i].size = 3087 qla_host_to_le32(NUM_STATUS_DESCRIPTORS); 3088 3089 add_rcv->sds[i].intr_id = qla_host_to_le16(hw->intr_id[j]); 3090 add_rcv->sds[i].intr_src_bit = qla_host_to_le16(0); 3091 3092 } 3093 3094 for (i = 0; (i < nsds); i++) { 3095 j = i + sds_idx; 3096 3097 add_rcv->rds[i].paddr_std = 3098 qla_host_to_le64(hw->dma_buf.rds_ring[j].dma_addr); 3099 3100 if (ha->hw.enable_9kb) 3101 add_rcv->rds[i].std_bsize = 3102 qla_host_to_le64(MJUM9BYTES); 3103 else 3104 add_rcv->rds[i].std_bsize = qla_host_to_le64(MCLBYTES); 3105 3106 add_rcv->rds[i].std_nentries = 3107 qla_host_to_le32(NUM_RX_DESCRIPTORS); 3108 } 3109 3110 3111 if (qla_mbx_cmd(ha, (uint32_t *)add_rcv, 3112 (sizeof (q80_rq_add_rcv_rings_t) >> 2), 3113 ha->hw.mbox, (sizeof(q80_rsp_add_rcv_rings_t) >> 2), 0)) { 3114 device_printf(dev, "%s: failed0\n", __func__); 3115 return (-1); 3116 } 3117 3118 add_rcv_rsp = (q80_rsp_add_rcv_rings_t *)ha->hw.mbox; 3119 3120 err = Q8_MBX_RSP_STATUS(add_rcv_rsp->regcnt_status); 3121 3122 if (err) { 3123 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3124 return (-1); 3125 } 3126 3127 for (i = 0; i < nsds; i++) { 3128 hw->sds[(i + sds_idx)].sds_consumer = add_rcv_rsp->sds_cons[i]; 3129 } 3130 3131 for (i = 0; i < nsds; i++) { 3132 hw->rds[(i + sds_idx)].prod_std = add_rcv_rsp->rds[i].prod_std; 3133 } 3134 3135 return (0); 3136 } 3137 3138 /* 3139 * Name: qla_del_rcv_cntxt 3140 * Function: Destroys the Receive Context. 3141 */ 3142 static void 3143 qla_del_rcv_cntxt(qla_host_t *ha) 3144 { 3145 device_t dev = ha->pci_dev; 3146 q80_rcv_cntxt_destroy_t *rcntxt; 3147 q80_rcv_cntxt_destroy_rsp_t *rcntxt_rsp; 3148 uint32_t err; 3149 uint8_t bcast_mac[6]; 3150 3151 if (!ha->hw.flags.init_rx_cnxt) 3152 return; 3153 3154 if (qla_hw_del_all_mcast(ha)) 3155 return; 3156 3157 if (ha->hw.flags.bcast_mac) { 3158 3159 bcast_mac[0] = 0xFF; bcast_mac[1] = 0xFF; bcast_mac[2] = 0xFF; 3160 bcast_mac[3] = 0xFF; bcast_mac[4] = 0xFF; bcast_mac[5] = 0xFF; 3161 3162 if (qla_config_mac_addr(ha, bcast_mac, 0, 1)) 3163 return; 3164 ha->hw.flags.bcast_mac = 0; 3165 3166 } 3167 3168 if (ha->hw.flags.unicast_mac) { 3169 if (qla_config_mac_addr(ha, ha->hw.mac_addr, 0, 1)) 3170 return; 3171 ha->hw.flags.unicast_mac = 0; 3172 } 3173 3174 rcntxt = (q80_rcv_cntxt_destroy_t *)ha->hw.mbox; 3175 bzero(rcntxt, (sizeof (q80_rcv_cntxt_destroy_t))); 3176 3177 rcntxt->opcode = Q8_MBX_DESTROY_RX_CNTXT; 3178 rcntxt->count_version = (sizeof (q80_rcv_cntxt_destroy_t) >> 2); 3179 rcntxt->count_version |= Q8_MBX_CMD_VERSION; 3180 3181 rcntxt->cntxt_id = ha->hw.rcv_cntxt_id; 3182 3183 if (qla_mbx_cmd(ha, (uint32_t *)rcntxt, 3184 (sizeof (q80_rcv_cntxt_destroy_t) >> 2), 3185 ha->hw.mbox, (sizeof(q80_rcv_cntxt_destroy_rsp_t) >> 2), 0)) { 3186 device_printf(dev, "%s: failed0\n", __func__); 3187 return; 3188 } 3189 rcntxt_rsp = (q80_rcv_cntxt_destroy_rsp_t *)ha->hw.mbox; 3190 3191 err = Q8_MBX_RSP_STATUS(rcntxt_rsp->regcnt_status); 3192 3193 if (err) { 3194 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3195 } 3196 3197 ha->hw.flags.init_rx_cnxt = 0; 3198 return; 3199 } 3200 3201 /* 3202 * Name: qla_init_xmt_cntxt 3203 * Function: Creates the Transmit Context. 3204 */ 3205 static int 3206 qla_init_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx) 3207 { 3208 device_t dev; 3209 qla_hw_t *hw = &ha->hw; 3210 q80_rq_tx_cntxt_t *tcntxt; 3211 q80_rsp_tx_cntxt_t *tcntxt_rsp; 3212 uint32_t err; 3213 qla_hw_tx_cntxt_t *hw_tx_cntxt; 3214 uint32_t intr_idx; 3215 3216 hw_tx_cntxt = &hw->tx_cntxt[txr_idx]; 3217 3218 dev = ha->pci_dev; 3219 3220 /* 3221 * Create Transmit Context 3222 */ 3223 tcntxt = (q80_rq_tx_cntxt_t *)ha->hw.mbox; 3224 bzero(tcntxt, (sizeof (q80_rq_tx_cntxt_t))); 3225 3226 tcntxt->opcode = Q8_MBX_CREATE_TX_CNTXT; 3227 tcntxt->count_version = (sizeof (q80_rq_tx_cntxt_t) >> 2); 3228 tcntxt->count_version |= Q8_MBX_CMD_VERSION; 3229 3230 intr_idx = txr_idx; 3231 3232 #ifdef QL_ENABLE_ISCSI_TLV 3233 3234 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO | 3235 Q8_TX_CNTXT_CAP0_TC; 3236 3237 if (txr_idx >= (ha->hw.num_tx_rings >> 1)) { 3238 tcntxt->traffic_class = 1; 3239 } 3240 3241 intr_idx = txr_idx % (ha->hw.num_tx_rings >> 1); 3242 3243 #else 3244 tcntxt->cap0 = Q8_TX_CNTXT_CAP0_BASEFW | Q8_TX_CNTXT_CAP0_LSO; 3245 3246 #endif /* #ifdef QL_ENABLE_ISCSI_TLV */ 3247 3248 tcntxt->ntx_rings = 1; 3249 3250 tcntxt->tx_ring[0].paddr = 3251 qla_host_to_le64(hw_tx_cntxt->tx_ring_paddr); 3252 tcntxt->tx_ring[0].tx_consumer = 3253 qla_host_to_le64(hw_tx_cntxt->tx_cons_paddr); 3254 tcntxt->tx_ring[0].nentries = qla_host_to_le16(NUM_TX_DESCRIPTORS); 3255 3256 tcntxt->tx_ring[0].intr_id = qla_host_to_le16(hw->intr_id[intr_idx]); 3257 tcntxt->tx_ring[0].intr_src_bit = qla_host_to_le16(0); 3258 3259 hw_tx_cntxt->txr_free = NUM_TX_DESCRIPTORS; 3260 hw_tx_cntxt->txr_next = hw_tx_cntxt->txr_comp = 0; 3261 *(hw_tx_cntxt->tx_cons) = 0; 3262 3263 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt, 3264 (sizeof (q80_rq_tx_cntxt_t) >> 2), 3265 ha->hw.mbox, 3266 (sizeof(q80_rsp_tx_cntxt_t) >> 2), 0)) { 3267 device_printf(dev, "%s: failed0\n", __func__); 3268 return (-1); 3269 } 3270 tcntxt_rsp = (q80_rsp_tx_cntxt_t *)ha->hw.mbox; 3271 3272 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status); 3273 3274 if (err) { 3275 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3276 return -1; 3277 } 3278 3279 hw_tx_cntxt->tx_prod_reg = tcntxt_rsp->tx_ring[0].prod_index; 3280 hw_tx_cntxt->tx_cntxt_id = tcntxt_rsp->tx_ring[0].cntxt_id; 3281 3282 if (qla_config_intr_coalesce(ha, hw_tx_cntxt->tx_cntxt_id, 0, 0)) 3283 return (-1); 3284 3285 return (0); 3286 } 3287 3288 3289 /* 3290 * Name: qla_del_xmt_cntxt 3291 * Function: Destroys the Transmit Context. 3292 */ 3293 static int 3294 qla_del_xmt_cntxt_i(qla_host_t *ha, uint32_t txr_idx) 3295 { 3296 device_t dev = ha->pci_dev; 3297 q80_tx_cntxt_destroy_t *tcntxt; 3298 q80_tx_cntxt_destroy_rsp_t *tcntxt_rsp; 3299 uint32_t err; 3300 3301 tcntxt = (q80_tx_cntxt_destroy_t *)ha->hw.mbox; 3302 bzero(tcntxt, (sizeof (q80_tx_cntxt_destroy_t))); 3303 3304 tcntxt->opcode = Q8_MBX_DESTROY_TX_CNTXT; 3305 tcntxt->count_version = (sizeof (q80_tx_cntxt_destroy_t) >> 2); 3306 tcntxt->count_version |= Q8_MBX_CMD_VERSION; 3307 3308 tcntxt->cntxt_id = ha->hw.tx_cntxt[txr_idx].tx_cntxt_id; 3309 3310 if (qla_mbx_cmd(ha, (uint32_t *)tcntxt, 3311 (sizeof (q80_tx_cntxt_destroy_t) >> 2), 3312 ha->hw.mbox, (sizeof (q80_tx_cntxt_destroy_rsp_t) >> 2), 0)) { 3313 device_printf(dev, "%s: failed0\n", __func__); 3314 return (-1); 3315 } 3316 tcntxt_rsp = (q80_tx_cntxt_destroy_rsp_t *)ha->hw.mbox; 3317 3318 err = Q8_MBX_RSP_STATUS(tcntxt_rsp->regcnt_status); 3319 3320 if (err) { 3321 device_printf(dev, "%s: failed1 [0x%08x]\n", __func__, err); 3322 return (-1); 3323 } 3324 3325 return (0); 3326 } 3327 static void 3328 qla_del_xmt_cntxt(qla_host_t *ha) 3329 { 3330 uint32_t i; 3331 3332 if (!ha->hw.flags.init_tx_cnxt) 3333 return; 3334 3335 for (i = 0; i < ha->hw.num_tx_rings; i++) { 3336 if (qla_del_xmt_cntxt_i(ha, i)) 3337 break; 3338 } 3339 ha->hw.flags.init_tx_cnxt = 0; 3340 } 3341 3342 static int 3343 qla_init_xmt_cntxt(qla_host_t *ha) 3344 { 3345 uint32_t i, j; 3346 3347 for (i = 0; i < ha->hw.num_tx_rings; i++) { 3348 if (qla_init_xmt_cntxt_i(ha, i) != 0) { 3349 for (j = 0; j < i; j++) 3350 qla_del_xmt_cntxt_i(ha, j); 3351 return (-1); 3352 } 3353 } 3354 ha->hw.flags.init_tx_cnxt = 1; 3355 return (0); 3356 } 3357 3358 static int 3359 qla_hw_all_mcast(qla_host_t *ha, uint32_t add_mcast) 3360 { 3361 int i, nmcast; 3362 uint32_t count = 0; 3363 uint8_t *mcast; 3364 3365 nmcast = ha->hw.nmcast; 3366 3367 QL_DPRINT2(ha, (ha->pci_dev, 3368 "%s:[0x%x] enter nmcast = %d \n", __func__, add_mcast, nmcast)); 3369 3370 mcast = ha->hw.mac_addr_arr; 3371 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3372 3373 for (i = 0 ; ((i < Q8_MAX_NUM_MULTICAST_ADDRS) && nmcast); i++) { 3374 if ((ha->hw.mcast[i].addr[0] != 0) || 3375 (ha->hw.mcast[i].addr[1] != 0) || 3376 (ha->hw.mcast[i].addr[2] != 0) || 3377 (ha->hw.mcast[i].addr[3] != 0) || 3378 (ha->hw.mcast[i].addr[4] != 0) || 3379 (ha->hw.mcast[i].addr[5] != 0)) { 3380 3381 bcopy(ha->hw.mcast[i].addr, mcast, ETHER_ADDR_LEN); 3382 mcast = mcast + ETHER_ADDR_LEN; 3383 count++; 3384 3385 if (count == Q8_MAX_MAC_ADDRS) { 3386 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, 3387 add_mcast, count)) { 3388 device_printf(ha->pci_dev, 3389 "%s: failed\n", __func__); 3390 return (-1); 3391 } 3392 3393 count = 0; 3394 mcast = ha->hw.mac_addr_arr; 3395 memset(mcast, 0, 3396 (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3397 } 3398 3399 nmcast--; 3400 } 3401 } 3402 3403 if (count) { 3404 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mcast, 3405 count)) { 3406 device_printf(ha->pci_dev, "%s: failed\n", __func__); 3407 return (-1); 3408 } 3409 } 3410 QL_DPRINT2(ha, (ha->pci_dev, 3411 "%s:[0x%x] exit nmcast = %d \n", __func__, add_mcast, nmcast)); 3412 3413 return 0; 3414 } 3415 3416 static int 3417 qla_hw_add_all_mcast(qla_host_t *ha) 3418 { 3419 int ret; 3420 3421 ret = qla_hw_all_mcast(ha, 1); 3422 3423 return (ret); 3424 } 3425 3426 int 3427 qla_hw_del_all_mcast(qla_host_t *ha) 3428 { 3429 int ret; 3430 3431 ret = qla_hw_all_mcast(ha, 0); 3432 3433 bzero(ha->hw.mcast, (sizeof (qla_mcast_t) * Q8_MAX_NUM_MULTICAST_ADDRS)); 3434 ha->hw.nmcast = 0; 3435 3436 return (ret); 3437 } 3438 3439 static int 3440 qla_hw_mac_addr_present(qla_host_t *ha, uint8_t *mta) 3441 { 3442 int i; 3443 3444 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { 3445 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) 3446 return (0); /* its been already added */ 3447 } 3448 return (-1); 3449 } 3450 3451 static int 3452 qla_hw_add_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast) 3453 { 3454 int i; 3455 3456 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { 3457 3458 if ((ha->hw.mcast[i].addr[0] == 0) && 3459 (ha->hw.mcast[i].addr[1] == 0) && 3460 (ha->hw.mcast[i].addr[2] == 0) && 3461 (ha->hw.mcast[i].addr[3] == 0) && 3462 (ha->hw.mcast[i].addr[4] == 0) && 3463 (ha->hw.mcast[i].addr[5] == 0)) { 3464 3465 bcopy(mta, ha->hw.mcast[i].addr, Q8_MAC_ADDR_LEN); 3466 ha->hw.nmcast++; 3467 3468 mta = mta + ETHER_ADDR_LEN; 3469 nmcast--; 3470 3471 if (nmcast == 0) 3472 break; 3473 } 3474 3475 } 3476 return 0; 3477 } 3478 3479 static int 3480 qla_hw_del_mcast(qla_host_t *ha, uint8_t *mta, uint32_t nmcast) 3481 { 3482 int i; 3483 3484 for (i = 0; i < Q8_MAX_NUM_MULTICAST_ADDRS; i++) { 3485 if (QL_MAC_CMP(ha->hw.mcast[i].addr, mta) == 0) { 3486 3487 ha->hw.mcast[i].addr[0] = 0; 3488 ha->hw.mcast[i].addr[1] = 0; 3489 ha->hw.mcast[i].addr[2] = 0; 3490 ha->hw.mcast[i].addr[3] = 0; 3491 ha->hw.mcast[i].addr[4] = 0; 3492 ha->hw.mcast[i].addr[5] = 0; 3493 3494 ha->hw.nmcast--; 3495 3496 mta = mta + ETHER_ADDR_LEN; 3497 nmcast--; 3498 3499 if (nmcast == 0) 3500 break; 3501 } 3502 } 3503 return 0; 3504 } 3505 3506 /* 3507 * Name: ql_hw_set_multi 3508 * Function: Sets the Multicast Addresses provided by the host O.S into the 3509 * hardware (for the given interface) 3510 */ 3511 int 3512 ql_hw_set_multi(qla_host_t *ha, uint8_t *mcast_addr, uint32_t mcnt, 3513 uint32_t add_mac) 3514 { 3515 uint8_t *mta = mcast_addr; 3516 int i; 3517 int ret = 0; 3518 uint32_t count = 0; 3519 uint8_t *mcast; 3520 3521 mcast = ha->hw.mac_addr_arr; 3522 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3523 3524 for (i = 0; i < mcnt; i++) { 3525 if (mta[0] || mta[1] || mta[2] || mta[3] || mta[4] || mta[5]) { 3526 if (add_mac) { 3527 if (qla_hw_mac_addr_present(ha, mta) != 0) { 3528 bcopy(mta, mcast, ETHER_ADDR_LEN); 3529 mcast = mcast + ETHER_ADDR_LEN; 3530 count++; 3531 } 3532 } else { 3533 if (qla_hw_mac_addr_present(ha, mta) == 0) { 3534 bcopy(mta, mcast, ETHER_ADDR_LEN); 3535 mcast = mcast + ETHER_ADDR_LEN; 3536 count++; 3537 } 3538 } 3539 } 3540 if (count == Q8_MAX_MAC_ADDRS) { 3541 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, 3542 add_mac, count)) { 3543 device_printf(ha->pci_dev, "%s: failed\n", 3544 __func__); 3545 return (-1); 3546 } 3547 3548 if (add_mac) { 3549 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, 3550 count); 3551 } else { 3552 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, 3553 count); 3554 } 3555 3556 count = 0; 3557 mcast = ha->hw.mac_addr_arr; 3558 memset(mcast, 0, (Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)); 3559 } 3560 3561 mta += Q8_MAC_ADDR_LEN; 3562 } 3563 3564 if (count) { 3565 if (qla_config_mac_addr(ha, ha->hw.mac_addr_arr, add_mac, 3566 count)) { 3567 device_printf(ha->pci_dev, "%s: failed\n", __func__); 3568 return (-1); 3569 } 3570 if (add_mac) { 3571 qla_hw_add_mcast(ha, ha->hw.mac_addr_arr, count); 3572 } else { 3573 qla_hw_del_mcast(ha, ha->hw.mac_addr_arr, count); 3574 } 3575 } 3576 3577 return (ret); 3578 } 3579 3580 /* 3581 * Name: ql_hw_tx_done_locked 3582 * Function: Handle Transmit Completions 3583 */ 3584 void 3585 ql_hw_tx_done_locked(qla_host_t *ha, uint32_t txr_idx) 3586 { 3587 qla_tx_buf_t *txb; 3588 qla_hw_t *hw = &ha->hw; 3589 uint32_t comp_idx, comp_count = 0; 3590 qla_hw_tx_cntxt_t *hw_tx_cntxt; 3591 3592 hw_tx_cntxt = &hw->tx_cntxt[txr_idx]; 3593 3594 /* retrieve index of last entry in tx ring completed */ 3595 comp_idx = qla_le32_to_host(*(hw_tx_cntxt->tx_cons)); 3596 3597 while (comp_idx != hw_tx_cntxt->txr_comp) { 3598 3599 txb = &ha->tx_ring[txr_idx].tx_buf[hw_tx_cntxt->txr_comp]; 3600 3601 hw_tx_cntxt->txr_comp++; 3602 if (hw_tx_cntxt->txr_comp == NUM_TX_DESCRIPTORS) 3603 hw_tx_cntxt->txr_comp = 0; 3604 3605 comp_count++; 3606 3607 if (txb->m_head) { 3608 if_inc_counter(ha->ifp, IFCOUNTER_OPACKETS, 1); 3609 3610 bus_dmamap_sync(ha->tx_tag, txb->map, 3611 BUS_DMASYNC_POSTWRITE); 3612 bus_dmamap_unload(ha->tx_tag, txb->map); 3613 m_freem(txb->m_head); 3614 3615 txb->m_head = NULL; 3616 } 3617 } 3618 3619 hw_tx_cntxt->txr_free += comp_count; 3620 return; 3621 } 3622 3623 void 3624 ql_update_link_state(qla_host_t *ha) 3625 { 3626 uint32_t link_state; 3627 uint32_t prev_link_state; 3628 3629 if (!(ha->ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3630 ha->hw.link_up = 0; 3631 return; 3632 } 3633 link_state = READ_REG32(ha, Q8_LINK_STATE); 3634 3635 prev_link_state = ha->hw.link_up; 3636 3637 if (ha->pci_func == 0) 3638 ha->hw.link_up = (((link_state & 0xF) == 1)? 1 : 0); 3639 else 3640 ha->hw.link_up = ((((link_state >> 4)& 0xF) == 1)? 1 : 0); 3641 3642 if (prev_link_state != ha->hw.link_up) { 3643 if (ha->hw.link_up) { 3644 if_link_state_change(ha->ifp, LINK_STATE_UP); 3645 } else { 3646 if_link_state_change(ha->ifp, LINK_STATE_DOWN); 3647 } 3648 } 3649 return; 3650 } 3651 3652 int 3653 ql_hw_check_health(qla_host_t *ha) 3654 { 3655 uint32_t val; 3656 3657 ha->hw.health_count++; 3658 3659 if (ha->hw.health_count < 500) 3660 return 0; 3661 3662 ha->hw.health_count = 0; 3663 3664 val = READ_REG32(ha, Q8_ASIC_TEMPERATURE); 3665 3666 if (((val & 0xFFFF) == 2) || ((val & 0xFFFF) == 3) || 3667 (QL_ERR_INJECT(ha, INJCT_TEMPERATURE_FAILURE))) { 3668 device_printf(ha->pci_dev, "%s: Temperature Alert [0x%08x]\n", 3669 __func__, val); 3670 return -1; 3671 } 3672 3673 val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT); 3674 3675 if ((val != ha->hw.hbeat_value) && 3676 (!(QL_ERR_INJECT(ha, INJCT_HEARTBEAT_FAILURE)))) { 3677 ha->hw.hbeat_value = val; 3678 ha->hw.hbeat_failure = 0; 3679 return 0; 3680 } 3681 3682 ha->hw.hbeat_failure++; 3683 3684 3685 if ((ha->dbg_level & 0x8000) && (ha->hw.hbeat_failure == 1)) 3686 device_printf(ha->pci_dev, "%s: Heartbeat Failue 1[0x%08x]\n", 3687 __func__, val); 3688 if (ha->hw.hbeat_failure < 2) /* we ignore the first failure */ 3689 return 0; 3690 else 3691 device_printf(ha->pci_dev, "%s: Heartbeat Failue [0x%08x]\n", 3692 __func__, val); 3693 3694 return -1; 3695 } 3696 3697 static int 3698 qla_init_nic_func(qla_host_t *ha) 3699 { 3700 device_t dev; 3701 q80_init_nic_func_t *init_nic; 3702 q80_init_nic_func_rsp_t *init_nic_rsp; 3703 uint32_t err; 3704 3705 dev = ha->pci_dev; 3706 3707 init_nic = (q80_init_nic_func_t *)ha->hw.mbox; 3708 bzero(init_nic, sizeof(q80_init_nic_func_t)); 3709 3710 init_nic->opcode = Q8_MBX_INIT_NIC_FUNC; 3711 init_nic->count_version = (sizeof (q80_init_nic_func_t) >> 2); 3712 init_nic->count_version |= Q8_MBX_CMD_VERSION; 3713 3714 init_nic->options = Q8_INIT_NIC_REG_DCBX_CHNG_AEN; 3715 init_nic->options |= Q8_INIT_NIC_REG_SFP_CHNG_AEN; 3716 init_nic->options |= Q8_INIT_NIC_REG_IDC_AEN; 3717 3718 //qla_dump_buf8(ha, __func__, init_nic, sizeof (q80_init_nic_func_t)); 3719 if (qla_mbx_cmd(ha, (uint32_t *)init_nic, 3720 (sizeof (q80_init_nic_func_t) >> 2), 3721 ha->hw.mbox, (sizeof (q80_init_nic_func_rsp_t) >> 2), 0)) { 3722 device_printf(dev, "%s: failed\n", __func__); 3723 return -1; 3724 } 3725 3726 init_nic_rsp = (q80_init_nic_func_rsp_t *)ha->hw.mbox; 3727 // qla_dump_buf8(ha, __func__, init_nic_rsp, sizeof (q80_init_nic_func_rsp_t)); 3728 3729 err = Q8_MBX_RSP_STATUS(init_nic_rsp->regcnt_status); 3730 3731 if (err) { 3732 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3733 } 3734 3735 return 0; 3736 } 3737 3738 static int 3739 qla_stop_nic_func(qla_host_t *ha) 3740 { 3741 device_t dev; 3742 q80_stop_nic_func_t *stop_nic; 3743 q80_stop_nic_func_rsp_t *stop_nic_rsp; 3744 uint32_t err; 3745 3746 dev = ha->pci_dev; 3747 3748 stop_nic = (q80_stop_nic_func_t *)ha->hw.mbox; 3749 bzero(stop_nic, sizeof(q80_stop_nic_func_t)); 3750 3751 stop_nic->opcode = Q8_MBX_STOP_NIC_FUNC; 3752 stop_nic->count_version = (sizeof (q80_stop_nic_func_t) >> 2); 3753 stop_nic->count_version |= Q8_MBX_CMD_VERSION; 3754 3755 stop_nic->options = Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN; 3756 stop_nic->options |= Q8_STOP_NIC_DEREG_SFP_CHNG_AEN; 3757 3758 //qla_dump_buf8(ha, __func__, stop_nic, sizeof (q80_stop_nic_func_t)); 3759 if (qla_mbx_cmd(ha, (uint32_t *)stop_nic, 3760 (sizeof (q80_stop_nic_func_t) >> 2), 3761 ha->hw.mbox, (sizeof (q80_stop_nic_func_rsp_t) >> 2), 0)) { 3762 device_printf(dev, "%s: failed\n", __func__); 3763 return -1; 3764 } 3765 3766 stop_nic_rsp = (q80_stop_nic_func_rsp_t *)ha->hw.mbox; 3767 //qla_dump_buf8(ha, __func__, stop_nic_rsp, sizeof (q80_stop_nic_func_rsp_ t)); 3768 3769 err = Q8_MBX_RSP_STATUS(stop_nic_rsp->regcnt_status); 3770 3771 if (err) { 3772 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3773 } 3774 3775 return 0; 3776 } 3777 3778 static int 3779 qla_query_fw_dcbx_caps(qla_host_t *ha) 3780 { 3781 device_t dev; 3782 q80_query_fw_dcbx_caps_t *fw_dcbx; 3783 q80_query_fw_dcbx_caps_rsp_t *fw_dcbx_rsp; 3784 uint32_t err; 3785 3786 dev = ha->pci_dev; 3787 3788 fw_dcbx = (q80_query_fw_dcbx_caps_t *)ha->hw.mbox; 3789 bzero(fw_dcbx, sizeof(q80_query_fw_dcbx_caps_t)); 3790 3791 fw_dcbx->opcode = Q8_MBX_GET_FW_DCBX_CAPS; 3792 fw_dcbx->count_version = (sizeof (q80_query_fw_dcbx_caps_t) >> 2); 3793 fw_dcbx->count_version |= Q8_MBX_CMD_VERSION; 3794 3795 ql_dump_buf8(ha, __func__, fw_dcbx, sizeof (q80_query_fw_dcbx_caps_t)); 3796 if (qla_mbx_cmd(ha, (uint32_t *)fw_dcbx, 3797 (sizeof (q80_query_fw_dcbx_caps_t) >> 2), 3798 ha->hw.mbox, (sizeof (q80_query_fw_dcbx_caps_rsp_t) >> 2), 0)) { 3799 device_printf(dev, "%s: failed\n", __func__); 3800 return -1; 3801 } 3802 3803 fw_dcbx_rsp = (q80_query_fw_dcbx_caps_rsp_t *)ha->hw.mbox; 3804 ql_dump_buf8(ha, __func__, fw_dcbx_rsp, 3805 sizeof (q80_query_fw_dcbx_caps_rsp_t)); 3806 3807 err = Q8_MBX_RSP_STATUS(fw_dcbx_rsp->regcnt_status); 3808 3809 if (err) { 3810 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3811 } 3812 3813 return 0; 3814 } 3815 3816 static int 3817 qla_idc_ack(qla_host_t *ha, uint32_t aen_mb1, uint32_t aen_mb2, 3818 uint32_t aen_mb3, uint32_t aen_mb4) 3819 { 3820 device_t dev; 3821 q80_idc_ack_t *idc_ack; 3822 q80_idc_ack_rsp_t *idc_ack_rsp; 3823 uint32_t err; 3824 int count = 300; 3825 3826 dev = ha->pci_dev; 3827 3828 idc_ack = (q80_idc_ack_t *)ha->hw.mbox; 3829 bzero(idc_ack, sizeof(q80_idc_ack_t)); 3830 3831 idc_ack->opcode = Q8_MBX_IDC_ACK; 3832 idc_ack->count_version = (sizeof (q80_idc_ack_t) >> 2); 3833 idc_ack->count_version |= Q8_MBX_CMD_VERSION; 3834 3835 idc_ack->aen_mb1 = aen_mb1; 3836 idc_ack->aen_mb2 = aen_mb2; 3837 idc_ack->aen_mb3 = aen_mb3; 3838 idc_ack->aen_mb4 = aen_mb4; 3839 3840 ha->hw.imd_compl= 0; 3841 3842 if (qla_mbx_cmd(ha, (uint32_t *)idc_ack, 3843 (sizeof (q80_idc_ack_t) >> 2), 3844 ha->hw.mbox, (sizeof (q80_idc_ack_rsp_t) >> 2), 0)) { 3845 device_printf(dev, "%s: failed\n", __func__); 3846 return -1; 3847 } 3848 3849 idc_ack_rsp = (q80_idc_ack_rsp_t *)ha->hw.mbox; 3850 3851 err = Q8_MBX_RSP_STATUS(idc_ack_rsp->regcnt_status); 3852 3853 if (err) { 3854 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3855 return(-1); 3856 } 3857 3858 while (count && !ha->hw.imd_compl) { 3859 qla_mdelay(__func__, 100); 3860 count--; 3861 } 3862 3863 if (!count) 3864 return -1; 3865 else 3866 device_printf(dev, "%s: count %d\n", __func__, count); 3867 3868 return (0); 3869 } 3870 3871 static int 3872 qla_set_port_config(qla_host_t *ha, uint32_t cfg_bits) 3873 { 3874 device_t dev; 3875 q80_set_port_cfg_t *pcfg; 3876 q80_set_port_cfg_rsp_t *pfg_rsp; 3877 uint32_t err; 3878 int count = 300; 3879 3880 dev = ha->pci_dev; 3881 3882 pcfg = (q80_set_port_cfg_t *)ha->hw.mbox; 3883 bzero(pcfg, sizeof(q80_set_port_cfg_t)); 3884 3885 pcfg->opcode = Q8_MBX_SET_PORT_CONFIG; 3886 pcfg->count_version = (sizeof (q80_set_port_cfg_t) >> 2); 3887 pcfg->count_version |= Q8_MBX_CMD_VERSION; 3888 3889 pcfg->cfg_bits = cfg_bits; 3890 3891 device_printf(dev, "%s: cfg_bits" 3892 " [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]" 3893 " [0x%x, 0x%x, 0x%x]\n", __func__, 3894 ((cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20), 3895 ((cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5), 3896 ((cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0)); 3897 3898 ha->hw.imd_compl= 0; 3899 3900 if (qla_mbx_cmd(ha, (uint32_t *)pcfg, 3901 (sizeof (q80_set_port_cfg_t) >> 2), 3902 ha->hw.mbox, (sizeof (q80_set_port_cfg_rsp_t) >> 2), 0)) { 3903 device_printf(dev, "%s: failed\n", __func__); 3904 return -1; 3905 } 3906 3907 pfg_rsp = (q80_set_port_cfg_rsp_t *)ha->hw.mbox; 3908 3909 err = Q8_MBX_RSP_STATUS(pfg_rsp->regcnt_status); 3910 3911 if (err == Q8_MBX_RSP_IDC_INTRMD_RSP) { 3912 while (count && !ha->hw.imd_compl) { 3913 qla_mdelay(__func__, 100); 3914 count--; 3915 } 3916 if (count) { 3917 device_printf(dev, "%s: count %d\n", __func__, count); 3918 3919 err = 0; 3920 } 3921 } 3922 3923 if (err) { 3924 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3925 return(-1); 3926 } 3927 3928 return (0); 3929 } 3930 3931 3932 static int 3933 qla_get_minidump_tmplt_size(qla_host_t *ha, uint32_t *size) 3934 { 3935 uint32_t err; 3936 device_t dev = ha->pci_dev; 3937 q80_config_md_templ_size_t *md_size; 3938 q80_config_md_templ_size_rsp_t *md_size_rsp; 3939 3940 #ifndef QL_LDFLASH_FW 3941 3942 ql_minidump_template_hdr_t *hdr; 3943 3944 hdr = (ql_minidump_template_hdr_t *)ql83xx_minidump; 3945 *size = hdr->size_of_template; 3946 return (0); 3947 3948 #endif /* #ifdef QL_LDFLASH_FW */ 3949 3950 md_size = (q80_config_md_templ_size_t *) ha->hw.mbox; 3951 bzero(md_size, sizeof(q80_config_md_templ_size_t)); 3952 3953 md_size->opcode = Q8_MBX_GET_MINIDUMP_TMPLT_SIZE; 3954 md_size->count_version = (sizeof (q80_config_md_templ_size_t) >> 2); 3955 md_size->count_version |= Q8_MBX_CMD_VERSION; 3956 3957 if (qla_mbx_cmd(ha, (uint32_t *) md_size, 3958 (sizeof(q80_config_md_templ_size_t) >> 2), ha->hw.mbox, 3959 (sizeof(q80_config_md_templ_size_rsp_t) >> 2), 0)) { 3960 3961 device_printf(dev, "%s: failed\n", __func__); 3962 3963 return (-1); 3964 } 3965 3966 md_size_rsp = (q80_config_md_templ_size_rsp_t *) ha->hw.mbox; 3967 3968 err = Q8_MBX_RSP_STATUS(md_size_rsp->regcnt_status); 3969 3970 if (err) { 3971 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 3972 return(-1); 3973 } 3974 3975 *size = md_size_rsp->templ_size; 3976 3977 return (0); 3978 } 3979 3980 static int 3981 qla_get_port_config(qla_host_t *ha, uint32_t *cfg_bits) 3982 { 3983 device_t dev; 3984 q80_get_port_cfg_t *pcfg; 3985 q80_get_port_cfg_rsp_t *pcfg_rsp; 3986 uint32_t err; 3987 3988 dev = ha->pci_dev; 3989 3990 pcfg = (q80_get_port_cfg_t *)ha->hw.mbox; 3991 bzero(pcfg, sizeof(q80_get_port_cfg_t)); 3992 3993 pcfg->opcode = Q8_MBX_GET_PORT_CONFIG; 3994 pcfg->count_version = (sizeof (q80_get_port_cfg_t) >> 2); 3995 pcfg->count_version |= Q8_MBX_CMD_VERSION; 3996 3997 if (qla_mbx_cmd(ha, (uint32_t *)pcfg, 3998 (sizeof (q80_get_port_cfg_t) >> 2), 3999 ha->hw.mbox, (sizeof (q80_get_port_cfg_rsp_t) >> 2), 0)) { 4000 device_printf(dev, "%s: failed\n", __func__); 4001 return -1; 4002 } 4003 4004 pcfg_rsp = (q80_get_port_cfg_rsp_t *)ha->hw.mbox; 4005 4006 err = Q8_MBX_RSP_STATUS(pcfg_rsp->regcnt_status); 4007 4008 if (err) { 4009 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 4010 return(-1); 4011 } 4012 4013 device_printf(dev, "%s: [cfg_bits, port type]" 4014 " [0x%08x, 0x%02x] [STD_PAUSE_DIR, PAUSE_TYPE, DCBX]" 4015 " [0x%x, 0x%x, 0x%x]\n", __func__, 4016 pcfg_rsp->cfg_bits, pcfg_rsp->phys_port_type, 4017 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK)>>20), 4018 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_PAUSE_CFG_MASK) >> 5), 4019 ((pcfg_rsp->cfg_bits & Q8_PORT_CFG_BITS_DCBX_ENABLE) ? 1: 0) 4020 ); 4021 4022 *cfg_bits = pcfg_rsp->cfg_bits; 4023 4024 return (0); 4025 } 4026 4027 int 4028 ql_iscsi_pdu(qla_host_t *ha, struct mbuf *mp) 4029 { 4030 struct ether_vlan_header *eh; 4031 uint16_t etype; 4032 struct ip *ip = NULL; 4033 struct ip6_hdr *ip6 = NULL; 4034 struct tcphdr *th = NULL; 4035 uint32_t hdrlen; 4036 uint32_t offset; 4037 uint8_t buf[sizeof(struct ip6_hdr)]; 4038 4039 eh = mtod(mp, struct ether_vlan_header *); 4040 4041 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 4042 hdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 4043 etype = ntohs(eh->evl_proto); 4044 } else { 4045 hdrlen = ETHER_HDR_LEN; 4046 etype = ntohs(eh->evl_encap_proto); 4047 } 4048 4049 if (etype == ETHERTYPE_IP) { 4050 4051 offset = (hdrlen + sizeof (struct ip)); 4052 4053 if (mp->m_len >= offset) { 4054 ip = (struct ip *)(mp->m_data + hdrlen); 4055 } else { 4056 m_copydata(mp, hdrlen, sizeof (struct ip), buf); 4057 ip = (struct ip *)buf; 4058 } 4059 4060 if (ip->ip_p == IPPROTO_TCP) { 4061 4062 hdrlen += ip->ip_hl << 2; 4063 offset = hdrlen + 4; 4064 4065 if (mp->m_len >= offset) { 4066 th = (struct tcphdr *)(mp->m_data + hdrlen);; 4067 } else { 4068 m_copydata(mp, hdrlen, 4, buf); 4069 th = (struct tcphdr *)buf; 4070 } 4071 } 4072 4073 } else if (etype == ETHERTYPE_IPV6) { 4074 4075 offset = (hdrlen + sizeof (struct ip6_hdr)); 4076 4077 if (mp->m_len >= offset) { 4078 ip6 = (struct ip6_hdr *)(mp->m_data + hdrlen); 4079 } else { 4080 m_copydata(mp, hdrlen, sizeof (struct ip6_hdr), buf); 4081 ip6 = (struct ip6_hdr *)buf; 4082 } 4083 4084 if (ip6->ip6_nxt == IPPROTO_TCP) { 4085 4086 hdrlen += sizeof(struct ip6_hdr); 4087 offset = hdrlen + 4; 4088 4089 if (mp->m_len >= offset) { 4090 th = (struct tcphdr *)(mp->m_data + hdrlen);; 4091 } else { 4092 m_copydata(mp, hdrlen, 4, buf); 4093 th = (struct tcphdr *)buf; 4094 } 4095 } 4096 } 4097 4098 if (th != NULL) { 4099 if ((th->th_sport == htons(3260)) || 4100 (th->th_dport == htons(3260))) 4101 return 0; 4102 } 4103 return (-1); 4104 } 4105 4106 void 4107 qla_hw_async_event(qla_host_t *ha) 4108 { 4109 switch (ha->hw.aen_mb0) { 4110 case 0x8101: 4111 (void)qla_idc_ack(ha, ha->hw.aen_mb1, ha->hw.aen_mb2, 4112 ha->hw.aen_mb3, ha->hw.aen_mb4); 4113 4114 break; 4115 4116 default: 4117 break; 4118 } 4119 4120 return; 4121 } 4122 4123 #ifdef QL_LDFLASH_FW 4124 static int 4125 ql_get_minidump_template(qla_host_t *ha) 4126 { 4127 uint32_t err; 4128 device_t dev = ha->pci_dev; 4129 q80_config_md_templ_cmd_t *md_templ; 4130 q80_config_md_templ_cmd_rsp_t *md_templ_rsp; 4131 4132 md_templ = (q80_config_md_templ_cmd_t *) ha->hw.mbox; 4133 bzero(md_templ, (sizeof (q80_config_md_templ_cmd_t))); 4134 4135 md_templ->opcode = Q8_MBX_GET_MINIDUMP_TMPLT; 4136 md_templ->count_version = ( sizeof(q80_config_md_templ_cmd_t) >> 2); 4137 md_templ->count_version |= Q8_MBX_CMD_VERSION; 4138 4139 md_templ->buf_addr = ha->hw.dma_buf.minidump.dma_addr; 4140 md_templ->buff_size = ha->hw.dma_buf.minidump.size; 4141 4142 if (qla_mbx_cmd(ha, (uint32_t *) md_templ, 4143 (sizeof(q80_config_md_templ_cmd_t) >> 2), 4144 ha->hw.mbox, 4145 (sizeof(q80_config_md_templ_cmd_rsp_t) >> 2), 0)) { 4146 4147 device_printf(dev, "%s: failed\n", __func__); 4148 4149 return (-1); 4150 } 4151 4152 md_templ_rsp = (q80_config_md_templ_cmd_rsp_t *) ha->hw.mbox; 4153 4154 err = Q8_MBX_RSP_STATUS(md_templ_rsp->regcnt_status); 4155 4156 if (err) { 4157 device_printf(dev, "%s: failed [0x%08x]\n", __func__, err); 4158 return (-1); 4159 } 4160 4161 return (0); 4162 4163 } 4164 #endif /* #ifdef QL_LDFLASH_FW */ 4165 4166 /* 4167 * Minidump related functionality 4168 */ 4169 4170 static int ql_parse_template(qla_host_t *ha); 4171 4172 static uint32_t ql_rdcrb(qla_host_t *ha, 4173 ql_minidump_entry_rdcrb_t *crb_entry, 4174 uint32_t * data_buff); 4175 4176 static uint32_t ql_pollrd(qla_host_t *ha, 4177 ql_minidump_entry_pollrd_t *entry, 4178 uint32_t * data_buff); 4179 4180 static uint32_t ql_pollrd_modify_write(qla_host_t *ha, 4181 ql_minidump_entry_rd_modify_wr_with_poll_t *entry, 4182 uint32_t *data_buff); 4183 4184 static uint32_t ql_L2Cache(qla_host_t *ha, 4185 ql_minidump_entry_cache_t *cacheEntry, 4186 uint32_t * data_buff); 4187 4188 static uint32_t ql_L1Cache(qla_host_t *ha, 4189 ql_minidump_entry_cache_t *cacheEntry, 4190 uint32_t *data_buff); 4191 4192 static uint32_t ql_rdocm(qla_host_t *ha, 4193 ql_minidump_entry_rdocm_t *ocmEntry, 4194 uint32_t *data_buff); 4195 4196 static uint32_t ql_rdmem(qla_host_t *ha, 4197 ql_minidump_entry_rdmem_t *mem_entry, 4198 uint32_t *data_buff); 4199 4200 static uint32_t ql_rdrom(qla_host_t *ha, 4201 ql_minidump_entry_rdrom_t *romEntry, 4202 uint32_t *data_buff); 4203 4204 static uint32_t ql_rdmux(qla_host_t *ha, 4205 ql_minidump_entry_mux_t *muxEntry, 4206 uint32_t *data_buff); 4207 4208 static uint32_t ql_rdmux2(qla_host_t *ha, 4209 ql_minidump_entry_mux2_t *muxEntry, 4210 uint32_t *data_buff); 4211 4212 static uint32_t ql_rdqueue(qla_host_t *ha, 4213 ql_minidump_entry_queue_t *queueEntry, 4214 uint32_t *data_buff); 4215 4216 static uint32_t ql_cntrl(qla_host_t *ha, 4217 ql_minidump_template_hdr_t *template_hdr, 4218 ql_minidump_entry_cntrl_t *crbEntry); 4219 4220 4221 static uint32_t 4222 ql_minidump_size(qla_host_t *ha) 4223 { 4224 uint32_t i, k; 4225 uint32_t size = 0; 4226 ql_minidump_template_hdr_t *hdr; 4227 4228 hdr = (ql_minidump_template_hdr_t *)ha->hw.dma_buf.minidump.dma_b; 4229 4230 i = 0x2; 4231 4232 for (k = 1; k < QL_DBG_CAP_SIZE_ARRAY_LEN; k++) { 4233 if (i & ha->hw.mdump_capture_mask) 4234 size += hdr->capture_size_array[k]; 4235 i = i << 1; 4236 } 4237 return (size); 4238 } 4239 4240 static void 4241 ql_free_minidump_buffer(qla_host_t *ha) 4242 { 4243 if (ha->hw.mdump_buffer != NULL) { 4244 free(ha->hw.mdump_buffer, M_QLA83XXBUF); 4245 ha->hw.mdump_buffer = NULL; 4246 ha->hw.mdump_buffer_size = 0; 4247 } 4248 return; 4249 } 4250 4251 static int 4252 ql_alloc_minidump_buffer(qla_host_t *ha) 4253 { 4254 ha->hw.mdump_buffer_size = ql_minidump_size(ha); 4255 4256 if (!ha->hw.mdump_buffer_size) 4257 return (-1); 4258 4259 ha->hw.mdump_buffer = malloc(ha->hw.mdump_buffer_size, M_QLA83XXBUF, 4260 M_NOWAIT); 4261 4262 if (ha->hw.mdump_buffer == NULL) 4263 return (-1); 4264 4265 return (0); 4266 } 4267 4268 static void 4269 ql_free_minidump_template_buffer(qla_host_t *ha) 4270 { 4271 if (ha->hw.mdump_template != NULL) { 4272 free(ha->hw.mdump_template, M_QLA83XXBUF); 4273 ha->hw.mdump_template = NULL; 4274 ha->hw.mdump_template_size = 0; 4275 } 4276 return; 4277 } 4278 4279 static int 4280 ql_alloc_minidump_template_buffer(qla_host_t *ha) 4281 { 4282 ha->hw.mdump_template_size = ha->hw.dma_buf.minidump.size; 4283 4284 ha->hw.mdump_template = malloc(ha->hw.mdump_template_size, 4285 M_QLA83XXBUF, M_NOWAIT); 4286 4287 if (ha->hw.mdump_template == NULL) 4288 return (-1); 4289 4290 return (0); 4291 } 4292 4293 static int 4294 ql_alloc_minidump_buffers(qla_host_t *ha) 4295 { 4296 int ret; 4297 4298 ret = ql_alloc_minidump_template_buffer(ha); 4299 4300 if (ret) 4301 return (ret); 4302 4303 ret = ql_alloc_minidump_buffer(ha); 4304 4305 if (ret) 4306 ql_free_minidump_template_buffer(ha); 4307 4308 return (ret); 4309 } 4310 4311 4312 static uint32_t 4313 ql_validate_minidump_checksum(qla_host_t *ha) 4314 { 4315 uint64_t sum = 0; 4316 int count; 4317 uint32_t *template_buff; 4318 4319 count = ha->hw.dma_buf.minidump.size / sizeof (uint32_t); 4320 template_buff = ha->hw.dma_buf.minidump.dma_b; 4321 4322 while (count-- > 0) { 4323 sum += *template_buff++; 4324 } 4325 4326 while (sum >> 32) { 4327 sum = (sum & 0xFFFFFFFF) + (sum >> 32); 4328 } 4329 4330 return (~sum); 4331 } 4332 4333 int 4334 ql_minidump_init(qla_host_t *ha) 4335 { 4336 int ret = 0; 4337 uint32_t template_size = 0; 4338 device_t dev = ha->pci_dev; 4339 4340 /* 4341 * Get Minidump Template Size 4342 */ 4343 ret = qla_get_minidump_tmplt_size(ha, &template_size); 4344 4345 if (ret || (template_size == 0)) { 4346 device_printf(dev, "%s: failed [%d, %d]\n", __func__, ret, 4347 template_size); 4348 return (-1); 4349 } 4350 4351 /* 4352 * Allocate Memory for Minidump Template 4353 */ 4354 4355 ha->hw.dma_buf.minidump.alignment = 8; 4356 ha->hw.dma_buf.minidump.size = template_size; 4357 4358 #ifdef QL_LDFLASH_FW 4359 if (ql_alloc_dmabuf(ha, &ha->hw.dma_buf.minidump)) { 4360 4361 device_printf(dev, "%s: minidump dma alloc failed\n", __func__); 4362 4363 return (-1); 4364 } 4365 ha->hw.dma_buf.flags.minidump = 1; 4366 4367 /* 4368 * Retrieve Minidump Template 4369 */ 4370 ret = ql_get_minidump_template(ha); 4371 #else 4372 ha->hw.dma_buf.minidump.dma_b = ql83xx_minidump; 4373 4374 #endif /* #ifdef QL_LDFLASH_FW */ 4375 4376 if (ret == 0) { 4377 4378 ret = ql_validate_minidump_checksum(ha); 4379 4380 if (ret == 0) { 4381 4382 ret = ql_alloc_minidump_buffers(ha); 4383 4384 if (ret == 0) 4385 ha->hw.mdump_init = 1; 4386 else 4387 device_printf(dev, 4388 "%s: ql_alloc_minidump_buffers" 4389 " failed\n", __func__); 4390 } else { 4391 device_printf(dev, "%s: ql_validate_minidump_checksum" 4392 " failed\n", __func__); 4393 } 4394 } else { 4395 device_printf(dev, "%s: ql_get_minidump_template failed\n", 4396 __func__); 4397 } 4398 4399 if (ret) 4400 ql_minidump_free(ha); 4401 4402 return (ret); 4403 } 4404 4405 static void 4406 ql_minidump_free(qla_host_t *ha) 4407 { 4408 ha->hw.mdump_init = 0; 4409 if (ha->hw.dma_buf.flags.minidump) { 4410 ha->hw.dma_buf.flags.minidump = 0; 4411 ql_free_dmabuf(ha, &ha->hw.dma_buf.minidump); 4412 } 4413 4414 ql_free_minidump_template_buffer(ha); 4415 ql_free_minidump_buffer(ha); 4416 4417 return; 4418 } 4419 4420 void 4421 ql_minidump(qla_host_t *ha) 4422 { 4423 if (!ha->hw.mdump_init) 4424 return; 4425 4426 if (ha->hw.mdump_done) 4427 return; 4428 4429 ha->hw.mdump_start_seq_index = ql_stop_sequence(ha); 4430 4431 bzero(ha->hw.mdump_buffer, ha->hw.mdump_buffer_size); 4432 bzero(ha->hw.mdump_template, ha->hw.mdump_template_size); 4433 4434 bcopy(ha->hw.dma_buf.minidump.dma_b, ha->hw.mdump_template, 4435 ha->hw.mdump_template_size); 4436 4437 ql_parse_template(ha); 4438 4439 ql_start_sequence(ha, ha->hw.mdump_start_seq_index); 4440 4441 ha->hw.mdump_done = 1; 4442 4443 return; 4444 } 4445 4446 4447 /* 4448 * helper routines 4449 */ 4450 static void 4451 ql_entry_err_chk(ql_minidump_entry_t *entry, uint32_t esize) 4452 { 4453 if (esize != entry->hdr.entry_capture_size) { 4454 entry->hdr.entry_capture_size = esize; 4455 entry->hdr.driver_flags |= QL_DBG_SIZE_ERR_FLAG; 4456 } 4457 return; 4458 } 4459 4460 4461 static int 4462 ql_parse_template(qla_host_t *ha) 4463 { 4464 uint32_t num_of_entries, buff_level, e_cnt, esize; 4465 uint32_t end_cnt, rv = 0; 4466 char *dump_buff, *dbuff; 4467 int sane_start = 0, sane_end = 0; 4468 ql_minidump_template_hdr_t *template_hdr; 4469 ql_minidump_entry_t *entry; 4470 uint32_t capture_mask; 4471 uint32_t dump_size; 4472 4473 /* Setup parameters */ 4474 template_hdr = (ql_minidump_template_hdr_t *)ha->hw.mdump_template; 4475 4476 if (template_hdr->entry_type == TLHDR) 4477 sane_start = 1; 4478 4479 dump_buff = (char *) ha->hw.mdump_buffer; 4480 4481 num_of_entries = template_hdr->num_of_entries; 4482 4483 entry = (ql_minidump_entry_t *) ((char *)template_hdr 4484 + template_hdr->first_entry_offset ); 4485 4486 template_hdr->saved_state_array[QL_OCM0_ADDR_INDX] = 4487 template_hdr->ocm_window_array[ha->pci_func]; 4488 template_hdr->saved_state_array[QL_PCIE_FUNC_INDX] = ha->pci_func; 4489 4490 capture_mask = ha->hw.mdump_capture_mask; 4491 dump_size = ha->hw.mdump_buffer_size; 4492 4493 template_hdr->driver_capture_mask = capture_mask; 4494 4495 QL_DPRINT80(ha, (ha->pci_dev, 4496 "%s: sane_start = %d num_of_entries = %d " 4497 "capture_mask = 0x%x dump_size = %d \n", 4498 __func__, sane_start, num_of_entries, capture_mask, dump_size)); 4499 4500 for (buff_level = 0, e_cnt = 0; e_cnt < num_of_entries; e_cnt++) { 4501 4502 /* 4503 * If the capture_mask of the entry does not match capture mask 4504 * skip the entry after marking the driver_flags indicator. 4505 */ 4506 4507 if (!(entry->hdr.entry_capture_mask & capture_mask)) { 4508 4509 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4510 entry = (ql_minidump_entry_t *) ((char *) entry 4511 + entry->hdr.entry_size); 4512 continue; 4513 } 4514 4515 /* 4516 * This is ONLY needed in implementations where 4517 * the capture buffer allocated is too small to capture 4518 * all of the required entries for a given capture mask. 4519 * We need to empty the buffer contents to a file 4520 * if possible, before processing the next entry 4521 * If the buff_full_flag is set, no further capture will happen 4522 * and all remaining non-control entries will be skipped. 4523 */ 4524 if (entry->hdr.entry_capture_size != 0) { 4525 if ((buff_level + entry->hdr.entry_capture_size) > 4526 dump_size) { 4527 /* Try to recover by emptying buffer to file */ 4528 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4529 entry = (ql_minidump_entry_t *) ((char *) entry 4530 + entry->hdr.entry_size); 4531 continue; 4532 } 4533 } 4534 4535 /* 4536 * Decode the entry type and process it accordingly 4537 */ 4538 4539 switch (entry->hdr.entry_type) { 4540 case RDNOP: 4541 break; 4542 4543 case RDEND: 4544 if (sane_end == 0) { 4545 end_cnt = e_cnt; 4546 } 4547 sane_end++; 4548 break; 4549 4550 case RDCRB: 4551 dbuff = dump_buff + buff_level; 4552 esize = ql_rdcrb(ha, (void *)entry, (void *)dbuff); 4553 ql_entry_err_chk(entry, esize); 4554 buff_level += esize; 4555 break; 4556 4557 case POLLRD: 4558 dbuff = dump_buff + buff_level; 4559 esize = ql_pollrd(ha, (void *)entry, (void *)dbuff); 4560 ql_entry_err_chk(entry, esize); 4561 buff_level += esize; 4562 break; 4563 4564 case POLLRDMWR: 4565 dbuff = dump_buff + buff_level; 4566 esize = ql_pollrd_modify_write(ha, (void *)entry, 4567 (void *)dbuff); 4568 ql_entry_err_chk(entry, esize); 4569 buff_level += esize; 4570 break; 4571 4572 case L2ITG: 4573 case L2DTG: 4574 case L2DAT: 4575 case L2INS: 4576 dbuff = dump_buff + buff_level; 4577 esize = ql_L2Cache(ha, (void *)entry, (void *)dbuff); 4578 if (esize == -1) { 4579 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4580 } else { 4581 ql_entry_err_chk(entry, esize); 4582 buff_level += esize; 4583 } 4584 break; 4585 4586 case L1DAT: 4587 case L1INS: 4588 dbuff = dump_buff + buff_level; 4589 esize = ql_L1Cache(ha, (void *)entry, (void *)dbuff); 4590 ql_entry_err_chk(entry, esize); 4591 buff_level += esize; 4592 break; 4593 4594 case RDOCM: 4595 dbuff = dump_buff + buff_level; 4596 esize = ql_rdocm(ha, (void *)entry, (void *)dbuff); 4597 ql_entry_err_chk(entry, esize); 4598 buff_level += esize; 4599 break; 4600 4601 case RDMEM: 4602 dbuff = dump_buff + buff_level; 4603 esize = ql_rdmem(ha, (void *)entry, (void *)dbuff); 4604 ql_entry_err_chk(entry, esize); 4605 buff_level += esize; 4606 break; 4607 4608 case BOARD: 4609 case RDROM: 4610 dbuff = dump_buff + buff_level; 4611 esize = ql_rdrom(ha, (void *)entry, (void *)dbuff); 4612 ql_entry_err_chk(entry, esize); 4613 buff_level += esize; 4614 break; 4615 4616 case RDMUX: 4617 dbuff = dump_buff + buff_level; 4618 esize = ql_rdmux(ha, (void *)entry, (void *)dbuff); 4619 ql_entry_err_chk(entry, esize); 4620 buff_level += esize; 4621 break; 4622 4623 case RDMUX2: 4624 dbuff = dump_buff + buff_level; 4625 esize = ql_rdmux2(ha, (void *)entry, (void *)dbuff); 4626 ql_entry_err_chk(entry, esize); 4627 buff_level += esize; 4628 break; 4629 4630 case QUEUE: 4631 dbuff = dump_buff + buff_level; 4632 esize = ql_rdqueue(ha, (void *)entry, (void *)dbuff); 4633 ql_entry_err_chk(entry, esize); 4634 buff_level += esize; 4635 break; 4636 4637 case CNTRL: 4638 if ((rv = ql_cntrl(ha, template_hdr, (void *)entry))) { 4639 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4640 } 4641 break; 4642 default: 4643 entry->hdr.driver_flags |= QL_DBG_SKIPPED_FLAG; 4644 break; 4645 } 4646 /* next entry in the template */ 4647 entry = (ql_minidump_entry_t *) ((char *) entry 4648 + entry->hdr.entry_size); 4649 } 4650 4651 if (!sane_start || (sane_end > 1)) { 4652 device_printf(ha->pci_dev, 4653 "\n%s: Template configuration error. Check Template\n", 4654 __func__); 4655 } 4656 4657 QL_DPRINT80(ha, (ha->pci_dev, "%s: Minidump num of entries = %d\n", 4658 __func__, template_hdr->num_of_entries)); 4659 4660 return 0; 4661 } 4662 4663 /* 4664 * Read CRB operation. 4665 */ 4666 static uint32_t 4667 ql_rdcrb(qla_host_t *ha, ql_minidump_entry_rdcrb_t * crb_entry, 4668 uint32_t * data_buff) 4669 { 4670 int loop_cnt; 4671 int ret; 4672 uint32_t op_count, addr, stride, value = 0; 4673 4674 addr = crb_entry->addr; 4675 op_count = crb_entry->op_count; 4676 stride = crb_entry->addr_stride; 4677 4678 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { 4679 4680 ret = ql_rdwr_indreg32(ha, addr, &value, 1); 4681 4682 if (ret) 4683 return (0); 4684 4685 *data_buff++ = addr; 4686 *data_buff++ = value; 4687 addr = addr + stride; 4688 } 4689 4690 /* 4691 * for testing purpose we return amount of data written 4692 */ 4693 return (op_count * (2 * sizeof(uint32_t))); 4694 } 4695 4696 /* 4697 * Handle L2 Cache. 4698 */ 4699 4700 static uint32_t 4701 ql_L2Cache(qla_host_t *ha, ql_minidump_entry_cache_t *cacheEntry, 4702 uint32_t * data_buff) 4703 { 4704 int i, k; 4705 int loop_cnt; 4706 int ret; 4707 4708 uint32_t read_value; 4709 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr, cntl_value_w; 4710 uint32_t tag_value, read_cnt; 4711 volatile uint8_t cntl_value_r; 4712 long timeout; 4713 uint32_t data; 4714 4715 loop_cnt = cacheEntry->op_count; 4716 4717 read_addr = cacheEntry->read_addr; 4718 cntrl_addr = cacheEntry->control_addr; 4719 cntl_value_w = (uint32_t) cacheEntry->write_value; 4720 4721 tag_reg_addr = cacheEntry->tag_reg_addr; 4722 4723 tag_value = cacheEntry->init_tag_value; 4724 read_cnt = cacheEntry->read_addr_cnt; 4725 4726 for (i = 0; i < loop_cnt; i++) { 4727 4728 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0); 4729 if (ret) 4730 return (0); 4731 4732 if (cacheEntry->write_value != 0) { 4733 4734 ret = ql_rdwr_indreg32(ha, cntrl_addr, 4735 &cntl_value_w, 0); 4736 if (ret) 4737 return (0); 4738 } 4739 4740 if (cacheEntry->poll_mask != 0) { 4741 4742 timeout = cacheEntry->poll_wait; 4743 4744 ret = ql_rdwr_indreg32(ha, cntrl_addr, &data, 1); 4745 if (ret) 4746 return (0); 4747 4748 cntl_value_r = (uint8_t)data; 4749 4750 while ((cntl_value_r & cacheEntry->poll_mask) != 0) { 4751 4752 if (timeout) { 4753 qla_mdelay(__func__, 1); 4754 timeout--; 4755 } else 4756 break; 4757 4758 ret = ql_rdwr_indreg32(ha, cntrl_addr, 4759 &data, 1); 4760 if (ret) 4761 return (0); 4762 4763 cntl_value_r = (uint8_t)data; 4764 } 4765 if (!timeout) { 4766 /* Report timeout error. 4767 * core dump capture failed 4768 * Skip remaining entries. 4769 * Write buffer out to file 4770 * Use driver specific fields in template header 4771 * to report this error. 4772 */ 4773 return (-1); 4774 } 4775 } 4776 4777 addr = read_addr; 4778 for (k = 0; k < read_cnt; k++) { 4779 4780 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 4781 if (ret) 4782 return (0); 4783 4784 *data_buff++ = read_value; 4785 addr += cacheEntry->read_addr_stride; 4786 } 4787 4788 tag_value += cacheEntry->tag_value_stride; 4789 } 4790 4791 return (read_cnt * loop_cnt * sizeof(uint32_t)); 4792 } 4793 4794 /* 4795 * Handle L1 Cache. 4796 */ 4797 4798 static uint32_t 4799 ql_L1Cache(qla_host_t *ha, 4800 ql_minidump_entry_cache_t *cacheEntry, 4801 uint32_t *data_buff) 4802 { 4803 int ret; 4804 int i, k; 4805 int loop_cnt; 4806 4807 uint32_t read_value; 4808 uint32_t addr, read_addr, cntrl_addr, tag_reg_addr; 4809 uint32_t tag_value, read_cnt; 4810 uint32_t cntl_value_w; 4811 4812 loop_cnt = cacheEntry->op_count; 4813 4814 read_addr = cacheEntry->read_addr; 4815 cntrl_addr = cacheEntry->control_addr; 4816 cntl_value_w = (uint32_t) cacheEntry->write_value; 4817 4818 tag_reg_addr = cacheEntry->tag_reg_addr; 4819 4820 tag_value = cacheEntry->init_tag_value; 4821 read_cnt = cacheEntry->read_addr_cnt; 4822 4823 for (i = 0; i < loop_cnt; i++) { 4824 4825 ret = ql_rdwr_indreg32(ha, tag_reg_addr, &tag_value, 0); 4826 if (ret) 4827 return (0); 4828 4829 ret = ql_rdwr_indreg32(ha, cntrl_addr, &cntl_value_w, 0); 4830 if (ret) 4831 return (0); 4832 4833 addr = read_addr; 4834 for (k = 0; k < read_cnt; k++) { 4835 4836 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 4837 if (ret) 4838 return (0); 4839 4840 *data_buff++ = read_value; 4841 addr += cacheEntry->read_addr_stride; 4842 } 4843 4844 tag_value += cacheEntry->tag_value_stride; 4845 } 4846 4847 return (read_cnt * loop_cnt * sizeof(uint32_t)); 4848 } 4849 4850 /* 4851 * Reading OCM memory 4852 */ 4853 4854 static uint32_t 4855 ql_rdocm(qla_host_t *ha, 4856 ql_minidump_entry_rdocm_t *ocmEntry, 4857 uint32_t *data_buff) 4858 { 4859 int i, loop_cnt; 4860 volatile uint32_t addr; 4861 volatile uint32_t value; 4862 4863 addr = ocmEntry->read_addr; 4864 loop_cnt = ocmEntry->op_count; 4865 4866 for (i = 0; i < loop_cnt; i++) { 4867 value = READ_REG32(ha, addr); 4868 *data_buff++ = value; 4869 addr += ocmEntry->read_addr_stride; 4870 } 4871 return (loop_cnt * sizeof(value)); 4872 } 4873 4874 /* 4875 * Read memory 4876 */ 4877 4878 static uint32_t 4879 ql_rdmem(qla_host_t *ha, 4880 ql_minidump_entry_rdmem_t *mem_entry, 4881 uint32_t *data_buff) 4882 { 4883 int ret; 4884 int i, loop_cnt; 4885 volatile uint32_t addr; 4886 q80_offchip_mem_val_t val; 4887 4888 addr = mem_entry->read_addr; 4889 4890 /* size in bytes / 16 */ 4891 loop_cnt = mem_entry->read_data_size / (sizeof(uint32_t) * 4); 4892 4893 for (i = 0; i < loop_cnt; i++) { 4894 4895 ret = ql_rdwr_offchip_mem(ha, (addr & 0x0ffffffff), &val, 1); 4896 if (ret) 4897 return (0); 4898 4899 *data_buff++ = val.data_lo; 4900 *data_buff++ = val.data_hi; 4901 *data_buff++ = val.data_ulo; 4902 *data_buff++ = val.data_uhi; 4903 4904 addr += (sizeof(uint32_t) * 4); 4905 } 4906 4907 return (loop_cnt * (sizeof(uint32_t) * 4)); 4908 } 4909 4910 /* 4911 * Read Rom 4912 */ 4913 4914 static uint32_t 4915 ql_rdrom(qla_host_t *ha, 4916 ql_minidump_entry_rdrom_t *romEntry, 4917 uint32_t *data_buff) 4918 { 4919 int ret; 4920 int i, loop_cnt; 4921 uint32_t addr; 4922 uint32_t value; 4923 4924 addr = romEntry->read_addr; 4925 loop_cnt = romEntry->read_data_size; /* This is size in bytes */ 4926 loop_cnt /= sizeof(value); 4927 4928 for (i = 0; i < loop_cnt; i++) { 4929 4930 ret = ql_rd_flash32(ha, addr, &value); 4931 if (ret) 4932 return (0); 4933 4934 *data_buff++ = value; 4935 addr += sizeof(value); 4936 } 4937 4938 return (loop_cnt * sizeof(value)); 4939 } 4940 4941 /* 4942 * Read MUX data 4943 */ 4944 4945 static uint32_t 4946 ql_rdmux(qla_host_t *ha, 4947 ql_minidump_entry_mux_t *muxEntry, 4948 uint32_t *data_buff) 4949 { 4950 int ret; 4951 int loop_cnt; 4952 uint32_t read_value, sel_value; 4953 uint32_t read_addr, select_addr; 4954 4955 select_addr = muxEntry->select_addr; 4956 sel_value = muxEntry->select_value; 4957 read_addr = muxEntry->read_addr; 4958 4959 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) { 4960 4961 ret = ql_rdwr_indreg32(ha, select_addr, &sel_value, 0); 4962 if (ret) 4963 return (0); 4964 4965 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 4966 if (ret) 4967 return (0); 4968 4969 *data_buff++ = sel_value; 4970 *data_buff++ = read_value; 4971 4972 sel_value += muxEntry->select_value_stride; 4973 } 4974 4975 return (loop_cnt * (2 * sizeof(uint32_t))); 4976 } 4977 4978 static uint32_t 4979 ql_rdmux2(qla_host_t *ha, 4980 ql_minidump_entry_mux2_t *muxEntry, 4981 uint32_t *data_buff) 4982 { 4983 int ret; 4984 int loop_cnt; 4985 4986 uint32_t select_addr_1, select_addr_2; 4987 uint32_t select_value_1, select_value_2; 4988 uint32_t select_value_count, select_value_mask; 4989 uint32_t read_addr, read_value; 4990 4991 select_addr_1 = muxEntry->select_addr_1; 4992 select_addr_2 = muxEntry->select_addr_2; 4993 select_value_1 = muxEntry->select_value_1; 4994 select_value_2 = muxEntry->select_value_2; 4995 select_value_count = muxEntry->select_value_count; 4996 select_value_mask = muxEntry->select_value_mask; 4997 4998 read_addr = muxEntry->read_addr; 4999 5000 for (loop_cnt = 0; loop_cnt < muxEntry->select_value_count; 5001 loop_cnt++) { 5002 5003 uint32_t temp_sel_val; 5004 5005 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_1, 0); 5006 if (ret) 5007 return (0); 5008 5009 temp_sel_val = select_value_1 & select_value_mask; 5010 5011 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0); 5012 if (ret) 5013 return (0); 5014 5015 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5016 if (ret) 5017 return (0); 5018 5019 *data_buff++ = temp_sel_val; 5020 *data_buff++ = read_value; 5021 5022 ret = ql_rdwr_indreg32(ha, select_addr_1, &select_value_2, 0); 5023 if (ret) 5024 return (0); 5025 5026 temp_sel_val = select_value_2 & select_value_mask; 5027 5028 ret = ql_rdwr_indreg32(ha, select_addr_2, &temp_sel_val, 0); 5029 if (ret) 5030 return (0); 5031 5032 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5033 if (ret) 5034 return (0); 5035 5036 *data_buff++ = temp_sel_val; 5037 *data_buff++ = read_value; 5038 5039 select_value_1 += muxEntry->select_value_stride; 5040 select_value_2 += muxEntry->select_value_stride; 5041 } 5042 5043 return (loop_cnt * (4 * sizeof(uint32_t))); 5044 } 5045 5046 /* 5047 * Handling Queue State Reads. 5048 */ 5049 5050 static uint32_t 5051 ql_rdqueue(qla_host_t *ha, 5052 ql_minidump_entry_queue_t *queueEntry, 5053 uint32_t *data_buff) 5054 { 5055 int ret; 5056 int loop_cnt, k; 5057 uint32_t read_value; 5058 uint32_t read_addr, read_stride, select_addr; 5059 uint32_t queue_id, read_cnt; 5060 5061 read_cnt = queueEntry->read_addr_cnt; 5062 read_stride = queueEntry->read_addr_stride; 5063 select_addr = queueEntry->select_addr; 5064 5065 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count; 5066 loop_cnt++) { 5067 5068 ret = ql_rdwr_indreg32(ha, select_addr, &queue_id, 0); 5069 if (ret) 5070 return (0); 5071 5072 read_addr = queueEntry->read_addr; 5073 5074 for (k = 0; k < read_cnt; k++) { 5075 5076 ret = ql_rdwr_indreg32(ha, read_addr, &read_value, 1); 5077 if (ret) 5078 return (0); 5079 5080 *data_buff++ = read_value; 5081 read_addr += read_stride; 5082 } 5083 5084 queue_id += queueEntry->queue_id_stride; 5085 } 5086 5087 return (loop_cnt * (read_cnt * sizeof(uint32_t))); 5088 } 5089 5090 /* 5091 * Handling control entries. 5092 */ 5093 5094 static uint32_t 5095 ql_cntrl(qla_host_t *ha, 5096 ql_minidump_template_hdr_t *template_hdr, 5097 ql_minidump_entry_cntrl_t *crbEntry) 5098 { 5099 int ret; 5100 int count; 5101 uint32_t opcode, read_value, addr, entry_addr; 5102 long timeout; 5103 5104 entry_addr = crbEntry->addr; 5105 5106 for (count = 0; count < crbEntry->op_count; count++) { 5107 opcode = crbEntry->opcode; 5108 5109 if (opcode & QL_DBG_OPCODE_WR) { 5110 5111 ret = ql_rdwr_indreg32(ha, entry_addr, 5112 &crbEntry->value_1, 0); 5113 if (ret) 5114 return (0); 5115 5116 opcode &= ~QL_DBG_OPCODE_WR; 5117 } 5118 5119 if (opcode & QL_DBG_OPCODE_RW) { 5120 5121 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1); 5122 if (ret) 5123 return (0); 5124 5125 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0); 5126 if (ret) 5127 return (0); 5128 5129 opcode &= ~QL_DBG_OPCODE_RW; 5130 } 5131 5132 if (opcode & QL_DBG_OPCODE_AND) { 5133 5134 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1); 5135 if (ret) 5136 return (0); 5137 5138 read_value &= crbEntry->value_2; 5139 opcode &= ~QL_DBG_OPCODE_AND; 5140 5141 if (opcode & QL_DBG_OPCODE_OR) { 5142 read_value |= crbEntry->value_3; 5143 opcode &= ~QL_DBG_OPCODE_OR; 5144 } 5145 5146 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0); 5147 if (ret) 5148 return (0); 5149 } 5150 5151 if (opcode & QL_DBG_OPCODE_OR) { 5152 5153 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 1); 5154 if (ret) 5155 return (0); 5156 5157 read_value |= crbEntry->value_3; 5158 5159 ret = ql_rdwr_indreg32(ha, entry_addr, &read_value, 0); 5160 if (ret) 5161 return (0); 5162 5163 opcode &= ~QL_DBG_OPCODE_OR; 5164 } 5165 5166 if (opcode & QL_DBG_OPCODE_POLL) { 5167 5168 opcode &= ~QL_DBG_OPCODE_POLL; 5169 timeout = crbEntry->poll_timeout; 5170 addr = entry_addr; 5171 5172 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 5173 if (ret) 5174 return (0); 5175 5176 while ((read_value & crbEntry->value_2) 5177 != crbEntry->value_1) { 5178 5179 if (timeout) { 5180 qla_mdelay(__func__, 1); 5181 timeout--; 5182 } else 5183 break; 5184 5185 ret = ql_rdwr_indreg32(ha, addr, 5186 &read_value, 1); 5187 if (ret) 5188 return (0); 5189 } 5190 5191 if (!timeout) { 5192 /* 5193 * Report timeout error. 5194 * core dump capture failed 5195 * Skip remaining entries. 5196 * Write buffer out to file 5197 * Use driver specific fields in template header 5198 * to report this error. 5199 */ 5200 return (-1); 5201 } 5202 } 5203 5204 if (opcode & QL_DBG_OPCODE_RDSTATE) { 5205 /* 5206 * decide which address to use. 5207 */ 5208 if (crbEntry->state_index_a) { 5209 addr = template_hdr->saved_state_array[ 5210 crbEntry-> state_index_a]; 5211 } else { 5212 addr = entry_addr; 5213 } 5214 5215 ret = ql_rdwr_indreg32(ha, addr, &read_value, 1); 5216 if (ret) 5217 return (0); 5218 5219 template_hdr->saved_state_array[crbEntry->state_index_v] 5220 = read_value; 5221 opcode &= ~QL_DBG_OPCODE_RDSTATE; 5222 } 5223 5224 if (opcode & QL_DBG_OPCODE_WRSTATE) { 5225 /* 5226 * decide which value to use. 5227 */ 5228 if (crbEntry->state_index_v) { 5229 read_value = template_hdr->saved_state_array[ 5230 crbEntry->state_index_v]; 5231 } else { 5232 read_value = crbEntry->value_1; 5233 } 5234 /* 5235 * decide which address to use. 5236 */ 5237 if (crbEntry->state_index_a) { 5238 addr = template_hdr->saved_state_array[ 5239 crbEntry-> state_index_a]; 5240 } else { 5241 addr = entry_addr; 5242 } 5243 5244 ret = ql_rdwr_indreg32(ha, addr, &read_value, 0); 5245 if (ret) 5246 return (0); 5247 5248 opcode &= ~QL_DBG_OPCODE_WRSTATE; 5249 } 5250 5251 if (opcode & QL_DBG_OPCODE_MDSTATE) { 5252 /* Read value from saved state using index */ 5253 read_value = template_hdr->saved_state_array[ 5254 crbEntry->state_index_v]; 5255 5256 read_value <<= crbEntry->shl; /*Shift left operation */ 5257 read_value >>= crbEntry->shr; /*Shift right operation */ 5258 5259 if (crbEntry->value_2) { 5260 /* check if AND mask is provided */ 5261 read_value &= crbEntry->value_2; 5262 } 5263 5264 read_value |= crbEntry->value_3; /* OR operation */ 5265 read_value += crbEntry->value_1; /* increment op */ 5266 5267 /* Write value back to state area. */ 5268 5269 template_hdr->saved_state_array[crbEntry->state_index_v] 5270 = read_value; 5271 opcode &= ~QL_DBG_OPCODE_MDSTATE; 5272 } 5273 5274 entry_addr += crbEntry->addr_stride; 5275 } 5276 5277 return (0); 5278 } 5279 5280 /* 5281 * Handling rd poll entry. 5282 */ 5283 5284 static uint32_t 5285 ql_pollrd(qla_host_t *ha, ql_minidump_entry_pollrd_t *entry, 5286 uint32_t *data_buff) 5287 { 5288 int ret; 5289 int loop_cnt; 5290 uint32_t op_count, select_addr, select_value_stride, select_value; 5291 uint32_t read_addr, poll, mask, data_size, data; 5292 uint32_t wait_count = 0; 5293 5294 select_addr = entry->select_addr; 5295 read_addr = entry->read_addr; 5296 select_value = entry->select_value; 5297 select_value_stride = entry->select_value_stride; 5298 op_count = entry->op_count; 5299 poll = entry->poll; 5300 mask = entry->mask; 5301 data_size = entry->data_size; 5302 5303 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) { 5304 5305 ret = ql_rdwr_indreg32(ha, select_addr, &select_value, 0); 5306 if (ret) 5307 return (0); 5308 5309 wait_count = 0; 5310 5311 while (wait_count < poll) { 5312 5313 uint32_t temp; 5314 5315 ret = ql_rdwr_indreg32(ha, select_addr, &temp, 1); 5316 if (ret) 5317 return (0); 5318 5319 if ( (temp & mask) != 0 ) { 5320 break; 5321 } 5322 wait_count++; 5323 } 5324 5325 if (wait_count == poll) { 5326 device_printf(ha->pci_dev, 5327 "%s: Error in processing entry\n", __func__); 5328 device_printf(ha->pci_dev, 5329 "%s: wait_count <0x%x> poll <0x%x>\n", 5330 __func__, wait_count, poll); 5331 return 0; 5332 } 5333 5334 ret = ql_rdwr_indreg32(ha, read_addr, &data, 1); 5335 if (ret) 5336 return (0); 5337 5338 *data_buff++ = select_value; 5339 *data_buff++ = data; 5340 select_value = select_value + select_value_stride; 5341 } 5342 5343 /* 5344 * for testing purpose we return amount of data written 5345 */ 5346 return (loop_cnt * (2 * sizeof(uint32_t))); 5347 } 5348 5349 5350 /* 5351 * Handling rd modify write poll entry. 5352 */ 5353 5354 static uint32_t 5355 ql_pollrd_modify_write(qla_host_t *ha, 5356 ql_minidump_entry_rd_modify_wr_with_poll_t *entry, 5357 uint32_t *data_buff) 5358 { 5359 int ret; 5360 uint32_t addr_1, addr_2, value_1, value_2, data; 5361 uint32_t poll, mask, data_size, modify_mask; 5362 uint32_t wait_count = 0; 5363 5364 addr_1 = entry->addr_1; 5365 addr_2 = entry->addr_2; 5366 value_1 = entry->value_1; 5367 value_2 = entry->value_2; 5368 5369 poll = entry->poll; 5370 mask = entry->mask; 5371 modify_mask = entry->modify_mask; 5372 data_size = entry->data_size; 5373 5374 5375 ret = ql_rdwr_indreg32(ha, addr_1, &value_1, 0); 5376 if (ret) 5377 return (0); 5378 5379 wait_count = 0; 5380 while (wait_count < poll) { 5381 5382 uint32_t temp; 5383 5384 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1); 5385 if (ret) 5386 return (0); 5387 5388 if ( (temp & mask) != 0 ) { 5389 break; 5390 } 5391 wait_count++; 5392 } 5393 5394 if (wait_count == poll) { 5395 device_printf(ha->pci_dev, "%s Error in processing entry\n", 5396 __func__); 5397 } else { 5398 5399 ret = ql_rdwr_indreg32(ha, addr_2, &data, 1); 5400 if (ret) 5401 return (0); 5402 5403 data = (data & modify_mask); 5404 5405 ret = ql_rdwr_indreg32(ha, addr_2, &data, 0); 5406 if (ret) 5407 return (0); 5408 5409 ret = ql_rdwr_indreg32(ha, addr_1, &value_2, 0); 5410 if (ret) 5411 return (0); 5412 5413 /* Poll again */ 5414 wait_count = 0; 5415 while (wait_count < poll) { 5416 5417 uint32_t temp; 5418 5419 ret = ql_rdwr_indreg32(ha, addr_1, &temp, 1); 5420 if (ret) 5421 return (0); 5422 5423 if ( (temp & mask) != 0 ) { 5424 break; 5425 } 5426 wait_count++; 5427 } 5428 *data_buff++ = addr_2; 5429 *data_buff++ = data; 5430 } 5431 5432 /* 5433 * for testing purpose we return amount of data written 5434 */ 5435 return (2 * sizeof(uint32_t)); 5436 } 5437 5438 5439