1 /* 2 * Copyright (c) 2013-2016 Qlogic Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * File: ql_def.h 32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 33 */ 34 35 #ifndef _QL_DEF_H_ 36 #define _QL_DEF_H_ 37 38 #define BIT_0 (0x1 << 0) 39 #define BIT_1 (0x1 << 1) 40 #define BIT_2 (0x1 << 2) 41 #define BIT_3 (0x1 << 3) 42 #define BIT_4 (0x1 << 4) 43 #define BIT_5 (0x1 << 5) 44 #define BIT_6 (0x1 << 6) 45 #define BIT_7 (0x1 << 7) 46 #define BIT_8 (0x1 << 8) 47 #define BIT_9 (0x1 << 9) 48 #define BIT_10 (0x1 << 10) 49 #define BIT_11 (0x1 << 11) 50 #define BIT_12 (0x1 << 12) 51 #define BIT_13 (0x1 << 13) 52 #define BIT_14 (0x1 << 14) 53 #define BIT_15 (0x1 << 15) 54 #define BIT_16 (0x1 << 16) 55 #define BIT_17 (0x1 << 17) 56 #define BIT_18 (0x1 << 18) 57 #define BIT_19 (0x1 << 19) 58 #define BIT_20 (0x1 << 20) 59 #define BIT_21 (0x1 << 21) 60 #define BIT_22 (0x1 << 22) 61 #define BIT_23 (0x1 << 23) 62 #define BIT_24 (0x1 << 24) 63 #define BIT_25 (0x1 << 25) 64 #define BIT_26 (0x1 << 26) 65 #define BIT_27 (0x1 << 27) 66 #define BIT_28 (0x1 << 28) 67 #define BIT_29 (0x1 << 29) 68 #define BIT_30 (0x1 << 30) 69 #define BIT_31 (0x1 << 31) 70 71 struct qla_rx_buf { 72 struct mbuf *m_head; 73 bus_dmamap_t map; 74 bus_addr_t paddr; 75 uint32_t handle; 76 void *next; 77 }; 78 typedef struct qla_rx_buf qla_rx_buf_t; 79 80 struct qla_rx_ring { 81 qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS]; 82 }; 83 typedef struct qla_rx_ring qla_rx_ring_t; 84 85 struct qla_tx_buf { 86 struct mbuf *m_head; 87 bus_dmamap_t map; 88 }; 89 typedef struct qla_tx_buf qla_tx_buf_t; 90 91 #define QLA_MAX_SEGMENTS 62 /* maximum # of segs in a sg list */ 92 #define QLA_MAX_MTU 9000 93 #define QLA_STD_FRAME_SIZE 1514 94 #define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22) 95 96 /* Number of MSIX/MSI Vectors required */ 97 98 struct qla_ivec { 99 uint32_t sds_idx; 100 void *ha; 101 struct resource *irq; 102 void *handle; 103 int irq_rid; 104 }; 105 106 typedef struct qla_ivec qla_ivec_t; 107 108 #define QLA_WATCHDOG_CALLOUT_TICKS 1 109 110 typedef struct _qla_tx_ring { 111 qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS]; 112 uint64_t count; 113 } qla_tx_ring_t; 114 115 /* 116 * Adapter structure contains the hardware independent information of the 117 * pci function. 118 */ 119 struct qla_host { 120 volatile struct { 121 volatile uint32_t 122 qla_callout_init :1, 123 qla_watchdog_active :1, 124 qla_watchdog_exit :1, 125 qla_watchdog_pause :1, 126 lro_init :1, 127 stop_rcv :1, 128 parent_tag :1, 129 lock_init :1; 130 } flags; 131 132 volatile uint32_t qla_watchdog_exited; 133 volatile uint32_t qla_watchdog_paused; 134 volatile uint32_t qla_initiate_recovery; 135 136 device_t pci_dev; 137 138 uint16_t watchdog_ticks; 139 uint8_t pci_func; 140 uint8_t resvd; 141 142 /* ioctl related */ 143 struct cdev *ioctl_dev; 144 145 /* register mapping */ 146 struct resource *pci_reg; 147 int reg_rid; 148 struct resource *pci_reg1; 149 int reg_rid1; 150 151 /* interrupts */ 152 struct resource *mbx_irq; 153 void *mbx_handle; 154 int mbx_irq_rid; 155 156 int msix_count; 157 158 qla_ivec_t irq_vec[MAX_SDS_RINGS]; 159 160 /* parent dma tag */ 161 bus_dma_tag_t parent_tag; 162 163 /* interface to o.s */ 164 struct ifnet *ifp; 165 166 struct ifmedia media; 167 uint16_t max_frame_size; 168 uint16_t rsrvd0; 169 int if_flags; 170 171 /* hardware access lock */ 172 173 struct mtx hw_lock; 174 volatile uint32_t hw_lock_held; 175 176 /* transmit and receive buffers */ 177 uint32_t txr_idx; /* index of the current tx ring */ 178 qla_tx_ring_t tx_ring[NUM_TX_RINGS]; 179 180 bus_dma_tag_t tx_tag; 181 struct task tx_task; 182 struct taskqueue *tx_tq; 183 struct callout tx_callout; 184 struct mtx tx_lock; 185 186 qla_rx_ring_t rx_ring[MAX_RDS_RINGS]; 187 bus_dma_tag_t rx_tag; 188 uint32_t std_replenish; 189 190 qla_rx_buf_t *rxb_free; 191 uint32_t rxb_free_count; 192 volatile uint32_t posting; 193 194 /* stats */ 195 uint32_t err_m_getcl; 196 uint32_t err_m_getjcl; 197 uint32_t err_tx_dmamap_create; 198 uint32_t err_tx_dmamap_load; 199 uint32_t err_tx_defrag; 200 201 uint64_t rx_frames; 202 uint64_t rx_bytes; 203 204 uint64_t lro_pkt_count; 205 uint64_t lro_bytes; 206 207 uint64_t ipv4_lro; 208 uint64_t ipv6_lro; 209 210 uint64_t tx_frames; 211 uint64_t tx_bytes; 212 uint64_t tx_tso_frames; 213 uint64_t hw_vlan_tx_frames; 214 215 uint32_t fw_ver_major; 216 uint32_t fw_ver_minor; 217 uint32_t fw_ver_sub; 218 uint32_t fw_ver_build; 219 220 /* hardware specific */ 221 qla_hw_t hw; 222 223 /* debug stuff */ 224 volatile const char *qla_lock; 225 volatile const char *qla_unlock; 226 uint32_t dbg_level; 227 228 uint8_t fw_ver_str[32]; 229 230 /* Error Injection Related */ 231 uint32_t err_inject; 232 struct task err_task; 233 struct taskqueue *err_tq; 234 235 /* Async Event Related */ 236 uint32_t async_event; 237 struct task async_event_task; 238 struct taskqueue *async_event_tq; 239 240 /* Peer Device */ 241 device_t peer_dev; 242 243 volatile uint32_t msg_from_peer; 244 #define QL_PEER_MSG_RESET 0x01 245 #define QL_PEER_MSG_ACK 0x02 246 247 }; 248 typedef struct qla_host qla_host_t; 249 250 /* note that align has to be a power of 2 */ 251 #define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1); 252 #define QL_MIN(x, y) ((x < y) ? x : y) 253 254 #define QL_RUNNING(ifp) \ 255 ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \ 256 IFF_DRV_RUNNING) 257 258 /* Return 0, if identical, else 1 */ 259 #define QL_MAC_CMP(mac1, mac2) \ 260 ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \ 261 (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1) 262 263 #endif /* #ifndef _QL_DEF_H_ */ 264