1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011-2013 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 /* 30 * File: qla_reg.h 31 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32 */ 33 34 #ifndef _QLA_REG_H_ 35 #define _QLA_REG_H_ 36 37 /* 38 * Begin Definitions for QLA82xx Registers 39 */ 40 41 /* 42 * Register offsets for QLA8022 43 */ 44 45 /****************************** 46 * PCIe Registers 47 ******************************/ 48 #define Q8_CRB_WINDOW_2M 0x130060 49 50 #define Q8_INT_VECTOR 0x130100 51 #define Q8_INT_MASK 0x130104 52 53 #define Q8_INT_TARGET_STATUS_F0 0x130118 54 #define Q8_INT_TARGET_MASK_F0 0x130128 55 #define Q8_INT_TARGET_STATUS_F1 0x130160 56 #define Q8_INT_TARGET_MASK_F1 0x130170 57 #define Q8_INT_TARGET_STATUS_F2 0x130164 58 #define Q8_INT_TARGET_MASK_F2 0x130174 59 #define Q8_INT_TARGET_STATUS_F3 0x130168 60 #define Q8_INT_TARGET_MASK_F3 0x130178 61 #define Q8_INT_TARGET_STATUS_F4 0x130360 62 #define Q8_INT_TARGET_MASK_F4 0x130370 63 #define Q8_INT_TARGET_STATUS_F5 0x130364 64 #define Q8_INT_TARGET_MASK_F5 0x130374 65 #define Q8_INT_TARGET_STATUS_F6 0x130368 66 #define Q8_INT_TARGET_MASK_F6 0x130378 67 #define Q8_INT_TARGET_STATUS_F7 0x13036C 68 #define Q8_INT_TARGET_MASK_F7 0x13037C 69 70 #define Q8_SEM2_LOCK 0x13C010 71 #define Q8_SEM2_UNLOCK 0x13C014 72 #define Q8_SEM3_LOCK 0x13C018 73 #define Q8_SEM3_UNLOCK 0x13C01C 74 #define Q8_SEM5_LOCK 0x13C028 75 #define Q8_SEM5_UNLOCK 0x13C02C 76 #define Q8_SEM7_LOCK 0x13C038 77 #define Q8_SEM7_UNLOCK 0x13C03C 78 79 /* Valid bit for a SEM<N>_LOCK registers */ 80 #define SEM_LOCK_BIT 0x00000001 81 82 #define Q8_ROM_LOCKID 0x1B2100 83 84 /******************************* 85 * Firmware Interface Registers 86 *******************************/ 87 #define Q8_FW_VER_MAJOR 0x1B2150 88 #define Q8_FW_VER_MINOR 0x1B2154 89 #define Q8_FW_VER_SUB 0x1B2158 90 #define Q8_FW_VER_BUILD 0x1B2168 91 92 #define Q8_CMDPEG_STATE 0x1B2250 93 #define Q8_RCVPEG_STATE 0x1B233C 94 /* 95 * definitions for Q8_CMDPEG_STATE 96 */ 97 #define CMDPEG_PHAN_INIT_COMPLETE 0xFF01 98 99 #define Q8_ROM_STATUS 0x1A0004 100 /* 101 * definitions for Q8_ROM_STATUS 102 * bit definitions for Q8_UNM_ROMUSB_GLB_STATUS 103 * 31:3 Reserved; Rest as below 104 */ 105 #define ROM_STATUS_RDY 0x0004 106 #define ROM_STATUS_DONE 0x0002 107 #define ROM_STATUS_AUTO_ROM_SHDW 0x0001 108 109 #define Q8_ASIC_RESET 0x1A0008 110 /* 111 * definitions for Q8_ASIC_RESET 112 */ 113 #define ASIC_RESET_RST_XDMA 0x00800000 /* Reset XDMA */ 114 #define ASIC_RESET_PEG_ICACHE 0x00000020 /* Reset PEG_ICACHE */ 115 #define ASIC_RESET_PEG_DCACHE 0x00000010 /* Reset PEG_DCACHE */ 116 #define ASIC_RESET_PEG_3 0x00000008 /* Reset PEG_3 */ 117 #define ASIC_RESET_PEG_2 0x00000004 /* Reset PEG_2 */ 118 #define ASIC_RESET_PEG_1 0x00000002 /* Reset PEG_1 */ 119 #define ASIC_RESET_PEG_0 0x00000001 /* Reset PEG_0 */ 120 121 #define Q8_COLD_BOOT 0x1B21FC 122 /* 123 * definitions for Q8_COLD_BOOT 124 */ 125 #define COLD_BOOT_VALUE 0x12345678 126 127 #define Q8_MIU_TEST_AGT_CTRL 0x180090 128 #define Q8_MIU_TEST_AGT_ADDR_LO 0x180094 129 #define Q8_MIU_TEST_AGT_ADDR_HI 0x180098 130 #define Q8_MIU_TEST_AGT_WRDATA_LO 0x1800A0 131 #define Q8_MIU_TEST_AGT_WRDATA_HI 0x1800A4 132 #define Q8_MIU_TEST_AGT_RDDATA_LO 0x1800A8 133 #define Q8_MIU_TEST_AGT_RDDATA_HI 0x1800AC 134 #define Q8_MIU_TEST_AGT_WRDATA_ULO 0x1800B0 135 #define Q8_MIU_TEST_AGT_WRDATA_UHI 0x1800B4 136 #define Q8_MIU_TEST_AGT_RDDATA_ULO 0x1800B8 137 #define Q8_MIU_TEST_AGT_RDDATA_UHI 0x1800BC 138 139 #define Q8_PEG_0_RESET 0x160018 140 #define Q8_PEG_0_CLR1 0x160008 141 #define Q8_PEG_0_CLR2 0x16000C 142 #define Q8_PEG_1_CLR1 0x161008 143 #define Q8_PEG_1_CLR2 0x16100C 144 #define Q8_PEG_2_CLR1 0x162008 145 #define Q8_PEG_2_CLR2 0x16200C 146 #define Q8_PEG_3_CLR1 0x163008 147 #define Q8_PEG_3_CLR2 0x16300C 148 #define Q8_PEG_4_CLR1 0x164008 149 #define Q8_PEG_4_CLR2 0x16400C 150 #define Q8_PEG_D_RESET1 0x1650EC 151 #define Q8_PEG_D_RESET2 0x16504C 152 #define Q8_PEG_HALT_STATUS1 0x1B20A8 153 #define Q8_PEG_HALT_STATUS2 0x1B20AC 154 #define Q8_FIRMWARE_HEARTBEAT 0x1B20B0 155 #define Q8_PEG_I_RESET 0x16604C 156 157 #define Q8_CRB_MAC_BLOCK_START 0x1B21C0 158 159 /*************************************************** 160 * Flash ROM Access Registers ( Indirect Registers ) 161 ***************************************************/ 162 163 #define Q8_ROM_INSTR_OPCODE 0x03310004 164 /* 165 * bit definitions for Q8_ROM_INSTR_OPCODE 166 * 31:8 Reserved; Rest Below 167 */ 168 #define ROM_OPCODE_WR_STATUS_REG 0x01 169 #define ROM_OPCODE_PROG_PAGE 0x02 170 #define ROM_OPCODE_RD_BYTE 0x03 171 #define ROM_OPCODE_WR_DISABLE 0x04 172 #define ROM_OPCODE_RD_STATUS_REG 0x05 173 #define ROM_OPCODE_WR_ENABLE 0x06 174 #define ROM_OPCODE_FAST_RD 0x0B 175 #define ROM_OPCODE_REL_DEEP_PWR_DWN 0xAB 176 #define ROM_OPCODE_BULK_ERASE 0xC7 177 #define ROM_OPCODE_DEEP_PWR_DWN 0xC9 178 #define ROM_OPCODE_SECTOR_ERASE 0xD8 179 180 #define Q8_ROM_ADDRESS 0x03310008 181 /* 182 * bit definitions for Q8_ROM_ADDRESS 183 * 31:24 Reserved; 184 * 23:0 Physical ROM Address in bytes 185 */ 186 187 #define Q8_ROM_ADDR_BYTE_COUNT 0x03310010 188 /* 189 * bit definitions for Q8_ROM_ADDR_BYTE_COUNT 190 * 31:2 Reserved; 191 * 1:0 max address bytes for ROM Interface 192 */ 193 194 #define Q8_ROM_DUMMY_BYTE_COUNT 0x03310014 195 /* 196 * bit definitions for Q8_ROM_DUMMY_BYTE_COUNT 197 * 31:2 Reserved; 198 * 1:0 dummy bytes for ROM Instructions 199 */ 200 201 #define Q8_ROM_RD_DATA 0x03310018 202 #define Q8_ROM_WR_DATA 0x0331000C 203 #define Q8_ROM_DIRECT_WINDOW 0x03310030 204 #define Q8_ROM_DIRECT_DATA_OFFSET 0x03310000 205 206 #define Q8_NX_CDRP_CMD_RSP 0x1B2218 207 #define Q8_NX_CDRP_ARG1 0x1B221C 208 #define Q8_NX_CDRP_ARG2 0x1B2220 209 #define Q8_NX_CDRP_ARG3 0x1B2224 210 #define Q8_NX_CDRP_SIGNATURE 0x1B2228 211 212 #define Q8_LINK_STATE 0x1B2298 213 #define Q8_LINK_SPEED_0 0x1B22E8 214 /* 215 * Macros for reading and writing registers 216 */ 217 218 #if defined(__i386__) || defined(__amd64__) 219 #define Q8_MB() __asm volatile("mfence" ::: "memory") 220 #define Q8_WMB() __asm volatile("sfence" ::: "memory") 221 #define Q8_RMB() __asm volatile("lfence" ::: "memory") 222 #else 223 #define Q8_MB() 224 #define Q8_WMB() 225 #define Q8_RMB() 226 #endif 227 228 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 229 #define READ_OFFSET32(ha, off) READ_REG32(ha, off) 230 231 #define WRITE_REG32(ha, reg, val) \ 232 {\ 233 bus_write_4((ha->pci_reg), reg, val);\ 234 bus_read_4((ha->pci_reg), reg);\ 235 } 236 237 #define WRITE_REG32_MB(ha, reg, val) \ 238 {\ 239 Q8_WMB();\ 240 bus_write_4((ha->pci_reg), reg, val);\ 241 } 242 243 #define WRITE_OFFSET32(ha, off, val)\ 244 {\ 245 bus_write_4((ha->pci_reg), off, val);\ 246 bus_read_4((ha->pci_reg), off);\ 247 } 248 249 #endif /* #ifndef _QLA_REG_H_ */ 250