xref: /freebsd/sys/dev/qlxgb/qla_reg.h (revision 4f52dfbb8d6c4d446500c5b097e3806ec219fbd4)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011-2013 Qlogic Corporation
5  * All rights reserved.
6  *
7  *  Redistribution and use in source and binary forms, with or without
8  *  modification, are permitted provided that the following conditions
9  *  are met:
10  *
11  *  1. Redistributions of source code must retain the above copyright
12  *     notice, this list of conditions and the following disclaimer.
13  *  2. Redistributions in binary form must reproduce the above copyright
14  *     notice, this list of conditions and the following disclaimer in the
15  *     documentation and/or other materials provided with the distribution.
16  *
17  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27  *  POSSIBILITY OF SUCH DAMAGE.
28  *
29  * $FreeBSD$
30  */
31 /*
32  * File: qla_reg.h
33  * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
34  */
35 
36 #ifndef _QLA_REG_H_
37 #define _QLA_REG_H_
38 
39 /*
40  * Begin Definitions for QLA82xx Registers
41  */
42 
43 /*
44  * Register offsets for QLA8022
45  */
46 
47 /******************************
48  * PCIe Registers
49  ******************************/
50 #define Q8_CRB_WINDOW_2M		0x130060
51 
52 #define Q8_INT_VECTOR			0x130100
53 #define Q8_INT_MASK			0x130104
54 
55 #define Q8_INT_TARGET_STATUS_F0		0x130118
56 #define Q8_INT_TARGET_MASK_F0		0x130128
57 #define Q8_INT_TARGET_STATUS_F1		0x130160
58 #define Q8_INT_TARGET_MASK_F1		0x130170
59 #define Q8_INT_TARGET_STATUS_F2		0x130164
60 #define Q8_INT_TARGET_MASK_F2		0x130174
61 #define Q8_INT_TARGET_STATUS_F3		0x130168
62 #define Q8_INT_TARGET_MASK_F3		0x130178
63 #define Q8_INT_TARGET_STATUS_F4		0x130360
64 #define Q8_INT_TARGET_MASK_F4		0x130370
65 #define Q8_INT_TARGET_STATUS_F5		0x130364
66 #define Q8_INT_TARGET_MASK_F5		0x130374
67 #define Q8_INT_TARGET_STATUS_F6		0x130368
68 #define Q8_INT_TARGET_MASK_F6		0x130378
69 #define Q8_INT_TARGET_STATUS_F7		0x13036C
70 #define Q8_INT_TARGET_MASK_F7		0x13037C
71 
72 #define Q8_SEM2_LOCK			0x13C010
73 #define Q8_SEM2_UNLOCK			0x13C014
74 #define Q8_SEM3_LOCK			0x13C018
75 #define Q8_SEM3_UNLOCK			0x13C01C
76 #define Q8_SEM5_LOCK			0x13C028
77 #define Q8_SEM5_UNLOCK			0x13C02C
78 #define Q8_SEM7_LOCK			0x13C038
79 #define Q8_SEM7_UNLOCK			0x13C03C
80 
81 /* Valid bit for a SEM<N>_LOCK registers */
82 #define SEM_LOCK_BIT			0x00000001
83 
84 
85 #define Q8_ROM_LOCKID			0x1B2100
86 
87 /*******************************
88  * Firmware Interface Registers
89  *******************************/
90 #define Q8_FW_VER_MAJOR			0x1B2150
91 #define Q8_FW_VER_MINOR			0x1B2154
92 #define Q8_FW_VER_SUB			0x1B2158
93 #define Q8_FW_VER_BUILD			0x1B2168
94 
95 #define Q8_CMDPEG_STATE			0x1B2250
96 #define Q8_RCVPEG_STATE			0x1B233C
97 /*
98  * definitions for Q8_CMDPEG_STATE
99  */
100 #define CMDPEG_PHAN_INIT_COMPLETE	0xFF01
101 
102 #define Q8_ROM_STATUS			0x1A0004
103 /*
104  * definitions for Q8_ROM_STATUS
105  * bit definitions for Q8_UNM_ROMUSB_GLB_STATUS
106  * 31:3 Reserved; Rest as below
107  */
108 #define	ROM_STATUS_RDY			0x0004
109 #define	ROM_STATUS_DONE			0x0002
110 #define	ROM_STATUS_AUTO_ROM_SHDW	0x0001
111 
112 #define Q8_ASIC_RESET			0x1A0008
113 /*
114  * definitions for Q8_ASIC_RESET
115  */
116 #define ASIC_RESET_RST_XDMA		0x00800000 /* Reset XDMA */
117 #define ASIC_RESET_PEG_ICACHE		0x00000020 /* Reset PEG_ICACHE */
118 #define ASIC_RESET_PEG_DCACHE		0x00000010 /* Reset PEG_DCACHE */
119 #define ASIC_RESET_PEG_3		0x00000008 /* Reset PEG_3 */
120 #define ASIC_RESET_PEG_2		0x00000004 /* Reset PEG_2 */
121 #define ASIC_RESET_PEG_1		0x00000002 /* Reset PEG_1 */
122 #define ASIC_RESET_PEG_0		0x00000001 /* Reset PEG_0 */
123 
124 #define Q8_COLD_BOOT			0x1B21FC
125 /*
126  * definitions for Q8_COLD_BOOT
127  */
128 #define COLD_BOOT_VALUE		0x12345678
129 
130 
131 #define Q8_MIU_TEST_AGT_CTRL		0x180090
132 #define Q8_MIU_TEST_AGT_ADDR_LO		0x180094
133 #define Q8_MIU_TEST_AGT_ADDR_HI		0x180098
134 #define Q8_MIU_TEST_AGT_WRDATA_LO	0x1800A0
135 #define Q8_MIU_TEST_AGT_WRDATA_HI	0x1800A4
136 #define Q8_MIU_TEST_AGT_RDDATA_LO	0x1800A8
137 #define Q8_MIU_TEST_AGT_RDDATA_HI	0x1800AC
138 #define Q8_MIU_TEST_AGT_WRDATA_ULO	0x1800B0
139 #define Q8_MIU_TEST_AGT_WRDATA_UHI	0x1800B4
140 #define Q8_MIU_TEST_AGT_RDDATA_ULO	0x1800B8
141 #define Q8_MIU_TEST_AGT_RDDATA_UHI	0x1800BC
142 
143 #define Q8_PEG_0_RESET			0x160018
144 #define Q8_PEG_0_CLR1			0x160008
145 #define Q8_PEG_0_CLR2			0x16000C
146 #define Q8_PEG_1_CLR1			0x161008
147 #define Q8_PEG_1_CLR2			0x16100C
148 #define Q8_PEG_2_CLR1			0x162008
149 #define Q8_PEG_2_CLR2			0x16200C
150 #define Q8_PEG_3_CLR1			0x163008
151 #define Q8_PEG_3_CLR2			0x16300C
152 #define Q8_PEG_4_CLR1			0x164008
153 #define Q8_PEG_4_CLR2			0x16400C
154 #define Q8_PEG_D_RESET1			0x1650EC
155 #define Q8_PEG_D_RESET2			0x16504C
156 #define Q8_PEG_HALT_STATUS1		0x1B20A8
157 #define Q8_PEG_HALT_STATUS2		0x1B20AC
158 #define Q8_FIRMWARE_HEARTBEAT		0x1B20B0
159 #define Q8_PEG_I_RESET			0x16604C
160 
161 #define Q8_CRB_MAC_BLOCK_START		0x1B21C0
162 
163 /***************************************************
164  * Flash ROM Access Registers ( Indirect Registers )
165  ***************************************************/
166 
167 #define Q8_ROM_INSTR_OPCODE		0x03310004
168 /*
169  * bit definitions for Q8_ROM_INSTR_OPCODE
170  * 31:8 Reserved; Rest Below
171  */
172 #define ROM_OPCODE_WR_STATUS_REG	0x01
173 #define ROM_OPCODE_PROG_PAGE		0x02
174 #define ROM_OPCODE_RD_BYTE		0x03
175 #define ROM_OPCODE_WR_DISABLE		0x04
176 #define ROM_OPCODE_RD_STATUS_REG	0x05
177 #define ROM_OPCODE_WR_ENABLE		0x06
178 #define ROM_OPCODE_FAST_RD		0x0B
179 #define ROM_OPCODE_REL_DEEP_PWR_DWN	0xAB
180 #define ROM_OPCODE_BULK_ERASE		0xC7
181 #define ROM_OPCODE_DEEP_PWR_DWN		0xC9
182 #define ROM_OPCODE_SECTOR_ERASE		0xD8
183 
184 #define Q8_ROM_ADDRESS			0x03310008
185 /*
186  * bit definitions for Q8_ROM_ADDRESS
187  * 31:24 Reserved;
188  * 23:0  Physical ROM Address in bytes
189  */
190 
191 #define Q8_ROM_ADDR_BYTE_COUNT		0x03310010
192 /*
193  * bit definitions for Q8_ROM_ADDR_BYTE_COUNT
194  * 31:2 Reserved;
195  * 1:0  max address bytes for ROM Interface
196  */
197 
198 #define Q8_ROM_DUMMY_BYTE_COUNT		0x03310014
199 /*
200  * bit definitions for Q8_ROM_DUMMY_BYTE_COUNT
201  * 31:2 Reserved;
202  * 1:0 dummy bytes for ROM Instructions
203  */
204 
205 #define Q8_ROM_RD_DATA			0x03310018
206 #define Q8_ROM_WR_DATA                  0x0331000C
207 #define Q8_ROM_DIRECT_WINDOW            0x03310030
208 #define Q8_ROM_DIRECT_DATA_OFFSET       0x03310000
209 
210 
211 #define Q8_NX_CDRP_CMD_RSP		0x1B2218
212 #define Q8_NX_CDRP_ARG1			0x1B221C
213 #define Q8_NX_CDRP_ARG2			0x1B2220
214 #define Q8_NX_CDRP_ARG3			0x1B2224
215 #define Q8_NX_CDRP_SIGNATURE		0x1B2228
216 
217 #define Q8_LINK_STATE			0x1B2298
218 #define Q8_LINK_SPEED_0			0x1B22E8
219 /*
220  * Macros for reading and writing registers
221  */
222 
223 #if defined(__i386__) || defined(__amd64__)
224 #define Q8_MB()    __asm volatile("mfence" ::: "memory")
225 #define Q8_WMB()   __asm volatile("sfence" ::: "memory")
226 #define Q8_RMB()   __asm volatile("lfence" ::: "memory")
227 #else
228 #define Q8_MB()
229 #define Q8_WMB()
230 #define Q8_RMB()
231 #endif
232 
233 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
234 #define READ_OFFSET32(ha, off) READ_REG32(ha, off)
235 
236 #define WRITE_REG32(ha, reg, val) \
237 	{\
238 		bus_write_4((ha->pci_reg), reg, val);\
239 		bus_read_4((ha->pci_reg), reg);\
240 	}
241 
242 #define WRITE_REG32_MB(ha, reg, val) \
243 	{\
244 		Q8_WMB();\
245 		bus_write_4((ha->pci_reg), reg, val);\
246 	}
247 
248 #define WRITE_OFFSET32(ha, off, val)\
249 		{\
250 			bus_write_4((ha->pci_reg), off, val);\
251 			bus_read_4((ha->pci_reg), off);\
252 		}
253 
254 #endif /* #ifndef _QLA_REG_H_ */
255