1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011-2013 Qlogic Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 /* 31 * File: qla_def.h 32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 33 */ 34 35 #ifndef _QLA_DEF_H_ 36 #define _QLA_DEF_H_ 37 38 #define BIT_0 (0x1 << 0) 39 #define BIT_1 (0x1 << 1) 40 #define BIT_2 (0x1 << 2) 41 #define BIT_3 (0x1 << 3) 42 #define BIT_4 (0x1 << 4) 43 #define BIT_5 (0x1 << 5) 44 #define BIT_6 (0x1 << 6) 45 #define BIT_7 (0x1 << 7) 46 #define BIT_8 (0x1 << 8) 47 #define BIT_9 (0x1 << 9) 48 #define BIT_10 (0x1 << 10) 49 #define BIT_11 (0x1 << 11) 50 #define BIT_12 (0x1 << 12) 51 #define BIT_13 (0x1 << 13) 52 #define BIT_14 (0x1 << 14) 53 #define BIT_15 (0x1 << 15) 54 #define BIT_16 (0x1 << 16) 55 #define BIT_17 (0x1 << 17) 56 #define BIT_18 (0x1 << 18) 57 #define BIT_19 (0x1 << 19) 58 #define BIT_20 (0x1 << 20) 59 #define BIT_21 (0x1 << 21) 60 #define BIT_22 (0x1 << 22) 61 #define BIT_23 (0x1 << 23) 62 #define BIT_24 (0x1 << 24) 63 #define BIT_25 (0x1 << 25) 64 #define BIT_26 (0x1 << 26) 65 #define BIT_27 (0x1 << 27) 66 #define BIT_28 (0x1 << 28) 67 #define BIT_29 (0x1 << 29) 68 #define BIT_30 (0x1 << 30) 69 #define BIT_31 (0x1 << 31) 70 71 struct qla_rx_buf { 72 struct mbuf *m_head; 73 bus_dmamap_t map; 74 bus_addr_t paddr; 75 uint32_t handle; 76 void *next; 77 }; 78 typedef struct qla_rx_buf qla_rx_buf_t; 79 80 struct qla_tx_buf { 81 struct mbuf *m_head; 82 bus_dmamap_t map; 83 }; 84 typedef struct qla_tx_buf qla_tx_buf_t; 85 86 #define QLA_MAX_SEGMENTS 63 /* maximum # of segs in a sg list */ 87 #define QLA_MAX_FRAME_SIZE MJUM9BYTES 88 #define QLA_STD_FRAME_SIZE 1514 89 #define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22) 90 91 /* Number of MSIX/MSI Vectors required */ 92 #define Q8_MSI_COUNT 4 93 94 struct qla_ivec { 95 struct resource *irq; 96 void *handle; 97 int irq_rid; 98 void *ha; 99 struct task rcv_task; 100 struct taskqueue *rcv_tq; 101 }; 102 103 typedef struct qla_ivec qla_ivec_t; 104 105 #define QLA_WATCHDOG_CALLOUT_TICKS 1 106 107 /* 108 * Adapter structure contains the hardware independent information of the 109 * pci function. 110 */ 111 struct qla_host { 112 volatile struct { 113 volatile uint32_t 114 qla_watchdog_active :1, 115 qla_watchdog_exit :1, 116 qla_watchdog_pause :1, 117 lro_init :1, 118 stop_rcv :1, 119 link_up :1, 120 parent_tag :1, 121 lock_init :1; 122 } flags; 123 124 device_t pci_dev; 125 126 uint8_t pci_func; 127 uint16_t watchdog_ticks; 128 uint8_t resvd; 129 130 /* ioctl related */ 131 struct cdev *ioctl_dev; 132 133 /* register mapping */ 134 struct resource *pci_reg; 135 int reg_rid; 136 137 /* interrupts */ 138 struct resource *irq; 139 int msix_count; 140 void *intr_handle; 141 qla_ivec_t irq_vec[Q8_MSI_COUNT]; 142 143 /* parent dma tag */ 144 bus_dma_tag_t parent_tag; 145 146 /* interface to o.s */ 147 if_t ifp; 148 149 struct ifmedia media; 150 uint16_t max_frame_size; 151 uint16_t rsrvd0; 152 int if_flags; 153 154 /* hardware access lock */ 155 struct mtx hw_lock; 156 volatile uint32_t hw_lock_held; 157 158 /* transmit and receive buffers */ 159 qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS]; 160 bus_dma_tag_t tx_tag; 161 struct mtx tx_lock; 162 struct task tx_task; 163 struct taskqueue *tx_tq; 164 struct callout tx_callout; 165 166 qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS]; 167 qla_rx_buf_t rx_jbuf[NUM_RX_JUMBO_DESCRIPTORS]; 168 bus_dma_tag_t rx_tag; 169 170 struct mtx rx_lock; 171 struct mtx rxj_lock; 172 173 /* stats */ 174 uint32_t err_m_getcl; 175 uint32_t err_m_getjcl; 176 uint32_t err_tx_dmamap_create; 177 uint32_t err_tx_dmamap_load; 178 uint32_t err_tx_defrag; 179 180 uint64_t rx_frames; 181 uint64_t rx_bytes; 182 183 uint64_t tx_frames; 184 uint64_t tx_bytes; 185 186 uint32_t fw_ver_major; 187 uint32_t fw_ver_minor; 188 uint32_t fw_ver_sub; 189 uint32_t fw_ver_build; 190 191 /* hardware specific */ 192 qla_hw_t hw; 193 194 /* debug stuff */ 195 volatile const char *qla_lock; 196 volatile const char *qla_unlock; 197 198 uint8_t fw_ver_str[32]; 199 }; 200 typedef struct qla_host qla_host_t; 201 202 /* note that align has to be a power of 2 */ 203 #define QL_ALIGN(size, align) (((size) + ((align) - 1)) & (~((align) - 1))) 204 #define QL_MIN(x, y) ((x < y) ? x : y) 205 206 #define QL_RUNNING(ifp) \ 207 ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \ 208 IFF_DRV_RUNNING) 209 210 #endif /* #ifndef _QLA_DEF_H_ */ 211