1 /* 2 * Copyright (c) 2018-2019 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef __QLNXR_USER_H__ 30 #define __QLNXR_USER_H__ 31 32 #define QLNXR_ABI_VERSION (7) 33 #define QLNXR_BE_ROCE_ABI_VERSION (1) 34 35 /* user kernel communication data structures. */ 36 37 struct qlnxr_alloc_ucontext_resp { 38 u64 db_pa; 39 u32 db_size; 40 41 uint32_t max_send_wr; 42 uint32_t max_recv_wr; 43 uint32_t max_srq_wr; 44 uint32_t sges_per_send_wr; 45 uint32_t sges_per_recv_wr; 46 uint32_t sges_per_srq_wr; 47 int max_cqes; 48 uint8_t dpm_enabled; 49 uint8_t wids_enabled; 50 uint16_t wid_count; 51 }; 52 53 struct qlnxr_alloc_pd_ureq { 54 u64 rsvd1; 55 }; 56 57 struct qlnxr_alloc_pd_uresp { 58 u32 pd_id; 59 }; 60 61 struct qlnxr_create_cq_ureq { 62 uint64_t addr; /* user space virtual address of CQ buffer */ 63 size_t len; /* size of CQ buffer */ 64 }; 65 66 struct qlnxr_create_cq_uresp { 67 u32 db_offset; 68 u16 icid; 69 }; 70 71 struct qlnxr_create_qp_ureq { 72 u32 qp_handle_hi; 73 u32 qp_handle_lo; 74 75 /* SQ */ 76 uint64_t sq_addr; /* user space virtual address of SQ buffer */ 77 size_t sq_len; /* length of SQ buffer */ 78 79 /* RQ */ 80 uint64_t rq_addr; /* user space virtual address of RQ buffer */ 81 size_t rq_len; /* length of RQ buffer */ 82 }; 83 84 struct qlnxr_create_qp_uresp { 85 u32 qp_id; 86 int atomic_supported; 87 88 /* SQ*/ 89 u32 sq_db_offset; 90 u16 sq_icid; 91 92 /* RQ */ 93 u32 rq_db_offset; 94 u16 rq_icid; 95 96 u32 rq_db2_offset; 97 }; 98 99 struct qlnxr_create_srq_ureq { 100 /* user space virtual address of producer pair */ 101 uint64_t prod_pair_addr; 102 uint64_t srq_addr; /* user space virtual address of SQ buffer */ 103 size_t srq_len; /* length of SQ buffer */ 104 }; 105 106 struct qlnxr_create_srq_uresp { 107 u16 srq_id; 108 }; 109 110 #endif /* #ifndef __QLNXR_USER_H__ */ 111