1 /* 2 * Copyright (c) 2018-2019 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __QLNXR_ROCE_H__ 32 #define __QLNXR_ROCE_H__ 33 34 35 /* 36 * roce completion notification queue element 37 */ 38 struct roce_cnqe { 39 struct regpair cq_handle; 40 }; 41 42 43 struct roce_cqe_responder { 44 struct regpair srq_wr_id; 45 struct regpair qp_handle; 46 __le32 imm_data_or_inv_r_Key; 47 __le32 length; 48 __le32 reserved0; 49 __le16 rq_cons; 50 u8 flags; 51 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1 52 #define ROCE_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0 53 #define ROCE_CQE_RESPONDER_TYPE_MASK 0x3 54 #define ROCE_CQE_RESPONDER_TYPE_SHIFT 1 55 #define ROCE_CQE_RESPONDER_INV_FLG_MASK 0x1 56 #define ROCE_CQE_RESPONDER_INV_FLG_SHIFT 3 57 #define ROCE_CQE_RESPONDER_IMM_FLG_MASK 0x1 58 #define ROCE_CQE_RESPONDER_IMM_FLG_SHIFT 4 59 #define ROCE_CQE_RESPONDER_RDMA_FLG_MASK 0x1 60 #define ROCE_CQE_RESPONDER_RDMA_FLG_SHIFT 5 61 #define ROCE_CQE_RESPONDER_RESERVED2_MASK 0x3 62 #define ROCE_CQE_RESPONDER_RESERVED2_SHIFT 6 63 u8 status; 64 }; 65 66 struct roce_cqe_requester { 67 __le16 sq_cons; 68 __le16 reserved0; 69 __le32 reserved1; 70 struct regpair qp_handle; 71 struct regpair reserved2; 72 __le32 reserved3; 73 __le16 reserved4; 74 u8 flags; 75 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1 76 #define ROCE_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0 77 #define ROCE_CQE_REQUESTER_TYPE_MASK 0x3 78 #define ROCE_CQE_REQUESTER_TYPE_SHIFT 1 79 #define ROCE_CQE_REQUESTER_RESERVED5_MASK 0x1F 80 #define ROCE_CQE_REQUESTER_RESERVED5_SHIFT 3 81 u8 status; 82 }; 83 84 struct roce_cqe_common { 85 struct regpair reserved0; 86 struct regpair qp_handle; 87 __le16 reserved1[7]; 88 u8 flags; 89 #define ROCE_CQE_COMMON_TOGGLE_BIT_MASK 0x1 90 #define ROCE_CQE_COMMON_TOGGLE_BIT_SHIFT 0 91 #define ROCE_CQE_COMMON_TYPE_MASK 0x3 92 #define ROCE_CQE_COMMON_TYPE_SHIFT 1 93 #define ROCE_CQE_COMMON_RESERVED2_MASK 0x1F 94 #define ROCE_CQE_COMMON_RESERVED2_SHIFT 3 95 u8 status; 96 }; 97 98 /* 99 * roce completion queue element 100 */ 101 union roce_cqe { 102 struct roce_cqe_responder resp; 103 struct roce_cqe_requester req; 104 struct roce_cqe_common cmn; 105 }; 106 107 108 109 110 /* 111 * CQE requester status enumeration 112 */ 113 enum roce_cqe_requester_status_enum { 114 ROCE_CQE_REQ_STS_OK, 115 ROCE_CQE_REQ_STS_BAD_RESPONSE_ERR, 116 ROCE_CQE_REQ_STS_LOCAL_LENGTH_ERR, 117 ROCE_CQE_REQ_STS_LOCAL_QP_OPERATION_ERR, 118 ROCE_CQE_REQ_STS_LOCAL_PROTECTION_ERR, 119 ROCE_CQE_REQ_STS_MEMORY_MGT_OPERATION_ERR, 120 ROCE_CQE_REQ_STS_REMOTE_INVALID_REQUEST_ERR, 121 ROCE_CQE_REQ_STS_REMOTE_ACCESS_ERR, 122 ROCE_CQE_REQ_STS_REMOTE_OPERATION_ERR, 123 ROCE_CQE_REQ_STS_RNR_NAK_RETRY_CNT_ERR, 124 ROCE_CQE_REQ_STS_TRANSPORT_RETRY_CNT_ERR, 125 ROCE_CQE_REQ_STS_WORK_REQUEST_FLUSHED_ERR, 126 MAX_ROCE_CQE_REQUESTER_STATUS_ENUM 127 }; 128 129 130 131 /* 132 * CQE responder status enumeration 133 */ 134 enum roce_cqe_responder_status_enum { 135 ROCE_CQE_RESP_STS_OK, 136 ROCE_CQE_RESP_STS_LOCAL_ACCESS_ERR, 137 ROCE_CQE_RESP_STS_LOCAL_LENGTH_ERR, 138 ROCE_CQE_RESP_STS_LOCAL_QP_OPERATION_ERR, 139 ROCE_CQE_RESP_STS_LOCAL_PROTECTION_ERR, 140 ROCE_CQE_RESP_STS_MEMORY_MGT_OPERATION_ERR, 141 ROCE_CQE_RESP_STS_REMOTE_INVALID_REQUEST_ERR, 142 ROCE_CQE_RESP_STS_WORK_REQUEST_FLUSHED_ERR, 143 MAX_ROCE_CQE_RESPONDER_STATUS_ENUM 144 }; 145 146 147 /* 148 * CQE type enumeration 149 */ 150 enum roce_cqe_type { 151 ROCE_CQE_TYPE_REQUESTER, 152 ROCE_CQE_TYPE_RESPONDER_RQ, 153 ROCE_CQE_TYPE_RESPONDER_SRQ, 154 ROCE_CQE_TYPE_INVALID, 155 MAX_ROCE_CQE_TYPE 156 }; 157 158 159 /* 160 * memory window type enumeration 161 */ 162 enum roce_mw_type { 163 ROCE_MW_TYPE_1, 164 ROCE_MW_TYPE_2A, 165 MAX_ROCE_MW_TYPE 166 }; 167 168 169 struct roce_rq_sge { 170 struct regpair addr; 171 __le32 length; 172 __le32 flags; 173 #define ROCE_RQ_SGE_L_KEY_MASK 0x3FFFFFF 174 #define ROCE_RQ_SGE_L_KEY_SHIFT 0 175 #define ROCE_RQ_SGE_NUM_SGES_MASK 0x7 176 #define ROCE_RQ_SGE_NUM_SGES_SHIFT 26 177 #define ROCE_RQ_SGE_RESERVED0_MASK 0x7 178 #define ROCE_RQ_SGE_RESERVED0_SHIFT 29 179 }; 180 181 182 struct roce_sq_atomic_wqe { 183 struct regpair remote_va; 184 __le32 xrc_srq; 185 u8 req_type; 186 u8 flags; 187 #define ROCE_SQ_ATOMIC_WQE_COMP_FLG_MASK 0x1 188 #define ROCE_SQ_ATOMIC_WQE_COMP_FLG_SHIFT 0 189 #define ROCE_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK 0x1 190 #define ROCE_SQ_ATOMIC_WQE_RD_FENCE_FLG_SHIFT 1 191 #define ROCE_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK 0x1 192 #define ROCE_SQ_ATOMIC_WQE_INV_FENCE_FLG_SHIFT 2 193 #define ROCE_SQ_ATOMIC_WQE_SE_FLG_MASK 0x1 194 #define ROCE_SQ_ATOMIC_WQE_SE_FLG_SHIFT 3 195 #define ROCE_SQ_ATOMIC_WQE_INLINE_FLG_MASK 0x1 196 #define ROCE_SQ_ATOMIC_WQE_INLINE_FLG_SHIFT 4 197 #define ROCE_SQ_ATOMIC_WQE_RESERVED0_MASK 0x7 198 #define ROCE_SQ_ATOMIC_WQE_RESERVED0_SHIFT 5 199 u8 reserved1; 200 u8 prev_wqe_size; 201 struct regpair swap_data; 202 __le32 r_key; 203 __le32 reserved2; 204 struct regpair cmp_data; 205 struct regpair reserved3; 206 }; 207 208 209 /* 210 * First element (16 bytes) of atomic wqe 211 */ 212 struct roce_sq_atomic_wqe_1st { 213 struct regpair remote_va; 214 __le32 xrc_srq; 215 u8 req_type; 216 u8 flags; 217 #define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK 0x1 218 #define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT 0 219 #define ROCE_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK 0x1 220 #define ROCE_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_SHIFT 1 221 #define ROCE_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK 0x1 222 #define ROCE_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_SHIFT 2 223 #define ROCE_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK 0x1 224 #define ROCE_SQ_ATOMIC_WQE_1ST_SE_FLG_SHIFT 3 225 #define ROCE_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK 0x1 226 #define ROCE_SQ_ATOMIC_WQE_1ST_INLINE_FLG_SHIFT 4 227 #define ROCE_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK 0x7 228 #define ROCE_SQ_ATOMIC_WQE_1ST_RESERVED0_SHIFT 5 229 u8 reserved1; 230 u8 prev_wqe_size; 231 }; 232 233 234 /* 235 * Second element (16 bytes) of atomic wqe 236 */ 237 struct roce_sq_atomic_wqe_2nd { 238 struct regpair swap_data; 239 __le32 r_key; 240 __le32 reserved2; 241 }; 242 243 244 /* 245 * Third element (16 bytes) of atomic wqe 246 */ 247 struct roce_sq_atomic_wqe_3rd { 248 struct regpair cmp_data; 249 struct regpair reserved3; 250 }; 251 252 253 struct roce_sq_bind_wqe { 254 struct regpair addr; 255 __le32 l_key; 256 u8 req_type; 257 u8 flags; 258 #define ROCE_SQ_BIND_WQE_COMP_FLG_MASK 0x1 259 #define ROCE_SQ_BIND_WQE_COMP_FLG_SHIFT 0 260 #define ROCE_SQ_BIND_WQE_RD_FENCE_FLG_MASK 0x1 261 #define ROCE_SQ_BIND_WQE_RD_FENCE_FLG_SHIFT 1 262 #define ROCE_SQ_BIND_WQE_INV_FENCE_FLG_MASK 0x1 263 #define ROCE_SQ_BIND_WQE_INV_FENCE_FLG_SHIFT 2 264 #define ROCE_SQ_BIND_WQE_SE_FLG_MASK 0x1 265 #define ROCE_SQ_BIND_WQE_SE_FLG_SHIFT 3 266 #define ROCE_SQ_BIND_WQE_INLINE_FLG_MASK 0x1 267 #define ROCE_SQ_BIND_WQE_INLINE_FLG_SHIFT 4 268 #define ROCE_SQ_BIND_WQE_RESERVED0_MASK 0x7 269 #define ROCE_SQ_BIND_WQE_RESERVED0_SHIFT 5 270 u8 access_ctrl; 271 #define ROCE_SQ_BIND_WQE_REMOTE_READ_MASK 0x1 272 #define ROCE_SQ_BIND_WQE_REMOTE_READ_SHIFT 0 273 #define ROCE_SQ_BIND_WQE_REMOTE_WRITE_MASK 0x1 274 #define ROCE_SQ_BIND_WQE_REMOTE_WRITE_SHIFT 1 275 #define ROCE_SQ_BIND_WQE_ENABLE_ATOMIC_MASK 0x1 276 #define ROCE_SQ_BIND_WQE_ENABLE_ATOMIC_SHIFT 2 277 #define ROCE_SQ_BIND_WQE_LOCAL_READ_MASK 0x1 278 #define ROCE_SQ_BIND_WQE_LOCAL_READ_SHIFT 3 279 #define ROCE_SQ_BIND_WQE_LOCAL_WRITE_MASK 0x1 280 #define ROCE_SQ_BIND_WQE_LOCAL_WRITE_SHIFT 4 281 #define ROCE_SQ_BIND_WQE_RESERVED1_MASK 0x7 282 #define ROCE_SQ_BIND_WQE_RESERVED1_SHIFT 5 283 u8 prev_wqe_size; 284 u8 bind_ctrl; 285 #define ROCE_SQ_BIND_WQE_ZERO_BASED_MASK 0x1 286 #define ROCE_SQ_BIND_WQE_ZERO_BASED_SHIFT 0 287 #define ROCE_SQ_BIND_WQE_MW_TYPE_MASK 0x1 288 #define ROCE_SQ_BIND_WQE_MW_TYPE_SHIFT 1 289 #define ROCE_SQ_BIND_WQE_RESERVED2_MASK 0x3F 290 #define ROCE_SQ_BIND_WQE_RESERVED2_SHIFT 2 291 u8 reserved3[2]; 292 u8 length_hi; 293 __le32 length_lo; 294 __le32 parent_l_key; 295 __le32 reserved6; 296 }; 297 298 299 /* 300 * First element (16 bytes) of bind wqe 301 */ 302 struct roce_sq_bind_wqe_1st { 303 struct regpair addr; 304 __le32 l_key; 305 u8 req_type; 306 u8 flags; 307 #define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_MASK 0x1 308 #define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT 0 309 #define ROCE_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK 0x1 310 #define ROCE_SQ_BIND_WQE_1ST_RD_FENCE_FLG_SHIFT 1 311 #define ROCE_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK 0x1 312 #define ROCE_SQ_BIND_WQE_1ST_INV_FENCE_FLG_SHIFT 2 313 #define ROCE_SQ_BIND_WQE_1ST_SE_FLG_MASK 0x1 314 #define ROCE_SQ_BIND_WQE_1ST_SE_FLG_SHIFT 3 315 #define ROCE_SQ_BIND_WQE_1ST_INLINE_FLG_MASK 0x1 316 #define ROCE_SQ_BIND_WQE_1ST_INLINE_FLG_SHIFT 4 317 #define ROCE_SQ_BIND_WQE_1ST_RESERVED0_MASK 0x7 318 #define ROCE_SQ_BIND_WQE_1ST_RESERVED0_SHIFT 5 319 u8 access_ctrl; 320 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_MASK 0x1 321 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_SHIFT 0 322 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_WRITE_MASK 0x1 323 #define ROCE_SQ_BIND_WQE_1ST_REMOTE_WRITE_SHIFT 1 324 #define ROCE_SQ_BIND_WQE_1ST_ENABLE_ATOMIC_MASK 0x1 325 #define ROCE_SQ_BIND_WQE_1ST_ENABLE_ATOMIC_SHIFT 2 326 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_READ_MASK 0x1 327 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_READ_SHIFT 3 328 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_WRITE_MASK 0x1 329 #define ROCE_SQ_BIND_WQE_1ST_LOCAL_WRITE_SHIFT 4 330 #define ROCE_SQ_BIND_WQE_1ST_RESERVED1_MASK 0x7 331 #define ROCE_SQ_BIND_WQE_1ST_RESERVED1_SHIFT 5 332 u8 prev_wqe_size; 333 }; 334 335 336 /* 337 * Second element (16 bytes) of bind wqe 338 */ 339 struct roce_sq_bind_wqe_2nd { 340 u8 bind_ctrl; 341 #define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_MASK 0x1 342 #define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT 0 343 #define ROCE_SQ_BIND_WQE_2ND_MW_TYPE_MASK 0x1 344 #define ROCE_SQ_BIND_WQE_2ND_MW_TYPE_SHIFT 1 345 #define ROCE_SQ_BIND_WQE_2ND_RESERVED2_MASK 0x3F 346 #define ROCE_SQ_BIND_WQE_2ND_RESERVED2_SHIFT 2 347 u8 reserved3[2]; 348 u8 length_hi; 349 __le32 length_lo; 350 __le32 parent_l_key; 351 __le32 reserved6; 352 }; 353 354 355 /* 356 * Structure with only the SQ WQE common fields. Size is of one SQ element (16B) 357 */ 358 struct roce_sq_common_wqe { 359 __le32 reserved1[3]; 360 u8 req_type; 361 u8 flags; 362 #define ROCE_SQ_COMMON_WQE_COMP_FLG_MASK 0x1 363 #define ROCE_SQ_COMMON_WQE_COMP_FLG_SHIFT 0 364 #define ROCE_SQ_COMMON_WQE_RD_FENCE_FLG_MASK 0x1 365 #define ROCE_SQ_COMMON_WQE_RD_FENCE_FLG_SHIFT 1 366 #define ROCE_SQ_COMMON_WQE_INV_FENCE_FLG_MASK 0x1 367 #define ROCE_SQ_COMMON_WQE_INV_FENCE_FLG_SHIFT 2 368 #define ROCE_SQ_COMMON_WQE_SE_FLG_MASK 0x1 369 #define ROCE_SQ_COMMON_WQE_SE_FLG_SHIFT 3 370 #define ROCE_SQ_COMMON_WQE_INLINE_FLG_MASK 0x1 371 #define ROCE_SQ_COMMON_WQE_INLINE_FLG_SHIFT 4 372 #define ROCE_SQ_COMMON_WQE_RESERVED0_MASK 0x7 373 #define ROCE_SQ_COMMON_WQE_RESERVED0_SHIFT 5 374 u8 reserved2; 375 u8 prev_wqe_size; 376 }; 377 378 379 struct roce_sq_fmr_wqe { 380 struct regpair addr; 381 __le32 l_key; 382 u8 req_type; 383 u8 flags; 384 #define ROCE_SQ_FMR_WQE_COMP_FLG_MASK 0x1 385 #define ROCE_SQ_FMR_WQE_COMP_FLG_SHIFT 0 386 #define ROCE_SQ_FMR_WQE_RD_FENCE_FLG_MASK 0x1 387 #define ROCE_SQ_FMR_WQE_RD_FENCE_FLG_SHIFT 1 388 #define ROCE_SQ_FMR_WQE_INV_FENCE_FLG_MASK 0x1 389 #define ROCE_SQ_FMR_WQE_INV_FENCE_FLG_SHIFT 2 390 #define ROCE_SQ_FMR_WQE_SE_FLG_MASK 0x1 391 #define ROCE_SQ_FMR_WQE_SE_FLG_SHIFT 3 392 #define ROCE_SQ_FMR_WQE_INLINE_FLG_MASK 0x1 393 #define ROCE_SQ_FMR_WQE_INLINE_FLG_SHIFT 4 394 #define ROCE_SQ_FMR_WQE_RESERVED0_MASK 0x7 395 #define ROCE_SQ_FMR_WQE_RESERVED0_SHIFT 5 396 u8 access_ctrl; 397 #define ROCE_SQ_FMR_WQE_REMOTE_READ_MASK 0x1 398 #define ROCE_SQ_FMR_WQE_REMOTE_READ_SHIFT 0 399 #define ROCE_SQ_FMR_WQE_REMOTE_WRITE_MASK 0x1 400 #define ROCE_SQ_FMR_WQE_REMOTE_WRITE_SHIFT 1 401 #define ROCE_SQ_FMR_WQE_ENABLE_ATOMIC_MASK 0x1 402 #define ROCE_SQ_FMR_WQE_ENABLE_ATOMIC_SHIFT 2 403 #define ROCE_SQ_FMR_WQE_LOCAL_READ_MASK 0x1 404 #define ROCE_SQ_FMR_WQE_LOCAL_READ_SHIFT 3 405 #define ROCE_SQ_FMR_WQE_LOCAL_WRITE_MASK 0x1 406 #define ROCE_SQ_FMR_WQE_LOCAL_WRITE_SHIFT 4 407 #define ROCE_SQ_FMR_WQE_RESERVED1_MASK 0x7 408 #define ROCE_SQ_FMR_WQE_RESERVED1_SHIFT 5 409 u8 prev_wqe_size; 410 u8 fmr_ctrl; 411 #define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK 0x1F 412 #define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT 0 413 #define ROCE_SQ_FMR_WQE_ZERO_BASED_MASK 0x1 414 #define ROCE_SQ_FMR_WQE_ZERO_BASED_SHIFT 5 415 #define ROCE_SQ_FMR_WQE_BIND_EN_MASK 0x1 416 #define ROCE_SQ_FMR_WQE_BIND_EN_SHIFT 6 417 #define ROCE_SQ_FMR_WQE_RESERVED2_MASK 0x1 418 #define ROCE_SQ_FMR_WQE_RESERVED2_SHIFT 7 419 u8 reserved3[2]; 420 u8 length_hi; 421 __le32 length_lo; 422 struct regpair pbl_addr; 423 }; 424 425 426 /* 427 * First element (16 bytes) of fmr wqe 428 */ 429 struct roce_sq_fmr_wqe_1st { 430 struct regpair addr; 431 __le32 l_key; 432 u8 req_type; 433 u8 flags; 434 #define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_MASK 0x1 435 #define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT 0 436 #define ROCE_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK 0x1 437 #define ROCE_SQ_FMR_WQE_1ST_RD_FENCE_FLG_SHIFT 1 438 #define ROCE_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK 0x1 439 #define ROCE_SQ_FMR_WQE_1ST_INV_FENCE_FLG_SHIFT 2 440 #define ROCE_SQ_FMR_WQE_1ST_SE_FLG_MASK 0x1 441 #define ROCE_SQ_FMR_WQE_1ST_SE_FLG_SHIFT 3 442 #define ROCE_SQ_FMR_WQE_1ST_INLINE_FLG_MASK 0x1 443 #define ROCE_SQ_FMR_WQE_1ST_INLINE_FLG_SHIFT 4 444 #define ROCE_SQ_FMR_WQE_1ST_RESERVED0_MASK 0x7 445 #define ROCE_SQ_FMR_WQE_1ST_RESERVED0_SHIFT 5 446 u8 access_ctrl; 447 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_MASK 0x1 448 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_SHIFT 0 449 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_WRITE_MASK 0x1 450 #define ROCE_SQ_FMR_WQE_1ST_REMOTE_WRITE_SHIFT 1 451 #define ROCE_SQ_FMR_WQE_1ST_ENABLE_ATOMIC_MASK 0x1 452 #define ROCE_SQ_FMR_WQE_1ST_ENABLE_ATOMIC_SHIFT 2 453 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_READ_MASK 0x1 454 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_READ_SHIFT 3 455 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_WRITE_MASK 0x1 456 #define ROCE_SQ_FMR_WQE_1ST_LOCAL_WRITE_SHIFT 4 457 #define ROCE_SQ_FMR_WQE_1ST_RESERVED1_MASK 0x7 458 #define ROCE_SQ_FMR_WQE_1ST_RESERVED1_SHIFT 5 459 u8 prev_wqe_size; 460 }; 461 462 463 /* 464 * Second element (16 bytes) of fmr wqe 465 */ 466 struct roce_sq_fmr_wqe_2nd { 467 u8 fmr_ctrl; 468 #define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK 0x1F 469 #define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT 0 470 #define ROCE_SQ_FMR_WQE_2ND_ZERO_BASED_MASK 0x1 471 #define ROCE_SQ_FMR_WQE_2ND_ZERO_BASED_SHIFT 5 472 #define ROCE_SQ_FMR_WQE_2ND_BIND_EN_MASK 0x1 473 #define ROCE_SQ_FMR_WQE_2ND_BIND_EN_SHIFT 6 474 #define ROCE_SQ_FMR_WQE_2ND_RESERVED2_MASK 0x1 475 #define ROCE_SQ_FMR_WQE_2ND_RESERVED2_SHIFT 7 476 u8 reserved3[2]; 477 u8 length_hi; 478 __le32 length_lo; 479 struct regpair pbl_addr; 480 }; 481 482 483 struct roce_sq_local_inv_wqe { 484 struct regpair reserved; 485 __le32 inv_l_key; 486 u8 req_type; 487 u8 flags; 488 #define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_MASK 0x1 489 #define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT 0 490 #define ROCE_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK 0x1 491 #define ROCE_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_SHIFT 1 492 #define ROCE_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK 0x1 493 #define ROCE_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_SHIFT 2 494 #define ROCE_SQ_LOCAL_INV_WQE_SE_FLG_MASK 0x1 495 #define ROCE_SQ_LOCAL_INV_WQE_SE_FLG_SHIFT 3 496 #define ROCE_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK 0x1 497 #define ROCE_SQ_LOCAL_INV_WQE_INLINE_FLG_SHIFT 4 498 #define ROCE_SQ_LOCAL_INV_WQE_RESERVED0_MASK 0x7 499 #define ROCE_SQ_LOCAL_INV_WQE_RESERVED0_SHIFT 5 500 u8 reserved1; 501 u8 prev_wqe_size; 502 }; 503 504 505 struct roce_sq_rdma_wqe { 506 __le32 imm_data; 507 __le32 length; 508 __le32 xrc_srq; 509 u8 req_type; 510 u8 flags; 511 #define ROCE_SQ_RDMA_WQE_COMP_FLG_MASK 0x1 512 #define ROCE_SQ_RDMA_WQE_COMP_FLG_SHIFT 0 513 #define ROCE_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1 514 #define ROCE_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT 1 515 #define ROCE_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1 516 #define ROCE_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT 2 517 #define ROCE_SQ_RDMA_WQE_SE_FLG_MASK 0x1 518 #define ROCE_SQ_RDMA_WQE_SE_FLG_SHIFT 3 519 #define ROCE_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1 520 #define ROCE_SQ_RDMA_WQE_INLINE_FLG_SHIFT 4 521 #define ROCE_SQ_RDMA_WQE_RESERVED0_MASK 0x7 522 #define ROCE_SQ_RDMA_WQE_RESERVED0_SHIFT 5 523 u8 wqe_size; 524 u8 prev_wqe_size; 525 struct regpair remote_va; 526 __le32 r_key; 527 __le32 reserved1; 528 }; 529 530 531 /* 532 * First element (16 bytes) of rdma wqe 533 */ 534 struct roce_sq_rdma_wqe_1st { 535 __le32 imm_data; 536 __le32 length; 537 __le32 xrc_srq; 538 u8 req_type; 539 u8 flags; 540 #define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_MASK 0x1 541 #define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT 0 542 #define ROCE_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK 0x1 543 #define ROCE_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_SHIFT 1 544 #define ROCE_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK 0x1 545 #define ROCE_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_SHIFT 2 546 #define ROCE_SQ_RDMA_WQE_1ST_SE_FLG_MASK 0x1 547 #define ROCE_SQ_RDMA_WQE_1ST_SE_FLG_SHIFT 3 548 #define ROCE_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK 0x1 549 #define ROCE_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT 4 550 #define ROCE_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x7 551 #define ROCE_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT 5 552 u8 wqe_size; 553 u8 prev_wqe_size; 554 }; 555 556 557 /* 558 * Second element (16 bytes) of rdma wqe 559 */ 560 struct roce_sq_rdma_wqe_2nd { 561 struct regpair remote_va; 562 __le32 r_key; 563 __le32 reserved1; 564 }; 565 566 567 /* 568 * SQ WQE req type enumeration 569 */ 570 enum roce_sq_req_type { 571 ROCE_SQ_REQ_TYPE_SEND, 572 ROCE_SQ_REQ_TYPE_SEND_WITH_IMM, 573 ROCE_SQ_REQ_TYPE_SEND_WITH_INVALIDATE, 574 ROCE_SQ_REQ_TYPE_RDMA_WR, 575 ROCE_SQ_REQ_TYPE_RDMA_WR_WITH_IMM, 576 ROCE_SQ_REQ_TYPE_RDMA_RD, 577 ROCE_SQ_REQ_TYPE_ATOMIC_CMP_AND_SWAP, 578 ROCE_SQ_REQ_TYPE_ATOMIC_ADD, 579 ROCE_SQ_REQ_TYPE_LOCAL_INVALIDATE, 580 ROCE_SQ_REQ_TYPE_FAST_MR, 581 ROCE_SQ_REQ_TYPE_BIND, 582 ROCE_SQ_REQ_TYPE_INVALID, 583 MAX_ROCE_SQ_REQ_TYPE 584 }; 585 586 587 struct roce_sq_send_wqe { 588 __le32 inv_key_or_imm_data; 589 __le32 length; 590 __le32 xrc_srq; 591 u8 req_type; 592 u8 flags; 593 #define ROCE_SQ_SEND_WQE_COMP_FLG_MASK 0x1 594 #define ROCE_SQ_SEND_WQE_COMP_FLG_SHIFT 0 595 #define ROCE_SQ_SEND_WQE_RD_FENCE_FLG_MASK 0x1 596 #define ROCE_SQ_SEND_WQE_RD_FENCE_FLG_SHIFT 1 597 #define ROCE_SQ_SEND_WQE_INV_FENCE_FLG_MASK 0x1 598 #define ROCE_SQ_SEND_WQE_INV_FENCE_FLG_SHIFT 2 599 #define ROCE_SQ_SEND_WQE_SE_FLG_MASK 0x1 600 #define ROCE_SQ_SEND_WQE_SE_FLG_SHIFT 3 601 #define ROCE_SQ_SEND_WQE_INLINE_FLG_MASK 0x1 602 #define ROCE_SQ_SEND_WQE_INLINE_FLG_SHIFT 4 603 #define ROCE_SQ_SEND_WQE_RESERVED0_MASK 0x7 604 #define ROCE_SQ_SEND_WQE_RESERVED0_SHIFT 5 605 u8 wqe_size; 606 u8 prev_wqe_size; 607 }; 608 609 610 struct roce_sq_sge { 611 __le32 length; 612 struct regpair addr; 613 __le32 l_key; 614 }; 615 616 617 struct roce_srq_prod { 618 __le16 prod; 619 }; 620 621 622 struct roce_srq_sge { 623 struct regpair addr; 624 __le32 length; 625 __le32 l_key; 626 struct regpair wr_id; 627 u8 flags; 628 #define ROCE_SRQ_SGE_NUM_SGES_MASK 0x3 629 #define ROCE_SRQ_SGE_NUM_SGES_SHIFT 0 630 #define ROCE_SRQ_SGE_RESERVED0_MASK 0x3F 631 #define ROCE_SRQ_SGE_RESERVED0_SHIFT 2 632 u8 reserved1; 633 __le16 reserved2; 634 __le32 reserved3; 635 }; 636 637 638 /* 639 * RoCE doorbell data for SQ and RQ 640 */ 641 struct roce_pwm_val16_data { 642 __le16 icid; 643 __le16 prod_val; 644 }; 645 646 647 union roce_pwm_val16_data_union { 648 struct roce_pwm_val16_data as_struct; 649 __le32 as_dword; 650 }; 651 652 653 /* 654 * RoCE doorbell data for CQ 655 */ 656 struct roce_pwm_val32_data { 657 __le16 icid; 658 u8 agg_flags; 659 u8 params; 660 #define ROCE_PWM_VAL32_DATA_AGG_CMD_MASK 0x3 661 #define ROCE_PWM_VAL32_DATA_AGG_CMD_SHIFT 0 662 #define ROCE_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1 663 #define ROCE_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2 664 #define ROCE_PWM_VAL32_DATA_RESERVED_MASK 0x1F 665 #define ROCE_PWM_VAL32_DATA_RESERVED_SHIFT 3 666 __le32 cq_cons_val; 667 }; 668 669 670 union roce_pwm_val32_data_union { 671 struct roce_pwm_val32_data as_struct; 672 struct regpair as_repair; 673 }; 674 675 #endif /* __QLNXR_ROCE_H__ */ 676