1 /* 2 * Copyright (c) 2018-2019 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 29 /* 30 * File: qlnxr_os.c 31 */ 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "qlnxr_def.h" 36 37 SYSCTL_NODE(_dev, OID_AUTO, qnxr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 38 "Qlogic RDMA module"); 39 40 uint32_t delayed_ack = 0; 41 SYSCTL_UINT(_dev_qnxr, OID_AUTO, delayed_ack, CTLFLAG_RW, &delayed_ack, 1, 42 "iWARP: Delayed Ack: 0 - Disabled 1 - Enabled. Default: Disabled"); 43 44 uint32_t timestamp = 1; 45 SYSCTL_UINT(_dev_qnxr, OID_AUTO, timestamp, CTLFLAG_RW, ×tamp, 1, 46 "iWARP: Timestamp: 0 - Disabled 1 - Enabled. Default:Enabled"); 47 48 uint32_t rcv_wnd_size = 0; 49 SYSCTL_UINT(_dev_qnxr, OID_AUTO, rcv_wnd_size, CTLFLAG_RW, &rcv_wnd_size, 1, 50 "iWARP: Receive Window Size in K. Default 1M"); 51 52 uint32_t crc_needed = 1; 53 SYSCTL_UINT(_dev_qnxr, OID_AUTO, crc_needed, CTLFLAG_RW, &crc_needed, 1, 54 "iWARP: CRC needed 0 - Disabled 1 - Enabled. Default:Enabled"); 55 56 uint32_t peer2peer = 1; 57 SYSCTL_UINT(_dev_qnxr, OID_AUTO, peer2peer, CTLFLAG_RW, &peer2peer, 1, 58 "iWARP: Support peer2peer ULPs 0 - Disabled 1 - Enabled. Default:Enabled"); 59 60 uint32_t mpa_enhanced = 1; 61 SYSCTL_UINT(_dev_qnxr, OID_AUTO, mpa_enhanced, CTLFLAG_RW, &mpa_enhanced, 1, 62 "iWARP: MPA Enhanced mode. Default:1"); 63 64 uint32_t rtr_type = 7; 65 SYSCTL_UINT(_dev_qnxr, OID_AUTO, rtr_type, CTLFLAG_RW, &rtr_type, 1, 66 "iWARP: RDMAP opcode to use for the RTR message: BITMAP 1: RDMA_SEND 2: RDMA_WRITE 4: RDMA_READ. Default: 7"); 67 68 69 #define QNXR_WQ_MULTIPLIER_MIN (1) 70 #define QNXR_WQ_MULTIPLIER_MAX (7) 71 #define QNXR_WQ_MULTIPLIER_DFT (3) 72 73 uint32_t wq_multiplier= QNXR_WQ_MULTIPLIER_DFT; 74 SYSCTL_UINT(_dev_qnxr, OID_AUTO, wq_multiplier, CTLFLAG_RW, &wq_multiplier, 1, 75 " When creating a WQ the actual number of WQE created will" 76 " be multiplied by this number (default is 3)."); 77 static ssize_t 78 show_rev(struct device *device, struct device_attribute *attr, 79 char *buf) 80 { 81 struct qlnxr_dev *dev = dev_get_drvdata(device); 82 83 return sprintf(buf, "0x%x\n", dev->cdev->vendor_id); 84 } 85 86 static ssize_t 87 show_hca_type(struct device *device, 88 struct device_attribute *attr, char *buf) 89 { 90 struct qlnxr_dev *dev = dev_get_drvdata(device); 91 return sprintf(buf, "QLogic0x%x\n", dev->cdev->device_id); 92 } 93 94 static ssize_t 95 show_fw_ver(struct device *device, 96 struct device_attribute *attr, char *buf) 97 { 98 struct qlnxr_dev *dev = dev_get_drvdata(device); 99 uint32_t fw_ver = (uint32_t) dev->attr.fw_ver; 100 101 return sprintf(buf, "%d.%d.%d\n", 102 (fw_ver >> 24) & 0xff, (fw_ver >> 16) & 0xff, 103 (fw_ver >> 8) & 0xff); 104 } 105 static ssize_t 106 show_board(struct device *device, 107 struct device_attribute *attr, char *buf) 108 { 109 struct qlnxr_dev *dev = dev_get_drvdata(device); 110 return sprintf(buf, "%x\n", dev->cdev->device_id); 111 } 112 113 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 114 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca_type, NULL); 115 static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL); 116 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 117 118 static struct device_attribute *qlnxr_class_attributes[] = { 119 &dev_attr_hw_rev, 120 &dev_attr_hca_type, 121 &dev_attr_fw_ver, 122 &dev_attr_board_id 123 }; 124 125 static void 126 qlnxr_ib_dispatch_event(qlnxr_dev_t *dev, uint8_t port_num, 127 enum ib_event_type type) 128 { 129 struct ib_event ibev; 130 131 QL_DPRINT12(dev->ha, "enter\n"); 132 133 ibev.device = &dev->ibdev; 134 ibev.element.port_num = port_num; 135 ibev.event = type; 136 137 ib_dispatch_event(&ibev); 138 139 QL_DPRINT12(dev->ha, "exit\n"); 140 } 141 142 static int 143 __qlnxr_iw_destroy_listen(struct iw_cm_id *cm_id) 144 { 145 qlnxr_iw_destroy_listen(cm_id); 146 147 return (0); 148 } 149 150 static int 151 qlnxr_register_device(qlnxr_dev_t *dev) 152 { 153 struct ib_device *ibdev; 154 struct iw_cm_verbs *iwcm; 155 int ret; 156 157 QL_DPRINT12(dev->ha, "enter\n"); 158 159 ibdev = &dev->ibdev; 160 161 strlcpy(ibdev->name, "qlnxr%d", IB_DEVICE_NAME_MAX); 162 163 memset(&ibdev->node_guid, 0, sizeof(ibdev->node_guid)); 164 memcpy(&ibdev->node_guid, dev->ha->primary_mac, ETHER_ADDR_LEN); 165 166 memcpy(ibdev->node_desc, QLNXR_NODE_DESC, sizeof(QLNXR_NODE_DESC)); 167 168 ibdev->owner = THIS_MODULE; 169 ibdev->uverbs_abi_ver = 7; 170 ibdev->local_dma_lkey = 0; 171 172 ibdev->uverbs_cmd_mask = 173 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 174 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 175 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 176 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 177 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 178 (1ull << IB_USER_VERBS_CMD_REG_MR) | 179 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 180 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 181 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 182 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 183 (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) | 184 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 185 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 186 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 187 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 188 (1ull << IB_USER_VERBS_CMD_POLL_CQ) | 189 (1ull << IB_USER_VERBS_CMD_POST_SEND) | 190 (1ull << IB_USER_VERBS_CMD_POST_RECV); 191 192 if (QLNX_IS_IWARP(dev)) { 193 ibdev->node_type = RDMA_NODE_RNIC; 194 ibdev->query_gid = qlnxr_iw_query_gid; 195 } else { 196 ibdev->node_type = RDMA_NODE_IB_CA; 197 ibdev->query_gid = qlnxr_query_gid; 198 ibdev->uverbs_cmd_mask |= 199 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 200 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 201 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 202 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 203 (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV); 204 ibdev->create_srq = qlnxr_create_srq; 205 ibdev->destroy_srq = qlnxr_destroy_srq; 206 ibdev->modify_srq = qlnxr_modify_srq; 207 ibdev->query_srq = qlnxr_query_srq; 208 ibdev->post_srq_recv = qlnxr_post_srq_recv; 209 } 210 211 ibdev->phys_port_cnt = 1; 212 ibdev->num_comp_vectors = dev->num_cnq; 213 214 /* mandatory verbs. */ 215 ibdev->query_device = qlnxr_query_device; 216 ibdev->query_port = qlnxr_query_port; 217 ibdev->modify_port = qlnxr_modify_port; 218 219 ibdev->alloc_ucontext = qlnxr_alloc_ucontext; 220 ibdev->dealloc_ucontext = qlnxr_dealloc_ucontext; 221 /* mandatory to support user space verbs consumer. */ 222 ibdev->mmap = qlnxr_mmap; 223 224 ibdev->alloc_pd = qlnxr_alloc_pd; 225 ibdev->dealloc_pd = qlnxr_dealloc_pd; 226 227 ibdev->create_cq = qlnxr_create_cq; 228 ibdev->destroy_cq = qlnxr_destroy_cq; 229 ibdev->resize_cq = qlnxr_resize_cq; 230 ibdev->req_notify_cq = qlnxr_arm_cq; 231 232 ibdev->create_qp = qlnxr_create_qp; 233 ibdev->modify_qp = qlnxr_modify_qp; 234 ibdev->query_qp = qlnxr_query_qp; 235 ibdev->destroy_qp = qlnxr_destroy_qp; 236 237 ibdev->query_pkey = qlnxr_query_pkey; 238 ibdev->create_ah = qlnxr_create_ah; 239 ibdev->destroy_ah = qlnxr_destroy_ah; 240 ibdev->query_ah = qlnxr_query_ah; 241 ibdev->modify_ah = qlnxr_modify_ah; 242 ibdev->get_dma_mr = qlnxr_get_dma_mr; 243 ibdev->dereg_mr = qlnxr_dereg_mr; 244 ibdev->reg_user_mr = qlnxr_reg_user_mr; 245 246 #if __FreeBSD_version >= 1102000 247 ibdev->alloc_mr = qlnxr_alloc_mr; 248 ibdev->map_mr_sg = qlnxr_map_mr_sg; 249 ibdev->get_port_immutable = qlnxr_get_port_immutable; 250 #else 251 ibdev->reg_phys_mr = qlnxr_reg_kernel_mr; 252 ibdev->alloc_fast_reg_mr = qlnxr_alloc_frmr; 253 ibdev->alloc_fast_reg_page_list = qlnxr_alloc_frmr_page_list; 254 ibdev->free_fast_reg_page_list = qlnxr_free_frmr_page_list; 255 #endif /* #if __FreeBSD_version >= 1102000 */ 256 257 ibdev->poll_cq = qlnxr_poll_cq; 258 ibdev->post_send = qlnxr_post_send; 259 ibdev->post_recv = qlnxr_post_recv; 260 ibdev->process_mad = qlnxr_process_mad; 261 262 263 264 ibdev->dma_device = &dev->pdev->dev; 265 266 ibdev->get_link_layer = qlnxr_link_layer; 267 268 if (QLNX_IS_IWARP(dev)) { 269 iwcm = kmalloc(sizeof(*iwcm), GFP_KERNEL); 270 271 device_printf(dev->ha->pci_dev, "device is IWARP\n"); 272 if (iwcm == NULL) 273 return (-ENOMEM); 274 275 ibdev->iwcm = iwcm; 276 277 iwcm->connect = qlnxr_iw_connect; 278 iwcm->accept = qlnxr_iw_accept; 279 iwcm->reject = qlnxr_iw_reject; 280 281 #if (__FreeBSD_version >= 1004000) && (__FreeBSD_version < 1102000) 282 283 iwcm->create_listen_ep = qlnxr_iw_create_listen; 284 iwcm->destroy_listen_ep = qlnxr_iw_destroy_listen; 285 #else 286 iwcm->create_listen = qlnxr_iw_create_listen; 287 iwcm->destroy_listen = __qlnxr_iw_destroy_listen; 288 #endif 289 iwcm->add_ref = qlnxr_iw_qp_add_ref; 290 iwcm->rem_ref = qlnxr_iw_qp_rem_ref; 291 iwcm->get_qp = qlnxr_iw_get_qp; 292 } 293 294 ret = ib_register_device(ibdev, NULL); 295 if (ret) { 296 kfree(iwcm); 297 } 298 299 QL_DPRINT12(dev->ha, "exit\n"); 300 return ret; 301 } 302 303 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 304 305 static void 306 qlnxr_intr(void *handle) 307 { 308 struct qlnxr_cnq *cnq = handle; 309 struct qlnxr_cq *cq; 310 struct regpair *cq_handle; 311 u16 hw_comp_cons, sw_comp_cons; 312 qlnx_host_t *ha; 313 314 ha = cnq->dev->ha; 315 316 QL_DPRINT12(ha, "enter cnq = %p\n", handle); 317 318 ecore_sb_ack(cnq->sb, IGU_INT_DISABLE, 0 /*do not update*/); 319 320 ecore_sb_update_sb_idx(cnq->sb); 321 322 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr); 323 sw_comp_cons = ecore_chain_get_cons_idx(&cnq->pbl); 324 325 rmb(); 326 327 QL_DPRINT12(ha, "enter cnq = %p hw_comp_cons = 0x%x sw_comp_cons = 0x%x\n", 328 handle, hw_comp_cons, sw_comp_cons); 329 330 while (sw_comp_cons != hw_comp_cons) { 331 cq_handle = (struct regpair *)ecore_chain_consume(&cnq->pbl); 332 cq = (struct qlnxr_cq *)(uintptr_t)HILO_U64(cq_handle->hi, 333 cq_handle->lo); 334 335 if (cq == NULL) { 336 QL_DPRINT11(ha, "cq == NULL\n"); 337 break; 338 } 339 340 if (cq->sig != QLNXR_CQ_MAGIC_NUMBER) { 341 QL_DPRINT11(ha, 342 "cq->sig = 0x%x QLNXR_CQ_MAGIC_NUMBER = 0x%x\n", 343 cq->sig, QLNXR_CQ_MAGIC_NUMBER); 344 break; 345 } 346 cq->arm_flags = 0; 347 348 if (!cq->destroyed && cq->ibcq.comp_handler) { 349 QL_DPRINT11(ha, "calling comp_handler = %p " 350 "ibcq = %p cq_context = 0x%x\n", 351 &cq->ibcq, cq->ibcq.cq_context); 352 353 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context); 354 } 355 cq->cnq_notif++; 356 357 sw_comp_cons = ecore_chain_get_cons_idx(&cnq->pbl); 358 359 cnq->n_comp++; 360 } 361 362 ecore_rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index, sw_comp_cons); 363 364 ecore_sb_ack(cnq->sb, IGU_INT_ENABLE, 1 /*update*/); 365 366 QL_DPRINT12(ha, "exit cnq = %p\n", handle); 367 return; 368 } 369 370 static void 371 qlnxr_release_irqs(struct qlnxr_dev *dev) 372 { 373 int i; 374 qlnx_host_t *ha; 375 376 ha = dev->ha; 377 378 QL_DPRINT12(ha, "enter\n"); 379 380 for (i = 0; i < dev->num_cnq; i++) { 381 if (dev->cnq_array[i].irq_handle) 382 (void)bus_teardown_intr(dev->ha->pci_dev, 383 dev->cnq_array[i].irq, 384 dev->cnq_array[i].irq_handle); 385 386 if (dev->cnq_array[i].irq) 387 (void) bus_release_resource(dev->ha->pci_dev, 388 SYS_RES_IRQ, 389 dev->cnq_array[i].irq_rid, 390 dev->cnq_array[i].irq); 391 } 392 QL_DPRINT12(ha, "exit\n"); 393 return; 394 } 395 396 static int 397 qlnxr_setup_irqs(struct qlnxr_dev *dev) 398 { 399 int start_irq_rid; 400 int i; 401 qlnx_host_t *ha; 402 403 ha = dev->ha; 404 405 start_irq_rid = dev->sb_start + 2; 406 407 QL_DPRINT12(ha, "enter start_irq_rid = %d num_rss = %d\n", 408 start_irq_rid, dev->ha->num_rss); 409 410 411 for (i = 0; i < dev->num_cnq; i++) { 412 413 dev->cnq_array[i].irq_rid = start_irq_rid + i; 414 415 dev->cnq_array[i].irq = bus_alloc_resource_any(dev->ha->pci_dev, 416 SYS_RES_IRQ, 417 &dev->cnq_array[i].irq_rid, 418 (RF_ACTIVE | RF_SHAREABLE)); 419 420 if (dev->cnq_array[i].irq == NULL) { 421 422 QL_DPRINT11(ha, 423 "bus_alloc_resource_any failed irq_rid = %d\n", 424 dev->cnq_array[i].irq_rid); 425 426 goto qlnxr_setup_irqs_err; 427 } 428 429 if (bus_setup_intr(dev->ha->pci_dev, 430 dev->cnq_array[i].irq, 431 (INTR_TYPE_NET | INTR_MPSAFE), 432 NULL, qlnxr_intr, &dev->cnq_array[i], 433 &dev->cnq_array[i].irq_handle)) { 434 435 QL_DPRINT11(ha, "bus_setup_intr failed\n"); 436 goto qlnxr_setup_irqs_err; 437 } 438 QL_DPRINT12(ha, "irq_rid = %d irq = %p irq_handle = %p\n", 439 dev->cnq_array[i].irq_rid, dev->cnq_array[i].irq, 440 dev->cnq_array[i].irq_handle); 441 } 442 443 QL_DPRINT12(ha, "exit\n"); 444 return (0); 445 446 qlnxr_setup_irqs_err: 447 qlnxr_release_irqs(dev); 448 449 QL_DPRINT12(ha, "exit -1\n"); 450 return (-1); 451 } 452 453 static void 454 qlnxr_free_resources(struct qlnxr_dev *dev) 455 { 456 int i; 457 qlnx_host_t *ha; 458 459 ha = dev->ha; 460 461 QL_DPRINT12(ha, "enter dev->num_cnq = %d\n", dev->num_cnq); 462 463 if (QLNX_IS_IWARP(dev)) { 464 if (dev->iwarp_wq != NULL) 465 destroy_workqueue(dev->iwarp_wq); 466 } 467 468 for (i = 0; i < dev->num_cnq; i++) { 469 qlnx_free_mem_sb(dev->ha, &dev->sb_array[i]); 470 ecore_chain_free(&dev->ha->cdev, &dev->cnq_array[i].pbl); 471 } 472 473 bzero(dev->cnq_array, (sizeof(struct qlnxr_cnq) * QLNXR_MAX_MSIX)); 474 bzero(dev->sb_array, (sizeof(struct ecore_sb_info) * QLNXR_MAX_MSIX)); 475 bzero(dev->sgid_tbl, (sizeof(union ib_gid) * QLNXR_MAX_SGID)); 476 477 if (mtx_initialized(&dev->idr_lock)) 478 mtx_destroy(&dev->idr_lock); 479 480 if (mtx_initialized(&dev->sgid_lock)) 481 mtx_destroy(&dev->sgid_lock); 482 483 QL_DPRINT12(ha, "exit\n"); 484 return; 485 } 486 487 488 static int 489 qlnxr_alloc_resources(struct qlnxr_dev *dev) 490 { 491 uint16_t n_entries; 492 int i, rc; 493 qlnx_host_t *ha; 494 495 ha = dev->ha; 496 497 QL_DPRINT12(ha, "enter\n"); 498 499 bzero(dev->sgid_tbl, (sizeof (union ib_gid) * QLNXR_MAX_SGID)); 500 501 mtx_init(&dev->idr_lock, "idr_lock", NULL, MTX_DEF); 502 mtx_init(&dev->sgid_lock, "sgid_lock", NULL, MTX_DEF); 503 504 idr_init(&dev->qpidr); 505 506 bzero(dev->sb_array, (sizeof (struct ecore_sb_info) * QLNXR_MAX_MSIX)); 507 bzero(dev->cnq_array, (sizeof (struct qlnxr_cnq) * QLNXR_MAX_MSIX)); 508 509 dev->sb_start = ecore_rdma_get_sb_id(dev->rdma_ctx, 0); 510 511 QL_DPRINT12(ha, "dev->sb_start = 0x%x\n", dev->sb_start); 512 513 /* Allocate CNQ PBLs */ 514 515 n_entries = min_t(u32, ECORE_RDMA_MAX_CNQ_SIZE, QLNXR_ROCE_MAX_CNQ_SIZE); 516 517 for (i = 0; i < dev->num_cnq; i++) { 518 rc = qlnx_alloc_mem_sb(dev->ha, &dev->sb_array[i], 519 dev->sb_start + i); 520 if (rc) 521 goto qlnxr_alloc_resources_exit; 522 523 rc = ecore_chain_alloc(&dev->ha->cdev, 524 ECORE_CHAIN_USE_TO_CONSUME_PRODUCE, 525 ECORE_CHAIN_MODE_PBL, 526 ECORE_CHAIN_CNT_TYPE_U16, 527 n_entries, 528 sizeof(struct regpair *), 529 &dev->cnq_array[i].pbl, 530 NULL); 531 532 /* configure cnq, except name since ibdev.name is still NULL */ 533 dev->cnq_array[i].dev = dev; 534 dev->cnq_array[i].sb = &dev->sb_array[i]; 535 dev->cnq_array[i].hw_cons_ptr = 536 &(dev->sb_array[i].sb_virt->pi_array[ECORE_ROCE_PROTOCOL_INDEX]); 537 dev->cnq_array[i].index = i; 538 sprintf(dev->cnq_array[i].name, "qlnxr%d@pci:%d", 539 i, (dev->ha->pci_func)); 540 541 } 542 543 QL_DPRINT12(ha, "exit\n"); 544 return 0; 545 546 qlnxr_alloc_resources_exit: 547 548 qlnxr_free_resources(dev); 549 550 QL_DPRINT12(ha, "exit -ENOMEM\n"); 551 return -ENOMEM; 552 } 553 554 void 555 qlnxr_affiliated_event(void *context, u8 e_code, void *fw_handle) 556 { 557 #define EVENT_TYPE_NOT_DEFINED 0 558 #define EVENT_TYPE_CQ 1 559 #define EVENT_TYPE_QP 2 560 #define EVENT_TYPE_GENERAL 3 561 562 struct qlnxr_dev *dev = (struct qlnxr_dev *)context; 563 struct regpair *async_handle = (struct regpair *)fw_handle; 564 u64 roceHandle64 = ((u64)async_handle->hi << 32) + async_handle->lo; 565 struct qlnxr_cq *cq = (struct qlnxr_cq *)(uintptr_t)roceHandle64; 566 struct qlnxr_qp *qp = (struct qlnxr_qp *)(uintptr_t)roceHandle64; 567 u8 event_type = EVENT_TYPE_NOT_DEFINED; 568 struct ib_event event; 569 qlnx_host_t *ha; 570 571 ha = dev->ha; 572 573 QL_DPRINT12(ha, "enter context = %p e_code = 0x%x fw_handle = %p\n", 574 context, e_code, fw_handle); 575 576 if (QLNX_IS_IWARP(dev)) { 577 switch (e_code) { 578 579 case ECORE_IWARP_EVENT_CQ_OVERFLOW: 580 event.event = IB_EVENT_CQ_ERR; 581 event_type = EVENT_TYPE_CQ; 582 break; 583 584 default: 585 QL_DPRINT12(ha, 586 "unsupported event %d on handle=%llx\n", 587 e_code, roceHandle64); 588 break; 589 } 590 } else { 591 switch (e_code) { 592 593 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR: 594 event.event = IB_EVENT_CQ_ERR; 595 event_type = EVENT_TYPE_CQ; 596 break; 597 598 case ROCE_ASYNC_EVENT_SQ_DRAINED: 599 event.event = IB_EVENT_SQ_DRAINED; 600 event_type = EVENT_TYPE_QP; 601 break; 602 603 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR: 604 event.event = IB_EVENT_QP_FATAL; 605 event_type = EVENT_TYPE_QP; 606 break; 607 608 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR: 609 event.event = IB_EVENT_QP_REQ_ERR; 610 event_type = EVENT_TYPE_QP; 611 break; 612 613 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR: 614 event.event = IB_EVENT_QP_ACCESS_ERR; 615 event_type = EVENT_TYPE_QP; 616 break; 617 618 /* NOTE the following are not implemented in FW 619 * ROCE_ASYNC_EVENT_CQ_ERR 620 * ROCE_ASYNC_EVENT_COMM_EST 621 */ 622 /* TODO associate the following events - 623 * ROCE_ASYNC_EVENT_SRQ_LIMIT 624 * ROCE_ASYNC_EVENT_LAST_WQE_REACHED 625 * ROCE_ASYNC_EVENT_LOCAL_CATASTROPHIC_ERR (un-affiliated) 626 */ 627 default: 628 QL_DPRINT12(ha, 629 "unsupported event 0x%x on fw_handle = %p\n", 630 e_code, fw_handle); 631 break; 632 } 633 } 634 635 switch (event_type) { 636 637 case EVENT_TYPE_CQ: 638 if (cq && cq->sig == QLNXR_CQ_MAGIC_NUMBER) { 639 struct ib_cq *ibcq = &cq->ibcq; 640 641 if (ibcq->event_handler) { 642 event.device = ibcq->device; 643 event.element.cq = ibcq; 644 ibcq->event_handler(&event, ibcq->cq_context); 645 } 646 } else { 647 QL_DPRINT11(ha, 648 "CQ event with invalid CQ pointer" 649 " Handle = %llx\n", roceHandle64); 650 } 651 QL_DPRINT12(ha, 652 "CQ event 0x%x on handle = %p\n", e_code, cq); 653 break; 654 655 case EVENT_TYPE_QP: 656 if (qp && qp->sig == QLNXR_QP_MAGIC_NUMBER) { 657 struct ib_qp *ibqp = &qp->ibqp; 658 659 if (ibqp->event_handler) { 660 event.device = ibqp->device; 661 event.element.qp = ibqp; 662 ibqp->event_handler(&event, ibqp->qp_context); 663 } 664 } else { 665 QL_DPRINT11(ha, 666 "QP event 0x%x with invalid QP pointer" 667 " qp handle = %p\n", 668 e_code, roceHandle64); 669 } 670 QL_DPRINT12(ha, "QP event 0x%x on qp handle = %p\n", 671 e_code, qp); 672 break; 673 674 case EVENT_TYPE_GENERAL: 675 break; 676 677 default: 678 break; 679 680 } 681 682 QL_DPRINT12(ha, "exit\n"); 683 684 return; 685 } 686 687 void 688 qlnxr_unaffiliated_event(void *context, u8 e_code) 689 { 690 struct qlnxr_dev *dev = (struct qlnxr_dev *)context; 691 qlnx_host_t *ha; 692 693 ha = dev->ha; 694 695 QL_DPRINT12(ha, "enter/exit \n"); 696 return; 697 } 698 699 700 static int 701 qlnxr_set_device_attr(struct qlnxr_dev *dev) 702 { 703 struct ecore_rdma_device *ecore_attr; 704 struct qlnxr_device_attr *attr; 705 u32 page_size; 706 707 ecore_attr = ecore_rdma_query_device(dev->rdma_ctx); 708 709 page_size = ~dev->attr.page_size_caps + 1; 710 if(page_size > PAGE_SIZE) { 711 QL_DPRINT12(dev->ha, "Kernel page size : %ld is smaller than" 712 " minimum page size : %ld required by qlnxr\n", 713 PAGE_SIZE, page_size); 714 return -ENODEV; 715 } 716 attr = &dev->attr; 717 attr->vendor_id = ecore_attr->vendor_id; 718 attr->vendor_part_id = ecore_attr->vendor_part_id; 719 720 QL_DPRINT12(dev->ha, "in qlnxr_set_device_attr, vendor : %x device : %x\n", 721 attr->vendor_id, attr->vendor_part_id); 722 723 attr->hw_ver = ecore_attr->hw_ver; 724 attr->fw_ver = ecore_attr->fw_ver; 725 attr->node_guid = ecore_attr->node_guid; 726 attr->sys_image_guid = ecore_attr->sys_image_guid; 727 attr->max_cnq = ecore_attr->max_cnq; 728 attr->max_sge = ecore_attr->max_sge; 729 attr->max_inline = ecore_attr->max_inline; 730 attr->max_sqe = min_t(u32, ecore_attr->max_wqe, QLNXR_MAX_SQE); 731 attr->max_rqe = min_t(u32, ecore_attr->max_wqe, QLNXR_MAX_RQE); 732 attr->max_qp_resp_rd_atomic_resc = ecore_attr->max_qp_resp_rd_atomic_resc; 733 attr->max_qp_req_rd_atomic_resc = ecore_attr->max_qp_req_rd_atomic_resc; 734 attr->max_dev_resp_rd_atomic_resc = 735 ecore_attr->max_dev_resp_rd_atomic_resc; 736 attr->max_cq = ecore_attr->max_cq; 737 attr->max_qp = ecore_attr->max_qp; 738 attr->max_mr = ecore_attr->max_mr; 739 attr->max_mr_size = ecore_attr->max_mr_size; 740 attr->max_cqe = min_t(u64, ecore_attr->max_cqe, QLNXR_MAX_CQES); 741 attr->max_mw = ecore_attr->max_mw; 742 attr->max_fmr = ecore_attr->max_fmr; 743 attr->max_mr_mw_fmr_pbl = ecore_attr->max_mr_mw_fmr_pbl; 744 attr->max_mr_mw_fmr_size = ecore_attr->max_mr_mw_fmr_size; 745 attr->max_pd = ecore_attr->max_pd; 746 attr->max_ah = ecore_attr->max_ah; 747 attr->max_pkey = ecore_attr->max_pkey; 748 attr->max_srq = ecore_attr->max_srq; 749 attr->max_srq_wr = ecore_attr->max_srq_wr; 750 //attr->dev_caps = ecore_attr->dev_caps; 751 attr->page_size_caps = ecore_attr->page_size_caps; 752 attr->dev_ack_delay = ecore_attr->dev_ack_delay; 753 attr->reserved_lkey = ecore_attr->reserved_lkey; 754 attr->bad_pkey_counter = ecore_attr->bad_pkey_counter; 755 attr->max_stats_queues = ecore_attr->max_stats_queues; 756 757 return 0; 758 } 759 760 761 static int 762 qlnxr_init_hw(struct qlnxr_dev *dev) 763 { 764 struct ecore_rdma_events events; 765 struct ecore_rdma_add_user_out_params out_params; 766 struct ecore_rdma_cnq_params *cur_pbl; 767 struct ecore_rdma_start_in_params *in_params; 768 dma_addr_t p_phys_table; 769 u32 page_cnt; 770 int rc = 0; 771 int i; 772 qlnx_host_t *ha; 773 774 ha = dev->ha; 775 776 QL_DPRINT12(ha, "enter\n"); 777 778 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL); 779 if (!in_params) { 780 rc = -ENOMEM; 781 goto out; 782 } 783 784 bzero(&out_params, sizeof(struct ecore_rdma_add_user_out_params)); 785 bzero(&events, sizeof(struct ecore_rdma_events)); 786 787 in_params->desired_cnq = dev->num_cnq; 788 789 for (i = 0; i < dev->num_cnq; i++) { 790 cur_pbl = &in_params->cnq_pbl_list[i]; 791 792 page_cnt = ecore_chain_get_page_cnt(&dev->cnq_array[i].pbl); 793 cur_pbl->num_pbl_pages = page_cnt; 794 795 p_phys_table = ecore_chain_get_pbl_phys(&dev->cnq_array[i].pbl); 796 cur_pbl->pbl_ptr = (u64)p_phys_table; 797 } 798 799 events.affiliated_event = qlnxr_affiliated_event; 800 events.unaffiliated_event = qlnxr_unaffiliated_event; 801 events.context = dev; 802 803 in_params->events = &events; 804 in_params->roce.cq_mode = ECORE_RDMA_CQ_MODE_32_BITS; 805 in_params->max_mtu = dev->ha->max_frame_size; 806 807 808 if (QLNX_IS_IWARP(dev)) { 809 if (delayed_ack) 810 in_params->iwarp.flags |= ECORE_IWARP_DA_EN; 811 812 if (timestamp) 813 in_params->iwarp.flags |= ECORE_IWARP_TS_EN; 814 815 in_params->iwarp.rcv_wnd_size = rcv_wnd_size*1024; 816 in_params->iwarp.crc_needed = crc_needed; 817 in_params->iwarp.ooo_num_rx_bufs = 818 (MAX_RXMIT_CONNS * in_params->iwarp.rcv_wnd_size) / 819 in_params->max_mtu; 820 821 in_params->iwarp.mpa_peer2peer = peer2peer; 822 in_params->iwarp.mpa_rev = 823 mpa_enhanced ? ECORE_MPA_REV2 : ECORE_MPA_REV1; 824 in_params->iwarp.mpa_rtr = rtr_type; 825 } 826 827 memcpy(&in_params->mac_addr[0], dev->ha->primary_mac, ETH_ALEN); 828 829 rc = ecore_rdma_start(dev->rdma_ctx, in_params); 830 if (rc) 831 goto out; 832 833 rc = ecore_rdma_add_user(dev->rdma_ctx, &out_params); 834 if (rc) 835 goto out; 836 837 dev->db_addr = (void *)(uintptr_t)out_params.dpi_addr; 838 dev->db_phys_addr = out_params.dpi_phys_addr; 839 dev->db_size = out_params.dpi_size; 840 dev->dpi = out_params.dpi; 841 842 qlnxr_set_device_attr(dev); 843 844 QL_DPRINT12(ha, 845 "cdev->doorbells = %p, db_phys_addr = %p db_size = 0x%x\n", 846 (void *)ha->cdev.doorbells, 847 (void *)ha->cdev.db_phys_addr, ha->cdev.db_size); 848 849 QL_DPRINT12(ha, 850 "db_addr = %p db_phys_addr = %p db_size = 0x%x dpi = 0x%x\n", 851 (void *)dev->db_addr, (void *)dev->db_phys_addr, 852 dev->db_size, dev->dpi); 853 out: 854 kfree(in_params); 855 856 QL_DPRINT12(ha, "exit\n"); 857 return rc; 858 } 859 860 static void 861 qlnxr_build_sgid_mac(union ib_gid *sgid, unsigned char *mac_addr, 862 bool is_vlan, u16 vlan_id) 863 { 864 sgid->global.subnet_prefix = OSAL_CPU_TO_BE64(0xfe80000000000000LL); 865 sgid->raw[8] = mac_addr[0] ^ 2; 866 sgid->raw[9] = mac_addr[1]; 867 sgid->raw[10] = mac_addr[2]; 868 if (is_vlan) { 869 sgid->raw[11] = vlan_id >> 8; 870 sgid->raw[12] = vlan_id & 0xff; 871 } else { 872 sgid->raw[11] = 0xff; 873 sgid->raw[12] = 0xfe; 874 } 875 sgid->raw[13] = mac_addr[3]; 876 sgid->raw[14] = mac_addr[4]; 877 sgid->raw[15] = mac_addr[5]; 878 } 879 static bool 880 qlnxr_add_sgid(struct qlnxr_dev *dev, union ib_gid *new_sgid); 881 882 static void 883 qlnxr_add_ip_based_gid(struct qlnxr_dev *dev, struct ifnet *ifp) 884 { 885 struct ifaddr *ifa; 886 union ib_gid gid; 887 888 CK_STAILQ_FOREACH(ifa, &ifp->if_addrhead, ifa_link) { 889 if (ifa->ifa_addr && ifa->ifa_addr->sa_family == AF_INET) { 890 891 QL_DPRINT12(dev->ha, "IP address : %x\n", ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr); 892 ipv6_addr_set_v4mapped( 893 ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr, 894 (struct in6_addr *)&gid); 895 QL_DPRINT12(dev->ha, "gid generated : %llx\n", gid); 896 897 qlnxr_add_sgid(dev, &gid); 898 } 899 } 900 for (int i = 0; i < 16; i++) { 901 QL_DPRINT12(dev->ha, "gid generated : %x\n", gid.raw[i]); 902 } 903 } 904 905 static bool 906 qlnxr_add_sgid(struct qlnxr_dev *dev, union ib_gid *new_sgid) 907 { 908 union ib_gid zero_sgid = { { 0 } }; 909 int i; 910 //unsigned long flags; 911 mtx_lock(&dev->sgid_lock); 912 for (i = 0; i < QLNXR_MAX_SGID; i++) { 913 if (!memcmp(&dev->sgid_tbl[i], &zero_sgid, 914 sizeof(union ib_gid))) { 915 /* found free entry */ 916 memcpy(&dev->sgid_tbl[i], new_sgid, 917 sizeof(union ib_gid)); 918 QL_DPRINT12(dev->ha, "copying sgid : %llx\n", 919 *new_sgid); 920 mtx_unlock(&dev->sgid_lock); 921 //TODO ib_dispatch event here? 922 return true; 923 } else if (!memcmp(&dev->sgid_tbl[i], new_sgid, 924 sizeof(union ib_gid))) { 925 /* entry already present, no addition required */ 926 mtx_unlock(&dev->sgid_lock); 927 QL_DPRINT12(dev->ha, "sgid present : %llx\n", 928 *new_sgid); 929 return false; 930 } 931 } 932 if (i == QLNXR_MAX_SGID) { 933 QL_DPRINT12(dev->ha, "didn't find an empty entry in sgid_tbl\n"); 934 } 935 mtx_unlock(&dev->sgid_lock); 936 return false; 937 } 938 939 static bool qlnxr_del_sgid(struct qlnxr_dev *dev, union ib_gid *gid) 940 { 941 int found = false; 942 int i; 943 //unsigned long flags; 944 945 QL_DPRINT12(dev->ha, "removing gid %llx %llx\n", 946 gid->global.interface_id, 947 gid->global.subnet_prefix); 948 mtx_lock(&dev->sgid_lock); 949 /* first is the default sgid which cannot be deleted */ 950 for (i = 1; i < QLNXR_MAX_SGID; i++) { 951 if (!memcmp(&dev->sgid_tbl[i], gid, sizeof(union ib_gid))) { 952 /* found matching entry */ 953 memset(&dev->sgid_tbl[i], 0, sizeof(union ib_gid)); 954 found = true; 955 break; 956 } 957 } 958 mtx_unlock(&dev->sgid_lock); 959 960 return found; 961 } 962 963 #if __FreeBSD_version < 1100000 964 965 static inline int 966 is_vlan_dev(struct ifnet *ifp) 967 { 968 return (ifp->if_type == IFT_L2VLAN); 969 } 970 971 static inline uint16_t 972 vlan_dev_vlan_id(struct ifnet *ifp) 973 { 974 uint16_t vtag; 975 976 if (VLAN_TAG(ifp, &vtag) == 0) 977 return (vtag); 978 979 return (0); 980 } 981 982 #endif /* #if __FreeBSD_version < 1100000 */ 983 984 static void 985 qlnxr_add_sgids(struct qlnxr_dev *dev) 986 { 987 qlnx_host_t *ha = dev->ha; 988 u16 vlan_id; 989 bool is_vlan; 990 union ib_gid vgid; 991 992 qlnxr_add_ip_based_gid(dev, ha->ifp); 993 /* MAC/VLAN base GIDs */ 994 is_vlan = is_vlan_dev(ha->ifp); 995 vlan_id = (is_vlan) ? vlan_dev_vlan_id(ha->ifp) : 0; 996 qlnxr_build_sgid_mac(&vgid, ha->primary_mac, is_vlan, vlan_id); 997 qlnxr_add_sgid(dev, &vgid); 998 } 999 1000 static int 1001 qlnxr_add_default_sgid(struct qlnxr_dev *dev) 1002 { 1003 /* GID Index 0 - Invariant manufacturer-assigned EUI-64 */ 1004 union ib_gid *sgid = &dev->sgid_tbl[0]; 1005 struct ecore_rdma_device *qattr; 1006 qlnx_host_t *ha; 1007 ha = dev->ha; 1008 1009 qattr = ecore_rdma_query_device(dev->rdma_ctx); 1010 if(sgid == NULL) 1011 QL_DPRINT12(ha, "sgid = NULL?\n"); 1012 1013 sgid->global.subnet_prefix = OSAL_CPU_TO_BE64(0xfe80000000000000LL); 1014 QL_DPRINT12(ha, "node_guid = %llx", dev->attr.node_guid); 1015 memcpy(&sgid->raw[8], &qattr->node_guid, 1016 sizeof(qattr->node_guid)); 1017 //memcpy(&sgid->raw[8], &dev->attr.node_guid, 1018 // sizeof(dev->attr.node_guid)); 1019 QL_DPRINT12(ha, "DEFAULT sgid=[%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x][%x]\n", 1020 sgid->raw[0], sgid->raw[1], sgid->raw[2], sgid->raw[3], sgid->raw[4], sgid->raw[5], 1021 sgid->raw[6], sgid->raw[7], sgid->raw[8], sgid->raw[9], sgid->raw[10], sgid->raw[11], 1022 sgid->raw[12], sgid->raw[13], sgid->raw[14], sgid->raw[15]); 1023 return 0; 1024 } 1025 1026 static int qlnxr_addr_event (struct qlnxr_dev *dev, 1027 unsigned long event, 1028 struct ifnet *ifp, 1029 union ib_gid *gid) 1030 { 1031 bool is_vlan = false; 1032 union ib_gid vgid; 1033 u16 vlan_id = 0xffff; 1034 1035 QL_DPRINT12(dev->ha, "Link event occured\n"); 1036 is_vlan = is_vlan_dev(dev->ha->ifp); 1037 vlan_id = (is_vlan) ? vlan_dev_vlan_id(dev->ha->ifp) : 0; 1038 1039 switch (event) { 1040 case NETDEV_UP : 1041 qlnxr_add_sgid(dev, gid); 1042 if (is_vlan) { 1043 qlnxr_build_sgid_mac(&vgid, dev->ha->primary_mac, is_vlan, vlan_id); 1044 qlnxr_add_sgid(dev, &vgid); 1045 } 1046 break; 1047 case NETDEV_DOWN : 1048 qlnxr_del_sgid(dev, gid); 1049 if (is_vlan) { 1050 qlnxr_build_sgid_mac(&vgid, dev->ha->primary_mac, is_vlan, vlan_id); 1051 qlnxr_del_sgid(dev, &vgid); 1052 } 1053 break; 1054 default : 1055 break; 1056 } 1057 return 1; 1058 } 1059 1060 static int qlnxr_inetaddr_event(struct notifier_block *notifier, 1061 unsigned long event, void *ptr) 1062 { 1063 struct ifaddr *ifa = ptr; 1064 union ib_gid gid; 1065 struct qlnxr_dev *dev = container_of(notifier, struct qlnxr_dev, nb_inet); 1066 qlnx_host_t *ha = dev->ha; 1067 1068 ipv6_addr_set_v4mapped( 1069 ((struct sockaddr_in *) ifa->ifa_addr)->sin_addr.s_addr, 1070 (struct in6_addr *)&gid); 1071 return qlnxr_addr_event(dev, event, ha->ifp, &gid); 1072 } 1073 1074 static int 1075 qlnxr_register_inet(struct qlnxr_dev *dev) 1076 { 1077 int ret; 1078 dev->nb_inet.notifier_call = qlnxr_inetaddr_event; 1079 ret = register_inetaddr_notifier(&dev->nb_inet); 1080 if (ret) { 1081 QL_DPRINT12(dev->ha, "Failed to register inetaddr\n"); 1082 return ret; 1083 } 1084 /* TODO : add for CONFIG_IPV6) */ 1085 return 0; 1086 } 1087 1088 static int 1089 qlnxr_build_sgid_tbl(struct qlnxr_dev *dev) 1090 { 1091 qlnxr_add_default_sgid(dev); 1092 qlnxr_add_sgids(dev); 1093 return 0; 1094 } 1095 1096 static struct qlnx_rdma_if qlnxr_drv; 1097 1098 static void * 1099 qlnxr_add(void *eth_dev) 1100 { 1101 struct qlnxr_dev *dev; 1102 int ret; 1103 //device_t pci_dev; 1104 qlnx_host_t *ha; 1105 1106 ha = eth_dev; 1107 1108 QL_DPRINT12(ha, "enter [ha = %p]\n", ha); 1109 1110 dev = (struct qlnxr_dev *)ib_alloc_device(sizeof(struct qlnxr_dev)); 1111 1112 if (dev == NULL) 1113 return (NULL); 1114 1115 dev->ha = eth_dev; 1116 dev->cdev = &ha->cdev; 1117 /* Added to extend Application support */ 1118 dev->pdev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 1119 1120 dev->pdev->dev = *(dev->ha->pci_dev); 1121 dev->pdev->device = pci_get_device(dev->ha->pci_dev); 1122 dev->pdev->vendor = pci_get_vendor(dev->ha->pci_dev); 1123 1124 dev->rdma_ctx = &ha->cdev.hwfns[0]; 1125 dev->wq_multiplier = wq_multiplier; 1126 dev->num_cnq = QLNX_NUM_CNQ; 1127 1128 QL_DPRINT12(ha, 1129 "ha = %p dev = %p ha->cdev = %p\n", 1130 ha, dev, &ha->cdev); 1131 QL_DPRINT12(ha, 1132 "dev->cdev = %p dev->rdma_ctx = %p\n", 1133 dev->cdev, dev->rdma_ctx); 1134 1135 ret = qlnxr_alloc_resources(dev); 1136 1137 if (ret) 1138 goto qlnxr_add_err; 1139 1140 ret = qlnxr_setup_irqs(dev); 1141 1142 if (ret) { 1143 qlnxr_free_resources(dev); 1144 goto qlnxr_add_err; 1145 } 1146 1147 ret = qlnxr_init_hw(dev); 1148 1149 if (ret) { 1150 qlnxr_release_irqs(dev); 1151 qlnxr_free_resources(dev); 1152 goto qlnxr_add_err; 1153 } 1154 1155 qlnxr_register_device(dev); 1156 for (int i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) { 1157 if (device_create_file(&dev->ibdev.dev, qlnxr_class_attributes[i])) 1158 goto sysfs_err; 1159 } 1160 qlnxr_build_sgid_tbl(dev); 1161 //ret = qlnxr_register_inet(dev); 1162 QL_DPRINT12(ha, "exit\n"); 1163 if (!test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) { 1164 QL_DPRINT12(ha, "dispatching IB_PORT_ACITVE event\n"); 1165 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1166 IB_EVENT_PORT_ACTIVE); 1167 } 1168 1169 return (dev); 1170 sysfs_err: 1171 for (int i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) { 1172 device_remove_file(&dev->ibdev.dev, qlnxr_class_attributes[i]); 1173 } 1174 ib_unregister_device(&dev->ibdev); 1175 1176 qlnxr_add_err: 1177 ib_dealloc_device(&dev->ibdev); 1178 1179 QL_DPRINT12(ha, "exit failed\n"); 1180 return (NULL); 1181 } 1182 1183 static void 1184 qlnxr_remove_sysfiles(struct qlnxr_dev *dev) 1185 { 1186 int i; 1187 for (i = 0; i < ARRAY_SIZE(qlnxr_class_attributes); ++i) 1188 device_remove_file(&dev->ibdev.dev, qlnxr_class_attributes[i]); 1189 } 1190 1191 static int 1192 qlnxr_remove(void *eth_dev, void *qlnx_rdma_dev) 1193 { 1194 struct qlnxr_dev *dev; 1195 qlnx_host_t *ha; 1196 1197 dev = qlnx_rdma_dev; 1198 ha = eth_dev; 1199 1200 if ((ha == NULL) || (dev == NULL)) 1201 return (0); 1202 1203 QL_DPRINT12(ha, "enter ha = %p qlnx_rdma_dev = %p pd_count = %d\n", 1204 ha, qlnx_rdma_dev, dev->pd_count); 1205 1206 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1207 IB_EVENT_PORT_ERR); 1208 1209 if (QLNX_IS_IWARP(dev)) { 1210 if (dev->pd_count) 1211 return (EBUSY); 1212 } 1213 1214 ib_unregister_device(&dev->ibdev); 1215 1216 if (QLNX_IS_ROCE(dev)) { 1217 if (dev->pd_count) 1218 return (EBUSY); 1219 } 1220 1221 ecore_rdma_remove_user(dev->rdma_ctx, dev->dpi); 1222 ecore_rdma_stop(dev->rdma_ctx); 1223 1224 qlnxr_release_irqs(dev); 1225 1226 qlnxr_free_resources(dev); 1227 1228 qlnxr_remove_sysfiles(dev); 1229 ib_dealloc_device(&dev->ibdev); 1230 1231 QL_DPRINT12(ha, "exit ha = %p qlnx_rdma_dev = %p\n", ha, qlnx_rdma_dev); 1232 return (0); 1233 } 1234 1235 int 1236 qlnx_rdma_ll2_set_mac_filter(void *rdma_ctx, uint8_t *old_mac_address, 1237 uint8_t *new_mac_address) 1238 { 1239 struct ecore_hwfn *p_hwfn = rdma_ctx; 1240 struct qlnx_host *ha; 1241 int ret = 0; 1242 1243 ha = (struct qlnx_host *)(p_hwfn->p_dev); 1244 QL_DPRINT2(ha, "enter rdma_ctx (%p)\n", rdma_ctx); 1245 1246 if (old_mac_address) 1247 ecore_llh_remove_mac_filter(p_hwfn->p_dev, 0, old_mac_address); 1248 1249 if (new_mac_address) 1250 ret = ecore_llh_add_mac_filter(p_hwfn->p_dev, 0, new_mac_address); 1251 1252 QL_DPRINT2(ha, "exit rdma_ctx (%p)\n", rdma_ctx); 1253 return (ret); 1254 } 1255 1256 static void 1257 qlnxr_mac_address_change(struct qlnxr_dev *dev) 1258 { 1259 qlnx_host_t *ha; 1260 1261 ha = dev->ha; 1262 1263 QL_DPRINT12(ha, "enter/exit\n"); 1264 1265 return; 1266 } 1267 1268 static void 1269 qlnxr_notify(void *eth_dev, void *qlnx_rdma_dev, enum qlnx_rdma_event event) 1270 { 1271 struct qlnxr_dev *dev; 1272 qlnx_host_t *ha; 1273 1274 dev = qlnx_rdma_dev; 1275 1276 if (dev == NULL) 1277 return; 1278 1279 ha = dev->ha; 1280 1281 QL_DPRINT12(ha, "enter (%p, %d)\n", qlnx_rdma_dev, event); 1282 1283 switch (event) { 1284 1285 case QLNX_ETHDEV_UP: 1286 if (!test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) 1287 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1288 IB_EVENT_PORT_ACTIVE); 1289 break; 1290 1291 case QLNX_ETHDEV_CHANGE_ADDR: 1292 qlnxr_mac_address_change(dev); 1293 break; 1294 1295 case QLNX_ETHDEV_DOWN: 1296 if (test_and_set_bit(QLNXR_ENET_STATE_BIT, &dev->enet_state)) 1297 qlnxr_ib_dispatch_event(dev, QLNXR_PORT, 1298 IB_EVENT_PORT_ERR); 1299 break; 1300 } 1301 1302 QL_DPRINT12(ha, "exit (%p, %d)\n", qlnx_rdma_dev, event); 1303 return; 1304 } 1305 1306 static int 1307 qlnxr_mod_load(void) 1308 { 1309 int ret; 1310 1311 1312 qlnxr_drv.add = qlnxr_add; 1313 qlnxr_drv.remove = qlnxr_remove; 1314 qlnxr_drv.notify = qlnxr_notify; 1315 1316 ret = qlnx_rdma_register_if(&qlnxr_drv); 1317 1318 return (0); 1319 } 1320 1321 static int 1322 qlnxr_mod_unload(void) 1323 { 1324 int ret; 1325 1326 ret = qlnx_rdma_deregister_if(&qlnxr_drv); 1327 return (ret); 1328 } 1329 1330 static int 1331 qlnxr_event_handler(module_t mod, int event, void *arg) 1332 { 1333 1334 int ret = 0; 1335 1336 switch (event) { 1337 1338 case MOD_LOAD: 1339 ret = qlnxr_mod_load(); 1340 break; 1341 1342 case MOD_UNLOAD: 1343 ret = qlnxr_mod_unload(); 1344 break; 1345 1346 default: 1347 break; 1348 } 1349 1350 return (ret); 1351 } 1352 1353 static moduledata_t qlnxr_mod_info = { 1354 .name = "qlnxr", 1355 .evhand = qlnxr_event_handler, 1356 }; 1357 1358 MODULE_VERSION(qlnxr, 1); 1359 MODULE_DEPEND(qlnxr, if_qlnxe, 1, 1, 1); 1360 MODULE_DEPEND(qlnxr, ibcore, 1, 1, 1); 1361 1362 #if __FreeBSD_version >= 1100000 1363 MODULE_DEPEND(qlnxr, linuxkpi, 1, 1, 1); 1364 #endif /* #if __FreeBSD_version >= 1100000 */ 1365 1366 DECLARE_MODULE(qlnxr, qlnxr_mod_info, SI_SUB_LAST, SI_ORDER_ANY); 1367 1368