1 /* 2 * Copyright (c) 2018-2019 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * File: qlnxr_def.h 32 * Author: David C Somayajulu 33 */ 34 35 #ifndef __QLNX_DEF_H_ 36 #define __QLNX_DEF_H_ 37 38 #include <sys/ktr.h> 39 40 #include <linux/list.h> 41 #include <linux/spinlock.h> 42 #include <linux/idr.h> 43 #include <linux/completion.h> 44 #include <linux/sched.h> 45 #include <linux/pci.h> 46 #include <linux/dma-mapping.h> 47 #include <linux/wait.h> 48 #include <linux/kref.h> 49 #include <linux/timer.h> 50 #include <linux/io.h> 51 #include <linux/fs.h> 52 #include <sys/vmem.h> 53 54 #include <asm/byteorder.h> 55 56 #include <netinet/in.h> 57 #include <net/ipv6.h> 58 #include <netinet/toecore.h> 59 60 #include <rdma/ib_smi.h> 61 #include <rdma/ib_user_verbs.h> 62 #include <rdma/ib_addr.h> 63 #include <rdma/ib_verbs.h> 64 #include <rdma/iw_cm.h> 65 #include <rdma/ib_umem.h> 66 #include <rdma/ib_mad.h> 67 #include <rdma/ib_sa.h> 68 #include <rdma/uverbs_ioctl.h> 69 70 #include "qlnx_os.h" 71 #include "bcm_osal.h" 72 73 #include "reg_addr.h" 74 #include "ecore_gtt_reg_addr.h" 75 #include "ecore.h" 76 #include "ecore_chain.h" 77 #include "ecore_status.h" 78 #include "ecore_hw.h" 79 #include "ecore_rt_defs.h" 80 #include "ecore_init_ops.h" 81 #include "ecore_int.h" 82 #include "ecore_cxt.h" 83 #include "ecore_spq.h" 84 #include "ecore_init_fw_funcs.h" 85 #include "ecore_sp_commands.h" 86 #include "ecore_dev_api.h" 87 #include "ecore_l2_api.h" 88 #ifdef CONFIG_ECORE_SRIOV 89 #include "ecore_sriov.h" 90 #include "ecore_vf.h" 91 #endif 92 #ifdef CONFIG_ECORE_LL2 93 #include "ecore_ll2.h" 94 #endif 95 #ifdef CONFIG_ECORE_FCOE 96 #include "ecore_fcoe.h" 97 #endif 98 #ifdef CONFIG_ECORE_ISCSI 99 #include "ecore_iscsi.h" 100 #endif 101 #include "ecore_mcp.h" 102 #include "ecore_hw_defs.h" 103 #include "mcp_public.h" 104 105 #ifdef CONFIG_ECORE_RDMA 106 #include "ecore_rdma.h" 107 #include "ecore_rdma_api.h" 108 #endif 109 110 #ifdef CONFIG_ECORE_ROCE 111 #include "ecore_roce.h" 112 #endif 113 114 #ifdef CONFIG_ECORE_IWARP 115 #include "ecore_iwarp.h" 116 #endif 117 118 #include "ecore_iro.h" 119 #include "nvm_cfg.h" 120 121 #include "ecore_dbg_fw_funcs.h" 122 #include "rdma_common.h" 123 124 #include "qlnx_ioctl.h" 125 #include "qlnx_def.h" 126 #include "qlnx_rdma.h" 127 #include "qlnxr_verbs.h" 128 #include "qlnxr_user.h" 129 #include "qlnx_ver.h" 130 #include <sys/smp.h> 131 132 #define QLNXR_ROCE_INTERFACE_VERSION 1801 133 134 #define QLNXR_MODULE_VERSION "8.18.1.0" 135 #define QLNXR_NODE_DESC "QLogic 579xx RoCE HCA" 136 137 #define OC_SKH_DEVICE_PF 0x720 138 #define OC_SKH_DEVICE_VF 0x728 139 #define QLNXR_MAX_AH 512 140 141 /* QLNXR Limitations */ 142 143 /* SQ/RQ Limitations 144 * An S/RQ PBL contains a list a pointers to pages. Each page contains S/RQE 145 * elements. Several S/RQE elements make an S/RQE, up to a certain maximum that 146 * is different between SQ and RQ. The size of the PBL was chosen such as not to 147 * limit the MAX_WR supported by ECORE, and rounded up to a power of two. 148 */ 149 /* SQ */ 150 #define QLNXR_MAX_SQ_PBL (0x8000) /* 2^15 bytes */ 151 #define QLNXR_MAX_SQ_PBL_ENTRIES (0x10000 / sizeof(void *)) /* number */ 152 #define QLNXR_SQE_ELEMENT_SIZE (sizeof(struct rdma_sq_sge)) /* bytes */ 153 #define QLNXR_MAX_SQE_ELEMENTS_PER_SQE (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \ 154 QLNXR_SQE_ELEMENT_SIZE) /* number */ 155 #define QLNXR_MAX_SQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 156 QLNXR_SQE_ELEMENT_SIZE) /* number */ 157 #define QLNXR_MAX_SQE ((QLNXR_MAX_SQ_PBL_ENTRIES) * (RDMA_RING_PAGE_SIZE) / \ 158 (QLNXR_SQE_ELEMENT_SIZE) / (QLNXR_MAX_SQE_ELEMENTS_PER_SQE)) 159 /* RQ */ 160 #define QLNXR_MAX_RQ_PBL (0x2000) /* 2^13 bytes */ 161 #define QLNXR_MAX_RQ_PBL_ENTRIES (0x10000 / sizeof(void *)) /* number */ 162 #define QLNXR_RQE_ELEMENT_SIZE (sizeof(struct rdma_rq_sge)) /* bytes */ 163 #define QLNXR_MAX_RQE_ELEMENTS_PER_RQE (RDMA_MAX_SGE_PER_RQ_WQE) /* number */ 164 #define QLNXR_MAX_RQE_ELEMENTS_PER_PAGE ((RDMA_RING_PAGE_SIZE) / \ 165 QLNXR_RQE_ELEMENT_SIZE) /* number */ 166 #define QLNXR_MAX_RQE ((QLNXR_MAX_RQ_PBL_ENTRIES) * (RDMA_RING_PAGE_SIZE) / \ 167 (QLNXR_RQE_ELEMENT_SIZE) / (QLNXR_MAX_RQE_ELEMENTS_PER_RQE)) 168 169 /* CQE Limitation 170 * Although FW supports two layer PBL we use single layer since it is more 171 * than enough. For that layer we use a maximum size of 512 kB, again, because 172 * it reaches the maximum number of page pointers. Notice is the '-1' in the 173 * calculation that comes from having a u16 for the number of pages i.e. 0xffff 174 * is the maximum number of pages (in single layer). 175 */ 176 #define QLNXR_CQE_SIZE (sizeof(union rdma_cqe)) 177 #define QLNXR_MAX_CQE_PBL_SIZE (512*1024) /* 512kB */ 178 #define QLNXR_MAX_CQE_PBL_ENTRIES (((QLNXR_MAX_CQE_PBL_SIZE) / \ 179 sizeof(u64)) - 1) /* 64k -1 */ 180 #define QLNXR_MAX_CQES ((u32)((QLNXR_MAX_CQE_PBL_ENTRIES) * (ECORE_CHAIN_PAGE_SIZE)\ 181 / QLNXR_CQE_SIZE)) /* 8M -4096/32 = 8,388,480 */ 182 183 /* CNQ size Limitation 184 * The maximum CNQ size is not reachable because the FW supports a chain of u16 185 * (specifically 64k-1). The FW can buffer CNQ elements avoiding an overflow, on 186 * the expense of performance. Hence we set it to an arbitrarily smaller value 187 * than the maximum. 188 */ 189 #define QLNXR_ROCE_MAX_CNQ_SIZE (0x4000) /* 2^16 */ 190 191 #define QLNXR_MAX_PORT (1) 192 #define QLNXR_PORT (1) 193 194 #define QLNXR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME) 195 196 #define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo) 197 198 /* The following number is used to determine if a handle recevied from the FW 199 * actually point to a CQ/QP. 200 */ 201 #define QLNXR_CQ_MAGIC_NUMBER (0x11223344) 202 #define QLNXR_QP_MAGIC_NUMBER (0x77889900) 203 204 /* Fast path debug prints */ 205 #define FP_DP_VERBOSE(...) 206 /* #define FP_DP_VERBOSE(...) DP_VERBOSE(__VA_ARGS__) */ 207 208 #define FW_PAGE_SIZE (RDMA_RING_PAGE_SIZE) 209 210 #define QLNXR_MSG_INIT 0x10000, 211 #define QLNXR_MSG_FAIL 0x10000, 212 #define QLNXR_MSG_CQ 0x20000, 213 #define QLNXR_MSG_RQ 0x40000, 214 #define QLNXR_MSG_SQ 0x80000, 215 #define QLNXR_MSG_QP (QLNXR_MSG_SQ | QLNXR_MSG_RQ), 216 #define QLNXR_MSG_MR 0x100000, 217 #define QLNXR_MSG_GSI 0x200000, 218 #define QLNXR_MSG_MISC 0x400000, 219 #define QLNXR_MSG_SRQ 0x800000, 220 #define QLNXR_MSG_IWARP 0x1000000, 221 222 #define QLNXR_ROCE_PKEY_MAX 1 223 #define QLNXR_ROCE_PKEY_TABLE_LEN 1 224 #define QLNXR_ROCE_PKEY_DEFAULT 0xffff 225 226 #define QLNXR_MAX_SGID 128 /* TBD - add more source gids... */ 227 228 #define QLNXR_ENET_STATE_BIT (0) 229 230 #define QLNXR_MAX_MSIX (16) 231 232 struct qlnxr_cnq { 233 struct qlnxr_dev *dev; 234 struct ecore_chain pbl; 235 struct ecore_sb_info *sb; 236 char name[32]; 237 u64 n_comp; 238 __le16 *hw_cons_ptr; 239 u8 index; 240 int irq_rid; 241 struct resource *irq; 242 void *irq_handle; 243 }; 244 245 struct qlnxr_device_attr { 246 /* Vendor specific information */ 247 u32 vendor_id; 248 u32 vendor_part_id; 249 u32 hw_ver; 250 u64 fw_ver; 251 252 u64 node_guid; /* node GUID */ 253 u64 sys_image_guid; /* System image GUID */ 254 255 u8 max_cnq; 256 u8 max_sge; /* Maximum # of scatter/gather entries 257 * per Work Request supported 258 */ 259 u16 max_inline; 260 u32 max_sqe; /* Maximum number of send outstanding send work 261 * requests on any Work Queue supported 262 */ 263 u32 max_rqe; /* Maximum number of receive outstanding receive 264 * work requests on any Work Queue supported 265 */ 266 u8 max_qp_resp_rd_atomic_resc; /* Maximum number of RDMA Reads 267 * & atomic operation that can 268 * be outstanding per QP 269 */ 270 271 u8 max_qp_req_rd_atomic_resc; /* The maximum depth per QP for 272 * initiation of RDMA Read 273 * & atomic operations 274 */ 275 u64 max_dev_resp_rd_atomic_resc; 276 u32 max_cq; 277 u32 max_qp; 278 u32 max_mr; /* Maximum # of MRs supported */ 279 u64 max_mr_size; /* Size (in bytes) of largest contiguous memory 280 * block that can be registered by this device 281 */ 282 u32 max_cqe; 283 u32 max_mw; /* Maximum # of memory windows supported */ 284 u32 max_fmr; 285 u32 max_mr_mw_fmr_pbl; 286 u64 max_mr_mw_fmr_size; 287 u32 max_pd; /* Maximum # of protection domains supported */ 288 u32 max_ah; 289 u8 max_pkey; 290 u32 max_srq; /* Maximum number of SRQs */ 291 u32 max_srq_wr; /* Maximum number of WRs per SRQ */ 292 u8 max_srq_sge; /* Maximum number of SGE per WQE */ 293 u8 max_stats_queues; /* Maximum number of statistics queues */ 294 u32 dev_caps; 295 296 /* Abilty to support RNR-NAK generation */ 297 298 #define QLNXR_ROCE_DEV_CAP_RNR_NAK_MASK 0x1 299 #define QLNXR_ROCE_DEV_CAP_RNR_NAK_SHIFT 0 300 /* Abilty to support shutdown port */ 301 #define QLNXR_ROCE_DEV_CAP_SHUTDOWN_PORT_MASK 0x1 302 #define QLNXR_ROCE_DEV_CAP_SHUTDOWN_PORT_SHIFT 1 303 /* Abilty to support port active event */ 304 #define QLNXR_ROCE_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1 305 #define QLNXR_ROCE_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2 306 /* Abilty to support port change event */ 307 #define QLNXR_ROCE_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1 308 #define QLNXR_ROCE_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3 309 /* Abilty to support system image GUID */ 310 #define QLNXR_ROCE_DEV_CAP_SYS_IMAGE_MASK 0x1 311 #define QLNXR_ROCE_DEV_CAP_SYS_IMAGE_SHIFT 4 312 /* Abilty to support bad P_Key counter support */ 313 #define QLNXR_ROCE_DEV_CAP_BAD_PKEY_CNT_MASK 0x1 314 #define QLNXR_ROCE_DEV_CAP_BAD_PKEY_CNT_SHIFT 5 315 /* Abilty to support atomic operations */ 316 #define QLNXR_ROCE_DEV_CAP_ATOMIC_OP_MASK 0x1 317 #define QLNXR_ROCE_DEV_CAP_ATOMIC_OP_SHIFT 6 318 #define QLNXR_ROCE_DEV_CAP_RESIZE_CQ_MASK 0x1 319 #define QLNXR_ROCE_DEV_CAP_RESIZE_CQ_SHIFT 7 320 /* Abilty to support modifying the maximum number of 321 * outstanding work requests per QP 322 */ 323 #define QLNXR_ROCE_DEV_CAP_RESIZE_MAX_WR_MASK 0x1 324 #define QLNXR_ROCE_DEV_CAP_RESIZE_MAX_WR_SHIFT 8 325 326 /* Abilty to support automatic path migration */ 327 #define QLNXR_ROCE_DEV_CAP_AUTO_PATH_MIG_MASK 0x1 328 #define QLNXR_ROCE_DEV_CAP_AUTO_PATH_MIG_SHIFT 9 329 /* Abilty to support the base memory management extensions */ 330 #define QLNXR_ROCE_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1 331 #define QLNXR_ROCE_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10 332 #define QLNXR_ROCE_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1 333 #define QLNXR_ROCE_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11 334 /* Abilty to support multipile page sizes per memory region */ 335 #define QLNXR_ROCE_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1 336 #define QLNXR_ROCE_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12 337 /* Abilty to support block list physical buffer list */ 338 #define QLNXR_ROCE_DEV_CAP_BLOCK_MODE_MASK 0x1 339 #define QLNXR_ROCE_DEV_CAP_BLOCK_MODE_SHIFT 13 340 /* Abilty to support zero based virtual addresses */ 341 #define QLNXR_ROCE_DEV_CAP_ZBVA_MASK 0x1 342 #define QLNXR_ROCE_DEV_CAP_ZBVA_SHIFT 14 343 /* Abilty to support local invalidate fencing */ 344 #define QLNXR_ROCE_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1 345 #define QLNXR_ROCE_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15 346 /* Abilty to support Loopback on QP */ 347 #define QLNXR_ROCE_DEV_CAP_LB_INDICATOR_MASK 0x1 348 #define QLNXR_ROCE_DEV_CAP_LB_INDICATOR_SHIFT 16 349 u64 page_size_caps; 350 u8 dev_ack_delay; 351 u32 reserved_lkey; /* Value of reserved L_key */ 352 u32 bad_pkey_counter;/* Bad P_key counter support 353 * indicator 354 */ 355 struct ecore_rdma_events events; 356 }; 357 358 struct qlnxr_dev { 359 struct ib_device ibdev; 360 qlnx_host_t *ha; 361 struct ecore_dev *cdev; 362 363 /* Added to extend Applications Support */ 364 struct pci_dev pdev; 365 uint32_t dp_module; 366 uint8_t dp_level; 367 368 void *rdma_ctx; 369 370 struct mtx idr_lock; 371 struct idr qpidr; 372 373 uint32_t wq_multiplier; 374 int num_cnq; 375 376 struct ecore_sb_info sb_array[QLNXR_MAX_MSIX]; 377 struct qlnxr_cnq cnq_array[QLNXR_MAX_MSIX]; 378 379 int sb_start; 380 381 int gsi_qp_created; 382 struct qlnxr_cq *gsi_sqcq; 383 struct qlnxr_cq *gsi_rqcq; 384 struct qlnxr_qp *gsi_qp; 385 386 /* TBD: we'll need an array of these probablly per DPI... */ 387 void __iomem *db_addr; 388 uint64_t db_phys_addr; 389 uint32_t db_size; 390 uint16_t dpi; 391 392 uint64_t guid; 393 enum ib_atomic_cap atomic_cap; 394 395 union ib_gid sgid_tbl[QLNXR_MAX_SGID]; 396 struct mtx sgid_lock; 397 struct notifier_block nb_inet; 398 struct notifier_block nb_inet6; 399 400 uint8_t mr_key; 401 struct list_head entry; 402 403 struct dentry *dbgfs; 404 405 uint8_t gsi_ll2_mac_address[ETH_ALEN]; 406 uint8_t gsi_ll2_handle; 407 408 unsigned long enet_state; 409 410 struct workqueue_struct *iwarp_wq; 411 412 volatile uint32_t pd_count; 413 struct qlnxr_device_attr attr; 414 uint8_t user_dpm_enabled; 415 }; 416 417 typedef struct qlnxr_dev qlnxr_dev_t; 418 419 struct qlnxr_pd { 420 struct ib_pd ibpd; 421 u32 pd_id; 422 struct qlnxr_ucontext *uctx; 423 }; 424 425 struct qlnxr_ucontext { 426 struct ib_ucontext ibucontext; 427 struct qlnxr_dev *dev; 428 struct qlnxr_pd *pd; 429 u64 dpi_addr; 430 u64 dpi_phys_addr; 431 u32 dpi_size; 432 u16 dpi; 433 434 struct list_head mm_head; 435 struct mutex mm_list_lock; 436 }; 437 438 struct qlnxr_dev_attr { 439 struct ib_device_attr ib_attr; 440 }; 441 442 struct qlnxr_dma_mem { 443 void *va; 444 dma_addr_t pa; 445 u32 size; 446 }; 447 448 struct qlnxr_pbl { 449 struct list_head list_entry; 450 void *va; 451 dma_addr_t pa; 452 }; 453 454 struct qlnxr_queue_info { 455 void *va; 456 dma_addr_t dma; 457 u32 size; 458 u16 len; 459 u16 entry_size; /* Size of an element in the queue */ 460 u16 id; /* qid, where to ring the doorbell. */ 461 u16 head, tail; 462 bool created; 463 }; 464 465 struct qlnxr_eq { 466 struct qlnxr_queue_info q; 467 u32 vector; 468 int cq_cnt; 469 struct qlnxr_dev *dev; 470 char irq_name[32]; 471 }; 472 473 struct qlnxr_mq { 474 struct qlnxr_queue_info sq; 475 struct qlnxr_queue_info cq; 476 bool rearm_cq; 477 }; 478 479 struct phy_info { 480 u16 auto_speeds_supported; 481 u16 fixed_speeds_supported; 482 u16 phy_type; 483 u16 interface_type; 484 }; 485 486 union db_prod64 { 487 struct rdma_pwm_val32_data data; 488 u64 raw; 489 }; 490 491 enum qlnxr_cq_type { 492 QLNXR_CQ_TYPE_GSI, 493 QLNXR_CQ_TYPE_KERNEL, 494 QLNXR_CQ_TYPE_USER 495 }; 496 497 struct qlnxr_pbl_info { 498 u32 num_pbls; 499 u32 num_pbes; 500 u32 pbl_size; 501 u32 pbe_size; 502 bool two_layered; 503 }; 504 505 struct qlnxr_userq { 506 struct ib_umem *umem; 507 struct qlnxr_pbl_info pbl_info; 508 struct qlnxr_pbl *pbl_tbl; 509 u64 buf_addr; 510 size_t buf_len; 511 }; 512 513 struct qlnxr_cq { 514 struct ib_cq ibcq; /* must be first */ 515 516 enum qlnxr_cq_type cq_type; 517 uint32_t sig; 518 uint16_t icid; 519 520 /* relevant to cqs created from kernel space only (ULPs) */ 521 spinlock_t cq_lock; 522 uint8_t arm_flags; 523 struct ecore_chain pbl; 524 525 void __iomem *db_addr; /* db address for cons update*/ 526 union db_prod64 db; 527 528 uint8_t pbl_toggle; 529 union rdma_cqe *latest_cqe; 530 union rdma_cqe *toggle_cqe; 531 532 /* TODO: remove since it is redundant with 32 bit chains */ 533 uint32_t cq_cons; 534 535 /* relevant to cqs created from user space only (applications) */ 536 struct qlnxr_userq q; 537 538 /* destroy-IRQ handler race prevention */ 539 uint8_t destroyed; 540 uint16_t cnq_notif; 541 }; 542 543 struct qlnxr_ah { 544 struct ib_ah ibah; 545 struct ib_ah_attr attr; 546 }; 547 548 union db_prod32 { 549 struct rdma_pwm_val16_data data; 550 u32 raw; 551 }; 552 553 struct qlnxr_qp_hwq_info { 554 /* WQE Elements*/ 555 struct ecore_chain pbl; 556 u64 p_phys_addr_tbl; 557 u32 max_sges; 558 559 /* WQE */ 560 u16 prod; /* WQE prod index for SW ring */ 561 u16 cons; /* WQE cons index for SW ring */ 562 u16 wqe_cons; 563 u16 gsi_cons; /* filled in by GSI implementation */ 564 u16 max_wr; 565 566 /* DB */ 567 void __iomem *db; /* Doorbell address */ 568 union db_prod32 db_data; /* Doorbell data */ 569 570 /* Required for iwarp_only */ 571 void __iomem *iwarp_db2; /* Doorbell address */ 572 union db_prod32 iwarp_db2_data; /* Doorbell data */ 573 }; 574 575 #define QLNXR_INC_SW_IDX(p_info, index) \ 576 do { \ 577 p_info->index = (p_info->index + 1) & \ 578 ecore_chain_get_capacity(p_info->pbl) \ 579 } while (0) 580 581 struct qlnxr_srq_hwq_info { 582 u32 max_sges; 583 u32 max_wr; 584 struct ecore_chain pbl; 585 u64 p_phys_addr_tbl; 586 u32 wqe_prod; /* WQE prod index in HW ring */ 587 u32 sge_prod; /* SGE prod index in HW ring */ 588 u32 wr_prod_cnt; /* wr producer count */ 589 u32 wr_cons_cnt; /* wr consumer count */ 590 u32 num_elems; 591 592 u32 *virt_prod_pair_addr; /* producer pair virtual address */ 593 dma_addr_t phy_prod_pair_addr; /* producer pair physical address */ 594 }; 595 596 struct qlnxr_srq { 597 struct ib_srq ibsrq; 598 struct qlnxr_dev *dev; 599 /* relevant to cqs created from user space only (applications) */ 600 struct qlnxr_userq usrq; 601 struct qlnxr_srq_hwq_info hw_srq; 602 struct ib_umem *prod_umem; 603 u16 srq_id; 604 /* lock to protect srq recv post */ 605 spinlock_t lock; 606 }; 607 608 enum qlnxr_qp_err_bitmap { 609 QLNXR_QP_ERR_SQ_FULL = 1 << 0, 610 QLNXR_QP_ERR_RQ_FULL = 1 << 1, 611 QLNXR_QP_ERR_BAD_SR = 1 << 2, 612 QLNXR_QP_ERR_BAD_RR = 1 << 3, 613 QLNXR_QP_ERR_SQ_PBL_FULL = 1 << 4, 614 QLNXR_QP_ERR_RQ_PBL_FULL = 1 << 5, 615 }; 616 617 struct mr_info { 618 struct qlnxr_pbl *pbl_table; 619 struct qlnxr_pbl_info pbl_info; 620 struct list_head free_pbl_list; 621 struct list_head inuse_pbl_list; 622 u32 completed; 623 u32 completed_handled; 624 }; 625 626 struct qlnxr_qp { 627 struct ib_qp ibqp; /* must be first */ 628 struct qlnxr_dev *dev; 629 struct qlnxr_iw_ep *ep; 630 struct qlnxr_qp_hwq_info sq; 631 struct qlnxr_qp_hwq_info rq; 632 633 u32 max_inline_data; 634 635 spinlock_t q_lock ____cacheline_aligned; 636 637 struct qlnxr_cq *sq_cq; 638 struct qlnxr_cq *rq_cq; 639 struct qlnxr_srq *srq; 640 enum ecore_roce_qp_state state; /* QP state */ 641 u32 id; 642 struct qlnxr_pd *pd; 643 enum ib_qp_type qp_type; 644 struct ecore_rdma_qp *ecore_qp; 645 u32 qp_id; 646 u16 icid; 647 u16 mtu; 648 int sgid_idx; 649 u32 rq_psn; 650 u32 sq_psn; 651 u32 qkey; 652 u32 dest_qp_num; 653 u32 sig; /* unique siganture to identify valid QP */ 654 655 /* relevant to qps created from kernel space only (ULPs) */ 656 u8 prev_wqe_size; 657 u16 wqe_cons; 658 u32 err_bitmap; 659 bool signaled; 660 /* SQ shadow */ 661 struct { 662 u64 wr_id; 663 enum ib_wc_opcode opcode; 664 u32 bytes_len; 665 u8 wqe_size; 666 bool signaled; 667 dma_addr_t icrc_mapping; 668 u32 *icrc; 669 struct qlnxr_mr *mr; 670 } *wqe_wr_id; 671 672 /* RQ shadow */ 673 struct { 674 u64 wr_id; 675 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE]; 676 uint8_t wqe_size; 677 678 /* for GSI only */ 679 u8 smac[ETH_ALEN]; 680 u16 vlan_id; 681 int rc; 682 } *rqe_wr_id; 683 684 /* relevant to qps created from user space only (applications) */ 685 struct qlnxr_userq usq; 686 struct qlnxr_userq urq; 687 atomic_t refcnt; 688 bool destroyed; 689 }; 690 691 enum qlnxr_mr_type { 692 QLNXR_MR_USER, 693 QLNXR_MR_KERNEL, 694 QLNXR_MR_DMA, 695 QLNXR_MR_FRMR 696 }; 697 698 struct qlnxr_mr { 699 struct ib_mr ibmr; 700 struct ib_umem *umem; 701 702 struct ecore_rdma_register_tid_in_params hw_mr; 703 enum qlnxr_mr_type type; 704 705 struct qlnxr_dev *dev; 706 struct mr_info info; 707 708 u64 *pages; 709 u32 npages; 710 711 u64 *iova_start; /* valid only for kernel_mr */ 712 }; 713 714 struct qlnxr_mm { 715 struct { 716 u64 phy_addr; 717 unsigned long len; 718 } key; 719 struct list_head entry; 720 }; 721 722 struct qlnxr_iw_listener { 723 struct qlnxr_dev *dev; 724 struct iw_cm_id *cm_id; 725 int backlog; 726 void *ecore_handle; 727 }; 728 729 struct qlnxr_iw_ep { 730 struct qlnxr_dev *dev; 731 struct iw_cm_id *cm_id; 732 struct qlnxr_qp *qp; 733 void *ecore_context; 734 u8 during_connect; 735 }; 736 737 static inline void 738 qlnxr_inc_sw_cons(struct qlnxr_qp_hwq_info *info) 739 { 740 info->cons = (info->cons + 1) % info->max_wr; 741 info->wqe_cons++; 742 } 743 744 static inline void 745 qlnxr_inc_sw_prod(struct qlnxr_qp_hwq_info *info) 746 { 747 info->prod = (info->prod + 1) % info->max_wr; 748 } 749 750 static inline struct qlnxr_dev * 751 get_qlnxr_dev(struct ib_device *ibdev) 752 { 753 return container_of(ibdev, struct qlnxr_dev, ibdev); 754 } 755 756 static inline struct qlnxr_ucontext * 757 get_qlnxr_ucontext(struct ib_ucontext *ibucontext) 758 { 759 return container_of(ibucontext, struct qlnxr_ucontext, ibucontext); 760 } 761 762 static inline struct qlnxr_pd * 763 get_qlnxr_pd(struct ib_pd *ibpd) 764 { 765 return container_of(ibpd, struct qlnxr_pd, ibpd); 766 } 767 768 static inline struct qlnxr_cq * 769 get_qlnxr_cq(struct ib_cq *ibcq) 770 { 771 return container_of(ibcq, struct qlnxr_cq, ibcq); 772 } 773 774 static inline struct qlnxr_qp * 775 get_qlnxr_qp(struct ib_qp *ibqp) 776 { 777 return container_of(ibqp, struct qlnxr_qp, ibqp); 778 } 779 780 static inline struct qlnxr_mr * 781 get_qlnxr_mr(struct ib_mr *ibmr) 782 { 783 return container_of(ibmr, struct qlnxr_mr, ibmr); 784 } 785 786 static inline struct qlnxr_ah * 787 get_qlnxr_ah(struct ib_ah *ibah) 788 { 789 return container_of(ibah, struct qlnxr_ah, ibah); 790 } 791 792 static inline struct qlnxr_srq * 793 get_qlnxr_srq(struct ib_srq *ibsrq) 794 { 795 return container_of(ibsrq, struct qlnxr_srq, ibsrq); 796 } 797 798 static inline bool qlnxr_qp_has_srq(struct qlnxr_qp *qp) 799 { 800 return !!qp->srq; 801 } 802 803 static inline bool qlnxr_qp_has_sq(struct qlnxr_qp *qp) 804 { 805 if (qp->qp_type == IB_QPT_GSI) 806 return 0; 807 808 return 1; 809 } 810 811 static inline bool qlnxr_qp_has_rq(struct qlnxr_qp *qp) 812 { 813 if (qp->qp_type == IB_QPT_GSI || qlnxr_qp_has_srq(qp)) 814 return 0; 815 816 return 1; 817 } 818 819 #define SET_FIELD2(value, name, flag) \ 820 do { \ 821 (value) |= ((flag) << (name ## _SHIFT)); \ 822 } while (0) 823 824 #define QLNXR_RESP_IMM (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \ 825 RDMA_CQE_RESPONDER_IMM_FLG_SHIFT) 826 #define QLNXR_RESP_RDMA (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \ 827 RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT) 828 #define QLNXR_RESP_INV (RDMA_CQE_RESPONDER_INV_FLG_MASK << \ 829 RDMA_CQE_RESPONDER_INV_FLG_SHIFT) 830 831 #define QLNXR_RESP_RDMA_IMM (QLNXR_RESP_IMM | QLNXR_RESP_RDMA) 832 833 static inline int 834 qlnxr_get_dmac(struct qlnxr_dev *dev, struct ib_ah_attr *ah_attr, u8 *mac_addr) 835 { 836 #ifdef DEFINE_NO_IP_BASED_GIDS 837 u8 *guid = &ah_attr->grh.dgid.raw[8]; /* GID's 64 MSBs are the GUID */ 838 #endif 839 union ib_gid zero_sgid = { { 0 } }; 840 struct in6_addr in6; 841 842 if (!memcmp(&ah_attr->grh.dgid, &zero_sgid, sizeof(union ib_gid))) { 843 memset(mac_addr, 0x00, ETH_ALEN); 844 return -EINVAL; 845 } 846 847 memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6)); 848 849 #ifdef DEFINE_NO_IP_BASED_GIDS 850 /* get the MAC address from the GUID i.e. EUI-64 to MAC address */ 851 mac_addr[0] = guid[0] ^ 2; /* toggle the local/universal bit to local */ 852 mac_addr[1] = guid[1]; 853 mac_addr[2] = guid[2]; 854 mac_addr[3] = guid[5]; 855 mac_addr[4] = guid[6]; 856 mac_addr[5] = guid[7]; 857 #else 858 memcpy(mac_addr, ah_attr->dmac, ETH_ALEN); 859 #endif 860 return 0; 861 } 862 863 extern int qlnx_rdma_ll2_set_mac_filter(void *rdma_ctx, uint8_t *old_mac_address, 864 uint8_t *new_mac_address); 865 866 #define QLNXR_ROCE_PKEY_MAX 1 867 #define QLNXR_ROCE_PKEY_TABLE_LEN 1 868 #define QLNXR_ROCE_PKEY_DEFAULT 0xffff 869 870 #define QLNX_IS_IWARP(rdev) IS_IWARP(ECORE_LEADING_HWFN(rdev->cdev)) 871 #define QLNX_IS_ROCE(rdev) IS_ROCE(ECORE_LEADING_HWFN(rdev->cdev)) 872 873 #define MAX_RXMIT_CONNS 16 874 875 #endif /* #ifndef __QLNX_DEF_H_ */ 876