1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 32 #ifndef _PCICS_REG_DRIVER_H 33 #define _PCICS_REG_DRIVER_H 34 35 /* offset of configuration space in the pci core register */ 36 #define PCICFG_OFFSET 0x2000 37 #define PCICFG_VENDOR_ID_OFFSET 0x00 38 #define PCICFG_DEVICE_ID_OFFSET 0x02 39 #define PCICFG_COMMAND_OFFSET 0x04 40 #define PCICFG_COMMAND_IO_SPACE (1<<0) 41 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 42 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 43 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 44 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 45 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 46 #define PCICFG_COMMAND_PERR_ENA (1<<6) 47 #define PCICFG_COMMAND_STEPPING (1<<7) 48 #define PCICFG_COMMAND_SERR_ENA (1<<8) 49 #define PCICFG_COMMAND_FAST_B2B (1<<9) 50 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 51 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 52 #define PCICFG_STATUS_OFFSET 0x06 53 #define PCICFG_REVISION_ID_OFFSET 0x08 54 #define PCICFG_REVESION_ID_MASK 0xff 55 #define PCICFG_REVESION_ID_ERROR_VAL 0xff 56 #define PCICFG_CACHE_LINE_SIZE 0x0c 57 #define PCICFG_LATENCY_TIMER 0x0d 58 #define PCICFG_HEADER_TYPE 0x0e 59 #define PCICFG_HEADER_TYPE_NORMAL 0 60 #define PCICFG_HEADER_TYPE_BRIDGE 1 61 #define PCICFG_HEADER_TYPE_CARDBUS 2 62 #define PCICFG_BAR_1_LOW 0x10 63 #define PCICFG_BAR_1_HIGH 0x14 64 #define PCICFG_BAR_2_LOW 0x18 65 #define PCICFG_BAR_2_HIGH 0x1c 66 #define PCICFG_BAR_3_LOW 0x20 67 #define PCICFG_BAR_3_HIGH 0x24 68 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 69 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 70 #define PCICFG_INT_LINE 0x3c 71 #define PCICFG_INT_PIN 0x3d 72 #define PCICFG_PM_CAPABILITY 0x48 73 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 74 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 75 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 76 #define PCICFG_PM_CAPABILITY_DSI (1<<21) 77 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 78 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 79 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 80 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 81 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 82 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 83 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 84 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 85 #define PCICFG_PM_CSR_OFFSET 0x4c 86 #define PCICFG_PM_CSR_STATE (0x3<<0) 87 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 88 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 89 #define PCICFG_MSI_CAP_ID_OFFSET 0x58 90 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 91 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 92 #define PCICFG_MSI_CONTROL_MENA (0x7<<20) 93 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 94 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 95 #define PCICFG_GRC_ADDRESS 0x78 96 #define PCICFG_GRC_DATA 0x80 97 #define PCICFG_ME_REGISTER 0x98 98 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 99 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 100 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 101 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 102 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 103 104 #define PCICFG_DEVICE_CONTROL 0xb4 105 #define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21) 106 #define PCICFG_DEVICE_STATUS 0xb6 107 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 108 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 109 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 110 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 111 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 112 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 113 #define PCICFG_LINK_CONTROL 0xbc 114 #define PCICFG_DEVICE_STATUS_CONTROL_2 (0xd4) 115 #define PCICFG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE (1<<6) 116 117 /* config_2 offset */ 118 #define GRC_CONFIG_2_SIZE_REG 0x408 119 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 120 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 121 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 122 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 123 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 124 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 125 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 126 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 127 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 128 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 129 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 130 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 131 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 132 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 133 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 134 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 135 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 136 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 137 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 138 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 139 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 140 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 141 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 142 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 143 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 144 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 145 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 146 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 147 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 148 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 149 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 150 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 151 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 152 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 153 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 154 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 155 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 156 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 157 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 158 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 159 160 /* config_3 offset */ 161 #define GRC_CONFIG_3_SIZE_REG 0x40c 162 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 163 #define PCI_CONFIG_3_FORCE_PME (1L<<24) 164 #define PCI_CONFIG_3_PME_STATUS (1L<<25) 165 #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 166 #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 167 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 168 #define PCI_CONFIG_3_PCI_POWER (1L<<31) 169 170 #define GRC_REG_DEVICE_CONTROL 0x4d8 171 172 /* When VF Enable is cleared(after it was previously set), 173 * this register will read a value of 1, indicating that all the 174 * VFs that belong to this PF should be flushed. 175 * Software should clear this bit within 1 second of VF Enable 176 * being set by writing a 1 to it, so that VFs are visible to the system 177 * again.WC 178 */ 179 #define PCIE_SRIOV_DISABLE_IN_PROGRESS (1 << 29) 180 181 /* When FLR is initiated, this register will read a value of 1 indicating 182 * that the Function is in FLR state. Func can be brought out of FLR state 183 * either bywriting 1 to this register (at least 50 ms after FLR was 184 * initiated),or it can also be cleared automatically after 55 ms if 185 * auto_clear bit in private reg space is set. This bit also exists in 186 * VF register space WC 187 */ 188 #define PCIE_FLR_IN_PROGRESS (1 << 27) 189 190 #define GRC_BAR2_CONFIG 0x4e0 191 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 192 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 193 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 194 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 195 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 196 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 197 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 198 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 199 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 200 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 201 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 202 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 203 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 204 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 205 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 206 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 207 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 208 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 209 210 #define GRC_BAR3_CONFIG 0x4f4 211 #define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0) 212 #define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0) 213 #define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0) 214 #define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0) 215 #define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0) 216 #define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0) 217 #define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0) 218 #define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0) 219 #define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0) 220 #define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0) 221 #define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0) 222 #define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0) 223 #define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0) 224 #define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0) 225 #define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0) 226 #define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0) 227 #define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0) 228 #define PCI_CONFIG_2_BAR3_64ENA (1L<<4) 229 #define PCI_PM_DATA_A 0x410 230 #define PCI_PM_DATA_B 0x414 231 #define PCI_ID_VAL1 0x434 232 #define PCI_ID_VAL2 0x438 233 #define PCI_ID_VAL3 0x43c 234 #define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24) 235 #define GRC_CONFIG_REG_VF_BAR_REG_1 0x608 236 #define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf 237 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C 238 239 /* This field resides in VF only and does not exist in PF. 240 * This register controls the read value of the MSIX_CONTROL[10:0] register 241 * in the VF configuration space. A value of "00000000011" indicates 242 * a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ 243 * define in version.v 244 */ 245 #define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK 0x3F 246 #define GRC_CONFIG_REG_PF_INIT_VF 0x624 247 248 /* First VF_NUM for PF is encoded in this register. 249 * The number of VFs assigned to a PF is assumed to be a multiple of 8. 250 * Software should program these bits based on Total Number of VFs programmed 251 * for each PF. 252 * Since registers from 0x000-0x7ff are spilt across functions, each PF will 253 * have the same location for the same 4 bits 254 */ 255 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xff 256 #define PXPCS_TL_CONTROL_5 0x814 257 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 258 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 259 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 260 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 261 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 262 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 263 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 264 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 265 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 266 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 267 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 268 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 269 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 270 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 271 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 272 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 273 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 274 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 275 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 276 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 277 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 278 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 279 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 280 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 281 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 282 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 283 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 284 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 285 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 286 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 287 #define PXPCS_TL_FUNC345_STAT 0x854 288 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 289 290 /*Unsupported Request Error Status in function4, if set, generate 291 *pcie_err_attn output when this error is seen. WC 292 */ 293 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 (1 << 28) 294 295 /*ECRC Error TLP Status Status in function 4, if set, 296 *generate pcie_err_attn output when this error is seen..WC 297 */ 298 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 (1 << 27) 299 300 /*Malformed TLP Status Status in function 4, if set, 301 *generate pcie_err_attn output when this error is seen..WC 302 */ 303 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 (1 << 26) 304 305 /*Receiver Overflow Status Status in function 4, if set, 306 *generate pcie_err_attn output when this error is seen..WC 307 */ 308 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 (1 << 25) 309 310 /*Unexpected Completion Status Status in function 4, if set, 311 *generate pcie_err_attn output when this error is seen..WC 312 */ 313 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 (1 << 24) 314 315 /* Receive UR Statusin function 4. If set, generate pcie_err_attn output 316 * when this error is seen. WC 317 */ 318 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 (1 << 23) 319 320 /* Completer Timeout Status Status in function 4, if set, 321 * generate pcie_err_attn output when this error is seen..WC 322 */ 323 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 (1 << 22) 324 325 /* Flow Control Protocol Error Status Status in function 4, 326 * if set, generate pcie_err_attn output when this error is seen. 327 * WC 328 */ 329 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 (1 << 21) 330 331 /* Poisoned Error Status Status in function 4, if set, generate 332 * pcie_err_attn output when this error is seen..WC 333 */ 334 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 (1 << 20) 335 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 336 337 /* Unsupported Request Error Status in function3, if set, generate 338 * pcie_err_attn output when this error is seen..WC 339 */ 340 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 (1 << 18) 341 342 /* ECRC Error TLP Status Status in function 3, if set, generate 343 * pcie_err_attn output when this error is seen.. WC 344 */ 345 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 (1 << 17) 346 347 /* Malformed TLP Status Status in function 3, if set, generate 348 * pcie_err_attn output when this error is seen..WC 349 */ 350 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 (1 << 16) 351 352 /* Receiver Overflow Status Status in function 3, if set, generate 353 * pcie_err_attn output when this error is seen..WC 354 */ 355 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 (1 << 15) 356 357 /* Unexpected Completion Status Status in function 3, if set, generate 358 * pcie_err_attn output when this error is seen. WC 359 */ 360 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 (1 << 14) 361 362 /* Receive UR Statusin function 3. If set, generate pcie_err_attn output 363 * when this error is seen. WC 364 */ 365 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 (1 << 13) 366 367 /* Completer Timeout Status Status in function 3, if set, generate 368 * pcie_err_attn output when this error is seen..WC 369 */ 370 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 (1 << 12) 371 372 /* Flow Control Protocol Error Status Status in function 3, if set, 373 * generate pcie_err_attn output when this error is seen..WC 374 */ 375 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 (1 << 11) 376 377 /* Poisoned Error Status Status in function 3, if set, generate 378 * pcie_err_attn output when this error is seen..WC 379 */ 380 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 (1 << 10) 381 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 382 383 /* Unsupported Request Error Status for Function 2, if set, 384 * generate pcie_err_attn output when this error is seen. WC 385 */ 386 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 (1 << 8) 387 388 /* ECRC Error TLP Status Status for Function 2, if set, generate 389 * pcie_err_attn output when this error is seen..WC 390 */ 391 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 (1 << 7) 392 393 /* Malformed TLP Status Status for Function 2, if set, generate 394 * pcie_err_attn output when this error is seen.. WC 395 */ 396 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 (1 << 6) 397 398 /* Receiver Overflow Status Status for Function 2, if set, generate 399 * pcie_err_attn output when this error is seen.. WC 400 */ 401 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 (1 << 5) 402 403 /* Unexpected Completion Status Status for Function 2, if set, generate 404 * pcie_err_attn output when this error is seen. WC 405 */ 406 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 (1 << 4) 407 408 /* Receive UR Statusfor Function 2. If set, generate pcie_err_attn output 409 * when this error is seen. WC 410 */ 411 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 (1 << 3) 412 413 /* Completer Timeout Status Status for Function 2, if set, generate 414 * pcie_err_attn output when this error is seen. WC 415 */ 416 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 (1 << 2) 417 418 /* Flow Control Protocol Error Status Status for Function 2, if set, 419 * generate pcie_err_attn output when this error is seen. WC 420 */ 421 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 (1 << 1) 422 423 /* Poisoned Error Status Status for Function 2, if set, generate 424 * pcie_err_attn output when this error is seen.. WC 425 */ 426 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 (1 << 0) 427 #define PXPCS_TL_FUNC678_STAT 0x85C 428 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 429 430 /* Unsupported Request Error Status in function7, if set, generate 431 * pcie_err_attn output when this error is seen. WC 432 */ 433 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 (1 << 28) 434 435 /* ECRC Error TLP Status Status in function 7, if set, generate 436 * pcie_err_attn output when this error is seen.. WC 437 */ 438 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 (1 << 27) 439 440 /* Malformed TLP Status Status in function 7, if set, generate 441 * pcie_err_attn output when this error is seen.. WC 442 */ 443 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 (1 << 26) 444 445 /* Receiver Overflow Status Status in function 7, if set, generate 446 * pcie_err_attn output when this error is seen.. WC 447 */ 448 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 (1 << 25) 449 450 /* Unexpected Completion Status Status in function 7, if set, generate 451 * pcie_err_attn output when this error is seen. WC 452 */ 453 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 (1 << 24) 454 455 /* Receive UR Statusin function 7. If set, generate pcie_err_attn 456 * output when this error is seen. WC 457 */ 458 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 (1 << 23) 459 460 /* Completer Timeout Status Status in function 7, if set, generate 461 * pcie_err_attn output when this error is seen. WC 462 */ 463 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 (1 << 22) 464 465 /* Flow Control Protocol Error Status Status in function 7, if set, 466 * generate pcie_err_attn output when this error is seen. WC 467 */ 468 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 (1 << 21) 469 470 /* Poisoned Error Status Status in function 7, if set, 471 * generate pcie_err_attn output when this error is seen.. WC 472 */ 473 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 (1 << 20) 474 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 475 476 /* Unsupported Request Error Status in function6, if set, generate 477 * pcie_err_attn output when this error is seen. WC 478 */ 479 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 (1 << 18) 480 481 /* ECRC Error TLP Status Status in function 6, if set, generate 482 * pcie_err_attn output when this error is seen.. WC 483 */ 484 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 (1 << 17) 485 486 /* Malformed TLP Status Status in function 6, if set, generate 487 * pcie_err_attn output when this error is seen.. WC 488 */ 489 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 (1 << 16) 490 491 /* Receiver Overflow Status Status in function 6, if set, generate 492 * pcie_err_attn output when this error is seen.. WC 493 */ 494 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 (1 << 15) 495 496 /* Unexpected Completion Status Status in function 6, if set, 497 * generate pcie_err_attn output when this error is seen. WC 498 */ 499 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 (1 << 14) 500 501 /* Receive UR Statusin function 6. If set, generate pcie_err_attn 502 * output when this error is seen. WC 503 */ 504 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 (1 << 13) 505 506 /* Completer Timeout Status Status in function 6, if set, generate 507 * pcie_err_attn output when this error is seen. WC 508 */ 509 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 (1 << 12) 510 511 /* Flow Control Protocol Error Status Status in function 6, if set, 512 * generate pcie_err_attn output when this error is seen. WC 513 */ 514 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 (1 << 11) 515 516 /* Poisoned Error Status Status in function 6, if set, generate 517 * pcie_err_attn output when this error is seen.. WC 518 */ 519 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 (1 << 10) 520 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 521 522 /* Unsupported Request Error Status for Function 5, if set, 523 * generate pcie_err_attn output when this error is seen. WC 524 */ 525 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 (1 << 8) 526 527 /* ECRC Error TLP Status Status for Function 5, if set, generate 528 * pcie_err_attn output when this error is seen.. WC 529 */ 530 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 (1 << 7) 531 532 /* Malformed TLP Status Status for Function 5, if set, generate 533 * pcie_err_attn output when this error is seen.. WC 534 */ 535 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 (1 << 6) 536 537 /* Receiver Overflow Status Status for Function 5, if set, generate 538 * pcie_err_attn output when this error is seen.. WC 539 */ 540 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 (1 << 5) 541 542 /* Unexpected Completion Status Status for Function 5, if set, generate 543 * pcie_err_attn output when this error is seen. WC 544 */ 545 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 (1 << 4) 546 547 /* Receive UR Statusfor Function 5. If set, generate pcie_err_attn output 548 * when this error is seen. WC 549 */ 550 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 (1 << 3) 551 552 /* Completer Timeout Status Status for Function 5, if set, generate 553 * pcie_err_attn output when this error is seen. WC 554 */ 555 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 (1 << 2) 556 557 /* Flow Control Protocol Error Status Status for Function 5, if set, 558 * generate pcie_err_attn output when this error is seen. WC 559 */ 560 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 (1 << 1) 561 562 /* Poisoned Error Status Status for Function 5, if set, 563 * generate pcie_err_attn output when this error is seen.. WC 564 */ 565 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 (1 << 0) 566 567 /* PCI CAPABILITIES 568 */ 569 570 #define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/ 571 572 #define PCIE_DEV_CAPS 0x04 573 #ifndef PCIE_DEV_CAPS_FLR_CAPABILITY 574 #define PCIE_DEV_CAPS_FLR_CAPABILITY (1 << 28) 575 #endif 576 577 #define PCIE_DEV_CTRL 0x08 578 #define PCIE_DEV_CTRL_FLR 0x8000 579 580 #define PCIE_DEV_STATUS 0x0A 581 #ifndef PCIE_DEV_STATUS_PENDING_TRANSACTION 582 #define PCIE_DEV_STATUS_PENDING_TRANSACTION (1 << 5) 583 #endif 584 585 #ifndef PCI_CAPABILITY_LIST 586 /* Ofset of first capability list entry */ 587 #define PCI_CAPABILITY_LIST 0x34 588 #endif 589 590 #define PCI_CAPABILITY_LIST_MASK 0xff 591 592 #ifndef PCI_CB_CAPABILITY_LIST 593 #define PCI_CB_CAPABILITY_LIST 0x14 594 #endif 595 596 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID)) 597 #define PCI_CAP_LIST_ID_DEF 598 #endif 599 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT)) 600 #define PCI_CAP_LIST_NEXT_DEF 601 #endif 602 #if (defined(__LINUX)) || (defined(PCI_STATUS)) 603 #define PCI_STATUS_DEF 604 #endif 605 #if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST)) 606 #define PCI_STATUS_CAP_LIST_DEF 607 #endif 608 609 #ifndef PCI_CAP_LIST_ID_DEF 610 #define PCI_CAP_LIST_ID 0x0 /* Capability ID */ 611 #endif 612 613 #define PCI_CAP_LIST_ID_MASK 0xff 614 615 #ifndef PCI_CAP_LIST_NEXT_DEF 616 /* Next capability in the list */ 617 #define PCI_CAP_LIST_NEXT 0x1 618 #endif 619 620 #define PCI_CAP_LIST_NEXT_MASK 0xff 621 622 #ifndef PCI_STATUS_DEF 623 #define PCI_STATUS 0x6 /* 16 bits */ 624 #endif 625 #ifndef PCI_STATUS_CAP_LIST_DEF 626 /* Support Capability List */ 627 #define PCI_STATUS_CAP_LIST 0x10 628 #endif 629 630 #ifndef PCI_SRIOV_CAP 631 632 /* Some PCI Config defines... need to put this in a better location... */ 633 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 634 #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 635 #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 636 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 637 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 638 #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ 639 #define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ 640 #define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ 641 #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ 642 #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ 643 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 644 #define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ 645 #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 646 #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 647 #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 648 #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 649 #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 650 #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 651 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 652 #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 653 #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ 654 655 #endif 656 657 #ifndef PCI_CAP_ID_EXP 658 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 659 #endif 660 #ifndef PCI_EXP_DEVCTL 661 #define PCI_EXP_DEVCTL 8 /* Device Control */ 662 #endif 663 #ifndef PCI_EXP_DEVCTL_RELAX_EN 664 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 665 #endif 666 667 #endif 668