1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef _PCICS_REG_DRIVER_H 32 #define _PCICS_REG_DRIVER_H 33 34 /* offset of configuration space in the pci core register */ 35 #ifndef __EXTRACT__LINUX__ 36 #define PCICFG_OFFSET 0x2000 37 #endif 38 #define PCICFG_VENDOR_ID_OFFSET 0x00 39 #define PCICFG_DEVICE_ID_OFFSET 0x02 40 #define PCICFG_COMMAND_OFFSET 0x04 41 #define PCICFG_COMMAND_IO_SPACE (1<<0) 42 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 43 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 44 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 45 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 46 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 47 #define PCICFG_COMMAND_PERR_ENA (1<<6) 48 #define PCICFG_COMMAND_STEPPING (1<<7) 49 #define PCICFG_COMMAND_SERR_ENA (1<<8) 50 #define PCICFG_COMMAND_FAST_B2B (1<<9) 51 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 52 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 53 #define PCICFG_STATUS_OFFSET 0x06 54 #define PCICFG_REVISION_ID_OFFSET 0x08 55 #define PCICFG_REVESION_ID_MASK 0xff 56 #define PCICFG_REVESION_ID_ERROR_VAL 0xff 57 #define PCICFG_CACHE_LINE_SIZE 0x0c 58 #define PCICFG_LATENCY_TIMER 0x0d 59 #define PCICFG_HEADER_TYPE 0x0e 60 #define PCICFG_HEADER_TYPE_NORMAL 0 61 #define PCICFG_HEADER_TYPE_BRIDGE 1 62 #define PCICFG_HEADER_TYPE_CARDBUS 2 63 #define PCICFG_BAR_1_LOW 0x10 64 #define PCICFG_BAR_1_HIGH 0x14 65 #define PCICFG_BAR_2_LOW 0x18 66 #define PCICFG_BAR_2_HIGH 0x1c 67 #define PCICFG_BAR_3_LOW 0x20 68 #define PCICFG_BAR_3_HIGH 0x24 69 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 70 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 71 #define PCICFG_INT_LINE 0x3c 72 #define PCICFG_INT_PIN 0x3d 73 #define PCICFG_PM_CAPABILITY 0x48 74 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 75 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 76 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 77 #define PCICFG_PM_CAPABILITY_DSI (1<<21) 78 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 79 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 80 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 81 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 82 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 83 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 84 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 85 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 86 #define PCICFG_PM_CSR_OFFSET 0x4c 87 #define PCICFG_PM_CSR_STATE (0x3<<0) 88 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 89 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 90 #define PCICFG_MSI_CAP_ID_OFFSET 0x58 91 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 92 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 93 #define PCICFG_MSI_CONTROL_MENA (0x7<<20) 94 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 95 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 96 #define PCICFG_GRC_ADDRESS 0x78 97 #define PCICFG_GRC_DATA 0x80 98 #define PCICFG_ME_REGISTER 0x98 99 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 100 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 101 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 102 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 103 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 104 105 #define PCICFG_DEVICE_CONTROL 0xb4 106 #define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21) 107 #define PCICFG_DEVICE_STATUS 0xb6 108 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 109 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 110 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 111 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 112 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 113 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 114 #define PCICFG_LINK_CONTROL 0xbc 115 #define PCICFG_DEVICE_STATUS_CONTROL_2 (0xd4) 116 #define PCICFG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE (1<<6) 117 118 /* config_2 offset */ 119 #define GRC_CONFIG_2_SIZE_REG 0x408 120 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 121 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 122 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 123 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 124 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 125 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 126 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 127 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 128 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 129 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 130 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 131 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 132 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 133 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 134 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 135 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 136 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 137 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 138 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 139 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 140 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 141 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 142 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 143 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 144 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 145 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 146 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 147 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 148 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 149 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 150 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 151 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 152 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 153 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 154 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 155 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 156 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 157 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 158 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 159 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 160 161 /* config_3 offset */ 162 #define GRC_CONFIG_3_SIZE_REG 0x40c 163 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 164 #define PCI_CONFIG_3_FORCE_PME (1L<<24) 165 #define PCI_CONFIG_3_PME_STATUS (1L<<25) 166 #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 167 #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 168 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 169 #define PCI_CONFIG_3_PCI_POWER (1L<<31) 170 171 #define GRC_REG_DEVICE_CONTROL 0x4d8 172 173 /* When VF Enable is cleared(after it was previously set), 174 * this register will read a value of 1, indicating that all the 175 * VFs that belong to this PF should be flushed. 176 * Software should clear this bit within 1 second of VF Enable 177 * being set by writing a 1 to it, so that VFs are visible to the system 178 * again.WC 179 */ 180 #define PCIE_SRIOV_DISABLE_IN_PROGRESS (1 << 29) 181 182 /* When FLR is initiated, this register will read a value of 1 indicating 183 * that the Function is in FLR state. Func can be brought out of FLR state 184 * either bywriting 1 to this register (at least 50 ms after FLR was 185 * initiated),or it can also be cleared automatically after 55 ms if 186 * auto_clear bit in private reg space is set. This bit also exists in 187 * VF register space WC 188 */ 189 #define PCIE_FLR_IN_PROGRESS (1 << 27) 190 191 #define GRC_BAR2_CONFIG 0x4e0 192 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 193 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 194 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 195 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 196 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 197 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 198 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 199 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 200 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 201 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 202 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 203 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 204 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 205 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 206 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 207 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 208 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 209 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 210 211 #define GRC_BAR3_CONFIG 0x4f4 212 #define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0) 213 #define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0) 214 #define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0) 215 #define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0) 216 #define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0) 217 #define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0) 218 #define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0) 219 #define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0) 220 #define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0) 221 #define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0) 222 #define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0) 223 #define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0) 224 #define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0) 225 #define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0) 226 #define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0) 227 #define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0) 228 #define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0) 229 #define PCI_CONFIG_2_BAR3_64ENA (1L<<4) 230 #define PCI_PM_DATA_A 0x410 231 #define PCI_PM_DATA_B 0x414 232 #define PCI_ID_VAL1 0x434 233 #define PCI_ID_VAL2 0x438 234 #define PCI_ID_VAL3 0x43c 235 #define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24) 236 #define GRC_CONFIG_REG_VF_BAR_REG_1 0x608 237 #define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf 238 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C 239 240 /* This field resides in VF only and does not exist in PF. 241 * This register controls the read value of the MSIX_CONTROL[10:0] register 242 * in the VF configuration space. A value of "00000000011" indicates 243 * a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ 244 * define in version.v 245 */ 246 #define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK 0x3F 247 #ifndef __EXTRACT__LINUX__ 248 #define GRC_CONFIG_REG_PF_INIT_VF 0x624 249 250 /* First VF_NUM for PF is encoded in this register. 251 * The number of VFs assigned to a PF is assumed to be a multiple of 8. 252 * Software should program these bits based on Total Number of VFs programmed 253 * for each PF. 254 * Since registers from 0x000-0x7ff are spilt across functions, each PF will 255 * have the same location for the same 4 bits 256 */ 257 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xff 258 #endif 259 #define PXPCS_TL_CONTROL_5 0x814 260 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 261 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 262 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 263 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 264 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 265 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 266 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 267 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 268 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 269 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 270 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 271 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 272 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 273 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 274 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 275 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 276 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 277 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 278 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 279 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 280 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 281 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 282 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 283 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 284 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 285 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 286 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 287 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 288 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 289 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 290 #define PXPCS_TL_FUNC345_STAT 0x854 291 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 292 293 /*Unsupported Request Error Status in function4, if set, generate 294 *pcie_err_attn output when this error is seen. WC 295 */ 296 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 (1 << 28) 297 298 /*ECRC Error TLP Status Status in function 4, if set, 299 *generate pcie_err_attn output when this error is seen..WC 300 */ 301 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 (1 << 27) 302 303 /*Malformed TLP Status Status in function 4, if set, 304 *generate pcie_err_attn output when this error is seen..WC 305 */ 306 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 (1 << 26) 307 308 /*Receiver Overflow Status Status in function 4, if set, 309 *generate pcie_err_attn output when this error is seen..WC 310 */ 311 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 (1 << 25) 312 313 /*Unexpected Completion Status Status in function 4, if set, 314 *generate pcie_err_attn output when this error is seen..WC 315 */ 316 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 (1 << 24) 317 318 /* Receive UR Statusin function 4. If set, generate pcie_err_attn output 319 * when this error is seen. WC 320 */ 321 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 (1 << 23) 322 323 /* Completer Timeout Status Status in function 4, if set, 324 * generate pcie_err_attn output when this error is seen..WC 325 */ 326 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 (1 << 22) 327 328 /* Flow Control Protocol Error Status Status in function 4, 329 * if set, generate pcie_err_attn output when this error is seen. 330 * WC 331 */ 332 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 (1 << 21) 333 334 /* Poisoned Error Status Status in function 4, if set, generate 335 * pcie_err_attn output when this error is seen..WC 336 */ 337 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 (1 << 20) 338 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 339 340 /* Unsupported Request Error Status in function3, if set, generate 341 * pcie_err_attn output when this error is seen..WC 342 */ 343 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 (1 << 18) 344 345 /* ECRC Error TLP Status Status in function 3, if set, generate 346 * pcie_err_attn output when this error is seen.. WC 347 */ 348 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 (1 << 17) 349 350 /* Malformed TLP Status Status in function 3, if set, generate 351 * pcie_err_attn output when this error is seen..WC 352 */ 353 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 (1 << 16) 354 355 /* Receiver Overflow Status Status in function 3, if set, generate 356 * pcie_err_attn output when this error is seen..WC 357 */ 358 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 (1 << 15) 359 360 /* Unexpected Completion Status Status in function 3, if set, generate 361 * pcie_err_attn output when this error is seen. WC 362 */ 363 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 (1 << 14) 364 365 /* Receive UR Statusin function 3. If set, generate pcie_err_attn output 366 * when this error is seen. WC 367 */ 368 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 (1 << 13) 369 370 /* Completer Timeout Status Status in function 3, if set, generate 371 * pcie_err_attn output when this error is seen..WC 372 */ 373 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 (1 << 12) 374 375 /* Flow Control Protocol Error Status Status in function 3, if set, 376 * generate pcie_err_attn output when this error is seen..WC 377 */ 378 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 (1 << 11) 379 380 /* Poisoned Error Status Status in function 3, if set, generate 381 * pcie_err_attn output when this error is seen..WC 382 */ 383 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 (1 << 10) 384 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 385 386 /* Unsupported Request Error Status for Function 2, if set, 387 * generate pcie_err_attn output when this error is seen. WC 388 */ 389 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 (1 << 8) 390 391 /* ECRC Error TLP Status Status for Function 2, if set, generate 392 * pcie_err_attn output when this error is seen..WC 393 */ 394 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 (1 << 7) 395 396 /* Malformed TLP Status Status for Function 2, if set, generate 397 * pcie_err_attn output when this error is seen.. WC 398 */ 399 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 (1 << 6) 400 401 /* Receiver Overflow Status Status for Function 2, if set, generate 402 * pcie_err_attn output when this error is seen.. WC 403 */ 404 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 (1 << 5) 405 406 /* Unexpected Completion Status Status for Function 2, if set, generate 407 * pcie_err_attn output when this error is seen. WC 408 */ 409 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 (1 << 4) 410 411 /* Receive UR Statusfor Function 2. If set, generate pcie_err_attn output 412 * when this error is seen. WC 413 */ 414 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 (1 << 3) 415 416 /* Completer Timeout Status Status for Function 2, if set, generate 417 * pcie_err_attn output when this error is seen. WC 418 */ 419 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 (1 << 2) 420 421 /* Flow Control Protocol Error Status Status for Function 2, if set, 422 * generate pcie_err_attn output when this error is seen. WC 423 */ 424 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 (1 << 1) 425 426 /* Poisoned Error Status Status for Function 2, if set, generate 427 * pcie_err_attn output when this error is seen.. WC 428 */ 429 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 (1 << 0) 430 #define PXPCS_TL_FUNC678_STAT 0x85C 431 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 432 433 /* Unsupported Request Error Status in function7, if set, generate 434 * pcie_err_attn output when this error is seen. WC 435 */ 436 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 (1 << 28) 437 438 /* ECRC Error TLP Status Status in function 7, if set, generate 439 * pcie_err_attn output when this error is seen.. WC 440 */ 441 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 (1 << 27) 442 443 /* Malformed TLP Status Status in function 7, if set, generate 444 * pcie_err_attn output when this error is seen.. WC 445 */ 446 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 (1 << 26) 447 448 /* Receiver Overflow Status Status in function 7, if set, generate 449 * pcie_err_attn output when this error is seen.. WC 450 */ 451 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 (1 << 25) 452 453 /* Unexpected Completion Status Status in function 7, if set, generate 454 * pcie_err_attn output when this error is seen. WC 455 */ 456 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 (1 << 24) 457 458 /* Receive UR Statusin function 7. If set, generate pcie_err_attn 459 * output when this error is seen. WC 460 */ 461 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 (1 << 23) 462 463 /* Completer Timeout Status Status in function 7, if set, generate 464 * pcie_err_attn output when this error is seen. WC 465 */ 466 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 (1 << 22) 467 468 /* Flow Control Protocol Error Status Status in function 7, if set, 469 * generate pcie_err_attn output when this error is seen. WC 470 */ 471 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 (1 << 21) 472 473 /* Poisoned Error Status Status in function 7, if set, 474 * generate pcie_err_attn output when this error is seen.. WC 475 */ 476 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 (1 << 20) 477 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 478 479 /* Unsupported Request Error Status in function6, if set, generate 480 * pcie_err_attn output when this error is seen. WC 481 */ 482 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 (1 << 18) 483 484 /* ECRC Error TLP Status Status in function 6, if set, generate 485 * pcie_err_attn output when this error is seen.. WC 486 */ 487 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 (1 << 17) 488 489 /* Malformed TLP Status Status in function 6, if set, generate 490 * pcie_err_attn output when this error is seen.. WC 491 */ 492 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 (1 << 16) 493 494 /* Receiver Overflow Status Status in function 6, if set, generate 495 * pcie_err_attn output when this error is seen.. WC 496 */ 497 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 (1 << 15) 498 499 /* Unexpected Completion Status Status in function 6, if set, 500 * generate pcie_err_attn output when this error is seen. WC 501 */ 502 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 (1 << 14) 503 504 /* Receive UR Statusin function 6. If set, generate pcie_err_attn 505 * output when this error is seen. WC 506 */ 507 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 (1 << 13) 508 509 /* Completer Timeout Status Status in function 6, if set, generate 510 * pcie_err_attn output when this error is seen. WC 511 */ 512 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 (1 << 12) 513 514 /* Flow Control Protocol Error Status Status in function 6, if set, 515 * generate pcie_err_attn output when this error is seen. WC 516 */ 517 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 (1 << 11) 518 519 /* Poisoned Error Status Status in function 6, if set, generate 520 * pcie_err_attn output when this error is seen.. WC 521 */ 522 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 (1 << 10) 523 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 524 525 /* Unsupported Request Error Status for Function 5, if set, 526 * generate pcie_err_attn output when this error is seen. WC 527 */ 528 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 (1 << 8) 529 530 /* ECRC Error TLP Status Status for Function 5, if set, generate 531 * pcie_err_attn output when this error is seen.. WC 532 */ 533 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 (1 << 7) 534 535 /* Malformed TLP Status Status for Function 5, if set, generate 536 * pcie_err_attn output when this error is seen.. WC 537 */ 538 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 (1 << 6) 539 540 /* Receiver Overflow Status Status for Function 5, if set, generate 541 * pcie_err_attn output when this error is seen.. WC 542 */ 543 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 (1 << 5) 544 545 /* Unexpected Completion Status Status for Function 5, if set, generate 546 * pcie_err_attn output when this error is seen. WC 547 */ 548 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 (1 << 4) 549 550 /* Receive UR Statusfor Function 5. If set, generate pcie_err_attn output 551 * when this error is seen. WC 552 */ 553 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 (1 << 3) 554 555 /* Completer Timeout Status Status for Function 5, if set, generate 556 * pcie_err_attn output when this error is seen. WC 557 */ 558 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 (1 << 2) 559 560 /* Flow Control Protocol Error Status Status for Function 5, if set, 561 * generate pcie_err_attn output when this error is seen. WC 562 */ 563 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 (1 << 1) 564 565 /* Poisoned Error Status Status for Function 5, if set, 566 * generate pcie_err_attn output when this error is seen.. WC 567 */ 568 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 (1 << 0) 569 570 /* PCI CAPABILITIES 571 */ 572 573 #define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/ 574 575 #define PCIE_DEV_CAPS 0x04 576 #ifndef PCIE_DEV_CAPS_FLR_CAPABILITY 577 #define PCIE_DEV_CAPS_FLR_CAPABILITY (1 << 28) 578 #endif 579 580 #define PCIE_DEV_CTRL 0x08 581 #define PCIE_DEV_CTRL_FLR 0x8000 582 583 #define PCIE_DEV_STATUS 0x0A 584 #ifndef PCIE_DEV_STATUS_PENDING_TRANSACTION 585 #define PCIE_DEV_STATUS_PENDING_TRANSACTION (1 << 5) 586 #endif 587 588 #ifndef PCI_CAPABILITY_LIST 589 /* Ofset of first capability list entry */ 590 #define PCI_CAPABILITY_LIST 0x34 591 #endif 592 593 #define PCI_CAPABILITY_LIST_MASK 0xff 594 595 #ifndef PCI_CB_CAPABILITY_LIST 596 #define PCI_CB_CAPABILITY_LIST 0x14 597 #endif 598 599 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID)) 600 #define PCI_CAP_LIST_ID_DEF 601 #endif 602 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT)) 603 #define PCI_CAP_LIST_NEXT_DEF 604 #endif 605 #if (defined(__LINUX)) || (defined(PCI_STATUS)) 606 #define PCI_STATUS_DEF 607 #endif 608 #if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST)) 609 #define PCI_STATUS_CAP_LIST_DEF 610 #endif 611 612 #ifndef PCI_CAP_LIST_ID_DEF 613 #define PCI_CAP_LIST_ID 0x0 /* Capability ID */ 614 #endif 615 616 #define PCI_CAP_LIST_ID_MASK 0xff 617 618 #ifndef PCI_CAP_LIST_NEXT_DEF 619 /* Next capability in the list */ 620 #define PCI_CAP_LIST_NEXT 0x1 621 #endif 622 623 #define PCI_CAP_LIST_NEXT_MASK 0xff 624 625 #ifndef PCI_STATUS_DEF 626 #define PCI_STATUS 0x6 /* 16 bits */ 627 #endif 628 #ifndef PCI_STATUS_CAP_LIST_DEF 629 /* Support Capability List */ 630 #define PCI_STATUS_CAP_LIST 0x10 631 #endif 632 633 #ifndef PCI_SRIOV_CAP 634 635 /* Some PCI Config defines... need to put this in a better location... */ 636 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 637 #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 638 #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 639 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 640 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 641 #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ 642 #define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ 643 #define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ 644 #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ 645 #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ 646 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 647 #define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ 648 #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 649 #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 650 #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 651 #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 652 #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 653 #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 654 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 655 #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 656 #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ 657 658 #endif 659 660 #ifndef PCI_CAP_ID_EXP 661 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 662 #endif 663 #ifndef PCI_EXP_DEVCTL 664 #define PCI_EXP_DEVCTL 8 /* Device Control */ 665 #endif 666 #ifndef PCI_EXP_DEVCTL_RELAX_EN 667 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 668 #endif 669 670 #endif 671