1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _PCICS_REG_DRIVER_H 30 #define _PCICS_REG_DRIVER_H 31 32 /* offset of configuration space in the pci core register */ 33 #ifndef __EXTRACT__LINUX__ 34 #define PCICFG_OFFSET 0x2000 35 #endif 36 #define PCICFG_VENDOR_ID_OFFSET 0x00 37 #define PCICFG_DEVICE_ID_OFFSET 0x02 38 #define PCICFG_COMMAND_OFFSET 0x04 39 #define PCICFG_COMMAND_IO_SPACE (1<<0) 40 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 41 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 42 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 43 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 44 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 45 #define PCICFG_COMMAND_PERR_ENA (1<<6) 46 #define PCICFG_COMMAND_STEPPING (1<<7) 47 #define PCICFG_COMMAND_SERR_ENA (1<<8) 48 #define PCICFG_COMMAND_FAST_B2B (1<<9) 49 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 50 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 51 #define PCICFG_STATUS_OFFSET 0x06 52 #define PCICFG_REVISION_ID_OFFSET 0x08 53 #define PCICFG_REVESION_ID_MASK 0xff 54 #define PCICFG_REVESION_ID_ERROR_VAL 0xff 55 #define PCICFG_CACHE_LINE_SIZE 0x0c 56 #define PCICFG_LATENCY_TIMER 0x0d 57 #define PCICFG_HEADER_TYPE 0x0e 58 #define PCICFG_HEADER_TYPE_NORMAL 0 59 #define PCICFG_HEADER_TYPE_BRIDGE 1 60 #define PCICFG_HEADER_TYPE_CARDBUS 2 61 #define PCICFG_BAR_1_LOW 0x10 62 #define PCICFG_BAR_1_HIGH 0x14 63 #define PCICFG_BAR_2_LOW 0x18 64 #define PCICFG_BAR_2_HIGH 0x1c 65 #define PCICFG_BAR_3_LOW 0x20 66 #define PCICFG_BAR_3_HIGH 0x24 67 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 68 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 69 #define PCICFG_INT_LINE 0x3c 70 #define PCICFG_INT_PIN 0x3d 71 #define PCICFG_PM_CAPABILITY 0x48 72 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 73 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 74 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 75 #define PCICFG_PM_CAPABILITY_DSI (1<<21) 76 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 77 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 78 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 79 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 80 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 81 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 82 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 83 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 84 #define PCICFG_PM_CSR_OFFSET 0x4c 85 #define PCICFG_PM_CSR_STATE (0x3<<0) 86 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 87 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 88 #define PCICFG_MSI_CAP_ID_OFFSET 0x58 89 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 90 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 91 #define PCICFG_MSI_CONTROL_MENA (0x7<<20) 92 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 93 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 94 #define PCICFG_GRC_ADDRESS 0x78 95 #define PCICFG_GRC_DATA 0x80 96 #define PCICFG_ME_REGISTER 0x98 97 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 98 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 99 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 100 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 101 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 102 103 #define PCICFG_DEVICE_CONTROL 0xb4 104 #define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21) 105 #define PCICFG_DEVICE_STATUS 0xb6 106 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 107 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 108 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 109 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 110 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 111 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 112 #define PCICFG_LINK_CONTROL 0xbc 113 #define PCICFG_DEVICE_STATUS_CONTROL_2 (0xd4) 114 #define PCICFG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE (1<<6) 115 116 /* config_2 offset */ 117 #define GRC_CONFIG_2_SIZE_REG 0x408 118 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 119 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 120 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 121 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 122 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 123 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 124 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 125 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 126 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 127 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 128 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 129 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 130 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 131 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 132 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 133 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 134 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 135 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 136 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 137 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 138 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 139 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 140 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 141 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 142 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 143 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 144 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 145 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 146 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 147 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 148 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 149 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 150 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 151 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 152 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 153 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 154 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 155 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 156 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 157 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 158 159 /* config_3 offset */ 160 #define GRC_CONFIG_3_SIZE_REG 0x40c 161 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 162 #define PCI_CONFIG_3_FORCE_PME (1L<<24) 163 #define PCI_CONFIG_3_PME_STATUS (1L<<25) 164 #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 165 #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 166 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 167 #define PCI_CONFIG_3_PCI_POWER (1L<<31) 168 169 #define GRC_REG_DEVICE_CONTROL 0x4d8 170 171 /* When VF Enable is cleared(after it was previously set), 172 * this register will read a value of 1, indicating that all the 173 * VFs that belong to this PF should be flushed. 174 * Software should clear this bit within 1 second of VF Enable 175 * being set by writing a 1 to it, so that VFs are visible to the system 176 * again.WC 177 */ 178 #define PCIE_SRIOV_DISABLE_IN_PROGRESS (1 << 29) 179 180 /* When FLR is initiated, this register will read a value of 1 indicating 181 * that the Function is in FLR state. Func can be brought out of FLR state 182 * either bywriting 1 to this register (at least 50 ms after FLR was 183 * initiated),or it can also be cleared automatically after 55 ms if 184 * auto_clear bit in private reg space is set. This bit also exists in 185 * VF register space WC 186 */ 187 #define PCIE_FLR_IN_PROGRESS (1 << 27) 188 189 #define GRC_BAR2_CONFIG 0x4e0 190 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 191 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 192 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 193 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 194 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 195 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 196 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 197 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 198 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 199 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 200 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 201 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 202 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 203 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 204 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 205 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 206 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 207 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 208 209 #define GRC_BAR3_CONFIG 0x4f4 210 #define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0) 211 #define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0) 212 #define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0) 213 #define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0) 214 #define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0) 215 #define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0) 216 #define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0) 217 #define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0) 218 #define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0) 219 #define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0) 220 #define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0) 221 #define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0) 222 #define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0) 223 #define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0) 224 #define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0) 225 #define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0) 226 #define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0) 227 #define PCI_CONFIG_2_BAR3_64ENA (1L<<4) 228 #define PCI_PM_DATA_A 0x410 229 #define PCI_PM_DATA_B 0x414 230 #define PCI_ID_VAL1 0x434 231 #define PCI_ID_VAL2 0x438 232 #define PCI_ID_VAL3 0x43c 233 #define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24) 234 #define GRC_CONFIG_REG_VF_BAR_REG_1 0x608 235 #define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf 236 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C 237 238 /* This field resides in VF only and does not exist in PF. 239 * This register controls the read value of the MSIX_CONTROL[10:0] register 240 * in the VF configuration space. A value of "00000000011" indicates 241 * a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ 242 * define in version.v 243 */ 244 #define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK 0x3F 245 #ifndef __EXTRACT__LINUX__ 246 #define GRC_CONFIG_REG_PF_INIT_VF 0x624 247 248 /* First VF_NUM for PF is encoded in this register. 249 * The number of VFs assigned to a PF is assumed to be a multiple of 8. 250 * Software should program these bits based on Total Number of VFs programmed 251 * for each PF. 252 * Since registers from 0x000-0x7ff are spilt across functions, each PF will 253 * have the same location for the same 4 bits 254 */ 255 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xff 256 #endif 257 #define PXPCS_TL_CONTROL_5 0x814 258 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 259 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 260 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 261 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 262 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 263 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 264 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 265 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 266 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 267 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 268 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 269 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 270 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 271 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 272 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 273 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 274 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 275 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 276 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 277 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 278 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 279 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 280 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 281 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 282 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 283 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 284 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 285 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 286 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 287 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 288 #define PXPCS_TL_FUNC345_STAT 0x854 289 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 290 291 /*Unsupported Request Error Status in function4, if set, generate 292 *pcie_err_attn output when this error is seen. WC 293 */ 294 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 (1 << 28) 295 296 /*ECRC Error TLP Status Status in function 4, if set, 297 *generate pcie_err_attn output when this error is seen..WC 298 */ 299 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 (1 << 27) 300 301 /*Malformed TLP Status Status in function 4, if set, 302 *generate pcie_err_attn output when this error is seen..WC 303 */ 304 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 (1 << 26) 305 306 /*Receiver Overflow Status Status in function 4, if set, 307 *generate pcie_err_attn output when this error is seen..WC 308 */ 309 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 (1 << 25) 310 311 /*Unexpected Completion Status Status in function 4, if set, 312 *generate pcie_err_attn output when this error is seen..WC 313 */ 314 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 (1 << 24) 315 316 /* Receive UR Statusin function 4. If set, generate pcie_err_attn output 317 * when this error is seen. WC 318 */ 319 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 (1 << 23) 320 321 /* Completer Timeout Status Status in function 4, if set, 322 * generate pcie_err_attn output when this error is seen..WC 323 */ 324 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 (1 << 22) 325 326 /* Flow Control Protocol Error Status Status in function 4, 327 * if set, generate pcie_err_attn output when this error is seen. 328 * WC 329 */ 330 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 (1 << 21) 331 332 /* Poisoned Error Status Status in function 4, if set, generate 333 * pcie_err_attn output when this error is seen..WC 334 */ 335 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 (1 << 20) 336 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 337 338 /* Unsupported Request Error Status in function3, if set, generate 339 * pcie_err_attn output when this error is seen..WC 340 */ 341 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 (1 << 18) 342 343 /* ECRC Error TLP Status Status in function 3, if set, generate 344 * pcie_err_attn output when this error is seen.. WC 345 */ 346 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 (1 << 17) 347 348 /* Malformed TLP Status Status in function 3, if set, generate 349 * pcie_err_attn output when this error is seen..WC 350 */ 351 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 (1 << 16) 352 353 /* Receiver Overflow Status Status in function 3, if set, generate 354 * pcie_err_attn output when this error is seen..WC 355 */ 356 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 (1 << 15) 357 358 /* Unexpected Completion Status Status in function 3, if set, generate 359 * pcie_err_attn output when this error is seen. WC 360 */ 361 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 (1 << 14) 362 363 /* Receive UR Statusin function 3. If set, generate pcie_err_attn output 364 * when this error is seen. WC 365 */ 366 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 (1 << 13) 367 368 /* Completer Timeout Status Status in function 3, if set, generate 369 * pcie_err_attn output when this error is seen..WC 370 */ 371 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 (1 << 12) 372 373 /* Flow Control Protocol Error Status Status in function 3, if set, 374 * generate pcie_err_attn output when this error is seen..WC 375 */ 376 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 (1 << 11) 377 378 /* Poisoned Error Status Status in function 3, if set, generate 379 * pcie_err_attn output when this error is seen..WC 380 */ 381 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 (1 << 10) 382 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 383 384 /* Unsupported Request Error Status for Function 2, if set, 385 * generate pcie_err_attn output when this error is seen. WC 386 */ 387 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 (1 << 8) 388 389 /* ECRC Error TLP Status Status for Function 2, if set, generate 390 * pcie_err_attn output when this error is seen..WC 391 */ 392 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 (1 << 7) 393 394 /* Malformed TLP Status Status for Function 2, if set, generate 395 * pcie_err_attn output when this error is seen.. WC 396 */ 397 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 (1 << 6) 398 399 /* Receiver Overflow Status Status for Function 2, if set, generate 400 * pcie_err_attn output when this error is seen.. WC 401 */ 402 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 (1 << 5) 403 404 /* Unexpected Completion Status Status for Function 2, if set, generate 405 * pcie_err_attn output when this error is seen. WC 406 */ 407 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 (1 << 4) 408 409 /* Receive UR Statusfor Function 2. If set, generate pcie_err_attn output 410 * when this error is seen. WC 411 */ 412 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 (1 << 3) 413 414 /* Completer Timeout Status Status for Function 2, if set, generate 415 * pcie_err_attn output when this error is seen. WC 416 */ 417 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 (1 << 2) 418 419 /* Flow Control Protocol Error Status Status for Function 2, if set, 420 * generate pcie_err_attn output when this error is seen. WC 421 */ 422 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 (1 << 1) 423 424 /* Poisoned Error Status Status for Function 2, if set, generate 425 * pcie_err_attn output when this error is seen.. WC 426 */ 427 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 (1 << 0) 428 #define PXPCS_TL_FUNC678_STAT 0x85C 429 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 430 431 /* Unsupported Request Error Status in function7, if set, generate 432 * pcie_err_attn output when this error is seen. WC 433 */ 434 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 (1 << 28) 435 436 /* ECRC Error TLP Status Status in function 7, if set, generate 437 * pcie_err_attn output when this error is seen.. WC 438 */ 439 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 (1 << 27) 440 441 /* Malformed TLP Status Status in function 7, if set, generate 442 * pcie_err_attn output when this error is seen.. WC 443 */ 444 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 (1 << 26) 445 446 /* Receiver Overflow Status Status in function 7, if set, generate 447 * pcie_err_attn output when this error is seen.. WC 448 */ 449 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 (1 << 25) 450 451 /* Unexpected Completion Status Status in function 7, if set, generate 452 * pcie_err_attn output when this error is seen. WC 453 */ 454 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 (1 << 24) 455 456 /* Receive UR Statusin function 7. If set, generate pcie_err_attn 457 * output when this error is seen. WC 458 */ 459 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 (1 << 23) 460 461 /* Completer Timeout Status Status in function 7, if set, generate 462 * pcie_err_attn output when this error is seen. WC 463 */ 464 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 (1 << 22) 465 466 /* Flow Control Protocol Error Status Status in function 7, if set, 467 * generate pcie_err_attn output when this error is seen. WC 468 */ 469 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 (1 << 21) 470 471 /* Poisoned Error Status Status in function 7, if set, 472 * generate pcie_err_attn output when this error is seen.. WC 473 */ 474 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 (1 << 20) 475 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 476 477 /* Unsupported Request Error Status in function6, if set, generate 478 * pcie_err_attn output when this error is seen. WC 479 */ 480 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 (1 << 18) 481 482 /* ECRC Error TLP Status Status in function 6, if set, generate 483 * pcie_err_attn output when this error is seen.. WC 484 */ 485 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 (1 << 17) 486 487 /* Malformed TLP Status Status in function 6, if set, generate 488 * pcie_err_attn output when this error is seen.. WC 489 */ 490 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 (1 << 16) 491 492 /* Receiver Overflow Status Status in function 6, if set, generate 493 * pcie_err_attn output when this error is seen.. WC 494 */ 495 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 (1 << 15) 496 497 /* Unexpected Completion Status Status in function 6, if set, 498 * generate pcie_err_attn output when this error is seen. WC 499 */ 500 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 (1 << 14) 501 502 /* Receive UR Statusin function 6. If set, generate pcie_err_attn 503 * output when this error is seen. WC 504 */ 505 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 (1 << 13) 506 507 /* Completer Timeout Status Status in function 6, if set, generate 508 * pcie_err_attn output when this error is seen. WC 509 */ 510 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 (1 << 12) 511 512 /* Flow Control Protocol Error Status Status in function 6, if set, 513 * generate pcie_err_attn output when this error is seen. WC 514 */ 515 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 (1 << 11) 516 517 /* Poisoned Error Status Status in function 6, if set, generate 518 * pcie_err_attn output when this error is seen.. WC 519 */ 520 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 (1 << 10) 521 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 522 523 /* Unsupported Request Error Status for Function 5, if set, 524 * generate pcie_err_attn output when this error is seen. WC 525 */ 526 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 (1 << 8) 527 528 /* ECRC Error TLP Status Status for Function 5, if set, generate 529 * pcie_err_attn output when this error is seen.. WC 530 */ 531 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 (1 << 7) 532 533 /* Malformed TLP Status Status for Function 5, if set, generate 534 * pcie_err_attn output when this error is seen.. WC 535 */ 536 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 (1 << 6) 537 538 /* Receiver Overflow Status Status for Function 5, if set, generate 539 * pcie_err_attn output when this error is seen.. WC 540 */ 541 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 (1 << 5) 542 543 /* Unexpected Completion Status Status for Function 5, if set, generate 544 * pcie_err_attn output when this error is seen. WC 545 */ 546 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 (1 << 4) 547 548 /* Receive UR Statusfor Function 5. If set, generate pcie_err_attn output 549 * when this error is seen. WC 550 */ 551 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 (1 << 3) 552 553 /* Completer Timeout Status Status for Function 5, if set, generate 554 * pcie_err_attn output when this error is seen. WC 555 */ 556 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 (1 << 2) 557 558 /* Flow Control Protocol Error Status Status for Function 5, if set, 559 * generate pcie_err_attn output when this error is seen. WC 560 */ 561 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 (1 << 1) 562 563 /* Poisoned Error Status Status for Function 5, if set, 564 * generate pcie_err_attn output when this error is seen.. WC 565 */ 566 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 (1 << 0) 567 568 /* PCI CAPABILITIES 569 */ 570 571 #define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/ 572 573 #define PCIE_DEV_CAPS 0x04 574 #ifndef PCIE_DEV_CAPS_FLR_CAPABILITY 575 #define PCIE_DEV_CAPS_FLR_CAPABILITY (1 << 28) 576 #endif 577 578 #define PCIE_DEV_CTRL 0x08 579 #define PCIE_DEV_CTRL_FLR 0x8000 580 581 #define PCIE_DEV_STATUS 0x0A 582 #ifndef PCIE_DEV_STATUS_PENDING_TRANSACTION 583 #define PCIE_DEV_STATUS_PENDING_TRANSACTION (1 << 5) 584 #endif 585 586 #ifndef PCI_CAPABILITY_LIST 587 /* Ofset of first capability list entry */ 588 #define PCI_CAPABILITY_LIST 0x34 589 #endif 590 591 #define PCI_CAPABILITY_LIST_MASK 0xff 592 593 #ifndef PCI_CB_CAPABILITY_LIST 594 #define PCI_CB_CAPABILITY_LIST 0x14 595 #endif 596 597 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID)) 598 #define PCI_CAP_LIST_ID_DEF 599 #endif 600 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT)) 601 #define PCI_CAP_LIST_NEXT_DEF 602 #endif 603 #if (defined(__LINUX)) || (defined(PCI_STATUS)) 604 #define PCI_STATUS_DEF 605 #endif 606 #if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST)) 607 #define PCI_STATUS_CAP_LIST_DEF 608 #endif 609 610 #ifndef PCI_CAP_LIST_ID_DEF 611 #define PCI_CAP_LIST_ID 0x0 /* Capability ID */ 612 #endif 613 614 #define PCI_CAP_LIST_ID_MASK 0xff 615 616 #ifndef PCI_CAP_LIST_NEXT_DEF 617 /* Next capability in the list */ 618 #define PCI_CAP_LIST_NEXT 0x1 619 #endif 620 621 #define PCI_CAP_LIST_NEXT_MASK 0xff 622 623 #ifndef PCI_STATUS_DEF 624 #define PCI_STATUS 0x6 /* 16 bits */ 625 #endif 626 #ifndef PCI_STATUS_CAP_LIST_DEF 627 /* Support Capability List */ 628 #define PCI_STATUS_CAP_LIST 0x10 629 #endif 630 631 #ifndef PCI_SRIOV_CAP 632 633 /* Some PCI Config defines... need to put this in a better location... */ 634 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ 635 #define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ 636 #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ 637 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 638 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ 639 #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ 640 #define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ 641 #define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ 642 #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ 643 #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ 644 #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ 645 #define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ 646 #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ 647 #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ 648 #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ 649 #define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */ 650 #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ 651 #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ 652 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ 653 #define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ 654 #define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */ 655 656 #endif 657 658 #ifndef PCI_CAP_ID_EXP 659 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 660 #endif 661 #ifndef PCI_EXP_DEVCTL 662 #define PCI_EXP_DEVCTL 8 /* Device Control */ 663 #endif 664 #ifndef PCI_EXP_DEVCTL_RELAX_EN 665 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */ 666 #endif 667 668 #endif 669