1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 32 /**************************************************************************** 33 * Name: nvm_map.h 34 * 35 * Description: Everest NVRAM map 36 * 37 ****************************************************************************/ 38 39 #ifndef NVM_MAP_H 40 #define NVM_MAP_H 41 42 #define CRC_MAGIC_VALUE 0xDEBB20E3 43 #define CRC32_POLYNOMIAL 0xEDB88320 44 #define NVM_CRC_SIZE (sizeof(u32)) 45 enum nvm_sw_arbitrator { 46 NVM_SW_ARB_HOST, 47 NVM_SW_ARB_MCP, 48 NVM_SW_ARB_UART, 49 NVM_SW_ARB_RESERVED 50 }; 51 52 /**************************************************************************** 53 * Boot Strap Region * 54 ****************************************************************************/ 55 struct legacy_bootstrap_region { 56 u32 magic_value; /* a pattern not likely to occur randomly */ 57 #define NVM_MAGIC_VALUE 0x669955aa 58 u32 sram_start_addr; /* where to locate LIM code (byte addr) */ 59 u32 code_len; /* boot code length (in dwords) */ 60 u32 code_start_addr; /* location of code on media (media byte addr) */ 61 u32 crc; /* 32-bit CRC */ 62 }; 63 64 /**************************************************************************** 65 * Directories Region * 66 ****************************************************************************/ 67 struct nvm_code_entry { 68 u32 image_type; /* Image type */ 69 u32 nvm_start_addr; /* NVM address of the image */ 70 u32 len; /* Include CRC */ 71 u32 sram_start_addr; /* Where to load the image on the scratchpad */ 72 u32 sram_run_addr; /* Relevant in case of MIM only */ 73 }; 74 75 enum nvm_image_type { 76 NVM_TYPE_TIM1 = 0x01, 77 NVM_TYPE_TIM2 = 0x02, 78 NVM_TYPE_MIM1 = 0x03, 79 NVM_TYPE_MIM2 = 0x04, 80 NVM_TYPE_MBA = 0x05, 81 NVM_TYPE_MODULES_PN = 0x06, 82 NVM_TYPE_VPD = 0x07, 83 NVM_TYPE_MFW_TRACE1 = 0x08, 84 NVM_TYPE_MFW_TRACE2 = 0x09, 85 NVM_TYPE_NVM_CFG1 = 0x0a, 86 NVM_TYPE_L2B = 0x0b, 87 NVM_TYPE_DIR1 = 0x0c, 88 NVM_TYPE_EAGLE_FW1 = 0x0d, 89 NVM_TYPE_FALCON_FW1 = 0x0e, 90 NVM_TYPE_PCIE_FW1 = 0x0f, 91 NVM_TYPE_HW_SET = 0x10, 92 NVM_TYPE_LIM = 0x11, 93 NVM_TYPE_AVS_FW1 = 0x12, 94 NVM_TYPE_DIR2 = 0x13, 95 NVM_TYPE_CCM = 0x14, 96 NVM_TYPE_EAGLE_FW2 = 0x15, 97 NVM_TYPE_FALCON_FW2 = 0x16, 98 NVM_TYPE_PCIE_FW2 = 0x17, 99 NVM_TYPE_AVS_FW2 = 0x18, 100 NVM_TYPE_INIT_HW = 0x19, 101 NVM_TYPE_DEFAULT_CFG= 0x1a, 102 NVM_TYPE_MDUMP = 0x1b, 103 NVM_TYPE_NVM_META = 0x1c, 104 NVM_TYPE_ISCSI_CFG = 0x1d, 105 NVM_TYPE_FCOE_CFG = 0x1f, 106 NVM_TYPE_ETH_PHY_FW1 = 0x20, 107 NVM_TYPE_ETH_PHY_FW2 = 0x21, 108 NVM_TYPE_BDN = 0x22, 109 NVM_TYPE_8485X_PHY_FW = 0x23, 110 NVM_TYPE_PUB_KEY = 0x24, 111 NVM_TYPE_RECOVERY = 0x25, 112 NVM_TYPE_MAX, 113 }; 114 115 #ifdef DEFINE_IMAGE_TABLE 116 struct image_map { 117 char name[32]; 118 char option[32]; 119 u32 image_type; 120 }; 121 122 struct image_map g_image_table[] = { 123 {"TIM1", "-tim1", NVM_TYPE_TIM1}, 124 {"TIM2", "-tim2", NVM_TYPE_TIM2}, 125 {"MIM1", "-mim1", NVM_TYPE_MIM1}, 126 {"MIM2", "-mim2", NVM_TYPE_MIM2}, 127 {"MBA", "-mba", NVM_TYPE_MBA}, 128 {"OPT_MODULES", "-optm", NVM_TYPE_MODULES_PN}, 129 {"VPD", "-vpd", NVM_TYPE_VPD}, 130 {"MFW_TRACE1", "-mfwt1", NVM_TYPE_MFW_TRACE1}, 131 {"MFW_TRACE2", "-mfwt2", NVM_TYPE_MFW_TRACE2}, 132 {"NVM_CFG1", "-cfg", NVM_TYPE_NVM_CFG1}, 133 {"L2B", "-l2b", NVM_TYPE_L2B}, 134 {"DIR1", "-dir1", NVM_TYPE_DIR1}, 135 {"EAGLE_FW1", "-eagle1", NVM_TYPE_EAGLE_FW1}, 136 {"FALCON_FW1", "-falcon1", NVM_TYPE_FALCON_FW1}, 137 {"PCIE_FW1", "-pcie1", NVM_TYPE_PCIE_FW1}, 138 {"HW_SET", "-hw_set", NVM_TYPE_HW_SET}, 139 {"LIM", "-lim", NVM_TYPE_LIM}, 140 {"AVS_FW1", "-avs1", NVM_TYPE_AVS_FW1}, 141 {"DIR2", "-dir2", NVM_TYPE_DIR2}, 142 {"CCM", "-ccm", NVM_TYPE_CCM}, 143 {"EAGLE_FW2", "-eagle2", NVM_TYPE_EAGLE_FW2}, 144 {"FALCON_FW2", "-falcon2", NVM_TYPE_FALCON_FW2}, 145 {"PCIE_FW2", "-pcie2", NVM_TYPE_PCIE_FW2}, 146 {"AVS_FW2", "-avs2", NVM_TYPE_AVS_FW2}, 147 {"INIT_HW", "-init_hw", NVM_TYPE_INIT_HW}, 148 {"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG}, 149 {"CRASH_DUMP", "-mdump", NVM_TYPE_MDUMP}, 150 {"META", "-meta", NVM_TYPE_NVM_META}, 151 {"ISCSI_CFG", "-iscsi_cfg", NVM_TYPE_ISCSI_CFG}, 152 {"FCOE_CFG", "-fcoe_cfg",NVM_TYPE_FCOE_CFG}, 153 {"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1}, 154 {"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2}, 155 {"BDN", "-bdn", NVM_TYPE_BDN}, 156 {"PK", "-pk", NVM_TYPE_PUB_KEY}, 157 {"RECOVERY", "-recovery",NVM_TYPE_RECOVERY} 158 }; 159 160 #define IMAGE_TABLE_SIZE (sizeof(g_image_table) / sizeof(struct image_map)) 161 162 #endif /* #ifdef DEFINE_IMAGE_TABLE */ 163 #define MAX_NVM_DIR_ENTRIES 150 164 /* Note: The has given 150 possible entries since anyway each file captures at least one page. */ 165 166 struct nvm_dir { 167 s32 seq; /* This dword is used to indicate whether this dir is valid, and whether it is more updated than the other dir */ 168 #define NVM_DIR_NEXT_MFW_MASK 0x00000001 169 #define NVM_DIR_SEQ_MASK 0xfffffffe 170 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK) 171 #define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \ 172 do { \ 173 _seq = (((_seq + 2) & NVM_DIR_SEQ_MASK) | (NVM_DIR_NEXT_MFW(_seq ^ swap_mfw))); \ 174 } while (0) 175 #define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK) 176 177 u32 num_images; 178 u32 rsrv; 179 struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */ 180 }; 181 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE) 182 183 struct nvm_vpd_image { 184 u32 format_revision; 185 #define VPD_IMAGE_VERSION 1 186 187 /* This array length depends on the number of VPD fields */ 188 u8 vpd_data[1]; 189 }; 190 191 /**************************************************************************** 192 * NVRAM FULL MAP * 193 ****************************************************************************/ 194 #define DIR_ID_1 (0) 195 #define DIR_ID_2 (1) 196 #define MAX_DIR_IDS (2) 197 198 #define MFW_BUNDLE_1 (0) 199 #define MFW_BUNDLE_2 (1) 200 #define MAX_MFW_BUNDLES (2) 201 202 #define FLASH_PAGE_SIZE 0x1000 203 #define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */ 204 #define ASIC_MIM_MAX_SIZE (300*FLASH_PAGE_SIZE) /* 1.2Mb */ 205 #define FPGA_MIM_MAX_SIZE (62*FLASH_PAGE_SIZE) /* 250Kb */ 206 207 /* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share the same page. 208 * The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we decrement the bootstrap size out of it. 209 */ 210 #define LIM_MAX_SIZE ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SIZE) 211 #define LIM_OFFSET (NVM_OFFSET(lim_image)) 212 #define NVM_RSV_SIZE (44) 213 #define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : FPGA_MIM_MAX_SIZE ) 214 #define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0)) 215 #define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + MIM_MAX_SIZE(is_asic)*2) 216 217 union nvm_dir_union { 218 struct nvm_dir dir; 219 u8 page[FLASH_PAGE_SIZE]; 220 }; 221 222 /* Address 223 * +-------------------+ 0x000000 224 * | Bootstrap: | 225 * | magic_number | 226 * | sram_start_addr | 227 * | code_len | 228 * | code_start_addr | 229 * | crc | 230 * +-------------------+ 0x000014 231 * | rsrv | 232 * +-------------------+ 0x000040 233 * | LIM | 234 * +-------------------+ 0x002000 235 * | Dir1 | 236 * +-------------------+ 0x003000 237 * | Dir2 | 238 * +-------------------+ 0x004000 239 * | MIM1 | 240 * +-------------------+ 0x130000 241 * | MIM2 | 242 * +-------------------+ 0x25C000 243 * | Rest Images: | 244 * | TIM1/2 | 245 * | MFW_TRACE1/2 | 246 * | Eagle/Falcon FW | 247 * | PCIE/AVS FW | 248 * | MBA/CCM/L2B | 249 * | VPD | 250 * | optic_modules | 251 * | ... | 252 * +-------------------+ 0x400000 253 */ 254 struct nvm_image { 255 /*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 256 /* NVM Offset (size) */ 257 struct legacy_bootstrap_region bootstrap; /* 0x000000 (0x000014) */ 258 u8 rsrv[NVM_RSV_SIZE]; /* 0x000014 (0x00002c) */ 259 u8 lim_image[LIM_MAX_SIZE]; /* 0x000040 (0x001fc0) */ 260 union nvm_dir_union dir[MAX_MFW_BUNDLES]; /* 0x002000 (0x001000)x2 */ 261 /* MIM1_IMAGE 0x004000 (0x12c000) */ 262 /* MIM2_IMAGE 0x130000 (0x12c000) */ 263 /*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 264 }; /* 0x134 */ 265 266 #define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f)))) 267 268 struct hw_set_info { 269 u32 reg_type; 270 #define GRC_REG_TYPE 1 271 #define PHY_REG_TYPE 2 272 #define PCI_REG_TYPE 4 273 274 u32 bank_num; 275 u32 pf_num; 276 u32 operation; 277 #define READ_OP 1 278 #define WRITE_OP 2 279 #define RMW_SET_OP 3 280 #define RMW_CLR_OP 4 281 282 u32 reg_addr; 283 u32 reg_data; 284 285 u32 reset_type; 286 #define POR_RESET_TYPE (1 << 0) 287 #define HARD_RESET_TYPE (1 << 1) 288 #define CORE_RESET_TYPE (1 << 2) 289 #define MCP_RESET_TYPE (1 << 3) 290 #define PERSET_ASSERT (1 << 4) 291 #define PERSET_DEASSERT (1 << 5) 292 293 }; 294 295 struct hw_set_image { 296 u32 format_version; 297 #define HW_SET_IMAGE_VERSION 1 298 u32 no_hw_sets; 299 /* This array length depends on the no_hw_sets */ 300 struct hw_set_info hw_sets[1]; 301 }; 302 303 #endif //NVM_MAP_H 304