1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 32 /**************************************************************************** 33 * 34 * Name: nvm_cfg.h 35 * 36 * Description: NVM config file - Generated file from nvm cfg excel. 37 * DO NOT MODIFY !!! 38 * 39 * Created: 3/15/2017 40 * 41 ****************************************************************************/ 42 43 #ifndef NVM_CFG_H 44 #define NVM_CFG_H 45 46 #define NVM_CFG_version 0x83000 47 48 #define NVM_CFG_new_option_seq 22 49 50 #define NVM_CFG_removed_option_seq 1 51 52 #define NVM_CFG_updated_value_seq 4 53 54 struct nvm_cfg_mac_address 55 { 56 u32 mac_addr_hi; 57 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF 58 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 59 u32 mac_addr_lo; 60 }; 61 62 /****************************************** 63 * nvm_cfg1 structs 64 ******************************************/ 65 struct nvm_cfg1_glob 66 { 67 u32 generic_cont0; /* 0x0 */ 68 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F 69 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0 70 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0 71 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1 72 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2 73 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3 74 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 75 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 76 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 77 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 78 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 79 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 80 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 81 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 82 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 83 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 84 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 85 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 86 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 87 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1 88 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000 89 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13 90 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000 91 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21 92 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000 93 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29 94 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0 95 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1 96 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000 97 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 98 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 99 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 100 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK 0x80000000 101 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31 102 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED 0x0 103 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1 104 u32 engineering_change[3]; /* 0x4 */ 105 u32 manufacturing_id; /* 0x10 */ 106 u32 serial_number[4]; /* 0x14 */ 107 u32 pcie_cfg; /* 0x24 */ 108 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003 109 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0 110 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0 111 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1 112 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2 113 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004 114 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2 115 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0 116 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1 117 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018 118 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3 119 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0 120 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1 121 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2 122 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3 123 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020 124 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5 125 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0 126 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6 127 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00 128 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10 129 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0 130 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1 131 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2 132 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3 133 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000 134 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13 135 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000 136 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21 137 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000 138 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29 139 /* Set the duration, in seconds, fan failure signal should be 140 sampled */ 141 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000 142 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31 143 u32 mgmt_traffic; /* 0x28 */ 144 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001 145 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0 146 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE 147 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1 148 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00 149 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9 150 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000 151 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17 152 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000 153 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25 154 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0 155 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1 156 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2 157 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000 158 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27 159 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0 160 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1 161 /* Indicates whether external thermal sonsor is available */ 162 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000 163 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31 164 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0 165 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1 166 u32 core_cfg; /* 0x2C */ 167 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF 168 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 169 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 170 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 171 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 172 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 173 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 174 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 175 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB 176 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC 177 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD 178 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE 179 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF 180 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100 181 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8 182 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0 183 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1 184 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200 185 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9 186 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0 187 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1 188 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00 189 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10 190 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000 191 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18 192 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000 193 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26 194 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0 195 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1 196 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2 197 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3 198 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000 199 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29 200 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0 201 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1 202 #define NVM_CFG1_GLOB_DCI_SUPPORT_MASK 0x80000000 203 #define NVM_CFG1_GLOB_DCI_SUPPORT_OFFSET 31 204 #define NVM_CFG1_GLOB_DCI_SUPPORT_DISABLED 0x0 205 #define NVM_CFG1_GLOB_DCI_SUPPORT_ENABLED 0x1 206 u32 e_lane_cfg1; /* 0x30 */ 207 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 208 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 209 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 210 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 211 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 212 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 213 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 214 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 215 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 216 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 217 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 218 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 219 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 220 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 221 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 222 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 223 u32 e_lane_cfg2; /* 0x34 */ 224 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 225 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 226 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 227 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 228 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 229 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 230 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 231 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 232 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 233 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 234 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 235 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 236 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 237 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 238 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 239 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 240 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00 241 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8 242 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0 243 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1 244 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2 245 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000 246 #define NVM_CFG1_GLOB_NCSI_OFFSET 12 247 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0 248 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1 249 /* Maximum advertised pcie link width */ 250 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000 251 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16 252 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0 253 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1 254 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2 255 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3 256 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4 257 /* ASPM L1 mode */ 258 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000 259 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20 260 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0 261 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1 262 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000 263 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22 264 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0 265 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1 266 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2 267 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3 268 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK 0x06000000 269 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25 270 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0 271 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1 272 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2 273 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3 274 /* Set the PLDM sensor modes */ 275 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000 276 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27 277 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0 278 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1 279 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2 280 /* Enable VDM interface */ 281 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_MASK 0x40000000 282 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_OFFSET 30 283 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_DISABLED 0x0 284 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_ENABLED 0x1 285 /* ROL enable */ 286 #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000 287 #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31 288 #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0 289 #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1 290 u32 f_lane_cfg1; /* 0x38 */ 291 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 292 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 293 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 294 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 295 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 296 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 297 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 298 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 299 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 300 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 301 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 302 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 303 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 304 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 305 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 306 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 307 u32 f_lane_cfg2; /* 0x3C */ 308 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 309 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 310 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 311 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 312 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 313 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 314 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 315 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 316 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 317 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 318 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 319 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 320 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 321 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 322 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 323 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 324 /* Control the period between two successive checks */ 325 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK 0x0000FF00 326 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8 327 /* Set shutdown temperature */ 328 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 329 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16 330 /* Set max. count for over operational temperature */ 331 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000 332 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24 333 u32 mps10_preemphasis; /* 0x40 */ 334 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 335 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 336 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 337 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 338 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 339 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 340 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 341 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 342 u32 mps10_driver_current; /* 0x44 */ 343 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 344 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 345 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 346 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 347 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 348 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 349 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 350 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 351 u32 mps25_preemphasis; /* 0x48 */ 352 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 353 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 354 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 355 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 356 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 357 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 358 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 359 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 360 u32 mps25_driver_current; /* 0x4C */ 361 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 362 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 363 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 364 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 365 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 366 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 367 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 368 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 369 u32 pci_id; /* 0x50 */ 370 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF 371 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0 372 /* Set caution temperature */ 373 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 374 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16 375 /* Set external thermal sensor I2C address */ 376 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK 0xFF000000 377 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24 378 u32 pci_subsys_id; /* 0x54 */ 379 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF 380 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0 381 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000 382 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16 383 u32 bar; /* 0x58 */ 384 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F 385 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0 386 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0 387 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1 388 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2 389 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3 390 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4 391 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5 392 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6 393 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7 394 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8 395 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9 396 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA 397 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB 398 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC 399 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD 400 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE 401 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF 402 /* BB VF BAR2 size */ 403 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0 404 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4 405 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0 406 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1 407 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2 408 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3 409 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4 410 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5 411 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6 412 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7 413 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8 414 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9 415 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA 416 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB 417 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC 418 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD 419 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE 420 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF 421 /* BB BAR2 size (global) */ 422 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00 423 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8 424 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0 425 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1 426 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2 427 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3 428 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4 429 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5 430 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6 431 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7 432 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8 433 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9 434 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA 435 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB 436 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC 437 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD 438 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE 439 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF 440 /* Set the duration, in seconds, fan failure signal should be 441 sampled */ 442 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000 443 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12 444 /* This field defines the board total budget for bar2 when disabled 445 the regular bar size is used. */ 446 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000 447 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16 448 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0 449 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1 450 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2 451 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3 452 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4 453 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5 454 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6 455 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7 456 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8 457 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9 458 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA 459 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB 460 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC 461 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD 462 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE 463 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF 464 /* Enable/Disable Crash dump triggers */ 465 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000 466 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24 467 u32 mps10_txfir_main; /* 0x5C */ 468 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 469 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 470 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 471 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 472 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 473 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 474 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 475 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 476 u32 mps10_txfir_post; /* 0x60 */ 477 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 478 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 479 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 480 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 481 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 482 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 483 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 484 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 485 u32 mps25_txfir_main; /* 0x64 */ 486 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 487 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 488 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 489 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 490 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 491 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 492 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 493 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 494 u32 mps25_txfir_post; /* 0x68 */ 495 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 496 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 497 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 498 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 499 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 500 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 501 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 502 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 503 u32 manufacture_ver; /* 0x6C */ 504 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F 505 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0 506 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0 507 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6 508 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000 509 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12 510 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000 511 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18 512 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000 513 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24 514 /* Select package id method */ 515 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000 516 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30 517 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0 518 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1 519 #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000 520 #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31 521 #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0 522 #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1 523 u32 manufacture_time; /* 0x70 */ 524 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F 525 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0 526 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0 527 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6 528 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000 529 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12 530 /* Max MSIX for Ethernet in default mode */ 531 #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000 532 #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18 533 /* PF Mapping */ 534 #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000 535 #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26 536 #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0 537 #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1 538 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000 539 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28 540 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0 541 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1 542 u32 led_global_settings; /* 0x74 */ 543 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F 544 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 545 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0 546 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4 547 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00 548 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8 549 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000 550 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12 551 /* Max. continues operating temperature */ 552 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000 553 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16 554 /* GPIO which triggers run-time port swap according to the map 555 specified in option 205 */ 556 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000 557 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24 558 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0 559 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1 560 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2 561 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3 562 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4 563 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5 564 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6 565 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7 566 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8 567 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9 568 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA 569 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB 570 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC 571 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD 572 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE 573 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF 574 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10 575 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11 576 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12 577 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13 578 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14 579 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15 580 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16 581 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17 582 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18 583 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19 584 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A 585 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B 586 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C 587 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D 588 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E 589 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F 590 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20 591 u32 generic_cont1; /* 0x78 */ 592 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF 593 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0 594 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00 595 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10 596 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000 597 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12 598 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000 599 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14 600 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000 601 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16 602 /* Enable option 195 - Overriding the PCIe Preset value */ 603 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000 604 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18 605 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0 606 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1 607 /* PCIe Preset value - applies only if option 194 is enabled */ 608 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000 609 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19 610 /* Port mapping to be used when the run-time GPIO for port-swap is 611 defined and set. */ 612 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000 613 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23 614 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000 615 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25 616 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000 617 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27 618 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000 619 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29 620 u32 mbi_version; /* 0x7C */ 621 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF 622 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 623 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 624 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 625 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 626 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 627 /* If set to other than NA, 0 - Normal operation, 1 - Thermal event 628 occurred */ 629 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000 630 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24 631 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0 632 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1 633 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2 634 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3 635 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4 636 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5 637 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6 638 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7 639 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8 640 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9 641 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA 642 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB 643 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC 644 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD 645 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE 646 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF 647 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10 648 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11 649 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12 650 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13 651 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14 652 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15 653 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16 654 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17 655 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18 656 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19 657 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A 658 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B 659 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C 660 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D 661 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E 662 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F 663 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20 664 u32 mbi_date; /* 0x80 */ 665 u32 misc_sig; /* 0x84 */ 666 /* Define the GPIO mapping to switch i2c mux */ 667 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF 668 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0 669 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00 670 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8 671 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0 672 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1 673 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2 674 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3 675 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4 676 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5 677 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6 678 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7 679 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8 680 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9 681 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA 682 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB 683 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC 684 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD 685 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE 686 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF 687 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10 688 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11 689 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12 690 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13 691 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14 692 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15 693 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16 694 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17 695 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18 696 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19 697 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A 698 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B 699 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C 700 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D 701 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E 702 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F 703 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20 704 /* Interrupt signal used for SMBus/I2C management interface 705 706 0 = Interrupt event occurred 707 1 = Normal 708 */ 709 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000 710 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16 711 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0 712 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1 713 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2 714 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3 715 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4 716 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5 717 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6 718 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7 719 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8 720 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9 721 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA 722 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB 723 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC 724 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD 725 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE 726 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF 727 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10 728 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11 729 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12 730 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13 731 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14 732 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15 733 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16 734 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17 735 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18 736 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19 737 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A 738 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B 739 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C 740 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D 741 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E 742 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F 743 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20 744 /* Set aLOM FAN on GPIO */ 745 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000 746 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24 747 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0 748 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1 749 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2 750 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3 751 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4 752 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5 753 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6 754 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7 755 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8 756 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9 757 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA 758 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB 759 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC 760 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD 761 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE 762 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF 763 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10 764 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11 765 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12 766 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13 767 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14 768 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15 769 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16 770 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17 771 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18 772 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19 773 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A 774 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B 775 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C 776 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D 777 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E 778 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F 779 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20 780 u32 device_capabilities; /* 0x88 */ 781 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 782 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 783 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 784 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 785 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10 786 u32 power_dissipated; /* 0x8C */ 787 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF 788 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0 789 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00 790 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8 791 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000 792 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16 793 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000 794 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24 795 u32 power_consumed; /* 0x90 */ 796 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF 797 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0 798 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00 799 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8 800 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000 801 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16 802 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000 803 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24 804 u32 efi_version; /* 0x94 */ 805 u32 multi_network_modes_capability; /* 0x98 */ 806 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1 807 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2 808 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4 809 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8 810 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10 811 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20 812 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40 813 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G 0x80 814 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100 815 u32 nvm_cfg_version; /* 0x9C */ 816 u32 nvm_cfg_new_option_seq; /* 0xA0 */ 817 u32 nvm_cfg_removed_option_seq; /* 0xA4 */ 818 u32 nvm_cfg_updated_value_seq; /* 0xA8 */ 819 u32 extended_serial_number[8]; /* 0xAC */ 820 u32 oem1_number[8]; /* 0xCC */ 821 u32 oem2_number[8]; /* 0xEC */ 822 u32 mps25_active_txfir_pre; /* 0x10C */ 823 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF 824 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0 825 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00 826 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8 827 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000 828 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16 829 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000 830 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24 831 u32 mps25_active_txfir_main; /* 0x110 */ 832 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF 833 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0 834 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00 835 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8 836 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000 837 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16 838 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000 839 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24 840 u32 mps25_active_txfir_post; /* 0x114 */ 841 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF 842 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0 843 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00 844 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8 845 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000 846 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16 847 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000 848 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24 849 u32 features; /* 0x118 */ 850 /* Set the Aux Fan on temperature */ 851 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF 852 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0 853 /* Set NC-SI package ID */ 854 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00 855 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8 856 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0 857 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1 858 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2 859 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3 860 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4 861 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5 862 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6 863 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7 864 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8 865 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9 866 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA 867 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB 868 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC 869 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD 870 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE 871 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF 872 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10 873 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11 874 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12 875 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13 876 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14 877 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15 878 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16 879 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17 880 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18 881 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19 882 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A 883 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B 884 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C 885 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D 886 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E 887 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F 888 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20 889 /* PMBUS Clock GPIO */ 890 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000 891 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16 892 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0 893 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1 894 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2 895 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3 896 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4 897 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5 898 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6 899 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7 900 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8 901 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9 902 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA 903 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB 904 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC 905 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD 906 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE 907 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF 908 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10 909 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11 910 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12 911 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13 912 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14 913 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15 914 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16 915 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17 916 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18 917 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19 918 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A 919 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B 920 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C 921 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D 922 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E 923 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F 924 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20 925 /* PMBUS Data GPIO */ 926 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000 927 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24 928 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0 929 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1 930 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2 931 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3 932 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4 933 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5 934 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6 935 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7 936 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8 937 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9 938 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA 939 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB 940 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC 941 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD 942 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE 943 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF 944 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10 945 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11 946 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12 947 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13 948 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14 949 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15 950 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16 951 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17 952 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18 953 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19 954 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A 955 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B 956 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C 957 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D 958 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E 959 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F 960 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20 961 u32 tx_rx_eq_25g_hlpc; /* 0x11C */ 962 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF 963 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0 964 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00 965 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8 966 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000 967 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16 968 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000 969 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24 970 u32 tx_rx_eq_25g_llpc; /* 0x120 */ 971 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF 972 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0 973 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00 974 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8 975 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000 976 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16 977 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000 978 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24 979 u32 tx_rx_eq_25g_ac; /* 0x124 */ 980 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF 981 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0 982 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00 983 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8 984 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000 985 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16 986 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000 987 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24 988 u32 tx_rx_eq_10g_pc; /* 0x128 */ 989 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF 990 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0 991 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00 992 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8 993 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000 994 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16 995 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000 996 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24 997 u32 tx_rx_eq_10g_ac; /* 0x12C */ 998 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF 999 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0 1000 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00 1001 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8 1002 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000 1003 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16 1004 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000 1005 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24 1006 u32 tx_rx_eq_1g; /* 0x130 */ 1007 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF 1008 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0 1009 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00 1010 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8 1011 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000 1012 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16 1013 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000 1014 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24 1015 u32 tx_rx_eq_25g_bt; /* 0x134 */ 1016 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF 1017 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0 1018 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00 1019 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8 1020 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000 1021 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16 1022 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000 1023 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24 1024 u32 tx_rx_eq_10g_bt; /* 0x138 */ 1025 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF 1026 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0 1027 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00 1028 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8 1029 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000 1030 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16 1031 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000 1032 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24 1033 u32 generic_cont4; /* 0x13C */ 1034 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF 1035 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0 1036 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0 1037 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1 1038 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2 1039 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3 1040 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4 1041 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5 1042 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6 1043 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7 1044 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8 1045 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9 1046 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA 1047 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB 1048 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC 1049 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD 1050 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE 1051 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF 1052 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10 1053 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11 1054 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12 1055 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13 1056 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14 1057 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15 1058 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16 1059 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17 1060 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18 1061 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19 1062 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A 1063 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B 1064 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C 1065 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D 1066 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E 1067 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F 1068 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20 1069 u32 preboot_debug_mode_std; /* 0x140 */ 1070 u32 preboot_debug_mode_ext; /* 0x144 */ 1071 u32 reserved[56]; /* 0x148 */ 1072 }; 1073 1074 struct nvm_cfg1_path 1075 { 1076 u32 reserved[1]; /* 0x0 */ 1077 }; 1078 1079 struct nvm_cfg1_port 1080 { 1081 u32 reserved__m_relocated_to_option_123; /* 0x0 */ 1082 u32 reserved__m_relocated_to_option_124; /* 0x4 */ 1083 u32 generic_cont0; /* 0x8 */ 1084 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF 1085 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0 1086 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0 1087 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1 1088 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2 1089 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3 1090 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4 1091 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5 1092 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6 1093 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7 1094 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8 1095 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9 1096 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA 1097 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB 1098 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC 1099 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD 1100 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE 1101 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF 1102 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10 1103 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00 1104 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8 1105 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 1106 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 1107 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 1108 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 1109 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 1110 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 1111 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 1112 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 1113 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 1114 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 1115 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 1116 /* GPIO for HW reset the PHY. In case it is the same for all ports, 1117 need to set same value for all ports */ 1118 #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000 1119 #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24 1120 #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0 1121 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1 1122 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2 1123 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3 1124 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4 1125 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5 1126 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6 1127 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7 1128 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8 1129 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9 1130 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA 1131 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB 1132 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC 1133 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD 1134 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE 1135 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF 1136 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10 1137 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11 1138 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12 1139 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13 1140 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14 1141 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15 1142 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16 1143 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17 1144 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18 1145 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19 1146 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A 1147 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B 1148 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C 1149 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D 1150 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E 1151 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F 1152 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20 1153 u32 pcie_cfg; /* 0xC */ 1154 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007 1155 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0 1156 u32 features; /* 0x10 */ 1157 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001 1158 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0 1159 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0 1160 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1 1161 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002 1162 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1 1163 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0 1164 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1 1165 u32 speed_cap_mask; /* 0x14 */ 1166 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1167 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1168 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1169 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1170 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1171 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1172 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1173 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1174 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1175 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1176 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1177 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1178 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1179 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1180 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1181 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1182 u32 link_settings; /* 0x18 */ 1183 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F 1184 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 1185 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 1186 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 1187 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 1188 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 1189 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 1190 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 1191 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 1192 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 1193 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 1194 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 1195 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 1196 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 1197 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780 1198 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7 1199 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 1200 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 1201 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 1202 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 1203 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 1204 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 1205 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7 1206 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800 1207 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11 1208 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1 1209 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2 1210 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4 1211 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000 1212 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14 1213 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0 1214 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1 1215 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000 1216 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15 1217 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0 1218 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1 1219 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000 1220 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 1221 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0 1222 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1 1223 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2 1224 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7 1225 #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000 1226 #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20 1227 #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0 1228 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1 1229 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2 1230 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3 1231 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4 1232 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5 1233 #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6 1234 #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000 1235 #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23 1236 #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0 1237 #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1 1238 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000 1239 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24 1240 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0 1241 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1 1242 u32 phy_cfg; /* 0x1C */ 1243 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF 1244 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 1245 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1 1246 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2 1247 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4 1248 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8 1249 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10 1250 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000 1251 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16 1252 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0 1253 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2 1254 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3 1255 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4 1256 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8 1257 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9 1258 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB 1259 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC 1260 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11 1261 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12 1262 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21 1263 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22 1264 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31 1265 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000 1266 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24 1267 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0 1268 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1 1269 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2 1270 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3 1271 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4 1272 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5 1273 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6 1274 u32 mgmt_traffic; /* 0x20 */ 1275 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F 1276 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0 1277 u32 ext_phy; /* 0x24 */ 1278 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF 1279 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0 1280 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 1281 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1 1282 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 1283 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 1284 /* EEE power saving mode */ 1285 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000 1286 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 1287 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 1288 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 1289 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 1290 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 1291 u32 mba_cfg1; /* 0x28 */ 1292 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001 1293 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0 1294 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0 1295 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1 1296 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006 1297 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1 1298 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078 1299 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3 1300 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080 1301 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7 1302 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0 1303 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1 1304 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100 1305 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8 1306 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0 1307 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1 1308 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00 1309 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9 1310 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000 1311 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17 1312 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 1313 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 1314 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 1315 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 1316 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 1317 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 1318 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7 1319 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000 1320 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21 1321 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK 0x01000000 1322 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24 1323 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED 0x0 1324 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1 1325 u32 mba_cfg2; /* 0x2C */ 1326 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF 1327 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0 1328 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 1329 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16 1330 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000 1331 #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17 1332 u32 vf_cfg; /* 0x30 */ 1333 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF 1334 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0 1335 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000 1336 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16 1337 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */ 1338 u32 led_port_settings; /* 0x3C */ 1339 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF 1340 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0 1341 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00 1342 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8 1343 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000 1344 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 1345 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 1346 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 1347 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4 1348 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8 1349 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8 1350 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10 1351 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10 1352 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20 1353 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40 1354 u32 transceiver_00; /* 0x40 */ 1355 /* Define for mapping of transceiver signal module absent */ 1356 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF 1357 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0 1358 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0 1359 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1 1360 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2 1361 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3 1362 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4 1363 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5 1364 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6 1365 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7 1366 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8 1367 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9 1368 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA 1369 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB 1370 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC 1371 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD 1372 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE 1373 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF 1374 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10 1375 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11 1376 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12 1377 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13 1378 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14 1379 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15 1380 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16 1381 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17 1382 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18 1383 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19 1384 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A 1385 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B 1386 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C 1387 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D 1388 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E 1389 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F 1390 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20 1391 /* Define the GPIO mux settings to switch i2c mux to this port */ 1392 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00 1393 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 1394 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 1395 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 1396 u32 device_ids; /* 0x44 */ 1397 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF 1398 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 1399 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00 1400 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8 1401 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000 1402 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16 1403 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000 1404 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24 1405 u32 board_cfg; /* 0x48 */ 1406 /* This field defines the board technology 1407 (backpane,transceiver,external PHY) */ 1408 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF 1409 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 1410 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 1411 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 1412 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 1413 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 1414 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 1415 /* This field defines the GPIO mapped to tx_disable signal in SFP */ 1416 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00 1417 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8 1418 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0 1419 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1 1420 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2 1421 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3 1422 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4 1423 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5 1424 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6 1425 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7 1426 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8 1427 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9 1428 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA 1429 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB 1430 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC 1431 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD 1432 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE 1433 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF 1434 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10 1435 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11 1436 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12 1437 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13 1438 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14 1439 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15 1440 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16 1441 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17 1442 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18 1443 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19 1444 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A 1445 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B 1446 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C 1447 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D 1448 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E 1449 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F 1450 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20 1451 u32 mnm_10g_cap; /* 0x4C */ 1452 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1453 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1454 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1455 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1456 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1457 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1458 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1459 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1460 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1461 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1462 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1463 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1464 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1465 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1466 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1467 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1468 u32 mnm_10g_ctrl; /* 0x50 */ 1469 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F 1470 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0 1471 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0 1472 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1 1473 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2 1474 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4 1475 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5 1476 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6 1477 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7 1478 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0 1479 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4 1480 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0 1481 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1 1482 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2 1483 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4 1484 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5 1485 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6 1486 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7 1487 /* This field defines the board technology 1488 (backpane,transceiver,external PHY) */ 1489 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00 1490 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8 1491 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0 1492 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1 1493 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2 1494 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3 1495 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4 1496 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1497 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16 1498 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0 1499 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2 1500 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3 1501 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4 1502 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8 1503 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9 1504 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB 1505 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC 1506 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11 1507 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12 1508 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21 1509 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22 1510 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31 1511 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000 1512 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24 1513 u32 mnm_10g_misc; /* 0x54 */ 1514 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007 1515 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0 1516 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0 1517 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1 1518 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2 1519 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7 1520 u32 mnm_25g_cap; /* 0x58 */ 1521 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1522 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1523 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1524 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1525 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1526 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1527 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1528 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1529 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1530 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1531 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1532 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1533 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1534 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1535 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1536 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1537 u32 mnm_25g_ctrl; /* 0x5C */ 1538 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F 1539 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0 1540 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0 1541 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1 1542 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2 1543 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4 1544 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5 1545 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6 1546 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7 1547 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0 1548 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4 1549 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0 1550 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1 1551 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2 1552 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4 1553 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5 1554 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6 1555 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7 1556 /* This field defines the board technology 1557 (backpane,transceiver,external PHY) */ 1558 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00 1559 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8 1560 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0 1561 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1 1562 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2 1563 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3 1564 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4 1565 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1566 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16 1567 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0 1568 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2 1569 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3 1570 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4 1571 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8 1572 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9 1573 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB 1574 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC 1575 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11 1576 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12 1577 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21 1578 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22 1579 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31 1580 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000 1581 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24 1582 u32 mnm_25g_misc; /* 0x60 */ 1583 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007 1584 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0 1585 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0 1586 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1 1587 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2 1588 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7 1589 u32 mnm_40g_cap; /* 0x64 */ 1590 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1591 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1592 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1593 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1594 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1595 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1596 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1597 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1598 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1599 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1600 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1601 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1602 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1603 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1604 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1605 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1606 u32 mnm_40g_ctrl; /* 0x68 */ 1607 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F 1608 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0 1609 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0 1610 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1 1611 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2 1612 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4 1613 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5 1614 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6 1615 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7 1616 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0 1617 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4 1618 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0 1619 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1 1620 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2 1621 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4 1622 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5 1623 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6 1624 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7 1625 /* This field defines the board technology 1626 (backpane,transceiver,external PHY) */ 1627 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00 1628 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8 1629 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0 1630 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1 1631 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2 1632 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3 1633 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4 1634 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1635 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16 1636 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0 1637 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2 1638 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3 1639 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4 1640 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8 1641 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9 1642 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB 1643 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC 1644 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11 1645 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12 1646 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21 1647 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22 1648 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31 1649 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000 1650 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24 1651 u32 mnm_40g_misc; /* 0x6C */ 1652 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007 1653 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0 1654 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0 1655 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1 1656 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2 1657 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7 1658 u32 mnm_50g_cap; /* 0x70 */ 1659 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1660 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1661 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1662 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1663 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1664 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1665 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1666 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1667 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1668 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1669 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1670 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1671 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1672 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1673 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1674 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1675 u32 mnm_50g_ctrl; /* 0x74 */ 1676 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F 1677 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0 1678 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0 1679 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1 1680 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2 1681 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4 1682 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5 1683 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6 1684 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7 1685 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0 1686 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4 1687 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0 1688 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1 1689 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2 1690 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4 1691 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5 1692 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6 1693 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7 1694 /* This field defines the board technology 1695 (backpane,transceiver,external PHY) */ 1696 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00 1697 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8 1698 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0 1699 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1 1700 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2 1701 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3 1702 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4 1703 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1704 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16 1705 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0 1706 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2 1707 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3 1708 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4 1709 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8 1710 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9 1711 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB 1712 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC 1713 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11 1714 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12 1715 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21 1716 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22 1717 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31 1718 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000 1719 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24 1720 u32 mnm_50g_misc; /* 0x78 */ 1721 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007 1722 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0 1723 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0 1724 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1 1725 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2 1726 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7 1727 u32 mnm_100g_cap; /* 0x7C */ 1728 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK 0x0000FFFF 1729 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0 1730 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1 1731 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2 1732 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8 1733 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10 1734 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20 1735 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40 1736 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK 0xFFFF0000 1737 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16 1738 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1 1739 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2 1740 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8 1741 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10 1742 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20 1743 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40 1744 u32 mnm_100g_ctrl; /* 0x80 */ 1745 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F 1746 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0 1747 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0 1748 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1 1749 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2 1750 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4 1751 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5 1752 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6 1753 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7 1754 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0 1755 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4 1756 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0 1757 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1 1758 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2 1759 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4 1760 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5 1761 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6 1762 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7 1763 /* This field defines the board technology 1764 (backpane,transceiver,external PHY) */ 1765 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00 1766 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8 1767 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0 1768 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1 1769 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2 1770 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3 1771 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4 1772 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1773 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16 1774 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0 1775 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2 1776 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3 1777 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4 1778 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8 1779 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9 1780 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB 1781 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC 1782 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11 1783 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12 1784 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21 1785 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22 1786 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31 1787 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000 1788 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24 1789 u32 mnm_100g_misc; /* 0x84 */ 1790 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007 1791 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0 1792 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0 1793 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1 1794 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2 1795 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7 1796 u32 temperature; /* 0x88 */ 1797 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF 1798 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0 1799 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK 0x0000FF00 1800 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8 1801 u32 reserved[115]; /* 0x8C */ 1802 }; 1803 1804 struct nvm_cfg1_func 1805 { 1806 struct nvm_cfg_mac_address mac_address; /* 0x0 */ 1807 u32 rsrv1; /* 0x8 */ 1808 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF 1809 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0 1810 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000 1811 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16 1812 u32 rsrv2; /* 0xC */ 1813 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF 1814 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0 1815 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000 1816 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16 1817 u32 device_id; /* 0x10 */ 1818 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF 1819 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0 1820 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000 1821 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16 1822 u32 cmn_cfg; /* 0x14 */ 1823 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007 1824 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0 1825 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0 1826 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3 1827 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4 1828 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7 1829 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8 1830 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3 1831 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000 1832 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19 1833 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 1834 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1 1835 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2 1836 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3 1837 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 1838 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 1839 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 1840 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31 1841 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0 1842 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1 1843 u32 pci_cfg; /* 0x18 */ 1844 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F 1845 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0 1846 /* AH VF BAR2 size */ 1847 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80 1848 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7 1849 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0 1850 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1 1851 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2 1852 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3 1853 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4 1854 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5 1855 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6 1856 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7 1857 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8 1858 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9 1859 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA 1860 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB 1861 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC 1862 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD 1863 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE 1864 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF 1865 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000 1866 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14 1867 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0 1868 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1 1869 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2 1870 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3 1871 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4 1872 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5 1873 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6 1874 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7 1875 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8 1876 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9 1877 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA 1878 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB 1879 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC 1880 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD 1881 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE 1882 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF 1883 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000 1884 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18 1885 /* Hide function in npar mode */ 1886 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000 1887 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26 1888 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0 1889 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1 1890 /* AH BAR2 size (per function) */ 1891 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000 1892 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27 1893 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0 1894 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5 1895 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6 1896 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7 1897 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8 1898 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9 1899 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA 1900 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB 1901 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC 1902 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD 1903 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE 1904 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF 1905 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */ 1906 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */ 1907 u32 preboot_generic_cfg; /* 0x2C */ 1908 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF 1909 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0 1910 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000 1911 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16 1912 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000 1913 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17 1914 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1 1915 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2 1916 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4 1917 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8 1918 u32 features; /* 0x30 */ 1919 /* RDMA protocol enablement */ 1920 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_MASK 0x00000003 1921 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_OFFSET 0 1922 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_NONE 0x0 1923 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_ROCE 0x1 1924 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_IWARP 0x2 1925 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_BOTH 0x3 1926 u32 reserved[7]; /* 0x34 */ 1927 }; 1928 1929 struct nvm_cfg1 1930 { 1931 struct nvm_cfg1_glob glob; /* 0x0 */ 1932 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */ 1933 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */ 1934 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */ 1935 }; 1936 1937 /****************************************** 1938 * nvm_cfg structs 1939 ******************************************/ 1940 enum nvm_cfg_sections 1941 { 1942 NVM_CFG_SECTION_NVM_CFG1, 1943 NVM_CFG_SECTION_MAX 1944 }; 1945 1946 struct nvm_cfg 1947 { 1948 u32 num_sections; 1949 u32 sections_offset[NVM_CFG_SECTION_MAX]; 1950 struct nvm_cfg1 cfg1; 1951 }; 1952 1953 #endif /* NVM_CFG_H */ 1954 1955