1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 32 /**************************************************************************** 33 * 34 * Name: nvm_cfg.h 35 * 36 * Description: NVM config file - Generated file from nvm cfg excel. 37 * DO NOT MODIFY !!! 38 * 39 * Created: 2/4/2017 40 * 41 ****************************************************************************/ 42 43 #ifndef NVM_CFG_H 44 #define NVM_CFG_H 45 46 #define NVM_CFG_version 0x81812 47 48 #define NVM_CFG_new_option_seq 20 49 50 #define NVM_CFG_removed_option_seq 1 51 52 #define NVM_CFG_updated_value_seq 3 53 54 struct nvm_cfg_mac_address 55 { 56 u32 mac_addr_hi; 57 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF 58 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 59 u32 mac_addr_lo; 60 }; 61 62 /****************************************** 63 * nvm_cfg1 structs 64 ******************************************/ 65 struct nvm_cfg1_glob 66 { 67 u32 generic_cont0; /* 0x0 */ 68 #define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F 69 #define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0 70 #define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0 71 #define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1 72 #define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2 73 #define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3 74 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 75 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 76 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 77 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 78 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 79 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 80 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 81 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 82 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 83 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 84 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 85 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 86 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 87 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1 88 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000 89 #define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13 90 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000 91 #define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21 92 #define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000 93 #define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29 94 #define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0 95 #define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1 96 #define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000 97 #define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30 98 #define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0 99 #define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1 100 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_MASK 0x80000000 101 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_OFFSET 31 102 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_DISABLED 0x0 103 #define NVM_CFG1_GLOB_RESERVED__M_WAS_CLOCK_SLOWDOWN_ENABLED 0x1 104 u32 engineering_change[3]; /* 0x4 */ 105 u32 manufacturing_id; /* 0x10 */ 106 u32 serial_number[4]; /* 0x14 */ 107 u32 pcie_cfg; /* 0x24 */ 108 #define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003 109 #define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0 110 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0 111 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1 112 #define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2 113 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004 114 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2 115 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0 116 #define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1 117 #define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018 118 #define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3 119 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0 120 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1 121 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2 122 #define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3 123 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020 124 #define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5 125 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0 126 #define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6 127 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00 128 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10 129 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0 130 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1 131 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2 132 #define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3 133 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000 134 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13 135 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000 136 #define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21 137 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000 138 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29 139 /* Set the duration, in seconds, fan failure signal should be 140 sampled */ 141 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000 142 #define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31 143 u32 mgmt_traffic; /* 0x28 */ 144 #define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001 145 #define NVM_CFG1_GLOB_RESERVED60_OFFSET 0 146 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE 147 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1 148 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00 149 #define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9 150 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000 151 #define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17 152 #define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000 153 #define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25 154 #define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0 155 #define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1 156 #define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2 157 #define NVM_CFG1_GLOB_AUX_MODE_MASK 0x78000000 158 #define NVM_CFG1_GLOB_AUX_MODE_OFFSET 27 159 #define NVM_CFG1_GLOB_AUX_MODE_DEFAULT 0x0 160 #define NVM_CFG1_GLOB_AUX_MODE_SMBUS_ONLY 0x1 161 /* Indicates whether external thermal sonsor is available */ 162 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_MASK 0x80000000 163 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_OFFSET 31 164 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_DISABLED 0x0 165 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ENABLED 0x1 166 u32 core_cfg; /* 0x2C */ 167 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF 168 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 169 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 170 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 171 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 172 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 173 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 174 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 175 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB 176 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC 177 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD 178 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE 179 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF 180 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100 181 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8 182 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0 183 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1 184 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200 185 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9 186 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0 187 #define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1 188 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00 189 #define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10 190 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000 191 #define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18 192 #define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000 193 #define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26 194 #define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0 195 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_CFG 0x1 196 #define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP_OTP 0x2 197 #define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3 198 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000 199 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29 200 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0 201 #define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1 202 #define NVM_CFG1_GLOB_DCI_SUPPORT_MASK 0x80000000 203 #define NVM_CFG1_GLOB_DCI_SUPPORT_OFFSET 31 204 #define NVM_CFG1_GLOB_DCI_SUPPORT_DISABLED 0x0 205 #define NVM_CFG1_GLOB_DCI_SUPPORT_ENABLED 0x1 206 u32 e_lane_cfg1; /* 0x30 */ 207 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 208 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 209 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 210 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 211 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 212 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 213 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 214 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 215 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 216 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 217 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 218 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 219 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 220 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 221 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 222 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 223 u32 e_lane_cfg2; /* 0x34 */ 224 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 225 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 226 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 227 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 228 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 229 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 230 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 231 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 232 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 233 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 234 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 235 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 236 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 237 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 238 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 239 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 240 #define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00 241 #define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8 242 #define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0 243 #define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1 244 #define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2 245 #define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000 246 #define NVM_CFG1_GLOB_NCSI_OFFSET 12 247 #define NVM_CFG1_GLOB_NCSI_DISABLED 0x0 248 #define NVM_CFG1_GLOB_NCSI_ENABLED 0x1 249 /* Maximum advertised pcie link width */ 250 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000 251 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16 252 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0 253 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1 254 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2 255 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3 256 #define NVM_CFG1_GLOB_MAX_LINK_WIDTH_8_LANES 0x4 257 /* ASPM L1 mode */ 258 #define NVM_CFG1_GLOB_ASPM_L1_MODE_MASK 0x00300000 259 #define NVM_CFG1_GLOB_ASPM_L1_MODE_OFFSET 20 260 #define NVM_CFG1_GLOB_ASPM_L1_MODE_FORCED 0x0 261 #define NVM_CFG1_GLOB_ASPM_L1_MODE_DYNAMIC_LOW_LATENCY 0x1 262 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_MASK 0x01C00000 263 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_OFFSET 22 264 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_DISABLED 0x0 265 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_I2C 0x1 266 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_ONLY 0x2 267 #define NVM_CFG1_GLOB_ON_CHIP_SENSOR_MODE_INT_EXT_SMBUS 0x3 268 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_MASK 0x06000000 269 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_OFFSET 25 270 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_DISABLE 0x0 271 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_INTERNAL 0x1 272 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_EXTERNAL 0x2 273 #define NVM_CFG1_GLOB_TEMPERATURE_MONITORING_MODE_BOTH 0x3 274 /* Set the PLDM sensor modes */ 275 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_MASK 0x38000000 276 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_OFFSET 27 277 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_INTERNAL 0x0 278 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_EXTERNAL 0x1 279 #define NVM_CFG1_GLOB_PLDM_SENSOR_MODE_BOTH 0x2 280 /* Enable VDM interface */ 281 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_MASK 0x40000000 282 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_OFFSET 30 283 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_DISABLED 0x0 284 #define NVM_CFG1_GLOB_PCIE_VDM_ENABLED_ENABLED 0x1 285 /* ROL enable */ 286 #define NVM_CFG1_GLOB_RESET_ON_LAN_MASK 0x80000000 287 #define NVM_CFG1_GLOB_RESET_ON_LAN_OFFSET 31 288 #define NVM_CFG1_GLOB_RESET_ON_LAN_DISABLED 0x0 289 #define NVM_CFG1_GLOB_RESET_ON_LAN_ENABLED 0x1 290 u32 f_lane_cfg1; /* 0x38 */ 291 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F 292 #define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0 293 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0 294 #define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4 295 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00 296 #define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8 297 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000 298 #define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12 299 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000 300 #define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16 301 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000 302 #define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20 303 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000 304 #define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24 305 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000 306 #define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28 307 u32 f_lane_cfg2; /* 0x3C */ 308 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001 309 #define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0 310 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002 311 #define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1 312 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004 313 #define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2 314 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008 315 #define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3 316 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010 317 #define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4 318 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020 319 #define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5 320 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040 321 #define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6 322 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080 323 #define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7 324 /* Control the period between two successive checks */ 325 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_MASK 0x0000FF00 326 #define NVM_CFG1_GLOB_TEMPERATURE_PERIOD_BETWEEN_CHECKS_OFFSET 8 327 /* Set shutdown temperature */ 328 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 329 #define NVM_CFG1_GLOB_SHUTDOWN_THRESHOLD_TEMPERATURE_OFFSET 16 330 /* Set max. count for over operational temperature */ 331 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000 332 #define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24 333 u32 mps10_preemphasis; /* 0x40 */ 334 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 335 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 336 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 337 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 338 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 339 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 340 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 341 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 342 u32 mps10_driver_current; /* 0x44 */ 343 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 344 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 345 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 346 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 347 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 348 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 349 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 350 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 351 u32 mps25_preemphasis; /* 0x48 */ 352 #define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF 353 #define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0 354 #define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00 355 #define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8 356 #define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000 357 #define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16 358 #define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000 359 #define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24 360 u32 mps25_driver_current; /* 0x4C */ 361 #define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF 362 #define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0 363 #define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00 364 #define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8 365 #define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000 366 #define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16 367 #define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000 368 #define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24 369 u32 pci_id; /* 0x50 */ 370 #define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF 371 #define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0 372 /* Set caution temperature */ 373 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_MASK 0x00FF0000 374 #define NVM_CFG1_GLOB_CAUTION_THRESHOLD_TEMPERATURE_OFFSET 16 375 /* Set external thermal sensor I2C address */ 376 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_MASK 0xFF000000 377 #define NVM_CFG1_GLOB_EXTERNAL_THERMAL_SENSOR_ADDRESS_OFFSET 24 378 u32 pci_subsys_id; /* 0x54 */ 379 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF 380 #define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0 381 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000 382 #define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16 383 u32 bar; /* 0x58 */ 384 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F 385 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0 386 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0 387 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1 388 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2 389 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3 390 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4 391 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5 392 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6 393 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7 394 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8 395 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9 396 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA 397 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB 398 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC 399 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD 400 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE 401 #define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF 402 /* BB VF BAR2 size */ 403 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0 404 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4 405 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0 406 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1 407 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2 408 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3 409 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4 410 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5 411 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6 412 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7 413 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8 414 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9 415 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA 416 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB 417 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC 418 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD 419 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE 420 #define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF 421 /* BB BAR2 size (global) */ 422 #define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00 423 #define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8 424 #define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0 425 #define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1 426 #define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2 427 #define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3 428 #define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4 429 #define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5 430 #define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6 431 #define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7 432 #define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8 433 #define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9 434 #define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA 435 #define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB 436 #define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC 437 #define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD 438 #define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE 439 #define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF 440 /* Set the duration, in seconds, fan failure signal should be 441 sampled */ 442 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000 443 #define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12 444 /* This field defines the board total budget for bar2 when disabled 445 the regular bar size is used. */ 446 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000 447 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16 448 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0 449 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1 450 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2 451 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3 452 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4 453 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5 454 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6 455 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7 456 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8 457 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9 458 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA 459 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB 460 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC 461 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD 462 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE 463 #define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF 464 /* Enable/Disable Crash dump triggers */ 465 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000 466 #define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24 467 u32 mps10_txfir_main; /* 0x5C */ 468 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 469 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 470 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 471 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 472 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 473 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 474 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 475 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 476 u32 mps10_txfir_post; /* 0x60 */ 477 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 478 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 479 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 480 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 481 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 482 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 483 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 484 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 485 u32 mps25_txfir_main; /* 0x64 */ 486 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF 487 #define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0 488 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00 489 #define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8 490 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000 491 #define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16 492 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000 493 #define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24 494 u32 mps25_txfir_post; /* 0x68 */ 495 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF 496 #define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0 497 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00 498 #define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8 499 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000 500 #define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16 501 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000 502 #define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24 503 u32 manufacture_ver; /* 0x6C */ 504 #define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F 505 #define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0 506 #define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0 507 #define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6 508 #define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000 509 #define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12 510 #define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000 511 #define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18 512 #define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000 513 #define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24 514 /* Select package id method */ 515 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_MASK 0x40000000 516 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_OFFSET 30 517 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_NVRAM 0x0 518 #define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_IO_IO_PINS 0x1 519 #define NVM_CFG1_GLOB_RECOVERY_MODE_MASK 0x80000000 520 #define NVM_CFG1_GLOB_RECOVERY_MODE_OFFSET 31 521 #define NVM_CFG1_GLOB_RECOVERY_MODE_DISABLED 0x0 522 #define NVM_CFG1_GLOB_RECOVERY_MODE_ENABLED 0x1 523 u32 manufacture_time; /* 0x70 */ 524 #define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F 525 #define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0 526 #define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0 527 #define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6 528 #define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000 529 #define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12 530 /* Max MSIX for Ethernet in default mode */ 531 #define NVM_CFG1_GLOB_MAX_MSIX_MASK 0x03FC0000 532 #define NVM_CFG1_GLOB_MAX_MSIX_OFFSET 18 533 /* PF Mapping */ 534 #define NVM_CFG1_GLOB_PF_MAPPING_MASK 0x0C000000 535 #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26 536 #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0 537 #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1 538 u32 led_global_settings; /* 0x74 */ 539 #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F 540 #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 541 #define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0 542 #define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4 543 #define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00 544 #define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8 545 #define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000 546 #define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12 547 /* Max. continues operating temperature */ 548 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_MASK 0x00FF0000 549 #define NVM_CFG1_GLOB_MAX_CONT_OPERATING_TEMP_OFFSET 16 550 /* GPIO which triggers run-time port swap according to the map 551 specified in option 205 */ 552 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_MASK 0xFF000000 553 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_OFFSET 24 554 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_NA 0x0 555 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO0 0x1 556 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO1 0x2 557 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO2 0x3 558 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO3 0x4 559 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO4 0x5 560 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO5 0x6 561 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO6 0x7 562 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO7 0x8 563 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO8 0x9 564 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO9 0xA 565 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO10 0xB 566 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO11 0xC 567 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO12 0xD 568 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO13 0xE 569 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO14 0xF 570 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO15 0x10 571 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO16 0x11 572 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO17 0x12 573 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO18 0x13 574 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO19 0x14 575 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO20 0x15 576 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO21 0x16 577 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO22 0x17 578 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO23 0x18 579 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO24 0x19 580 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO25 0x1A 581 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO26 0x1B 582 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO27 0x1C 583 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO28 0x1D 584 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO29 0x1E 585 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO30 0x1F 586 #define NVM_CFG1_GLOB_RUNTIME_PORT_SWAP_GPIO_GPIO31 0x20 587 u32 generic_cont1; /* 0x78 */ 588 #define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF 589 #define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0 590 #define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00 591 #define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10 592 #define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000 593 #define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12 594 #define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000 595 #define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14 596 #define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000 597 #define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16 598 /* Enable option 195 - Overriding the PCIe Preset value */ 599 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_MASK 0x00040000 600 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_OFFSET 18 601 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_DISABLED 0x0 602 #define NVM_CFG1_GLOB_OVERRIDE_PCIE_PRESET_EQUAL_ENABLED 0x1 603 /* PCIe Preset value - applies only if option 194 is enabled */ 604 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_MASK 0x00780000 605 #define NVM_CFG1_GLOB_PCIE_PRESET_VALUE_OFFSET 19 606 /* Port mapping to be used when the run-time GPIO for port-swap is 607 defined and set. */ 608 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_MASK 0x01800000 609 #define NVM_CFG1_GLOB_RUNTIME_PORT0_SWAP_MAP_OFFSET 23 610 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_MASK 0x06000000 611 #define NVM_CFG1_GLOB_RUNTIME_PORT1_SWAP_MAP_OFFSET 25 612 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_MASK 0x18000000 613 #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27 614 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000 615 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29 616 u32 mbi_version; /* 0x7C */ 617 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF 618 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 619 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 620 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 621 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 622 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 623 /* If set to other than NA, 0 - Normal operation, 1 - Thermal event 624 occurred */ 625 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_MASK 0xFF000000 626 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_OFFSET 24 627 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_NA 0x0 628 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO0 0x1 629 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO1 0x2 630 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO2 0x3 631 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO3 0x4 632 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO4 0x5 633 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO5 0x6 634 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO6 0x7 635 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO7 0x8 636 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO8 0x9 637 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO9 0xA 638 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO10 0xB 639 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO11 0xC 640 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO12 0xD 641 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO13 0xE 642 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO14 0xF 643 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO15 0x10 644 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO16 0x11 645 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO17 0x12 646 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO18 0x13 647 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO19 0x14 648 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO20 0x15 649 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO21 0x16 650 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO22 0x17 651 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO23 0x18 652 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO24 0x19 653 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO25 0x1A 654 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO26 0x1B 655 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO27 0x1C 656 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO28 0x1D 657 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO29 0x1E 658 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO30 0x1F 659 #define NVM_CFG1_GLOB_THERMAL_EVENT_GPIO_GPIO31 0x20 660 u32 mbi_date; /* 0x80 */ 661 u32 misc_sig; /* 0x84 */ 662 /* Define the GPIO mapping to switch i2c mux */ 663 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF 664 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0 665 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00 666 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8 667 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0 668 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1 669 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2 670 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3 671 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4 672 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5 673 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6 674 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7 675 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8 676 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9 677 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA 678 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB 679 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC 680 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD 681 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE 682 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF 683 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10 684 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11 685 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12 686 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13 687 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14 688 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15 689 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16 690 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17 691 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18 692 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19 693 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A 694 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B 695 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C 696 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D 697 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E 698 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F 699 #define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20 700 /* Interrupt signal used for SMBus/I2C management interface 701 702 0 = Interrupt event occurred 703 1 = Normal 704 */ 705 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_MASK 0x00FF0000 706 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_OFFSET 16 707 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_NA 0x0 708 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO0 0x1 709 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO1 0x2 710 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO2 0x3 711 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO3 0x4 712 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO4 0x5 713 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO5 0x6 714 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO6 0x7 715 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO7 0x8 716 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO8 0x9 717 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO9 0xA 718 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO10 0xB 719 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO11 0xC 720 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO12 0xD 721 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO13 0xE 722 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO14 0xF 723 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO15 0x10 724 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO16 0x11 725 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO17 0x12 726 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO18 0x13 727 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO19 0x14 728 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO20 0x15 729 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO21 0x16 730 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO22 0x17 731 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO23 0x18 732 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO24 0x19 733 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO25 0x1A 734 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO26 0x1B 735 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO27 0x1C 736 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO28 0x1D 737 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO29 0x1E 738 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO30 0x1F 739 #define NVM_CFG1_GLOB_I2C_INTERRUPT_GPIO_GPIO31 0x20 740 /* Set aLOM FAN on GPIO */ 741 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_MASK 0xFF000000 742 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_OFFSET 24 743 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_NA 0x0 744 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO0 0x1 745 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO1 0x2 746 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO2 0x3 747 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO3 0x4 748 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO4 0x5 749 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO5 0x6 750 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO6 0x7 751 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO7 0x8 752 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO8 0x9 753 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO9 0xA 754 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO10 0xB 755 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO11 0xC 756 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO12 0xD 757 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO13 0xE 758 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO14 0xF 759 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO15 0x10 760 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO16 0x11 761 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO17 0x12 762 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO18 0x13 763 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO19 0x14 764 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO20 0x15 765 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO21 0x16 766 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO22 0x17 767 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO23 0x18 768 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO24 0x19 769 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO25 0x1A 770 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO26 0x1B 771 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO27 0x1C 772 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO28 0x1D 773 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO29 0x1E 774 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO30 0x1F 775 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_GPIO_GPIO31 0x20 776 u32 device_capabilities; /* 0x88 */ 777 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 778 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 779 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 780 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 781 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10 782 u32 power_dissipated; /* 0x8C */ 783 #define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF 784 #define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0 785 #define NVM_CFG1_GLOB_POWER_DIS_D1_MASK 0x0000FF00 786 #define NVM_CFG1_GLOB_POWER_DIS_D1_OFFSET 8 787 #define NVM_CFG1_GLOB_POWER_DIS_D2_MASK 0x00FF0000 788 #define NVM_CFG1_GLOB_POWER_DIS_D2_OFFSET 16 789 #define NVM_CFG1_GLOB_POWER_DIS_D3_MASK 0xFF000000 790 #define NVM_CFG1_GLOB_POWER_DIS_D3_OFFSET 24 791 u32 power_consumed; /* 0x90 */ 792 #define NVM_CFG1_GLOB_POWER_CONS_D0_MASK 0x000000FF 793 #define NVM_CFG1_GLOB_POWER_CONS_D0_OFFSET 0 794 #define NVM_CFG1_GLOB_POWER_CONS_D1_MASK 0x0000FF00 795 #define NVM_CFG1_GLOB_POWER_CONS_D1_OFFSET 8 796 #define NVM_CFG1_GLOB_POWER_CONS_D2_MASK 0x00FF0000 797 #define NVM_CFG1_GLOB_POWER_CONS_D2_OFFSET 16 798 #define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000 799 #define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24 800 u32 efi_version; /* 0x94 */ 801 u32 multi_network_modes_capability; /* 0x98 */ 802 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1 803 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2 804 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4 805 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8 806 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10 807 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20 808 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40 809 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G 0x80 810 #define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X10G 0x100 811 u32 nvm_cfg_version; /* 0x9C */ 812 u32 nvm_cfg_new_option_seq; /* 0xA0 */ 813 u32 nvm_cfg_removed_option_seq; /* 0xA4 */ 814 u32 nvm_cfg_updated_value_seq; /* 0xA8 */ 815 u32 extended_serial_number[8]; /* 0xAC */ 816 u32 oem1_number[8]; /* 0xCC */ 817 u32 oem2_number[8]; /* 0xEC */ 818 u32 mps25_active_txfir_pre; /* 0x10C */ 819 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_MASK 0x000000FF 820 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_PRE_OFFSET 0 821 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_MASK 0x0000FF00 822 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_PRE_OFFSET 8 823 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_MASK 0x00FF0000 824 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_PRE_OFFSET 16 825 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_MASK 0xFF000000 826 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_PRE_OFFSET 24 827 u32 mps25_active_txfir_main; /* 0x110 */ 828 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_MASK 0x000000FF 829 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_MAIN_OFFSET 0 830 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_MASK 0x0000FF00 831 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_MAIN_OFFSET 8 832 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_MASK 0x00FF0000 833 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_MAIN_OFFSET 16 834 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_MASK 0xFF000000 835 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_MAIN_OFFSET 24 836 u32 mps25_active_txfir_post; /* 0x114 */ 837 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_MASK 0x000000FF 838 #define NVM_CFG1_GLOB_LANE0_ACT_TXFIR_POST_OFFSET 0 839 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_MASK 0x0000FF00 840 #define NVM_CFG1_GLOB_LANE1_ACT_TXFIR_POST_OFFSET 8 841 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_MASK 0x00FF0000 842 #define NVM_CFG1_GLOB_LANE2_ACT_TXFIR_POST_OFFSET 16 843 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_MASK 0xFF000000 844 #define NVM_CFG1_GLOB_LANE3_ACT_TXFIR_POST_OFFSET 24 845 u32 features; /* 0x118 */ 846 /* Set the Aux Fan on temperature */ 847 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_MASK 0x000000FF 848 #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_VALUE_OFFSET 0 849 /* Set NC-SI package ID */ 850 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_MASK 0x0000FF00 851 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_OFFSET 8 852 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_NA 0x0 853 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO0 0x1 854 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO1 0x2 855 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO2 0x3 856 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO3 0x4 857 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO4 0x5 858 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO5 0x6 859 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO6 0x7 860 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO7 0x8 861 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO8 0x9 862 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO9 0xA 863 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO10 0xB 864 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO11 0xC 865 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO12 0xD 866 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO13 0xE 867 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO14 0xF 868 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO15 0x10 869 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO16 0x11 870 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO17 0x12 871 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO18 0x13 872 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO19 0x14 873 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO20 0x15 874 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO21 0x16 875 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO22 0x17 876 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO23 0x18 877 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO24 0x19 878 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO25 0x1A 879 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO26 0x1B 880 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO27 0x1C 881 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO28 0x1D 882 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO29 0x1E 883 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO30 0x1F 884 #define NVM_CFG1_GLOB_SLOT_ID_GPIO_GPIO31 0x20 885 /* PMBUS Clock GPIO */ 886 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_MASK 0x00FF0000 887 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_OFFSET 16 888 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_NA 0x0 889 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO0 0x1 890 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO1 0x2 891 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO2 0x3 892 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO3 0x4 893 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO4 0x5 894 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO5 0x6 895 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO6 0x7 896 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO7 0x8 897 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO8 0x9 898 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO9 0xA 899 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO10 0xB 900 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO11 0xC 901 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO12 0xD 902 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO13 0xE 903 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO14 0xF 904 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO15 0x10 905 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO16 0x11 906 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO17 0x12 907 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO18 0x13 908 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO19 0x14 909 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO20 0x15 910 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO21 0x16 911 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO22 0x17 912 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO23 0x18 913 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO24 0x19 914 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO25 0x1A 915 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO26 0x1B 916 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO27 0x1C 917 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO28 0x1D 918 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO29 0x1E 919 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO30 0x1F 920 #define NVM_CFG1_GLOB_PMBUS_SCL_GPIO_GPIO31 0x20 921 /* PMBUS Data GPIO */ 922 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_MASK 0xFF000000 923 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_OFFSET 24 924 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_NA 0x0 925 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO0 0x1 926 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO1 0x2 927 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO2 0x3 928 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO3 0x4 929 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO4 0x5 930 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO5 0x6 931 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO6 0x7 932 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO7 0x8 933 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO8 0x9 934 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO9 0xA 935 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO10 0xB 936 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO11 0xC 937 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO12 0xD 938 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO13 0xE 939 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO14 0xF 940 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO15 0x10 941 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO16 0x11 942 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO17 0x12 943 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO18 0x13 944 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO19 0x14 945 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO20 0x15 946 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO21 0x16 947 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO22 0x17 948 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO23 0x18 949 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO24 0x19 950 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO25 0x1A 951 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO26 0x1B 952 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO27 0x1C 953 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO28 0x1D 954 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO29 0x1E 955 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO30 0x1F 956 #define NVM_CFG1_GLOB_PMBUS_SDA_GPIO_GPIO31 0x20 957 u32 tx_rx_eq_25g_hlpc; /* 0x11C */ 958 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_MASK 0x000000FF 959 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_HLPC_OFFSET 0 960 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_MASK 0x0000FF00 961 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_HLPC_OFFSET 8 962 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_MASK 0x00FF0000 963 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_HLPC_OFFSET 16 964 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_MASK 0xFF000000 965 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_HLPC_OFFSET 24 966 u32 tx_rx_eq_25g_llpc; /* 0x120 */ 967 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_MASK 0x000000FF 968 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_LLPC_OFFSET 0 969 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_MASK 0x0000FF00 970 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_LLPC_OFFSET 8 971 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_MASK 0x00FF0000 972 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_LLPC_OFFSET 16 973 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_MASK 0xFF000000 974 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_LLPC_OFFSET 24 975 u32 tx_rx_eq_25g_ac; /* 0x124 */ 976 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_MASK 0x000000FF 977 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_AC_OFFSET 0 978 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_MASK 0x0000FF00 979 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_AC_OFFSET 8 980 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_MASK 0x00FF0000 981 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_AC_OFFSET 16 982 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_MASK 0xFF000000 983 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_AC_OFFSET 24 984 u32 tx_rx_eq_10g_pc; /* 0x128 */ 985 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_MASK 0x000000FF 986 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_PC_OFFSET 0 987 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_MASK 0x0000FF00 988 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_PC_OFFSET 8 989 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_MASK 0x00FF0000 990 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_PC_OFFSET 16 991 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_MASK 0xFF000000 992 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_PC_OFFSET 24 993 u32 tx_rx_eq_10g_ac; /* 0x12C */ 994 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_MASK 0x000000FF 995 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_AC_OFFSET 0 996 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_MASK 0x0000FF00 997 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_AC_OFFSET 8 998 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_MASK 0x00FF0000 999 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_AC_OFFSET 16 1000 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_MASK 0xFF000000 1001 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_AC_OFFSET 24 1002 u32 tx_rx_eq_1g; /* 0x130 */ 1003 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_MASK 0x000000FF 1004 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_1G_OFFSET 0 1005 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_MASK 0x0000FF00 1006 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_1G_OFFSET 8 1007 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_MASK 0x00FF0000 1008 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_1G_OFFSET 16 1009 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_MASK 0xFF000000 1010 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_1G_OFFSET 24 1011 u32 tx_rx_eq_25g_bt; /* 0x134 */ 1012 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_MASK 0x000000FF 1013 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_25G_BT_OFFSET 0 1014 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_MASK 0x0000FF00 1015 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_25G_BT_OFFSET 8 1016 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_MASK 0x00FF0000 1017 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_25G_BT_OFFSET 16 1018 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_MASK 0xFF000000 1019 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_25G_BT_OFFSET 24 1020 u32 tx_rx_eq_10g_bt; /* 0x138 */ 1021 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_MASK 0x000000FF 1022 #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_10G_BT_OFFSET 0 1023 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_MASK 0x0000FF00 1024 #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_10G_BT_OFFSET 8 1025 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_MASK 0x00FF0000 1026 #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_10G_BT_OFFSET 16 1027 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_MASK 0xFF000000 1028 #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_10G_BT_OFFSET 24 1029 u32 generic_cont4; /* 0x13C */ 1030 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_MASK 0x000000FF 1031 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_OFFSET 0 1032 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_NA 0x0 1033 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO0 0x1 1034 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO1 0x2 1035 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO2 0x3 1036 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO3 0x4 1037 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO4 0x5 1038 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO5 0x6 1039 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO6 0x7 1040 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO7 0x8 1041 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO8 0x9 1042 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO9 0xA 1043 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO10 0xB 1044 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO11 0xC 1045 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO12 0xD 1046 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO13 0xE 1047 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO14 0xF 1048 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO15 0x10 1049 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO16 0x11 1050 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO17 0x12 1051 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO18 0x13 1052 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO19 0x14 1053 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO20 0x15 1054 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO21 0x16 1055 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO22 0x17 1056 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO23 0x18 1057 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO24 0x19 1058 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO25 0x1A 1059 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO26 0x1B 1060 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO27 0x1C 1061 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO28 0x1D 1062 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E 1063 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F 1064 #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20 1065 u32 preboot_debug_mode_std; /* 0x140 */ 1066 u32 preboot_debug_mode_ext; /* 0x144 */ 1067 u32 reserved[56]; /* 0x148 */ 1068 }; 1069 1070 struct nvm_cfg1_path 1071 { 1072 u32 reserved[1]; /* 0x0 */ 1073 }; 1074 1075 struct nvm_cfg1_port 1076 { 1077 u32 reserved__m_relocated_to_option_123; /* 0x0 */ 1078 u32 reserved__m_relocated_to_option_124; /* 0x4 */ 1079 u32 generic_cont0; /* 0x8 */ 1080 #define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF 1081 #define NVM_CFG1_PORT_LED_MODE_OFFSET 0 1082 #define NVM_CFG1_PORT_LED_MODE_MAC1 0x0 1083 #define NVM_CFG1_PORT_LED_MODE_PHY1 0x1 1084 #define NVM_CFG1_PORT_LED_MODE_PHY2 0x2 1085 #define NVM_CFG1_PORT_LED_MODE_PHY3 0x3 1086 #define NVM_CFG1_PORT_LED_MODE_MAC2 0x4 1087 #define NVM_CFG1_PORT_LED_MODE_PHY4 0x5 1088 #define NVM_CFG1_PORT_LED_MODE_PHY5 0x6 1089 #define NVM_CFG1_PORT_LED_MODE_PHY6 0x7 1090 #define NVM_CFG1_PORT_LED_MODE_MAC3 0x8 1091 #define NVM_CFG1_PORT_LED_MODE_PHY7 0x9 1092 #define NVM_CFG1_PORT_LED_MODE_PHY8 0xA 1093 #define NVM_CFG1_PORT_LED_MODE_PHY9 0xB 1094 #define NVM_CFG1_PORT_LED_MODE_MAC4 0xC 1095 #define NVM_CFG1_PORT_LED_MODE_PHY10 0xD 1096 #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE 1097 #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF 1098 #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10 1099 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00 1100 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8 1101 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 1102 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 1103 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 1104 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 1105 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 1106 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 1107 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 1108 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 1109 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 1110 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 1111 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 1112 /* GPIO for HW reset the PHY. In case it is the same for all ports, 1113 need to set same value for all ports */ 1114 #define NVM_CFG1_PORT_EXT_PHY_RESET_MASK 0xFF000000 1115 #define NVM_CFG1_PORT_EXT_PHY_RESET_OFFSET 24 1116 #define NVM_CFG1_PORT_EXT_PHY_RESET_NA 0x0 1117 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO0 0x1 1118 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO1 0x2 1119 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO2 0x3 1120 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO3 0x4 1121 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO4 0x5 1122 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO5 0x6 1123 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO6 0x7 1124 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO7 0x8 1125 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO8 0x9 1126 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO9 0xA 1127 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO10 0xB 1128 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO11 0xC 1129 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO12 0xD 1130 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO13 0xE 1131 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO14 0xF 1132 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO15 0x10 1133 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO16 0x11 1134 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO17 0x12 1135 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO18 0x13 1136 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO19 0x14 1137 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO20 0x15 1138 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO21 0x16 1139 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO22 0x17 1140 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO23 0x18 1141 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO24 0x19 1142 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO25 0x1A 1143 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO26 0x1B 1144 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO27 0x1C 1145 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO28 0x1D 1146 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO29 0x1E 1147 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO30 0x1F 1148 #define NVM_CFG1_PORT_EXT_PHY_RESET_GPIO31 0x20 1149 u32 pcie_cfg; /* 0xC */ 1150 #define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007 1151 #define NVM_CFG1_PORT_RESERVED15_OFFSET 0 1152 u32 features; /* 0x10 */ 1153 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001 1154 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0 1155 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0 1156 #define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1 1157 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002 1158 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1 1159 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0 1160 #define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1 1161 u32 speed_cap_mask; /* 0x14 */ 1162 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1163 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1164 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1165 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1166 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1167 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1168 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1169 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1170 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1171 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1172 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1173 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1174 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1175 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1176 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1177 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1178 u32 link_settings; /* 0x18 */ 1179 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F 1180 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 1181 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 1182 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 1183 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 1184 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 1185 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 1186 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 1187 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 1188 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 1189 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 1190 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 1191 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 1192 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 1193 #define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780 1194 #define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7 1195 #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 1196 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 1197 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 1198 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 1199 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 1200 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 1201 #define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7 1202 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800 1203 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11 1204 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1 1205 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2 1206 #define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4 1207 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000 1208 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14 1209 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0 1210 #define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1 1211 #define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000 1212 #define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15 1213 #define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0 1214 #define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1 1215 #define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000 1216 #define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17 1217 #define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0 1218 #define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1 1219 #define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2 1220 #define NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO 0x7 1221 #define NVM_CFG1_PORT_FEC_AN_MODE_MASK 0x00700000 1222 #define NVM_CFG1_PORT_FEC_AN_MODE_OFFSET 20 1223 #define NVM_CFG1_PORT_FEC_AN_MODE_NONE 0x0 1224 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_FIRECODE 0x1 1225 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE 0x2 1226 #define NVM_CFG1_PORT_FEC_AN_MODE_10G_AND_25G_FIRECODE 0x3 1227 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_RS 0x4 1228 #define NVM_CFG1_PORT_FEC_AN_MODE_25G_FIRECODE_AND_RS 0x5 1229 #define NVM_CFG1_PORT_FEC_AN_MODE_ALL 0x6 1230 #define NVM_CFG1_PORT_SMARTLINQ_MODE_MASK 0x00800000 1231 #define NVM_CFG1_PORT_SMARTLINQ_MODE_OFFSET 23 1232 #define NVM_CFG1_PORT_SMARTLINQ_MODE_DISABLED 0x0 1233 #define NVM_CFG1_PORT_SMARTLINQ_MODE_ENABLED 0x1 1234 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_MASK 0x01000000 1235 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24 1236 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0 1237 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1 1238 u32 phy_cfg; /* 0x1C */ 1239 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF 1240 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 1241 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1 1242 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2 1243 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4 1244 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8 1245 #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10 1246 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000 1247 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16 1248 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0 1249 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2 1250 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3 1251 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4 1252 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8 1253 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9 1254 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB 1255 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC 1256 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11 1257 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12 1258 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21 1259 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22 1260 #define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31 1261 #define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000 1262 #define NVM_CFG1_PORT_AN_MODE_OFFSET 24 1263 #define NVM_CFG1_PORT_AN_MODE_NONE 0x0 1264 #define NVM_CFG1_PORT_AN_MODE_CL73 0x1 1265 #define NVM_CFG1_PORT_AN_MODE_CL37 0x2 1266 #define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3 1267 #define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4 1268 #define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5 1269 #define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6 1270 u32 mgmt_traffic; /* 0x20 */ 1271 #define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F 1272 #define NVM_CFG1_PORT_RESERVED61_OFFSET 0 1273 u32 ext_phy; /* 0x24 */ 1274 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF 1275 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0 1276 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 1277 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1 1278 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 1279 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 1280 /* EEE power saving mode */ 1281 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000 1282 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 1283 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 1284 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 1285 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 1286 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 1287 u32 mba_cfg1; /* 0x28 */ 1288 #define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001 1289 #define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0 1290 #define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0 1291 #define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1 1292 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006 1293 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1 1294 #define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078 1295 #define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3 1296 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080 1297 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7 1298 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0 1299 #define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1 1300 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100 1301 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8 1302 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0 1303 #define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1 1304 #define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00 1305 #define NVM_CFG1_PORT_RESERVED5_OFFSET 9 1306 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000 1307 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17 1308 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 1309 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 1310 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 1311 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 1312 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 1313 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 1314 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7 1315 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000 1316 #define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21 1317 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_MASK 0x01000000 1318 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_OFFSET 24 1319 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_DISABLED 0x0 1320 #define NVM_CFG1_PORT_RESERVED_WAS_PREBOOT_SMARTLINQ_ENABLED 0x1 1321 u32 mba_cfg2; /* 0x2C */ 1322 #define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF 1323 #define NVM_CFG1_PORT_RESERVED65_OFFSET 0 1324 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 1325 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16 1326 u32 vf_cfg; /* 0x30 */ 1327 #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF 1328 #define NVM_CFG1_PORT_RESERVED8_OFFSET 0 1329 #define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000 1330 #define NVM_CFG1_PORT_RESERVED6_OFFSET 16 1331 struct nvm_cfg_mac_address lldp_mac_address; /* 0x34 */ 1332 u32 led_port_settings; /* 0x3C */ 1333 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF 1334 #define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0 1335 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00 1336 #define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8 1337 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000 1338 #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 1339 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 1340 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 1341 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4 1342 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8 1343 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8 1344 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10 1345 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10 1346 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20 1347 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40 1348 u32 transceiver_00; /* 0x40 */ 1349 /* Define for mapping of transceiver signal module absent */ 1350 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF 1351 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0 1352 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0 1353 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1 1354 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2 1355 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3 1356 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4 1357 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5 1358 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6 1359 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7 1360 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8 1361 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9 1362 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA 1363 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB 1364 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC 1365 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD 1366 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE 1367 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF 1368 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10 1369 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11 1370 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12 1371 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13 1372 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14 1373 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15 1374 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16 1375 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17 1376 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18 1377 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19 1378 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A 1379 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B 1380 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C 1381 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D 1382 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E 1383 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F 1384 #define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20 1385 /* Define the GPIO mux settings to switch i2c mux to this port */ 1386 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00 1387 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 1388 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 1389 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 1390 u32 device_ids; /* 0x44 */ 1391 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF 1392 #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 1393 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00 1394 #define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8 1395 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000 1396 #define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16 1397 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000 1398 #define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24 1399 u32 board_cfg; /* 0x48 */ 1400 /* This field defines the board technology 1401 (backpane,transceiver,external PHY) */ 1402 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF 1403 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 1404 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 1405 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 1406 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 1407 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 1408 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 1409 /* This field defines the GPIO mapped to tx_disable signal in SFP */ 1410 #define NVM_CFG1_PORT_TX_DISABLE_MASK 0x0000FF00 1411 #define NVM_CFG1_PORT_TX_DISABLE_OFFSET 8 1412 #define NVM_CFG1_PORT_TX_DISABLE_NA 0x0 1413 #define NVM_CFG1_PORT_TX_DISABLE_GPIO0 0x1 1414 #define NVM_CFG1_PORT_TX_DISABLE_GPIO1 0x2 1415 #define NVM_CFG1_PORT_TX_DISABLE_GPIO2 0x3 1416 #define NVM_CFG1_PORT_TX_DISABLE_GPIO3 0x4 1417 #define NVM_CFG1_PORT_TX_DISABLE_GPIO4 0x5 1418 #define NVM_CFG1_PORT_TX_DISABLE_GPIO5 0x6 1419 #define NVM_CFG1_PORT_TX_DISABLE_GPIO6 0x7 1420 #define NVM_CFG1_PORT_TX_DISABLE_GPIO7 0x8 1421 #define NVM_CFG1_PORT_TX_DISABLE_GPIO8 0x9 1422 #define NVM_CFG1_PORT_TX_DISABLE_GPIO9 0xA 1423 #define NVM_CFG1_PORT_TX_DISABLE_GPIO10 0xB 1424 #define NVM_CFG1_PORT_TX_DISABLE_GPIO11 0xC 1425 #define NVM_CFG1_PORT_TX_DISABLE_GPIO12 0xD 1426 #define NVM_CFG1_PORT_TX_DISABLE_GPIO13 0xE 1427 #define NVM_CFG1_PORT_TX_DISABLE_GPIO14 0xF 1428 #define NVM_CFG1_PORT_TX_DISABLE_GPIO15 0x10 1429 #define NVM_CFG1_PORT_TX_DISABLE_GPIO16 0x11 1430 #define NVM_CFG1_PORT_TX_DISABLE_GPIO17 0x12 1431 #define NVM_CFG1_PORT_TX_DISABLE_GPIO18 0x13 1432 #define NVM_CFG1_PORT_TX_DISABLE_GPIO19 0x14 1433 #define NVM_CFG1_PORT_TX_DISABLE_GPIO20 0x15 1434 #define NVM_CFG1_PORT_TX_DISABLE_GPIO21 0x16 1435 #define NVM_CFG1_PORT_TX_DISABLE_GPIO22 0x17 1436 #define NVM_CFG1_PORT_TX_DISABLE_GPIO23 0x18 1437 #define NVM_CFG1_PORT_TX_DISABLE_GPIO24 0x19 1438 #define NVM_CFG1_PORT_TX_DISABLE_GPIO25 0x1A 1439 #define NVM_CFG1_PORT_TX_DISABLE_GPIO26 0x1B 1440 #define NVM_CFG1_PORT_TX_DISABLE_GPIO27 0x1C 1441 #define NVM_CFG1_PORT_TX_DISABLE_GPIO28 0x1D 1442 #define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E 1443 #define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F 1444 #define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20 1445 u32 mnm_10g_cap; /* 0x4C */ 1446 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1447 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1448 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1449 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1450 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1451 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1452 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1453 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1454 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1455 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1456 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1457 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1458 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1459 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1460 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1461 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1462 u32 mnm_10g_ctrl; /* 0x50 */ 1463 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F 1464 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0 1465 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0 1466 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1 1467 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2 1468 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4 1469 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5 1470 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6 1471 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7 1472 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0 1473 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4 1474 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0 1475 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1 1476 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2 1477 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4 1478 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5 1479 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6 1480 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7 1481 /* This field defines the board technology 1482 (backpane,transceiver,external PHY) */ 1483 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00 1484 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8 1485 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0 1486 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1 1487 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2 1488 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3 1489 #define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4 1490 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1491 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16 1492 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0 1493 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2 1494 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3 1495 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4 1496 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8 1497 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9 1498 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB 1499 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC 1500 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11 1501 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12 1502 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21 1503 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22 1504 #define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31 1505 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000 1506 #define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24 1507 u32 mnm_10g_misc; /* 0x54 */ 1508 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007 1509 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0 1510 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0 1511 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1 1512 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2 1513 #define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_AUTO 0x7 1514 u32 mnm_25g_cap; /* 0x58 */ 1515 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1516 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1517 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1518 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1519 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1520 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1521 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1522 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1523 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1524 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1525 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1526 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1527 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1528 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1529 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1530 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1531 u32 mnm_25g_ctrl; /* 0x5C */ 1532 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F 1533 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0 1534 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0 1535 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1 1536 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2 1537 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4 1538 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5 1539 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6 1540 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7 1541 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0 1542 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4 1543 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0 1544 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1 1545 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2 1546 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4 1547 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5 1548 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6 1549 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7 1550 /* This field defines the board technology 1551 (backpane,transceiver,external PHY) */ 1552 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00 1553 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8 1554 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0 1555 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1 1556 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2 1557 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3 1558 #define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4 1559 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1560 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16 1561 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0 1562 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2 1563 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3 1564 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4 1565 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8 1566 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9 1567 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB 1568 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC 1569 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11 1570 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12 1571 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21 1572 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22 1573 #define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31 1574 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000 1575 #define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24 1576 u32 mnm_25g_misc; /* 0x60 */ 1577 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007 1578 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0 1579 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0 1580 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1 1581 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2 1582 #define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_AUTO 0x7 1583 u32 mnm_40g_cap; /* 0x64 */ 1584 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1585 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1586 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1587 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1588 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1589 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1590 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1591 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1592 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1593 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1594 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1595 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1596 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1597 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1598 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1599 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1600 u32 mnm_40g_ctrl; /* 0x68 */ 1601 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F 1602 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0 1603 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0 1604 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1 1605 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2 1606 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4 1607 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5 1608 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6 1609 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7 1610 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0 1611 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4 1612 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0 1613 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1 1614 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2 1615 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4 1616 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5 1617 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6 1618 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7 1619 /* This field defines the board technology 1620 (backpane,transceiver,external PHY) */ 1621 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00 1622 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8 1623 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0 1624 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1 1625 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2 1626 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3 1627 #define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4 1628 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1629 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16 1630 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0 1631 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2 1632 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3 1633 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4 1634 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8 1635 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9 1636 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB 1637 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC 1638 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11 1639 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12 1640 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21 1641 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22 1642 #define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31 1643 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000 1644 #define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24 1645 u32 mnm_40g_misc; /* 0x6C */ 1646 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007 1647 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0 1648 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0 1649 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1 1650 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2 1651 #define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_AUTO 0x7 1652 u32 mnm_50g_cap; /* 0x70 */ 1653 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 1654 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 1655 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 1656 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 1657 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 1658 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 1659 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 1660 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 1661 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000 1662 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 1663 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 1664 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 1665 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 1666 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 1667 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 1668 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40 1669 u32 mnm_50g_ctrl; /* 0x74 */ 1670 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F 1671 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0 1672 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0 1673 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1 1674 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2 1675 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4 1676 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5 1677 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6 1678 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7 1679 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0 1680 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4 1681 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0 1682 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1 1683 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2 1684 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4 1685 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5 1686 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6 1687 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7 1688 /* This field defines the board technology 1689 (backpane,transceiver,external PHY) */ 1690 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00 1691 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8 1692 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0 1693 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1 1694 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2 1695 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3 1696 #define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4 1697 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1698 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16 1699 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0 1700 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2 1701 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3 1702 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4 1703 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8 1704 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9 1705 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB 1706 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC 1707 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11 1708 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12 1709 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21 1710 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22 1711 #define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31 1712 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000 1713 #define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24 1714 u32 mnm_50g_misc; /* 0x78 */ 1715 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007 1716 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0 1717 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0 1718 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1 1719 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2 1720 #define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_AUTO 0x7 1721 u32 mnm_100g_cap; /* 0x7C */ 1722 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK 0x0000FFFF 1723 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0 1724 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1 1725 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2 1726 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8 1727 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10 1728 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20 1729 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40 1730 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK 0xFFFF0000 1731 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16 1732 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1 1733 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2 1734 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8 1735 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10 1736 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20 1737 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40 1738 u32 mnm_100g_ctrl; /* 0x80 */ 1739 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F 1740 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0 1741 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0 1742 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1 1743 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2 1744 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4 1745 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5 1746 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6 1747 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7 1748 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0 1749 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4 1750 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0 1751 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1 1752 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2 1753 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4 1754 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5 1755 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6 1756 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7 1757 /* This field defines the board technology 1758 (backpane,transceiver,external PHY) */ 1759 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00 1760 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8 1761 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0 1762 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1 1763 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2 1764 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3 1765 #define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4 1766 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK 0x00FF0000 1767 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16 1768 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0 1769 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2 1770 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3 1771 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4 1772 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8 1773 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9 1774 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB 1775 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC 1776 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11 1777 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12 1778 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21 1779 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22 1780 #define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31 1781 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000 1782 #define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24 1783 u32 mnm_100g_misc; /* 0x84 */ 1784 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007 1785 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0 1786 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0 1787 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1 1788 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2 1789 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7 1790 u32 temperature; /* 0x88 */ 1791 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF 1792 #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0 1793 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK 0x0000FF00 1794 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8 1795 u32 reserved[115]; /* 0x8C */ 1796 }; 1797 1798 struct nvm_cfg1_func 1799 { 1800 struct nvm_cfg_mac_address mac_address; /* 0x0 */ 1801 u32 rsrv1; /* 0x8 */ 1802 #define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF 1803 #define NVM_CFG1_FUNC_RESERVED1_OFFSET 0 1804 #define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000 1805 #define NVM_CFG1_FUNC_RESERVED2_OFFSET 16 1806 u32 rsrv2; /* 0xC */ 1807 #define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF 1808 #define NVM_CFG1_FUNC_RESERVED3_OFFSET 0 1809 #define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000 1810 #define NVM_CFG1_FUNC_RESERVED4_OFFSET 16 1811 u32 device_id; /* 0x10 */ 1812 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF 1813 #define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0 1814 #define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000 1815 #define NVM_CFG1_FUNC_RESERVED77_OFFSET 16 1816 u32 cmn_cfg; /* 0x14 */ 1817 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007 1818 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0 1819 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0 1820 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3 1821 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4 1822 #define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7 1823 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8 1824 #define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3 1825 #define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000 1826 #define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19 1827 #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 1828 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1 1829 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2 1830 #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3 1831 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 1832 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 1833 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 1834 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31 1835 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0 1836 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1 1837 u32 pci_cfg; /* 0x18 */ 1838 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F 1839 #define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0 1840 /* AH VF BAR2 size */ 1841 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80 1842 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7 1843 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0 1844 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1 1845 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2 1846 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3 1847 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4 1848 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5 1849 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6 1850 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7 1851 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8 1852 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9 1853 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA 1854 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB 1855 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC 1856 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD 1857 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE 1858 #define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF 1859 #define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000 1860 #define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14 1861 #define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0 1862 #define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1 1863 #define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2 1864 #define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3 1865 #define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4 1866 #define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5 1867 #define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6 1868 #define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7 1869 #define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8 1870 #define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9 1871 #define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA 1872 #define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB 1873 #define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC 1874 #define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD 1875 #define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE 1876 #define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF 1877 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000 1878 #define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18 1879 /* Hide function in npar mode */ 1880 #define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000 1881 #define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26 1882 #define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0 1883 #define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1 1884 /* AH BAR2 size (per function) */ 1885 #define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000 1886 #define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27 1887 #define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0 1888 #define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5 1889 #define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6 1890 #define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7 1891 #define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8 1892 #define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9 1893 #define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA 1894 #define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB 1895 #define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC 1896 #define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD 1897 #define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE 1898 #define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF 1899 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */ 1900 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */ 1901 u32 preboot_generic_cfg; /* 0x2C */ 1902 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF 1903 #define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0 1904 #define NVM_CFG1_FUNC_PREBOOT_VLAN_MASK 0x00010000 1905 #define NVM_CFG1_FUNC_PREBOOT_VLAN_OFFSET 16 1906 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_MASK 0x001E0000 1907 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_OFFSET 17 1908 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1 1909 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2 1910 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4 1911 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8 1912 u32 features; /* 0x30 */ 1913 /* RDMA protocol enablement */ 1914 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_MASK 0x00000003 1915 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_OFFSET 0 1916 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_NONE 0x0 1917 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_ROCE 0x1 1918 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_IWARP 0x2 1919 #define NVM_CFG1_FUNC_RDMA_ENABLEMENT_BOTH 0x3 1920 u32 reserved[7]; /* 0x34 */ 1921 }; 1922 1923 struct nvm_cfg1 1924 { 1925 struct nvm_cfg1_glob glob; /* 0x0 */ 1926 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; /* 0x228 */ 1927 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; /* 0x230 */ 1928 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; /* 0xB90 */ 1929 }; 1930 1931 /****************************************** 1932 * nvm_cfg structs 1933 ******************************************/ 1934 enum nvm_cfg_sections 1935 { 1936 NVM_CFG_SECTION_NVM_CFG1, 1937 NVM_CFG_SECTION_MAX 1938 }; 1939 1940 struct nvm_cfg 1941 { 1942 u32 num_sections; 1943 u32 sections_offset[NVM_CFG_SECTION_MAX]; 1944 struct nvm_cfg1 cfg1; 1945 }; 1946 1947 #endif /* NVM_CFG_H */ 1948