1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 /**************************************************************************** 32 * 33 * Name: mcp_private.h 34 * 35 * Description: MCP private data. Located in HSI only to provide debug access 36 * for diag. 37 * 38 ****************************************************************************/ 39 40 #ifndef MCP_PRIVATE_H 41 #define MCP_PRIVATE_H 42 43 #if (!defined MFW_SIM) && (!defined RECOVERY) 44 #include "eth.h" 45 #include "pmm.h" 46 #include "ah_eth.h" 47 #include "e5_eth.h" 48 #endif 49 #include "global.h" 50 #include "mcp_public.h" 51 52 typedef enum active_mf_mode { 53 MF_MODE_SF = 0, 54 MF_MODE_MF_ALLOWED, 55 MF_MODE_MF_SWITCH_INDEPENDENT, 56 MF_MODE_NIV 57 } active_mf_mode_t; 58 59 enum ov_current_cfg { 60 CURR_CFG_NONE = 0, 61 CURR_CFG_OS, 62 CURR_CFG_VENDOR_SPEC, 63 CURR_CFG_OTHER, 64 CURR_CFG_VC_CLP, 65 CURR_CFG_CNU, 66 CURR_CFG_DCI, 67 CURR_CFG_HII, 68 }; 69 70 struct dci_info_global { 71 u16 mba_ver; 72 u8 current_cfg; 73 u8 extern_dci_mgmt; 74 u8 pci_bus_num; 75 u8 boot_progress; 76 }; 77 78 /* Resource allocation information of one resource */ 79 struct resource_info_private { 80 u16 size; /* number of allocated resources */ 81 u16 offset; /* Offset of the 1st resource */ 82 u8 flags; 83 }; 84 85 /* Cache for resource allocation of one PF */ 86 struct res_alloc_cache { 87 u8 pf_num; 88 struct resource_info_private res[RESOURCE_MAX_NUM]; 89 }; 90 91 struct pf_sb_t { 92 u8 sb_for_pf_size; 93 u8 sb_for_pf_offset; 94 u8 sb_for_vf_size; 95 u8 sb_for_vf_offset; 96 }; 97 98 /**************************************/ 99 /* */ 100 /* P R I V A T E G L O B A L */ 101 /* */ 102 /**************************************/ 103 struct private_global { 104 active_mf_mode_t mf_mode; /* TBD - require initialization */ 105 u32 exp_rom_nvm_addr; 106 107 /* The pmm_config structure holds all active phy/link configuration */ 108 #if (!defined MFW_SIM) && (!defined RECOVERY) 109 #ifdef b900 110 struct pmm_config eth_cfg; 111 #elif b940 112 struct ah_eth eth_cfg; 113 #elif b510 114 struct e5_eth eth_cfg; 115 #else 116 #endif 117 #endif 118 u32 lldp_counter; 119 120 u32 avs_init_timestamp; 121 122 u32 seconds_since_mcp_reset; 123 124 u32 last_malloc_dir_used_timestamp; 125 #define MAX_USED_DIR_ALLOWED_TIME (3) /* Seconds */ 126 127 u32 drv_nvm_state; 128 /* Per PF bitmask */ 129 #define DRV_NVM_STATE_IN_PROGRESS_MASK (0x0001ffff) 130 #define DRV_NVM_STATE_IN_PROGRESS_OFFSET (0) 131 #define DRV_NVM_STATE_IN_PROGRESS_VAL_MFW (0x00010000) 132 133 u32 storm_fw_ver; 134 135 /* OneView data*/ 136 struct dci_info_global dci_global; 137 138 /* Resource allocation cached data */ 139 struct res_alloc_cache res_alloc; 140 #define G_RES_ALLOC_P (&g_spad.private_data.global.res_alloc) 141 u32 resource_max_values[RESOURCE_MAX_NUM]; 142 u32 glb_counter_100ms; 143 /*collection of global bits and controls*/ 144 u32 flags_and_ctrl; 145 #define PRV_GLOBAL_FIO_BMB_INITIATED_MASK 0x00000001 146 #define PRV_GLOBAL_FIO_BMB_INITIATED_OFFSET 0 147 #define PRV_GLOBAL_ENABLE_NET_THREAD_LONG_RUN_MASK 0x00000002 148 #define PRV_GLOBAL_ENABLE_NET_THREAD_LONG_RUN_OFFSET 1 149 150 #ifdef b900 151 u32 es_fir_engines : 8, es_fir_valid_bitmap : 8, es_l2_engines : 8, es_l2_valid_bitmap : 8; 152 #endif 153 u64 ecc_events; 154 }; 155 156 /**************************************/ 157 /* */ 158 /* P R I V A T E P A T H */ 159 /* */ 160 /**************************************/ 161 struct private_path { 162 u32 recovery_countdown; /* Counting down 2 seconds, using TMR3 */ 163 #define RECOVERY_MAX_COUNTDOWN_SECONDS 2 164 165 u32 drv_load_vars; /* When the seconds_since_mcp_reset gets here */ 166 #define DRV_LOAD_DEF_TIMEOUT 10 167 #define DRV_LOAD_TIMEOUT_MASK 0x0000ffff 168 #define DRV_LOAD_TIMEOUT_OFFSET 0 169 #define DRV_LOAD_NEED_FORCE_MASK 0xffff0000 170 #define DRV_LOAD_NEED_FORCE_OFFSET 16 171 struct load_rsp_stc drv_load_params; 172 u64 ecc_events; 173 }; 174 175 176 /**************************************/ 177 /* */ 178 /* P R I V A T E P O R T */ 179 /* */ 180 /**************************************/ 181 struct drv_port_info_t { 182 u32_t port_state; 183 #define DRV_STATE_LINK_LOCK_FLAG 0x00000001 184 #define DRV_WAIT_DBG_PRN 0x00000002 185 186 /* There are maximum 8 PFs per port */ 187 #define DRV_STATE_LOADED_MASK 0x0000ff00 188 #define DRV_STATE_LOADED_OFFSET 8 189 190 #define DRV_STATE_PF_TRANSITION_MASK 0x00ff0000 191 #define DRV_STATE_PF_TRANSITION_OFFSET 16 192 193 #define DRV_STATE_PF_PHY_INIT_MASK 0xff000000 194 #define DRV_STATE_PF_PHY_INIT_OFFSET 24 195 }; 196 197 typedef enum _lldp_subscriber_e { 198 LLDP_SUBSCRIBER_MANDATORY = 0, 199 LLDP_SUBSCRIBER_SYSTEM, 200 LLDP_SUBSCRIBER_DCBX_IEEE, 201 LLDP_SUBSCRIBER_DCBX_CEE, 202 LLDP_SUBSCRIBER_EEE, 203 LLDP_SUBSCRIBER_CDCP, 204 LLDP_SUBSCRIBER_DCI, 205 LLDP_SUBSCRIBER_UFP, 206 LLDP_SUBSCRIBER_NCSI, 207 MAX_SUBSCRIBERS 208 } lldp_subscriber_e; 209 210 typedef struct { 211 u16 valid; 212 u16 type_len; 213 #define LLDP_LEN_MASK (0x01ff) 214 #define LLDP_LEN_OFFSET (0) 215 #define LLDP_TYPE_MASK (0xfe00) 216 #define LLDP_TYPE_OFFSET (9) 217 u8 *value_p; 218 } tlv_s; 219 220 typedef u16(*lldp_prepare_tlv_func)(u8 port, lldp_agent_e lldp_agent, u8 *buffer); 221 222 typedef struct { 223 u16 valid; 224 lldp_prepare_tlv_func func; 225 } subscriber_callback_send_s; 226 227 typedef u8(*lldp_process_func)(u8 port, u8 num, u8 **tlvs); 228 229 #define MAX_NUM_SUBTYPES 4 230 typedef struct { 231 u8 valid; 232 u8 oui[3]; 233 u8 subtype_list[MAX_NUM_SUBTYPES]; 234 u8 num_subtypes; 235 lldp_process_func func; 236 } subscriber_callback_receive_s; 237 238 #define MAX_ETH_HEADER 14 /* TODO: to be extended per requirements */ 239 #define MAX_PACKET_SIZE (1516) /* So it can be devided by 4 */ 240 #define LLDP_CHASSIS_ID_TLV_LEN 7 241 #define LLDP_PORT_ID_TLV_LEN 7 242 typedef struct { 243 u16 len; 244 u8 header[MAX_ETH_HEADER]; 245 } lldp_eth_header_s; 246 247 typedef struct { 248 struct lldp_config_params_s lldp_config_params; 249 u16 lldp_ttl; 250 u8 lldp_cur_credit; 251 subscriber_callback_send_s subscriber_callback_send[MAX_SUBSCRIBERS]; 252 lldp_eth_header_s lldp_eth_header; 253 u32 lldp_time_to_send; 254 u32 lldp_ttl_expired; 255 u32 lldp_sent; 256 u8 first_lldp; 257 subscriber_callback_receive_s subscriber_callback_receive[MAX_SUBSCRIBERS]; 258 } lldp_params_s; 259 260 #define MAX_TLVS 20 261 typedef struct { 262 u8 current_received_tlv_index; 263 u8 *received_tlvs[MAX_TLVS]; 264 } lldp_receive_data_s; 265 266 #define MAX_REGISTERED_TLVS 12 267 268 typedef struct { 269 u32 config; /* Uses same defines as local config plus some more below*/ 270 #define DCBX_MODE_MASK 0x00000010 271 #define DCBX_MODE_OFFSET 4 272 #define DCBX_MODE_DRIVER 0 273 #define DCBX_MODE_DEFAULT 1 274 #define DCBX_CHANGED_MASK 0x00000f00 275 #define DCBX_CHANGED_OFFSET 8 276 #define DCBX_CONTROL_CHANGED_MASK 0x00000100 277 #define DCBX_CONTROL_CHANGED_OFFSET 8 278 #define DCBX_PFC_CHANGED_MASK 0x00000200 279 #define DCBX_PFC_CHANGED_OFFSET 9 280 #define DCBX_ETS_CHANGED_MASK 0x00000400 281 #define DCBX_ETS_CHANGED_OFFSET 10 282 #define DCBX_APP_CHANGED_MASK 0x00000800 283 #define DCBX_APP_CHANGED_OFFSET 11 284 285 u32 seq_no; 286 u32 ack_no; 287 u32 received_seq_no; 288 u8 tc_map[8]; 289 u8 num_used_tcs; 290 } dcbx_state_s; 291 292 #ifdef CONFIG_HP_DCI_SUPPORT 293 struct dci_info_port { 294 u32 config; 295 #define DCI_PORT_CFG_ENABLE_OFFSET (0) 296 #define DCI_PORT_CFG_ENABLE_MASK (1 << DCI_PORT_CFG_ENABLE_OFFSET) 297 #define DCI_PORT_CFG_ENABLE_DIAG_OFFSET (1) 298 #define DCI_PORT_CFG_ENABLE_DIAG_MASK (1 << DCI_PORT_CFG_ENABLE_DIAG_OFFSET) 299 #define DCI_PORT_CFG_DIAG_L_LOOP_OFFSET (2) 300 #define DCI_PORT_CFG_DIAG_L_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_L_LOOP_OFFSET) 301 #define DCI_PORT_CFG_DIAG_R_LOOP_OFFSET (3) 302 #define DCI_PORT_CFG_DIAG_R_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_R_LOOP_OFFSET) 303 304 }; 305 #endif 306 307 struct lldp_cdcp { 308 u32 flags; 309 #define NTPMR_TTL_EXPIRED 0x00000001 310 #define CDCP_TLV_RCVD 0x00000002 311 #define CDCP_TLV_SENT 0x00000004 312 313 u32 remote_mib; 314 #define CDCP_ROLE_MASK 0x00000001 315 #define CDCP_ROLE_OFFSET 0 316 #define CDCP_ROLE_BRIDGE 0x0 317 #define CDCP_ROLE_STATION 0x1 318 319 #define CDCP_SCOMP_MASK 0x00000002 320 #define CDCP_SCOMP_OFFSET 1 321 322 #define CDCP_CHAN_CAP_MASK 0x0000fff0 323 #define CDCP_CHAN_CAP_OFFSET 4 324 325 u32 num_of_chan; 326 }; 327 328 /* Accommodates link-tlv size for max-pf scids (27) + end-of-tlv size (2) */ 329 #define UFP_REQ_MAX_PAYLOAD_SIZE (32) 330 331 /* Accommodates max-NIC props-tlv-size (117:5 +(16*7)), link-tlv (27), 332 * end-tlv (2). 333 */ 334 #define UFP_RSP_MAX_PAYLOAD_SIZE (160) 335 struct ufp_info_port { 336 u8 req_payload[UFP_REQ_MAX_PAYLOAD_SIZE]; 337 u8 rsp_payload[UFP_RSP_MAX_PAYLOAD_SIZE]; 338 u16 req_len; 339 u16 rsp_len; 340 u8 switch_version; 341 u8 switch_status; 342 u8 flags; 343 #define UFP_CAP_ENABLED (1 << 0) 344 #define UFP_REQ_SENT (1 << 1) 345 #define UFP_RSP_SENT (1 << 2) 346 #define UFP_CAP_SENT (1 << 3) 347 u8 pending_flags; 348 #define UFP_REQ_PENDING (1 << 0) 349 #define UFP_RSP_PENDING (1 << 1) 350 }; 351 352 #define UFP_ENABLED(_port_) \ 353 (g_spad.private_data.port[_port_].ufp_port.flags & UFP_CAP_ENABLED) 354 355 /* Max 200-byte packet, accommodates UFP_RSP_MAX_PAYLOAD_SIZE */ 356 #define ECP_MAX_PKT_SIZE (200) 357 358 /* Tx-state machine, Qbg variable names specified in comments on the right */ 359 struct ecp_tx_state { 360 u8 tx_pkt[ECP_MAX_PKT_SIZE]; 361 BOOL ulp_req_rcvd; /* requestReceived */ 362 BOOL ack_rcvd; /* ackReceived */ 363 u16 req_seq_num; /* sequence */ 364 365 /* State used for timer-based retries */ 366 u16 ack_timer_counter; 367 #define ECP_TIMEOUT_COUNT 1 /* 1 second to detect ACK timeout */ 368 u16 num_retries; /* retries */ 369 #define ECP_MAX_RETRIES 3 370 u32 tx_errors; /* txErrors */ 371 u32 ulp_pkt_len; 372 }; 373 374 typedef void (*ulp_rx_indication_t)(u8 port, u16 subtype, u32 pkt_len, u8 *pkt); 375 /* Rx state machine, Qbg variable names specified in comments on the right */ 376 struct ecp_rx_state { 377 BOOL ecpdu_rcvd; /* ecpduReceived */ 378 u16 last_req_seq; /* lastSeq */ 379 u8 first_req_rcvd; 380 u8 rsvd; 381 ulp_rx_indication_t rx_cb_func; 382 }; 383 384 struct ecp_state_s { 385 struct ecp_tx_state tx_state; 386 struct ecp_rx_state rx_state; 387 u16 subtype; 388 }; 389 390 struct private_port { 391 struct drv_port_info_t port_info; 392 active_mf_mode_t mf_mode; 393 u32 prev_link_change_count; 394 /* LLDP structures */ 395 lldp_params_s lldp_params[LLDP_MAX_LLDP_AGENTS]; 396 lldp_receive_data_s lldp_receive_data[MAX_SUBSCRIBERS]; 397 398 /* DCBX */ 399 dcbx_state_s dcbx_state; 400 401 u32 net_buffer[MAX_PACKET_SIZE / 4]; /* Buffer to send any packet to network */ 402 403 /* time stamp of the end of NIG drain time for the TX drain */ 404 u32 nig_drain_end_ts; 405 /* time stamp of the end of NIG drain time for the TC pause drain, this timer is used togther for all TC */ 406 u32 nig_drain_tc_end_ts; 407 u32 tc_drain_en_bitmap; 408 tlv_s lldp_core_tlv_desc[LLDP_MAX_LLDP_AGENTS][MAX_REGISTERED_TLVS]; 409 u8 current_core_tlv_num[LLDP_MAX_LLDP_AGENTS]; 410 struct mcp_mac lldp_mac; 411 #ifdef CONFIG_HP_DCI_SUPPORT 412 struct dci_info_port dci_port; 413 #endif 414 struct lldp_cdcp cdcp_info; 415 struct ufp_info_port ufp_port; 416 struct ecp_state_s ecp_info; 417 struct lldp_stats_stc lldp_stats[LLDP_MAX_LLDP_AGENTS]; 418 u32 temperature; 419 u8 prev_ext_lasi_status; 420 u8 rsvd1; 421 u16 rsvd2; 422 423 }; 424 425 /**************************************/ 426 /* */ 427 /* P R I V A T E F U N C */ 428 /* */ 429 /**************************************/ 430 struct drv_func_info_t { 431 u32_t func_state; 432 #define DRV_STATE_UNKNOWN 0x00000000 433 #define DRV_STATE_UNLOADED 0x00000001 434 #define DRV_STATE_D3 0x00000004 435 436 #define DRV_STATE_PRESENT_FLAG 0x00000100 437 #define DRV_STATE_RUNNING (0x00000002 | DRV_STATE_PRESENT_FLAG) 438 439 #define DRV_STATE_NOT_RESPONDING 0x00000003 /* Will result with non-zero value when compared with DRV_STATE_RUNNING or with DRV_STATE_UNLOADED */ 440 #define DRV_STATE_BACK_AFTER_TO (DRV_STATE_NOT_RESPONDING | DRV_STATE_PRESENT_FLAG) 441 442 #define DRV_STATE_DIAG (0x00000010 | DRV_STATE_PRESENT_FLAG) 443 444 #define DRV_STATE_TRANSITION_FLAG 0x00001000 445 #define DRV_STATE_LOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG) 446 #define DRV_STATE_UNLOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG | DRV_STATE_UNLOADED) 447 448 u32_t driver_last_activity; 449 450 u32_t wol_mac_addr[2]; 451 u32_t drv_feature_support; /* See DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_* */ 452 453 u8_t unload_wol_param; /* See drv_mb_param */ 454 u8_t eswitch_mode; 455 u8_t ppfid_bmp; 456 }; 457 458 struct dci_info_func { 459 u8 config; 460 #define DCI_FUNC_CFG_FNIC_ENABLE_OFFSET (0) 461 #define DCI_FUNC_CFG_FNIC_ENABLE_MASK (1 << DCI_FUNC_CFG_FNIC_ENABLE_OFFSET) 462 #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_OFFSET (1) 463 #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_MASK (1 << DCI_FUNC_CFG_OS_MTU_OVERRIDE_OFFSET) 464 #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_OFFSET (2) 465 #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_MASK (1 << DCI_FUNC_CFG_DIAG_WOL_ENABLE_OFFSET) 466 467 u8 drv_state; 468 u16 fcoe_cvid; 469 u8 fcoe_fabric_name[8]; 470 #define CONNECTION_ID_LENGTH 16 471 u8 local_conn_id[CONNECTION_ID_LENGTH]; 472 }; 473 474 struct private_func { 475 struct drv_func_info_t func_info; 476 u32 init_hw_page; 477 struct pf_sb_t sb; 478 struct dci_info_func dci_func; 479 }; 480 481 482 /**************************************/ 483 /* */ 484 /* P R I V A T E D A T A */ 485 /* */ 486 /**************************************/ 487 struct mcp_private_data { 488 /* Basically no need for section offsets here, since this is private data. 489 * TBD - should consider adding section offsets if we want diag to parse this correctly !! 490 */ 491 struct private_global global; 492 struct private_path path[MCP_GLOB_PATH_MAX]; 493 struct private_port port[MCP_GLOB_PORT_MAX]; 494 struct private_func func[MCP_GLOB_FUNC_MAX]; 495 496 }; 497 #endif /* MCP_PRIVATE_H */ 498