1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 /**************************************************************************** 30 * 31 * Name: mcp_private.h 32 * 33 * Description: MCP private data. Located in HSI only to provide debug access 34 * for diag. 35 * 36 ****************************************************************************/ 37 38 #ifndef MCP_PRIVATE_H 39 #define MCP_PRIVATE_H 40 41 #if (!defined MFW_SIM) && (!defined RECOVERY) 42 #include "eth.h" 43 #include "pmm.h" 44 #include "ah_eth.h" 45 #include "e5_eth.h" 46 #endif 47 #include "global.h" 48 #include "mcp_public.h" 49 50 typedef enum active_mf_mode { 51 MF_MODE_SF = 0, 52 MF_MODE_MF_ALLOWED, 53 MF_MODE_MF_SWITCH_INDEPENDENT, 54 MF_MODE_NIV 55 } active_mf_mode_t; 56 57 enum ov_current_cfg { 58 CURR_CFG_NONE = 0, 59 CURR_CFG_OS, 60 CURR_CFG_VENDOR_SPEC, 61 CURR_CFG_OTHER, 62 CURR_CFG_VC_CLP, 63 CURR_CFG_CNU, 64 CURR_CFG_DCI, 65 CURR_CFG_HII, 66 }; 67 68 struct dci_info_global { 69 u16 mba_ver; 70 u8 current_cfg; 71 u8 extern_dci_mgmt; 72 u8 pci_bus_num; 73 u8 boot_progress; 74 }; 75 76 /* Resource allocation information of one resource */ 77 struct resource_info_private { 78 u16 size; /* number of allocated resources */ 79 u16 offset; /* Offset of the 1st resource */ 80 u8 flags; 81 }; 82 83 /* Cache for resource allocation of one PF */ 84 struct res_alloc_cache { 85 u8 pf_num; 86 struct resource_info_private res[RESOURCE_MAX_NUM]; 87 }; 88 89 struct pf_sb_t { 90 u8 sb_for_pf_size; 91 u8 sb_for_pf_offset; 92 u8 sb_for_vf_size; 93 u8 sb_for_vf_offset; 94 }; 95 96 /**************************************/ 97 /* */ 98 /* P R I V A T E G L O B A L */ 99 /* */ 100 /**************************************/ 101 struct private_global { 102 active_mf_mode_t mf_mode; /* TBD - require initialization */ 103 u32 exp_rom_nvm_addr; 104 105 /* The pmm_config structure holds all active phy/link configuration */ 106 #if (!defined MFW_SIM) && (!defined RECOVERY) 107 #ifdef b900 108 struct pmm_config eth_cfg; 109 #elif b940 110 struct ah_eth eth_cfg; 111 #elif b510 112 struct e5_eth eth_cfg; 113 #else 114 #endif 115 #endif 116 u32 lldp_counter; 117 118 u32 avs_init_timestamp; 119 120 u32 seconds_since_mcp_reset; 121 122 u32 last_malloc_dir_used_timestamp; 123 #define MAX_USED_DIR_ALLOWED_TIME (3) /* Seconds */ 124 125 u32 drv_nvm_state; 126 /* Per PF bitmask */ 127 #define DRV_NVM_STATE_IN_PROGRESS_MASK (0x0001ffff) 128 #define DRV_NVM_STATE_IN_PROGRESS_OFFSET (0) 129 #define DRV_NVM_STATE_IN_PROGRESS_VAL_MFW (0x00010000) 130 131 u32 storm_fw_ver; 132 133 /* OneView data*/ 134 struct dci_info_global dci_global; 135 136 /* Resource allocation cached data */ 137 struct res_alloc_cache res_alloc; 138 #define G_RES_ALLOC_P (&g_spad.private_data.global.res_alloc) 139 u32 resource_max_values[RESOURCE_MAX_NUM]; 140 u32 glb_counter_100ms; 141 /*collection of global bits and controls*/ 142 u32 flags_and_ctrl; 143 #define PRV_GLOBAL_FIO_BMB_INITIATED_MASK 0x00000001 144 #define PRV_GLOBAL_FIO_BMB_INITIATED_OFFSET 0 145 #define PRV_GLOBAL_ENABLE_NET_THREAD_LONG_RUN_MASK 0x00000002 146 #define PRV_GLOBAL_ENABLE_NET_THREAD_LONG_RUN_OFFSET 1 147 148 #ifdef b900 149 u32 es_fir_engines : 8, es_fir_valid_bitmap : 8, es_l2_engines : 8, es_l2_valid_bitmap : 8; 150 #endif 151 u64 ecc_events; 152 }; 153 154 /**************************************/ 155 /* */ 156 /* P R I V A T E P A T H */ 157 /* */ 158 /**************************************/ 159 struct private_path { 160 u32 recovery_countdown; /* Counting down 2 seconds, using TMR3 */ 161 #define RECOVERY_MAX_COUNTDOWN_SECONDS 2 162 163 u32 drv_load_vars; /* When the seconds_since_mcp_reset gets here */ 164 #define DRV_LOAD_DEF_TIMEOUT 10 165 #define DRV_LOAD_TIMEOUT_MASK 0x0000ffff 166 #define DRV_LOAD_TIMEOUT_OFFSET 0 167 #define DRV_LOAD_NEED_FORCE_MASK 0xffff0000 168 #define DRV_LOAD_NEED_FORCE_OFFSET 16 169 struct load_rsp_stc drv_load_params; 170 u64 ecc_events; 171 }; 172 173 /**************************************/ 174 /* */ 175 /* P R I V A T E P O R T */ 176 /* */ 177 /**************************************/ 178 struct drv_port_info_t { 179 u32_t port_state; 180 #define DRV_STATE_LINK_LOCK_FLAG 0x00000001 181 #define DRV_WAIT_DBG_PRN 0x00000002 182 183 /* There are maximum 8 PFs per port */ 184 #define DRV_STATE_LOADED_MASK 0x0000ff00 185 #define DRV_STATE_LOADED_OFFSET 8 186 187 #define DRV_STATE_PF_TRANSITION_MASK 0x00ff0000 188 #define DRV_STATE_PF_TRANSITION_OFFSET 16 189 190 #define DRV_STATE_PF_PHY_INIT_MASK 0xff000000 191 #define DRV_STATE_PF_PHY_INIT_OFFSET 24 192 }; 193 194 typedef enum _lldp_subscriber_e { 195 LLDP_SUBSCRIBER_MANDATORY = 0, 196 LLDP_SUBSCRIBER_SYSTEM, 197 LLDP_SUBSCRIBER_DCBX_IEEE, 198 LLDP_SUBSCRIBER_DCBX_CEE, 199 LLDP_SUBSCRIBER_EEE, 200 LLDP_SUBSCRIBER_CDCP, 201 LLDP_SUBSCRIBER_DCI, 202 LLDP_SUBSCRIBER_UFP, 203 LLDP_SUBSCRIBER_NCSI, 204 MAX_SUBSCRIBERS 205 } lldp_subscriber_e; 206 207 typedef struct { 208 u16 valid; 209 u16 type_len; 210 #define LLDP_LEN_MASK (0x01ff) 211 #define LLDP_LEN_OFFSET (0) 212 #define LLDP_TYPE_MASK (0xfe00) 213 #define LLDP_TYPE_OFFSET (9) 214 u8 *value_p; 215 } tlv_s; 216 217 typedef u16(*lldp_prepare_tlv_func)(u8 port, lldp_agent_e lldp_agent, u8 *buffer); 218 219 typedef struct { 220 u16 valid; 221 lldp_prepare_tlv_func func; 222 } subscriber_callback_send_s; 223 224 typedef u8(*lldp_process_func)(u8 port, u8 num, u8 **tlvs); 225 226 #define MAX_NUM_SUBTYPES 4 227 typedef struct { 228 u8 valid; 229 u8 oui[3]; 230 u8 subtype_list[MAX_NUM_SUBTYPES]; 231 u8 num_subtypes; 232 lldp_process_func func; 233 } subscriber_callback_receive_s; 234 235 #define MAX_ETH_HEADER 14 /* TODO: to be extended per requirements */ 236 #define MAX_PACKET_SIZE (1516) /* So it can be devided by 4 */ 237 #define LLDP_CHASSIS_ID_TLV_LEN 7 238 #define LLDP_PORT_ID_TLV_LEN 7 239 typedef struct { 240 u16 len; 241 u8 header[MAX_ETH_HEADER]; 242 } lldp_eth_header_s; 243 244 typedef struct { 245 struct lldp_config_params_s lldp_config_params; 246 u16 lldp_ttl; 247 u8 lldp_cur_credit; 248 subscriber_callback_send_s subscriber_callback_send[MAX_SUBSCRIBERS]; 249 lldp_eth_header_s lldp_eth_header; 250 u32 lldp_time_to_send; 251 u32 lldp_ttl_expired; 252 u32 lldp_sent; 253 u8 first_lldp; 254 subscriber_callback_receive_s subscriber_callback_receive[MAX_SUBSCRIBERS]; 255 } lldp_params_s; 256 257 #define MAX_TLVS 20 258 typedef struct { 259 u8 current_received_tlv_index; 260 u8 *received_tlvs[MAX_TLVS]; 261 } lldp_receive_data_s; 262 263 #define MAX_REGISTERED_TLVS 12 264 265 typedef struct { 266 u32 config; /* Uses same defines as local config plus some more below*/ 267 #define DCBX_MODE_MASK 0x00000010 268 #define DCBX_MODE_OFFSET 4 269 #define DCBX_MODE_DRIVER 0 270 #define DCBX_MODE_DEFAULT 1 271 #define DCBX_CHANGED_MASK 0x00000f00 272 #define DCBX_CHANGED_OFFSET 8 273 #define DCBX_CONTROL_CHANGED_MASK 0x00000100 274 #define DCBX_CONTROL_CHANGED_OFFSET 8 275 #define DCBX_PFC_CHANGED_MASK 0x00000200 276 #define DCBX_PFC_CHANGED_OFFSET 9 277 #define DCBX_ETS_CHANGED_MASK 0x00000400 278 #define DCBX_ETS_CHANGED_OFFSET 10 279 #define DCBX_APP_CHANGED_MASK 0x00000800 280 #define DCBX_APP_CHANGED_OFFSET 11 281 282 u32 seq_no; 283 u32 ack_no; 284 u32 received_seq_no; 285 u8 tc_map[8]; 286 u8 num_used_tcs; 287 } dcbx_state_s; 288 289 #ifdef CONFIG_HP_DCI_SUPPORT 290 struct dci_info_port { 291 u32 config; 292 #define DCI_PORT_CFG_ENABLE_OFFSET (0) 293 #define DCI_PORT_CFG_ENABLE_MASK (1 << DCI_PORT_CFG_ENABLE_OFFSET) 294 #define DCI_PORT_CFG_ENABLE_DIAG_OFFSET (1) 295 #define DCI_PORT_CFG_ENABLE_DIAG_MASK (1 << DCI_PORT_CFG_ENABLE_DIAG_OFFSET) 296 #define DCI_PORT_CFG_DIAG_L_LOOP_OFFSET (2) 297 #define DCI_PORT_CFG_DIAG_L_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_L_LOOP_OFFSET) 298 #define DCI_PORT_CFG_DIAG_R_LOOP_OFFSET (3) 299 #define DCI_PORT_CFG_DIAG_R_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_R_LOOP_OFFSET) 300 301 }; 302 #endif 303 304 struct lldp_cdcp { 305 u32 flags; 306 #define NTPMR_TTL_EXPIRED 0x00000001 307 #define CDCP_TLV_RCVD 0x00000002 308 #define CDCP_TLV_SENT 0x00000004 309 310 u32 remote_mib; 311 #define CDCP_ROLE_MASK 0x00000001 312 #define CDCP_ROLE_OFFSET 0 313 #define CDCP_ROLE_BRIDGE 0x0 314 #define CDCP_ROLE_STATION 0x1 315 316 #define CDCP_SCOMP_MASK 0x00000002 317 #define CDCP_SCOMP_OFFSET 1 318 319 #define CDCP_CHAN_CAP_MASK 0x0000fff0 320 #define CDCP_CHAN_CAP_OFFSET 4 321 322 u32 num_of_chan; 323 }; 324 325 /* Accommodates link-tlv size for max-pf scids (27) + end-of-tlv size (2) */ 326 #define UFP_REQ_MAX_PAYLOAD_SIZE (32) 327 328 /* Accommodates max-NIC props-tlv-size (117:5 +(16*7)), link-tlv (27), 329 * end-tlv (2). 330 */ 331 #define UFP_RSP_MAX_PAYLOAD_SIZE (160) 332 struct ufp_info_port { 333 u8 req_payload[UFP_REQ_MAX_PAYLOAD_SIZE]; 334 u8 rsp_payload[UFP_RSP_MAX_PAYLOAD_SIZE]; 335 u16 req_len; 336 u16 rsp_len; 337 u8 switch_version; 338 u8 switch_status; 339 u8 flags; 340 #define UFP_CAP_ENABLED (1 << 0) 341 #define UFP_REQ_SENT (1 << 1) 342 #define UFP_RSP_SENT (1 << 2) 343 #define UFP_CAP_SENT (1 << 3) 344 u8 pending_flags; 345 #define UFP_REQ_PENDING (1 << 0) 346 #define UFP_RSP_PENDING (1 << 1) 347 }; 348 349 #define UFP_ENABLED(_port_) \ 350 (g_spad.private_data.port[_port_].ufp_port.flags & UFP_CAP_ENABLED) 351 352 /* Max 200-byte packet, accommodates UFP_RSP_MAX_PAYLOAD_SIZE */ 353 #define ECP_MAX_PKT_SIZE (200) 354 355 /* Tx-state machine, Qbg variable names specified in comments on the right */ 356 struct ecp_tx_state { 357 u8 tx_pkt[ECP_MAX_PKT_SIZE]; 358 BOOL ulp_req_rcvd; /* requestReceived */ 359 BOOL ack_rcvd; /* ackReceived */ 360 u16 req_seq_num; /* sequence */ 361 362 /* State used for timer-based retries */ 363 u16 ack_timer_counter; 364 #define ECP_TIMEOUT_COUNT 1 /* 1 second to detect ACK timeout */ 365 u16 num_retries; /* retries */ 366 #define ECP_MAX_RETRIES 3 367 u32 tx_errors; /* txErrors */ 368 u32 ulp_pkt_len; 369 }; 370 371 typedef void (*ulp_rx_indication_t)(u8 port, u16 subtype, u32 pkt_len, u8 *pkt); 372 /* Rx state machine, Qbg variable names specified in comments on the right */ 373 struct ecp_rx_state { 374 BOOL ecpdu_rcvd; /* ecpduReceived */ 375 u16 last_req_seq; /* lastSeq */ 376 u8 first_req_rcvd; 377 u8 rsvd; 378 ulp_rx_indication_t rx_cb_func; 379 }; 380 381 struct ecp_state_s { 382 struct ecp_tx_state tx_state; 383 struct ecp_rx_state rx_state; 384 u16 subtype; 385 }; 386 387 struct private_port { 388 struct drv_port_info_t port_info; 389 active_mf_mode_t mf_mode; 390 u32 prev_link_change_count; 391 /* LLDP structures */ 392 lldp_params_s lldp_params[LLDP_MAX_LLDP_AGENTS]; 393 lldp_receive_data_s lldp_receive_data[MAX_SUBSCRIBERS]; 394 395 /* DCBX */ 396 dcbx_state_s dcbx_state; 397 398 u32 net_buffer[MAX_PACKET_SIZE / 4]; /* Buffer to send any packet to network */ 399 400 /* time stamp of the end of NIG drain time for the TX drain */ 401 u32 nig_drain_end_ts; 402 /* time stamp of the end of NIG drain time for the TC pause drain, this timer is used togther for all TC */ 403 u32 nig_drain_tc_end_ts; 404 u32 tc_drain_en_bitmap; 405 tlv_s lldp_core_tlv_desc[LLDP_MAX_LLDP_AGENTS][MAX_REGISTERED_TLVS]; 406 u8 current_core_tlv_num[LLDP_MAX_LLDP_AGENTS]; 407 struct mcp_mac lldp_mac; 408 #ifdef CONFIG_HP_DCI_SUPPORT 409 struct dci_info_port dci_port; 410 #endif 411 struct lldp_cdcp cdcp_info; 412 struct ufp_info_port ufp_port; 413 struct ecp_state_s ecp_info; 414 struct lldp_stats_stc lldp_stats[LLDP_MAX_LLDP_AGENTS]; 415 u32 temperature; 416 u8 prev_ext_lasi_status; 417 u8 rsvd1; 418 u16 rsvd2; 419 420 }; 421 422 /**************************************/ 423 /* */ 424 /* P R I V A T E F U N C */ 425 /* */ 426 /**************************************/ 427 struct drv_func_info_t { 428 u32_t func_state; 429 #define DRV_STATE_UNKNOWN 0x00000000 430 #define DRV_STATE_UNLOADED 0x00000001 431 #define DRV_STATE_D3 0x00000004 432 433 #define DRV_STATE_PRESENT_FLAG 0x00000100 434 #define DRV_STATE_RUNNING (0x00000002 | DRV_STATE_PRESENT_FLAG) 435 436 #define DRV_STATE_NOT_RESPONDING 0x00000003 /* Will result with non-zero value when compared with DRV_STATE_RUNNING or with DRV_STATE_UNLOADED */ 437 #define DRV_STATE_BACK_AFTER_TO (DRV_STATE_NOT_RESPONDING | DRV_STATE_PRESENT_FLAG) 438 439 #define DRV_STATE_DIAG (0x00000010 | DRV_STATE_PRESENT_FLAG) 440 441 #define DRV_STATE_TRANSITION_FLAG 0x00001000 442 #define DRV_STATE_LOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG) 443 #define DRV_STATE_UNLOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG | DRV_STATE_UNLOADED) 444 445 u32_t driver_last_activity; 446 447 u32_t wol_mac_addr[2]; 448 u32_t drv_feature_support; /* See DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_* */ 449 450 u8_t unload_wol_param; /* See drv_mb_param */ 451 u8_t eswitch_mode; 452 u8_t ppfid_bmp; 453 }; 454 455 struct dci_info_func { 456 u8 config; 457 #define DCI_FUNC_CFG_FNIC_ENABLE_OFFSET (0) 458 #define DCI_FUNC_CFG_FNIC_ENABLE_MASK (1 << DCI_FUNC_CFG_FNIC_ENABLE_OFFSET) 459 #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_OFFSET (1) 460 #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_MASK (1 << DCI_FUNC_CFG_OS_MTU_OVERRIDE_OFFSET) 461 #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_OFFSET (2) 462 #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_MASK (1 << DCI_FUNC_CFG_DIAG_WOL_ENABLE_OFFSET) 463 464 u8 drv_state; 465 u16 fcoe_cvid; 466 u8 fcoe_fabric_name[8]; 467 #define CONNECTION_ID_LENGTH 16 468 u8 local_conn_id[CONNECTION_ID_LENGTH]; 469 }; 470 471 struct private_func { 472 struct drv_func_info_t func_info; 473 u32 init_hw_page; 474 struct pf_sb_t sb; 475 struct dci_info_func dci_func; 476 }; 477 478 /**************************************/ 479 /* */ 480 /* P R I V A T E D A T A */ 481 /* */ 482 /**************************************/ 483 struct mcp_private_data { 484 /* Basically no need for section offsets here, since this is private data. 485 * TBD - should consider adding section offsets if we want diag to parse this correctly !! 486 */ 487 struct private_global global; 488 struct private_path path[MCP_GLOB_PATH_MAX]; 489 struct private_port port[MCP_GLOB_PORT_MAX]; 490 struct private_func func[MCP_GLOB_FUNC_MAX]; 491 492 }; 493 #endif /* MCP_PRIVATE_H */ 494