xref: /freebsd/sys/dev/qlnx/qlnxe/fcoe_common.h (revision a2aef24aa3c8458e4036735dd6928b4ef77294e5)
1 /*
2  * Copyright (c) 2017-2018 Cavium, Inc.
3  * All rights reserved.
4  *
5  *  Redistribution and use in source and binary forms, with or without
6  *  modification, are permitted provided that the following conditions
7  *  are met:
8  *
9  *  1. Redistributions of source code must retain the above copyright
10  *     notice, this list of conditions and the following disclaimer.
11  *  2. Redistributions in binary form must reproduce the above copyright
12  *     notice, this list of conditions and the following disclaimer in the
13  *     documentation and/or other materials provided with the distribution.
14  *
15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25  *  POSSIBILITY OF SUCH DAMAGE.
26  *
27  * $FreeBSD$
28  *
29  */
30 
31 
32 #ifndef __FCOE_COMMON__
33 #define __FCOE_COMMON__
34 /*********************/
35 /* FCOE FW CONSTANTS */
36 /*********************/
37 
38 #define FC_ABTS_REPLY_MAX_PAYLOAD_LEN	12
39 
40 
41 
42 
43 
44 /*
45  * The fcoe storm task context protection-information of Ystorm
46  */
47 struct protection_info_ctx
48 {
49 	__le16 flags;
50 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK        0x3 /* 0=none, 1=DIF, 2=DIX */
51 #define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT       0
52 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK           0x1 /* 0=no, 1=yes */
53 #define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT          2
54 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK  0x1 /* 0=no, 1=yes */
55 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
56 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK     0xF /* Protection log interval (9=512 10=1024  11=2048 12=4096 13=8192) */
57 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT    4
58 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK  0x1 /* 0=no, 1=yes */
59 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
60 #define PROTECTION_INFO_CTX_RESERVED0_MASK             0x7F
61 #define PROTECTION_INFO_CTX_RESERVED0_SHIFT            9
62 	u8 dix_block_size /* Source protection data size */;
63 	u8 dst_size /* Destination protection data size */;
64 };
65 
66 /*
67  * The fcoe storm task context protection-information of Ystorm
68  */
69 union protection_info_union_ctx
70 {
71 	struct protection_info_ctx info;
72 	__le32 value /* If and only if this field is not 0 then protection is set */;
73 };
74 
75 /*
76  * FCP CMD payload
77  */
78 struct fcoe_fcp_cmd_payload
79 {
80 	__le32 opaque[8] /* The FCP_CMD payload */;
81 };
82 
83 /*
84  * FCP RSP payload
85  */
86 struct fcoe_fcp_rsp_payload
87 {
88 	__le32 opaque[6] /* The FCP_RSP payload */;
89 };
90 
91 /*
92  * FCP RSP payload
93  */
94 struct fcp_rsp_payload_padded
95 {
96 	struct fcoe_fcp_rsp_payload rsp_payload /* The FCP_RSP payload */;
97 	__le32 reserved[2];
98 };
99 
100 /*
101  * FCP RSP payload
102  */
103 struct fcoe_fcp_xfer_payload
104 {
105 	__le32 opaque[3] /* The FCP_XFER payload */;
106 };
107 
108 /*
109  * FCP RSP payload
110  */
111 struct fcp_xfer_payload_padded
112 {
113 	struct fcoe_fcp_xfer_payload xfer_payload /* The FCP_XFER payload */;
114 	__le32 reserved[5];
115 };
116 
117 /*
118  * Task params
119  */
120 struct fcoe_tx_data_params
121 {
122 	__le32 data_offset /* Data offset */;
123 	__le32 offset_in_io /* For sequence cleanup */;
124 	u8 flags;
125 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK  0x1 /* Should we send offset in IO */
126 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
127 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK           0x1 /* Should the PBF drop this data */
128 #define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT          1
129 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK       0x1 /* Indication if the task after seqqence recovery flow */
130 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT      2
131 #define FCOE_TX_DATA_PARAMS_RESERVED0_MASK           0x1F
132 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT          3
133 	u8 dif_residual /* Residual from protection interval */;
134 	__le16 seq_cnt /* Sequence counter */;
135 	__le16 single_sge_saved_offset /* Saved SGE length for single SGE case */;
136 	__le16 next_dif_offset /* Tracking next DIF offset in FC payload */;
137 	__le16 seq_id /* Sequence ID (Set [saved] upon seq_cnt==0 (start of sequence) and used throughout sequence) */;
138 	__le16 reserved3;
139 };
140 
141 /*
142  * Middle path parameters: FC header fields provided by the driver
143  */
144 struct fcoe_tx_mid_path_params
145 {
146 	__le32 parameter;
147 	u8 r_ctl;
148 	u8 type;
149 	u8 cs_ctl;
150 	u8 df_ctl;
151 	__le16 rx_id;
152 	__le16 ox_id;
153 };
154 
155 /*
156  * Task params
157  */
158 struct fcoe_tx_params
159 {
160 	struct fcoe_tx_data_params data /* Data offset */;
161 	struct fcoe_tx_mid_path_params mid_path;
162 };
163 
164 /*
165  * Union of FCP CMD payload \ TX params \ ABTS \ Cleanup
166  */
167 union fcoe_tx_info_union_ctx
168 {
169 	struct fcoe_fcp_cmd_payload fcp_cmd_payload /* FCP CMD payload */;
170 	struct fcp_rsp_payload_padded fcp_rsp_payload /* FCP RSP payload */;
171 	struct fcp_xfer_payload_padded fcp_xfer_payload /* FCP XFER payload */;
172 	struct fcoe_tx_params tx_params /* Task TX params */;
173 };
174 
175 /*
176  * Data sgl
177  */
178 struct fcoe_slow_sgl_ctx
179 {
180 	struct regpair base_sgl_addr /* Address of first SGE in SGL */;
181 	__le16 curr_sge_off /* Offset in current BD (in bytes) */;
182 	__le16 remainder_num_sges /* Number of BDs */;
183 	__le16 curr_sgl_index /* Index of current SGE */;
184 	__le16 reserved;
185 };
186 
187 /*
188  * Union of DIX SGL \ cached DIX sges
189  */
190 union fcoe_dix_desc_ctx
191 {
192 	struct fcoe_slow_sgl_ctx dix_sgl /* DIX slow-SGL data base */;
193 	struct scsi_sge cached_dix_sge /* Cached DIX sge */;
194 };
195 
196 /*
197  * The fcoe storm task context of Ystorm
198  */
199 struct ystorm_fcoe_task_st_ctx
200 {
201 	u8 task_type /* Task type. use enum fcoe_task_type  */;
202 	u8 sgl_mode;
203 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK  0x1 /* use enum scsi_sgl_mode (use enum scsi_sgl_mode) */
204 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
205 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK         0x7F
206 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT        1
207 	u8 cached_dix_sge /* Dix sge is cached on task context */;
208 	u8 expect_first_xfer /* Will let Ystorm know when it should initialize fcp_cmd_payload_params_union.params */;
209 	__le32 num_pbf_zero_write /* The amount of bytes that PBF should dummy write - Relevant for protection only. */;
210 	union protection_info_union_ctx protection_info_union /* Protection information */;
211 	__le32 data_2_trns_rem /* Entire SGL-buffer remainder */;
212 	struct scsi_sgl_params sgl_params;
213 	u8 reserved1[12];
214 	union fcoe_tx_info_union_ctx tx_info_union /* Union of FCP CMD payload / TX params / ABTS / Cleanup */;
215 	union fcoe_dix_desc_ctx dix_desc /* Union of DIX SGL / cached DIX sges */;
216 	struct scsi_cached_sges data_desc /* Data cached SGEs */;
217 	__le16 ox_id /* OX-ID. Used in Target mode only */;
218 	__le16 rx_id /* RX-ID. Used in Target mode only */;
219 	__le32 task_rety_identifier /* Parameter field of the FCP CMDs FC header */;
220 	u8 reserved2[8];
221 };
222 
223 struct e4_ystorm_fcoe_task_ag_ctx
224 {
225 	u8 byte0 /* cdu_validation */;
226 	u8 byte1 /* state */;
227 	__le16 word0 /* icid */;
228 	u8 flags0;
229 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK     0xF /* connection_type */
230 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT    0
231 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK        0x1 /* exist_in_qm0 */
232 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT       4
233 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK        0x1 /* exist_in_qm1 */
234 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT       5
235 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK        0x1 /* bit2 */
236 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT       6
237 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK        0x1 /* bit3 */
238 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT       7
239 	u8 flags1;
240 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK         0x3 /* cf0 */
241 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT        0
242 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK         0x3 /* cf1 */
243 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT        2
244 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK  0x3 /* cf2special */
245 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
246 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK       0x1 /* cf0en */
247 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT      6
248 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK       0x1 /* cf1en */
249 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT      7
250 	u8 flags2;
251 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK        0x1 /* bit4 */
252 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT       0
253 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK     0x1 /* rule0en */
254 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT    1
255 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK     0x1 /* rule1en */
256 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT    2
257 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK     0x1 /* rule2en */
258 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT    3
259 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK     0x1 /* rule3en */
260 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT    4
261 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK     0x1 /* rule4en */
262 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT    5
263 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK     0x1 /* rule5en */
264 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT    6
265 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK     0x1 /* rule6en */
266 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT    7
267 	u8 byte2 /* byte2 */;
268 	__le32 reg0 /* reg0 */;
269 	u8 byte3 /* byte3 */;
270 	u8 byte4 /* byte4 */;
271 	__le16 rx_id /* word1 */;
272 	__le16 word2 /* word2 */;
273 	__le16 word3 /* word3 */;
274 	__le16 word4 /* word4 */;
275 	__le16 word5 /* word5 */;
276 	__le32 reg1 /* reg1 */;
277 	__le32 reg2 /* reg2 */;
278 };
279 
280 struct e4_tstorm_fcoe_task_ag_ctx
281 {
282 	u8 reserved /* cdu_validation */;
283 	u8 byte1 /* state */;
284 	__le16 icid /* icid */;
285 	u8 flags0;
286 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK     0xF /* connection_type */
287 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT    0
288 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK        0x1 /* exist_in_qm0 */
289 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT       4
290 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK                0x1 /* exist_in_qm1 */
291 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT               5
292 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK     0x1 /* bit2 */
293 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT    6
294 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK               0x1 /* bit3 */
295 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT              7
296 	u8 flags1;
297 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK        0x1 /* bit4 */
298 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT       0
299 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK                0x1 /* bit5 */
300 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT               1
301 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK       0x3 /* timer0cf */
302 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT      2
303 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK           0x3 /* timer1cf */
304 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT          4
305 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK                 0x3 /* timer2cf */
306 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT                6
307 	u8 flags2;
308 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK      0x3 /* timer_stop_all */
309 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT     0
310 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK       0x3 /* cf4 */
311 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT      2
312 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK         0x3 /* cf5 */
313 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT        4
314 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK     0x3 /* cf6 */
315 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT    6
316 	u8 flags3;
317 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK       0x3 /* cf7 */
318 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT      0
319 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK    0x1 /* cf0en */
320 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT   2
321 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK        0x1 /* cf1en */
322 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT       3
323 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK               0x1 /* cf2en */
324 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT              4
325 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK   0x1 /* cf3en */
326 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT  5
327 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK    0x1 /* cf4en */
328 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT   6
329 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK      0x1 /* cf5en */
330 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT     7
331 	u8 flags4;
332 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK  0x1 /* cf6en */
333 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
334 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK    0x1 /* cf7en */
335 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT   1
336 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK             0x1 /* rule0en */
337 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT            2
338 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK             0x1 /* rule1en */
339 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT            3
340 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK             0x1 /* rule2en */
341 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT            4
342 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK             0x1 /* rule3en */
343 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT            5
344 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK             0x1 /* rule4en */
345 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT            6
346 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK             0x1 /* rule5en */
347 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT            7
348 	u8 cleanup_state /* byte2 */;
349 	__le16 last_sent_tid /* word1 */;
350 	__le32 rec_rr_tov_exp_timeout /* reg0 */;
351 	u8 byte3 /* byte3 */;
352 	u8 byte4 /* byte4 */;
353 	__le16 word2 /* word2 */;
354 	__le16 word3 /* word3 */;
355 	__le16 word4 /* word4 */;
356 	__le32 data_offset_end_of_seq /* reg1 */;
357 	__le32 data_offset_next /* reg2 */;
358 };
359 
360 /*
361  * Cached data sges
362  */
363 struct fcoe_exp_ro
364 {
365 	__le32 data_offset /* data-offset */;
366 	__le32 reserved /* High data-offset */;
367 };
368 
369 /*
370  * Union of Cleanup address \ expected relative offsets
371  */
372 union fcoe_cleanup_addr_exp_ro_union
373 {
374 	struct regpair abts_rsp_fc_payload_hi /* Abts flow: first 64 bits of fcPayload, out of 96 */;
375 	struct fcoe_exp_ro exp_ro /* Expected relative offsets */;
376 };
377 
378 /*
379  * fields coppied from ABTSrsp pckt
380  */
381 struct fcoe_abts_pkt
382 {
383 	__le32 abts_rsp_fc_payload_lo /* Abts flow: last 32 bits of fcPayload, out of 96 */;
384 	__le16 abts_rsp_rx_id /* Abts flow: rxId parameter of the abts packet */;
385 	u8 abts_rsp_rctl /* Abts flow: rctl parameter of the abts packet */;
386 	u8 reserved2;
387 };
388 
389 /*
390  * FW read- write (modifyable) part The fcoe task storm context of Tstorm
391  */
392 struct fcoe_tstorm_fcoe_task_st_ctx_read_write
393 {
394 	union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union /* Union of Cleanup address / expected relative offsets */;
395 	__le16 flags;
396 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK       0x1 /* Rx SGL type. use enum scsi_sgl_mode  (use enum scsi_sgl_mode) */
397 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT      0
398 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK   0x1 /* Expected first frame flag */
399 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT  1
400 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK        0x1 /* Sequence active */
401 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT       2
402 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK       0x1 /* Sequence timeout for an active Sequence */
403 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT      3
404 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK  0x1 /* Set by Data-in flow. Indicate that this exchange contains a single FCP DATA packet */
405 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
406 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK   0x1 /* The status of the current out of order received Sequence */
407 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT  5
408 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK        0x3 /* number of additional CQE that will be produced for this task completion */
409 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT       6
410 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK             0xFF
411 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT            8
412 	__le16 seq_cnt /* Sequence counter */;
413 	u8 seq_id /* Sequence id */;
414 	u8 ooo_rx_seq_id /* The last out of order received SEQ_ID */;
415 	__le16 rx_id /* RX_ID of the exchange - should match each packet expect for the first */;
416 	struct fcoe_abts_pkt abts_data /* The last out of order received SEQ_CNT */;
417 	__le32 e_d_tov_exp_timeout_val /* E_D_TOV timer val (in msec) */;
418 	__le16 ooo_rx_seq_cnt /* The last out of order received SEQ_CNT */;
419 	__le16 reserved1;
420 };
421 
422 /*
423  * FW read only part The fcoe task storm context of Tstorm
424  */
425 struct fcoe_tstorm_fcoe_task_st_ctx_read_only
426 {
427 	u8 task_type /* Task type. use enum fcoe_task_type */;
428 	u8 dev_type /* Device type (disk or tape). use enum fcoe_device_type */;
429 	u8 conf_supported /* Confirmation supported indication */;
430 	u8 glbl_q_num /* Global RQ/CQ num to be used for sense data placement/completion */;
431 	__le32 cid /* CID which that tasks associated to */;
432 	__le32 fcp_cmd_trns_size /* IO size as reflected in FCP CMD */;
433 	__le32 rsrv;
434 };
435 
436 /*
437  * The fcoe task storm context of Tstorm
438  */
439 struct tstorm_fcoe_task_st_ctx
440 {
441 	struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write /* FW read- write (modifyable) part The fcoe task storm context of Tstorm */;
442 	struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only /* FW read only part The fcoe task storm context of Tstorm */;
443 };
444 
445 struct e4_mstorm_fcoe_task_ag_ctx
446 {
447 	u8 byte0 /* cdu_validation */;
448 	u8 byte1 /* state */;
449 	__le16 icid /* icid */;
450 	u8 flags0;
451 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK    0xF /* connection_type */
452 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT   0
453 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
454 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT      4
455 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK         0x1 /* exist_in_qm1 */
456 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT        5
457 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK               0x1 /* bit2 */
458 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT              6
459 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK               0x1 /* bit3 */
460 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT              7
461 	u8 flags1;
462 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK      0x3 /* cf0 */
463 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT     0
464 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK                0x3 /* cf1 */
465 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT               2
466 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK                0x3 /* cf2 */
467 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT               4
468 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK   0x1 /* cf0en */
469 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT  6
470 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
471 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT             7
472 	u8 flags2;
473 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
474 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT             0
475 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
476 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT           1
477 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
478 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT           2
479 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
480 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT           3
481 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
482 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT           4
483 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
484 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT           5
485 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK  0x1 /* rule5en */
486 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
487 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
488 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT           7
489 	u8 cleanup_state /* byte2 */;
490 	__le32 received_bytes /* reg0 */;
491 	u8 byte3 /* byte3 */;
492 	u8 glbl_q_num /* byte4 */;
493 	__le16 word1 /* word1 */;
494 	__le16 tid_to_xfer /* word2 */;
495 	__le16 word3 /* word3 */;
496 	__le16 word4 /* word4 */;
497 	__le16 word5 /* word5 */;
498 	__le32 expected_bytes /* reg1 */;
499 	__le32 reg2 /* reg2 */;
500 };
501 
502 /*
503  * The fcoe task storm context of Mstorm
504  */
505 struct mstorm_fcoe_task_st_ctx
506 {
507 	struct regpair rsp_buf_addr /* Buffer to place the sense/response data attached to FCP_RSP frame */;
508 	__le32 rsrv[2];
509 	struct scsi_sgl_params sgl_params;
510 	__le32 data_2_trns_rem /* Entire SGL buffer size remainder */;
511 	__le32 data_buffer_offset /* Buffer offset */;
512 	__le16 parent_id /* Used for multiple continuation in Target mode */;
513 	__le16 flags;
514 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK     0xF /* Protection log interval (9=512 10=1024  11=2048 12=4096 13=8192) */
515 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT    0
516 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK        0x3 /* 0=none, 1=DIF, 2=DIX */
517 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT       4
518 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK           0x1 /* 0=no, 1=yes */
519 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT          6
520 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK  0x1 /* 0 = 24 Bytes FC Header not included in Middle-Path placement, 1 = 24 Bytes FC Header included in MP placement */
521 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
522 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK        0x3 /* DIX block size: can be 0:2B, 1:4B, 2:8B */
523 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT       8
524 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK  0x1 /* 0=no, 1=yes */
525 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
526 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK    0x1 /* Indication to a single cached DIX SGE instead of SGL */
527 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT   11
528 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK         0x1
529 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT        12
530 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK           0x1 /* use_enum scsi_sgl_mode (use enum scsi_sgl_mode) */
531 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT          13
532 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK              0x3
533 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT             14
534 	struct scsi_cached_sges data_desc /* Union of Data SGL / cached sge */;
535 };
536 
537 struct e4_ustorm_fcoe_task_ag_ctx
538 {
539 	u8 reserved /* cdu_validation */;
540 	u8 byte1 /* state */;
541 	__le16 icid /* icid */;
542 	u8 flags0;
543 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
544 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
545 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
546 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
547 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
548 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT            5
549 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK              0x3 /* timer0cf */
550 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT             6
551 	u8 flags1;
552 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK              0x3 /* timer1cf */
553 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT             0
554 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK              0x3 /* timer2cf */
555 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT             2
556 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK              0x3 /* timer_stop_all */
557 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT             4
558 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK     0x3 /* cf4 */
559 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT    6
560 	u8 flags2;
561 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
562 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT           0
563 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
564 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT           1
565 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
566 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT           2
567 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK            0x1 /* cf3en */
568 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT           3
569 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK  0x1 /* cf4en */
570 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
571 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
572 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT         5
573 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
574 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT         6
575 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
576 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT         7
577 	u8 flags3;
578 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
579 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT         0
580 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
581 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT         1
582 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
583 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT         2
584 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
585 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT         3
586 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK   0xF /* nibble1 */
587 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT  4
588 	__le32 dif_err_intervals /* reg0 */;
589 	__le32 dif_error_1st_interval /* reg1 */;
590 	__le32 global_cq_num /* reg2 */;
591 	__le32 reg3 /* reg3 */;
592 	__le32 reg4 /* reg4 */;
593 	__le32 reg5 /* reg5 */;
594 };
595 
596 /*
597  * fcoe task context
598  */
599 struct e4_fcoe_task_context
600 {
601 	struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */;
602 	struct regpair ystorm_st_padding[2] /* padding */;
603 	struct tdif_task_context tdif_context /* tdif context */;
604 	struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
605 	struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
606 	struct timers_context timer_context /* timer context */;
607 	struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */;
608 	struct regpair tstorm_st_padding[2] /* padding */;
609 	struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
610 	struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */;
611 	struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
612 	struct rdif_task_context rdif_context /* rdif context */;
613 };
614 
615 
616 struct e5_ystorm_fcoe_task_ag_ctx
617 {
618 	u8 byte0 /* cdu_validation */;
619 	u8 byte1 /* state_and_core_id */;
620 	__le16 word0 /* icid */;
621 	u8 flags0;
622 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK       0xF /* connection_type */
623 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT      0
624 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK          0x1 /* exist_in_qm0 */
625 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT         4
626 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK          0x1 /* exist_in_qm1 */
627 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT         5
628 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK          0x1 /* bit2 */
629 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT         6
630 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK          0x1 /* bit3 */
631 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT         7
632 	u8 flags1;
633 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK           0x3 /* cf0 */
634 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT          0
635 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK           0x3 /* cf1 */
636 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT          2
637 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK    0x3 /* cf2special */
638 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT   4
639 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK         0x1 /* cf0en */
640 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT        6
641 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK         0x1 /* cf1en */
642 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT        7
643 	u8 flags2;
644 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK          0x1 /* bit4 */
645 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT         0
646 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK       0x1 /* rule0en */
647 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT      1
648 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK       0x1 /* rule1en */
649 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT      2
650 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK       0x1 /* rule2en */
651 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT      3
652 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK       0x1 /* rule3en */
653 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT      4
654 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK       0x1 /* rule4en */
655 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT      5
656 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK       0x1 /* rule5en */
657 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT      6
658 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK       0x1 /* rule6en */
659 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT      7
660 	u8 flags3;
661 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK  0x1 /* bit5 */
662 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0
663 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK  0x3 /* cf3 */
664 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1
665 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK  0x3 /* cf4 */
666 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3
667 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK  0x1 /* cf3en */
668 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5
669 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK  0x1 /* cf4en */
670 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6
671 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK  0x1 /* rule7en */
672 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7
673 	__le32 reg0 /* reg0 */;
674 	u8 byte2 /* byte2 */;
675 	u8 byte3 /* byte3 */;
676 	u8 byte4 /* byte4 */;
677 	u8 e4_reserved7 /* byte5 */;
678 	__le16 rx_id /* word1 */;
679 	__le16 word2 /* word2 */;
680 	__le16 word3 /* word3 */;
681 	__le16 word4 /* word4 */;
682 	__le16 word5 /* word5 */;
683 	__le16 e4_reserved8 /* word6 */;
684 	__le32 reg1 /* reg1 */;
685 };
686 
687 struct e5_tstorm_fcoe_task_ag_ctx
688 {
689 	u8 reserved /* cdu_validation */;
690 	u8 byte1 /* state_and_core_id */;
691 	__le16 icid /* icid */;
692 	u8 flags0;
693 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK     0xF /* connection_type */
694 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT    0
695 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK        0x1 /* exist_in_qm0 */
696 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT       4
697 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK                0x1 /* exist_in_qm1 */
698 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT               5
699 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK     0x1 /* bit2 */
700 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT    6
701 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK               0x1 /* bit3 */
702 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT              7
703 	u8 flags1;
704 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK        0x1 /* bit4 */
705 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT       0
706 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK                0x1 /* bit5 */
707 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT               1
708 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK       0x3 /* timer0cf */
709 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT      2
710 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK           0x3 /* timer1cf */
711 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT          4
712 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK                 0x3 /* timer2cf */
713 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT                6
714 	u8 flags2;
715 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK      0x3 /* timer_stop_all */
716 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT     0
717 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK       0x3 /* cf4 */
718 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT      2
719 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK         0x3 /* cf5 */
720 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT        4
721 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK     0x3 /* cf6 */
722 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT    6
723 	u8 flags3;
724 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK       0x3 /* cf7 */
725 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT      0
726 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK    0x1 /* cf0en */
727 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT   2
728 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK        0x1 /* cf1en */
729 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT       3
730 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK               0x1 /* cf2en */
731 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT              4
732 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK   0x1 /* cf3en */
733 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT  5
734 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK    0x1 /* cf4en */
735 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT   6
736 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK      0x1 /* cf5en */
737 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT     7
738 	u8 flags4;
739 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK  0x1 /* cf6en */
740 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
741 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK    0x1 /* cf7en */
742 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT   1
743 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK             0x1 /* rule0en */
744 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT            2
745 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK             0x1 /* rule1en */
746 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT            3
747 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK             0x1 /* rule2en */
748 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT            4
749 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK             0x1 /* rule3en */
750 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT            5
751 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK             0x1 /* rule4en */
752 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT            6
753 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK             0x1 /* rule5en */
754 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT            7
755 	u8 cleanup_state /* byte2 */;
756 	__le16 last_sent_tid /* word1 */;
757 	__le32 rec_rr_tov_exp_timeout /* reg0 */;
758 	u8 byte3 /* regpair0 */;
759 	u8 byte4 /* byte4 */;
760 	__le16 word2 /* word2 */;
761 	__le16 word3 /* word3 */;
762 	__le16 word4 /* word4 */;
763 	__le32 data_offset_end_of_seq /* regpair1 */;
764 	__le32 data_offset_next /* reg2 */;
765 };
766 
767 struct e5_mstorm_fcoe_task_ag_ctx
768 {
769 	u8 byte0 /* cdu_validation */;
770 	u8 byte1 /* state_and_core_id */;
771 	__le16 icid /* icid */;
772 	u8 flags0;
773 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK    0xF /* connection_type */
774 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT   0
775 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK       0x1 /* exist_in_qm0 */
776 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT      4
777 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK         0x1 /* exist_in_qm1 */
778 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT        5
779 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK               0x1 /* bit2 */
780 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT              6
781 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK               0x1 /* bit3 */
782 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT              7
783 	u8 flags1;
784 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK      0x3 /* cf0 */
785 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT     0
786 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK                0x3 /* cf1 */
787 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT               2
788 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK                0x3 /* cf2 */
789 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT               4
790 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK   0x1 /* cf0en */
791 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT  6
792 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK              0x1 /* cf1en */
793 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT             7
794 	u8 flags2;
795 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK              0x1 /* cf2en */
796 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT             0
797 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK            0x1 /* rule0en */
798 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT           1
799 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK            0x1 /* rule1en */
800 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT           2
801 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK            0x1 /* rule2en */
802 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT           3
803 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK            0x1 /* rule3en */
804 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT           4
805 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK            0x1 /* rule4en */
806 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT           5
807 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK  0x1 /* rule5en */
808 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
809 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK            0x1 /* rule6en */
810 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT           7
811 	u8 flags3;
812 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK       0x1 /* bit4 */
813 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT      0
814 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK       0x3 /* cf3 */
815 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT      1
816 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK       0x3 /* cf4 */
817 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT      3
818 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK       0x1 /* cf3en */
819 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT      5
820 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK       0x1 /* cf4en */
821 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT      6
822 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK       0x1 /* rule7en */
823 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT      7
824 	__le32 received_bytes /* reg0 */;
825 	u8 cleanup_state /* byte2 */;
826 	u8 byte3 /* byte3 */;
827 	u8 glbl_q_num /* byte4 */;
828 	u8 e4_reserved7 /* byte5 */;
829 	__le16 word1 /* regpair0 */;
830 	__le16 tid_to_xfer /* word2 */;
831 	__le16 word3 /* word3 */;
832 	__le16 word4 /* word4 */;
833 	__le16 word5 /* regpair1 */;
834 	__le16 e4_reserved8 /* word6 */;
835 	__le32 expected_bytes /* reg1 */;
836 };
837 
838 struct e5_ustorm_fcoe_task_ag_ctx
839 {
840 	u8 reserved /* cdu_validation */;
841 	u8 byte1 /* state_and_core_id */;
842 	__le16 icid /* icid */;
843 	u8 flags0;
844 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK  0xF /* connection_type */
845 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
846 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK     0x1 /* exist_in_qm0 */
847 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT    4
848 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK             0x1 /* exist_in_qm1 */
849 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT            5
850 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_MASK              0x3 /* timer0cf */
851 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT             6
852 	u8 flags1;
853 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_MASK              0x3 /* timer1cf */
854 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT             0
855 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_MASK              0x3 /* timer2cf */
856 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT             2
857 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_MASK              0x3 /* timer_stop_all */
858 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT             4
859 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK     0x3 /* dif_error_cf */
860 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT    6
861 	u8 flags2;
862 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK            0x1 /* cf0en */
863 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT           0
864 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK            0x1 /* cf1en */
865 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT           1
866 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK            0x1 /* cf2en */
867 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT           2
868 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK            0x1 /* cf3en */
869 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT           3
870 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK  0x1 /* cf4en */
871 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
872 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK          0x1 /* rule0en */
873 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT         5
874 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK          0x1 /* rule1en */
875 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT         6
876 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK          0x1 /* rule2en */
877 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT         7
878 	u8 flags3;
879 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK          0x1 /* rule3en */
880 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT         0
881 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK          0x1 /* rule4en */
882 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT         1
883 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK          0x1 /* rule5en */
884 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT         2
885 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK          0x1 /* rule6en */
886 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT         3
887 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK     0x1 /* bit2 */
888 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT    4
889 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK     0x1 /* bit3 */
890 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT    5
891 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK     0x1 /* bit4 */
892 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT    6
893 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK     0x1 /* rule7en */
894 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT    7
895 	u8 flags4;
896 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK     0x3 /* cf5 */
897 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT    0
898 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK     0x1 /* cf5en */
899 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT    2
900 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_MASK     0x1 /* rule8en */
901 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_SHIFT    3
902 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK   0xF /* dif_error_type */
903 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT  4
904 	u8 byte2 /* byte2 */;
905 	u8 byte3 /* byte3 */;
906 	u8 e4_reserved8 /* byte4 */;
907 	__le32 dif_err_intervals /* dif_err_intervals */;
908 	__le32 dif_error_1st_interval /* dif_error_1st_interval */;
909 	__le32 global_cq_num /* reg2 */;
910 	__le32 reg3 /* reg3 */;
911 	__le32 reg4 /* reg4 */;
912 };
913 
914 /*
915  * fcoe task context
916  */
917 struct e5_fcoe_task_context
918 {
919 	struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */;
920 	struct regpair ystorm_st_padding[2] /* padding */;
921 	struct tdif_task_context tdif_context /* tdif context */;
922 	struct e5_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */;
923 	struct e5_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */;
924 	struct timers_context timer_context /* timer context */;
925 	struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */;
926 	struct regpair tstorm_st_padding[2] /* padding */;
927 	struct e5_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */;
928 	struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */;
929 	struct e5_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */;
930 	struct rdif_task_context rdif_context /* rdif context */;
931 };
932 
933 
934 
935 /*
936  * FCoE additional WQE (Sq/ XferQ) information
937  */
938 union fcoe_additional_info_union
939 {
940 	__le32 previous_tid /* Previous tid. Used for Send XFER WQEs in Multiple continuation mode - Target only. */;
941 	__le32 parent_tid /* Parent tid. Used for write tasks in a continuation mode - Target only */;
942 	__le32 burst_length /* The desired burst length. */;
943 	__le32 seq_rec_updated_offset /* The updated offset in SGL - Used in sequence recovery */;
944 };
945 
946 
947 
948 /*
949  * FCoE Ramrod Command IDs
950  */
951 enum fcoe_completion_status
952 {
953 	FCOE_COMPLETION_STATUS_SUCCESS /* FCoE ramrod completed successfully */,
954 	FCOE_COMPLETION_STATUS_FCOE_VER_ERR /* Wrong FCoE version */,
955 	FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR /* src_mac_arr for the current physical port is full- allocation failed */,
956 	MAX_FCOE_COMPLETION_STATUS
957 };
958 
959 
960 /*
961  * FC address (SID/DID) network presentation
962  */
963 struct fc_addr_nw
964 {
965 	u8 addr_lo /* First byte of the SID/DID address that comes/goes from/to the NW (for example if SID is 11:22:33 - this is 0x11) */;
966 	u8 addr_mid;
967 	u8 addr_hi;
968 };
969 
970 /*
971  * FCoE connection offload
972  */
973 struct fcoe_conn_offload_ramrod_data
974 {
975 	struct regpair sq_pbl_addr /* SQ Pbl base address */;
976 	struct regpair sq_curr_page_addr /* SQ current page address */;
977 	struct regpair sq_next_page_addr /* SQ next page address */;
978 	struct regpair xferq_pbl_addr /* XFERQ Pbl base address */;
979 	struct regpair xferq_curr_page_addr /* XFERQ current page address */;
980 	struct regpair xferq_next_page_addr /* XFERQ next page address */;
981 	struct regpair respq_pbl_addr /* RESPQ Pbl base address */;
982 	struct regpair respq_curr_page_addr /* RESPQ current page address */;
983 	struct regpair respq_next_page_addr /* RESPQ next page address */;
984 	__le16 dst_mac_addr_lo /* First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */;
985 	__le16 dst_mac_addr_mid;
986 	__le16 dst_mac_addr_hi;
987 	__le16 src_mac_addr_lo /* Source MAC address in NW order - First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */;
988 	__le16 src_mac_addr_mid;
989 	__le16 src_mac_addr_hi;
990 	__le16 tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */;
991 	__le16 e_d_tov_timer_val /* E_D_TOV timeout value in resolution of 1 msec */;
992 	__le16 rx_max_fc_pay_len /* Maximum acceptable FC payload size supported by us */;
993 	__le16 vlan_tag;
994 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK              0xFFF /* Vlan id */
995 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT             0
996 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK                  0x1 /* Canonical format indicator */
997 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT                 12
998 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK             0x7 /* Vlan priority */
999 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT            13
1000 	__le16 physical_q0 /* Physical QM queue to be linked to logical queue 0 (fastPath queue) */;
1001 	__le16 rec_rr_tov_timer_val /* REC_TOV timeout value in resolution of 1 msec  */;
1002 	struct fc_addr_nw s_id /* Source ID in NW order, received during FLOGI */;
1003 	u8 max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by target, received during PLOGI */;
1004 	struct fc_addr_nw d_id /* Destination ID in NW order, received after inquiry of the fabric network */;
1005 	u8 flags;
1006 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK  0x1 /* Continuously increasing SEQ_CNT indication, received during PLOGI */
1007 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
1008 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK           0x1 /* Confirmation request supported */
1009 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT          1
1010 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK          0x1 /* REC allowed */
1011 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT         2
1012 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK          0x1 /* Does inner vlan exist */
1013 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT         3
1014 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK                 0x3 /* indication for conn mode: 0=Initiator, 1=Target, 2=Both Initiator and Traget */
1015 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT                4
1016 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK            0x3
1017 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT           6
1018 	__le16 conn_id /* Drivers connection ID. Should be sent in EQs to speed-up drivers access to connection data. */;
1019 	u8 def_q_idx /* Default queue number to be used for unsolicited traffic */;
1020 	u8 reserved[5];
1021 };
1022 
1023 
1024 /*
1025  * FCoE terminate connection request
1026  */
1027 struct fcoe_conn_terminate_ramrod_data
1028 {
1029 	struct regpair terminate_params_addr /* Terminate params ptr */;
1030 };
1031 
1032 
1033 
1034 
1035 /*
1036  * Data sgl
1037  */
1038 struct fcoe_fast_sgl_ctx
1039 {
1040 	struct regpair sgl_start_addr /* Current sge address */;
1041 	__le32 sgl_byte_offset /* Byte offset from the beginning of the first page in the SGL. In case SGL starts in the middle of page then driver should init this value with the start offset */;
1042 	__le16 task_reuse_cnt /* The reuse count for that task. Wrap ion 4K value. */;
1043 	__le16 init_offset_in_first_sge /* offset from the beginning of the first page in the SGL, never changed by FW */;
1044 };
1045 
1046 
1047 
1048 
1049 
1050 /*
1051  * FCoE firmware function init
1052  */
1053 struct fcoe_init_func_ramrod_data
1054 {
1055 	struct scsi_init_func_params func_params /* Common SCSI init params passed by driver to FW in function init ramrod */;
1056 	struct scsi_init_func_queues q_params /* SCSI RQ/CQ/CMDQ firmware function init parameters */;
1057 	__le16 mtu /* Max transmission unit */;
1058 	__le16 sq_num_pages_in_pbl /* Number of pages at Send Queue */;
1059 	__le32 reserved[3];
1060 };
1061 
1062 
1063 /*
1064  * FCoE: Mode of the connection: Target or Initiator or both
1065  */
1066 enum fcoe_mode_type
1067 {
1068 	FCOE_INITIATOR_MODE=0x0,
1069 	FCOE_TARGET_MODE=0x1,
1070 	FCOE_BOTH_OR_NOT_CHOSEN=0x3,
1071 	MAX_FCOE_MODE_TYPE
1072 };
1073 
1074 
1075 /*
1076  * Per PF FCoE receive path statistics - tStorm RAM structure
1077  */
1078 struct fcoe_rx_stat
1079 {
1080 	struct regpair fcoe_rx_byte_cnt /* Number of FCoE bytes that were received */;
1081 	struct regpair fcoe_rx_data_pkt_cnt /* Number of FCoE FCP DATA packets that were received */;
1082 	struct regpair fcoe_rx_xfer_pkt_cnt /* Number of FCoE FCP XFER RDY packets that were received */;
1083 	struct regpair fcoe_rx_other_pkt_cnt /* Number of FCoE packets which are not DATA/XFER_RDY that were received */;
1084 	__le32 fcoe_silent_drop_pkt_cmdq_full_cnt /* Number of packets that were silently dropped since CMDQ was full */;
1085 	__le32 fcoe_silent_drop_pkt_rq_full_cnt /* Number of packets that were silently dropped since RQ (BDQ) was full */;
1086 	__le32 fcoe_silent_drop_pkt_crc_error_cnt /* Number of packets that were silently dropped due to FC CRC error */;
1087 	__le32 fcoe_silent_drop_pkt_task_invalid_cnt /* Number of packets that were silently dropped since task was not valid */;
1088 	__le32 fcoe_silent_drop_total_pkt_cnt /* Number of FCoE packets that were silently dropped */;
1089 	__le32 rsrv;
1090 };
1091 
1092 
1093 
1094 /*
1095  * FCoe statistics request
1096  */
1097 struct fcoe_stat_ramrod_data
1098 {
1099 	struct regpair stat_params_addr /* Statistics host address */;
1100 };
1101 
1102 
1103 
1104 
1105 
1106 
1107 
1108 
1109 /*
1110  * Per PF FCoE transmit path statistics - pStorm RAM structure
1111  */
1112 struct fcoe_tx_stat
1113 {
1114 	struct regpair fcoe_tx_byte_cnt /* Transmitted FCoE bytes count */;
1115 	struct regpair fcoe_tx_data_pkt_cnt /* Transmitted FCoE FCP DATA packets count */;
1116 	struct regpair fcoe_tx_xfer_pkt_cnt /* Transmitted FCoE XFER_RDY packets count */;
1117 	struct regpair fcoe_tx_other_pkt_cnt /* Transmitted FCoE packets which are not DATA/XFER_RDY count */;
1118 };
1119 
1120 
1121 /*
1122  * FCoE SQ/XferQ element
1123  */
1124 struct fcoe_wqe
1125 {
1126 	__le16 task_id /* Initiator - The task identifier (OX_ID). Target - Continuation tid or RX_ID in non-continuation mode */;
1127 	__le16 flags;
1128 #define FCOE_WQE_REQ_TYPE_MASK       0xF /* Type of the wqe request. use enum fcoe_sqe_request_type  (use enum fcoe_sqe_request_type) */
1129 #define FCOE_WQE_REQ_TYPE_SHIFT      0
1130 #define FCOE_WQE_SGL_MODE_MASK       0x1 /* The driver will give a hint about sizes of SGEs for better credits evaluation at Xstorm. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */
1131 #define FCOE_WQE_SGL_MODE_SHIFT      4
1132 #define FCOE_WQE_CONTINUATION_MASK   0x1 /* Indication if this wqe is a continuation to an existing task (Target only) */
1133 #define FCOE_WQE_CONTINUATION_SHIFT  5
1134 #define FCOE_WQE_SEND_AUTO_RSP_MASK  0x1 /* Indication to FW to send FCP_RSP after all data was sent - Target only */
1135 #define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
1136 #define FCOE_WQE_RESERVED_MASK       0x1
1137 #define FCOE_WQE_RESERVED_SHIFT      7
1138 #define FCOE_WQE_NUM_SGES_MASK       0xF /* Number of SGEs. 8 = at least 8 sges */
1139 #define FCOE_WQE_NUM_SGES_SHIFT      8
1140 #define FCOE_WQE_RESERVED1_MASK      0xF
1141 #define FCOE_WQE_RESERVED1_SHIFT     12
1142 	union fcoe_additional_info_union additional_info_union /* Additional wqe information (if needed) */;
1143 };
1144 
1145 
1146 
1147 
1148 
1149 
1150 
1151 
1152 
1153 /*
1154  * FCoE XFRQ element
1155  */
1156 struct xfrqe_prot_flags
1157 {
1158 	u8 flags;
1159 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK  0xF /* Protection log interval (9=512 10=1024  11=2048 12=4096 13=8192) */
1160 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
1161 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK             0x1 /* If DIF protection is configured against target (0=no, 1=yes) */
1162 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT            4
1163 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK          0x3 /* If DIF/DIX protection is configured against the host (0=none, 1=DIF, 2=DIX) */
1164 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT         5
1165 #define XFRQE_PROT_FLAGS_RESERVED_MASK                0x1 /* Must set to 0 */
1166 #define XFRQE_PROT_FLAGS_RESERVED_SHIFT               7
1167 };
1168 
1169 
1170 
1171 
1172 
1173 
1174 
1175 
1176 
1177 
1178 
1179 /*
1180  * FCoE doorbell data
1181  */
1182 struct fcoe_db_data
1183 {
1184 	u8 params;
1185 #define FCOE_DB_DATA_DEST_MASK         0x3 /* destination of doorbell (use enum db_dest) */
1186 #define FCOE_DB_DATA_DEST_SHIFT        0
1187 #define FCOE_DB_DATA_AGG_CMD_MASK      0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */
1188 #define FCOE_DB_DATA_AGG_CMD_SHIFT     2
1189 #define FCOE_DB_DATA_BYPASS_EN_MASK    0x1 /* enable QM bypass */
1190 #define FCOE_DB_DATA_BYPASS_EN_SHIFT   4
1191 #define FCOE_DB_DATA_RESERVED_MASK     0x1
1192 #define FCOE_DB_DATA_RESERVED_SHIFT    5
1193 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK  0x3 /* aggregative value selection */
1194 #define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
1195 	u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */;
1196 	__le16 sq_prod;
1197 };
1198 
1199 #endif /* __FCOE_COMMON__ */
1200