1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __FCOE_COMMON__ 32 #define __FCOE_COMMON__ 33 /*********************/ 34 /* FCOE FW CONSTANTS */ 35 /*********************/ 36 37 #define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12 38 39 40 41 42 43 /* 44 * fields coppied from ABTSrsp pckt 45 */ 46 struct fcoe_abts_pkt 47 { 48 __le32 abts_rsp_fc_payload_lo /* Abts flow: last 32 bits of fcPayload, out of 96 */; 49 __le16 abts_rsp_rx_id /* Abts flow: rxId parameter of the abts packet */; 50 u8 abts_rsp_rctl /* Abts flow: rctl parameter of the abts packet */; 51 u8 reserved2; 52 }; 53 54 55 /* 56 * FCoE additional WQE (Sq/ XferQ) information 57 */ 58 union fcoe_additional_info_union 59 { 60 __le32 previous_tid /* Previous tid. Used for Send XFER WQEs in Multiple continuation mode - Target only. */; 61 __le32 parent_tid /* Parent tid. Used for write tasks in a continuation mode - Target only */; 62 __le32 burst_length /* The desired burst length. */; 63 __le32 seq_rec_updated_offset /* The updated offset in SGL - Used in sequence recovery */; 64 }; 65 66 67 /* 68 * Cached data sges 69 */ 70 struct fcoe_exp_ro 71 { 72 __le32 data_offset /* data-offset */; 73 __le32 reserved /* High data-offset */; 74 }; 75 76 /* 77 * Union of Cleanup address \ expected relative offsets 78 */ 79 union fcoe_cleanup_addr_exp_ro_union 80 { 81 struct regpair abts_rsp_fc_payload_hi /* Abts flow: first 64 bits of fcPayload, out of 96 */; 82 struct fcoe_exp_ro exp_ro /* Expected relative offsets */; 83 }; 84 85 86 /* 87 * FCoE Ramrod Command IDs 88 */ 89 enum fcoe_completion_status 90 { 91 FCOE_COMPLETION_STATUS_SUCCESS /* FCoE ramrod completed successfully */, 92 FCOE_COMPLETION_STATUS_FCOE_VER_ERR /* Wrong FCoE version */, 93 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR /* src_mac_arr for the current physical port is full- allocation failed */, 94 MAX_FCOE_COMPLETION_STATUS 95 }; 96 97 98 /* 99 * FC address (SID/DID) network presentation 100 */ 101 struct fc_addr_nw 102 { 103 u8 addr_lo /* First byte of the SID/DID address that comes/goes from/to the NW (for example if SID is 11:22:33 - this is 0x11) */; 104 u8 addr_mid; 105 u8 addr_hi; 106 }; 107 108 /* 109 * FCoE connection offload 110 */ 111 struct fcoe_conn_offload_ramrod_data 112 { 113 struct regpair sq_pbl_addr /* SQ Pbl base address */; 114 struct regpair sq_curr_page_addr /* SQ current page address */; 115 struct regpair sq_next_page_addr /* SQ next page address */; 116 struct regpair xferq_pbl_addr /* XFERQ Pbl base address */; 117 struct regpair xferq_curr_page_addr /* XFERQ current page address */; 118 struct regpair xferq_next_page_addr /* XFERQ next page address */; 119 struct regpair respq_pbl_addr /* RESPQ Pbl base address */; 120 struct regpair respq_curr_page_addr /* RESPQ current page address */; 121 struct regpair respq_next_page_addr /* RESPQ next page address */; 122 __le16 dst_mac_addr_lo /* First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */; 123 __le16 dst_mac_addr_mid; 124 __le16 dst_mac_addr_hi; 125 __le16 src_mac_addr_lo /* Source MAC address in NW order - First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */; 126 __le16 src_mac_addr_mid; 127 __le16 src_mac_addr_hi; 128 __le16 tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */; 129 __le16 e_d_tov_timer_val /* E_D_TOV timeout value in resolution of 1 msec */; 130 __le16 rx_max_fc_pay_len /* Maximum acceptable FC payload size supported by us */; 131 __le16 vlan_tag; 132 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF /* Vlan id */ 133 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0 134 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1 /* Canonical format indicator */ 135 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12 136 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7 /* Vlan priority */ 137 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13 138 __le16 physical_q0 /* Physical QM queue to be linked to logical queue 0 (fastPath queue) */; 139 __le16 rec_rr_tov_timer_val /* REC_TOV timeout value in resolution of 1 msec */; 140 struct fc_addr_nw s_id /* Source ID in NW order, received during FLOGI */; 141 u8 max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by target, received during PLOGI */; 142 struct fc_addr_nw d_id /* Destination ID in NW order, received after inquiry of the fabric network */; 143 u8 flags; 144 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1 /* Continuously increasing SEQ_CNT indication, received during PLOGI */ 145 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0 146 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1 /* Confirmation request supported */ 147 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1 148 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1 /* REC allowed */ 149 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2 150 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1 /* Does inner vlan exist */ 151 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3 152 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3 /* indication for conn mode: 0=Initiator, 1=Target, 2=Both Initiator and Traget */ 153 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4 154 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3 155 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6 156 __le16 conn_id /* Drivers connection ID. Should be sent in EQs to speed-up drivers access to connection data. */; 157 u8 def_q_idx /* Default queue number to be used for unsolicited traffic */; 158 u8 reserved[5]; 159 }; 160 161 162 /* 163 * FCoE terminate connection request 164 */ 165 struct fcoe_conn_terminate_ramrod_data 166 { 167 struct regpair terminate_params_addr /* Terminate params ptr */; 168 }; 169 170 171 /* 172 * Data sgl 173 */ 174 struct fcoe_slow_sgl_ctx 175 { 176 struct regpair base_sgl_addr /* Address of first SGE in SGL */; 177 __le16 curr_sge_off /* Offset in current BD (in bytes) */; 178 __le16 remainder_num_sges /* Number of BDs */; 179 __le16 curr_sgl_index /* Index of current SGE */; 180 __le16 reserved; 181 }; 182 183 /* 184 * Union of DIX SGL \ cached DIX sges 185 */ 186 union fcoe_dix_desc_ctx 187 { 188 struct fcoe_slow_sgl_ctx dix_sgl /* DIX slow-SGL data base */; 189 struct scsi_sge cached_dix_sge /* Cached DIX sge */; 190 }; 191 192 193 194 /* 195 * Data sgl 196 */ 197 struct fcoe_fast_sgl_ctx 198 { 199 struct regpair sgl_start_addr /* Current sge address */; 200 __le32 sgl_byte_offset /* Byte offset from the beginning of the first page in the SGL. In case SGL starts in the middle of page then driver should init this value with the start offset */; 201 __le16 task_reuse_cnt /* The reuse count for that task. Wrap ion 4K value. */; 202 __le16 init_offset_in_first_sge /* offset from the beginning of the first page in the SGL, never changed by FW */; 203 }; 204 205 206 /* 207 * FCP CMD payload 208 */ 209 struct fcoe_fcp_cmd_payload 210 { 211 __le32 opaque[8] /* The FCP_CMD payload */; 212 }; 213 214 215 /* 216 * FCP RSP payload 217 */ 218 struct fcoe_fcp_rsp_payload 219 { 220 __le32 opaque[6] /* The FCP_RSP payload */; 221 }; 222 223 224 /* 225 * FCP RSP payload 226 */ 227 struct fcoe_fcp_xfer_payload 228 { 229 __le32 opaque[3] /* The FCP_XFER payload */; 230 }; 231 232 233 /* 234 * FCoE firmware function init 235 */ 236 struct fcoe_init_func_ramrod_data 237 { 238 struct scsi_init_func_params func_params /* Common SCSI init params passed by driver to FW in function init ramrod */; 239 struct scsi_init_func_queues q_params /* SCSI RQ/CQ/CMDQ firmware function init parameters */; 240 __le16 mtu /* Max transmission unit */; 241 __le16 sq_num_pages_in_pbl /* Number of pages at Send Queue */; 242 __le32 reserved; 243 }; 244 245 246 /* 247 * FCoE: Mode of the connection: Target or Initiator or both 248 */ 249 enum fcoe_mode_type 250 { 251 FCOE_INITIATOR_MODE=0x0, 252 FCOE_TARGET_MODE=0x1, 253 FCOE_BOTH_OR_NOT_CHOSEN=0x3, 254 MAX_FCOE_MODE_TYPE 255 }; 256 257 258 /* 259 * Per PF FCoE receive path statistics - tStorm RAM structure 260 */ 261 struct fcoe_rx_stat 262 { 263 struct regpair fcoe_rx_byte_cnt /* Number of FCoE bytes that were received */; 264 struct regpair fcoe_rx_data_pkt_cnt /* Number of FCoE FCP DATA packets that were received */; 265 struct regpair fcoe_rx_xfer_pkt_cnt /* Number of FCoE FCP XFER RDY packets that were received */; 266 struct regpair fcoe_rx_other_pkt_cnt /* Number of FCoE packets which are not DATA/XFER_RDY that were received */; 267 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt /* Number of packets that were silently dropped since CMDQ was full */; 268 __le32 fcoe_silent_drop_pkt_rq_full_cnt /* Number of packets that were silently dropped since RQ (BDQ) was full */; 269 __le32 fcoe_silent_drop_pkt_crc_error_cnt /* Number of packets that were silently dropped due to FC CRC error */; 270 __le32 fcoe_silent_drop_pkt_task_invalid_cnt /* Number of packets that were silently dropped since task was not valid */; 271 __le32 fcoe_silent_drop_total_pkt_cnt /* Number of FCoE packets that were silently dropped */; 272 __le32 rsrv; 273 }; 274 275 276 277 /* 278 * FCoe statistics request 279 */ 280 struct fcoe_stat_ramrod_data 281 { 282 struct regpair stat_params_addr /* Statistics host address */; 283 }; 284 285 286 /* 287 * The fcoe storm task context protection-information of Ystorm 288 */ 289 struct protection_info_ctx 290 { 291 __le16 flags; 292 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */ 293 #define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0 294 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1 /* 0=no, 1=yes */ 295 #define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2 296 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1 /* 0=no, 1=yes */ 297 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3 298 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 299 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4 300 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 /* 0=no, 1=yes */ 301 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8 302 #define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F 303 #define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9 304 u8 dix_block_size /* Source protection data size */; 305 u8 dst_size /* Destination protection data size */; 306 }; 307 308 /* 309 * The fcoe storm task context protection-information of Ystorm 310 */ 311 union protection_info_union_ctx 312 { 313 struct protection_info_ctx info; 314 __le32 value /* If and only if this field is not 0 then protection is set */; 315 }; 316 317 /* 318 * FCP RSP payload 319 */ 320 struct fcp_rsp_payload_padded 321 { 322 struct fcoe_fcp_rsp_payload rsp_payload /* The FCP_RSP payload */; 323 __le32 reserved[2]; 324 }; 325 326 /* 327 * FCP RSP payload 328 */ 329 struct fcp_xfer_payload_padded 330 { 331 struct fcoe_fcp_xfer_payload xfer_payload /* The FCP_XFER payload */; 332 __le32 reserved[5]; 333 }; 334 335 /* 336 * Task params 337 */ 338 struct fcoe_tx_data_params 339 { 340 __le32 data_offset /* Data offset */; 341 __le32 offset_in_io /* For sequence cleanup */; 342 u8 flags; 343 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1 /* Should we send offset in IO */ 344 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0 345 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1 /* Should the PBF drop this data */ 346 #define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1 347 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1 /* Indication if the task after seqqence recovery flow */ 348 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2 349 #define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F 350 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3 351 u8 dif_residual /* Residual from protection interval */; 352 __le16 seq_cnt /* Sequence counter */; 353 __le16 single_sge_saved_offset /* Saved SGE length for single SGE case */; 354 __le16 next_dif_offset /* Tracking next DIF offset in FC payload */; 355 __le16 seq_id /* Sequence ID (Set [saved] upon seq_cnt==0 (start of sequence) and used throughout sequence) */; 356 __le16 reserved3; 357 }; 358 359 /* 360 * Middle path parameters: FC header fields provided by the driver 361 */ 362 struct fcoe_tx_mid_path_params 363 { 364 __le32 parameter; 365 u8 r_ctl; 366 u8 type; 367 u8 cs_ctl; 368 u8 df_ctl; 369 __le16 rx_id; 370 __le16 ox_id; 371 }; 372 373 /* 374 * Task params 375 */ 376 struct fcoe_tx_params 377 { 378 struct fcoe_tx_data_params data /* Data offset */; 379 struct fcoe_tx_mid_path_params mid_path; 380 }; 381 382 /* 383 * Union of FCP CMD payload \ TX params \ ABTS \ Cleanup 384 */ 385 union fcoe_tx_info_union_ctx 386 { 387 struct fcoe_fcp_cmd_payload fcp_cmd_payload /* FCP CMD payload */; 388 struct fcp_rsp_payload_padded fcp_rsp_payload /* FCP RSP payload */; 389 struct fcp_xfer_payload_padded fcp_xfer_payload /* FCP XFER payload */; 390 struct fcoe_tx_params tx_params /* Task TX params */; 391 }; 392 393 /* 394 * The fcoe storm task context of Ystorm 395 */ 396 struct ystorm_fcoe_task_st_ctx 397 { 398 u8 task_type /* Task type. use enum fcoe_task_type */; 399 u8 sgl_mode; 400 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 /* use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 401 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0 402 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F 403 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1 404 u8 cached_dix_sge /* Dix sge is cached on task context */; 405 u8 expect_first_xfer /* Will let Ystorm know when it should initialize fcp_cmd_payload_params_union.params */; 406 __le32 num_pbf_zero_write /* The amount of bytes that PBF should dummy write - Relevant for protection only. */; 407 union protection_info_union_ctx protection_info_union /* Protection information */; 408 __le32 data_2_trns_rem /* Entire SGL-buffer remainder */; 409 struct scsi_sgl_params sgl_params; 410 u8 reserved1[12]; 411 union fcoe_tx_info_union_ctx tx_info_union /* Union of FCP CMD payload / TX params / ABTS / Cleanup */; 412 union fcoe_dix_desc_ctx dix_desc /* Union of DIX SGL / cached DIX sges */; 413 struct scsi_cached_sges data_desc /* Data cached SGEs */; 414 __le16 ox_id /* OX-ID. Used in Target mode only */; 415 __le16 rx_id /* RX-ID. Used in Target mode only */; 416 __le32 task_rety_identifier /* Parameter field of the FCP CMDs FC header */; 417 u8 reserved2[8]; 418 }; 419 420 struct e4_ystorm_fcoe_task_ag_ctx 421 { 422 u8 byte0 /* cdu_validation */; 423 u8 byte1 /* state */; 424 __le16 word0 /* icid */; 425 u8 flags0; 426 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 427 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 428 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 429 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 430 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 431 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 432 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 433 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 434 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 435 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 436 u8 flags1; 437 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 438 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 439 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 440 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 441 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 442 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 443 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 444 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 445 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 446 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 447 u8 flags2; 448 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 449 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 450 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 451 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 452 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 453 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 454 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 455 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 456 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 457 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 458 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 459 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 460 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 461 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 462 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 463 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 464 u8 byte2 /* byte2 */; 465 __le32 reg0 /* reg0 */; 466 u8 byte3 /* byte3 */; 467 u8 byte4 /* byte4 */; 468 __le16 rx_id /* word1 */; 469 __le16 word2 /* word2 */; 470 __le16 word3 /* word3 */; 471 __le16 word4 /* word4 */; 472 __le16 word5 /* word5 */; 473 __le32 reg1 /* reg1 */; 474 __le32 reg2 /* reg2 */; 475 }; 476 477 struct e4_tstorm_fcoe_task_ag_ctx 478 { 479 u8 reserved /* cdu_validation */; 480 u8 byte1 /* state */; 481 __le16 icid /* icid */; 482 u8 flags0; 483 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 484 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 485 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 486 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 487 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 488 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 489 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 /* bit2 */ 490 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 491 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 /* bit3 */ 492 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 493 u8 flags1; 494 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 /* bit4 */ 495 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 496 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 497 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 498 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */ 499 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 500 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */ 501 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 502 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 503 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 504 u8 flags2; 505 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 506 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 507 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */ 508 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 509 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */ 510 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 511 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */ 512 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 513 u8 flags3; 514 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */ 515 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 516 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 /* cf0en */ 517 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 518 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 /* cf1en */ 519 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 520 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 521 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 522 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 523 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 524 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf4en */ 525 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 526 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 /* cf5en */ 527 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 528 u8 flags4; 529 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 /* cf6en */ 530 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 531 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 /* cf7en */ 532 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 533 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 534 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 535 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 536 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 537 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 538 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 539 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 540 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 541 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 542 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 543 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 544 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 545 u8 cleanup_state /* byte2 */; 546 __le16 last_sent_tid /* word1 */; 547 __le32 rec_rr_tov_exp_timeout /* reg0 */; 548 u8 byte3 /* byte3 */; 549 u8 byte4 /* byte4 */; 550 __le16 word2 /* word2 */; 551 __le16 word3 /* word3 */; 552 __le16 word4 /* word4 */; 553 __le32 data_offset_end_of_seq /* reg1 */; 554 __le32 data_offset_next /* reg2 */; 555 }; 556 557 /* 558 * FW read- write (modifyable) part The fcoe task storm context of Tstorm 559 */ 560 struct fcoe_tstorm_fcoe_task_st_ctx_read_write 561 { 562 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union /* Union of Cleanup address / expected relative offsets */; 563 __le16 flags; 564 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1 /* Rx SGL type. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 565 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0 566 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1 /* Expected first frame flag */ 567 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1 568 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1 /* Sequence active */ 569 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2 570 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1 /* Sequence timeout for an active Sequence */ 571 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3 572 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1 /* Set by Data-in flow. Indicate that this exchange contains a single FCP DATA packet */ 573 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4 574 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1 /* The status of the current out of order received Sequence */ 575 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5 576 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3 /* number of additional CQE that will be produced for this task completion */ 577 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6 578 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF 579 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8 580 __le16 seq_cnt /* Sequence counter */; 581 u8 seq_id /* Sequence id */; 582 u8 ooo_rx_seq_id /* The last out of order received SEQ_ID */; 583 __le16 rx_id /* RX_ID of the exchange - should match each packet expect for the first */; 584 struct fcoe_abts_pkt abts_data /* The last out of order received SEQ_CNT */; 585 __le32 e_d_tov_exp_timeout_val /* E_D_TOV timer val (in msec) */; 586 __le16 ooo_rx_seq_cnt /* The last out of order received SEQ_CNT */; 587 __le16 reserved1; 588 }; 589 590 /* 591 * FW read only part The fcoe task storm context of Tstorm 592 */ 593 struct fcoe_tstorm_fcoe_task_st_ctx_read_only 594 { 595 u8 task_type /* Task type. use enum fcoe_task_type */; 596 u8 dev_type /* Device type (disk or tape). use enum fcoe_device_type */; 597 u8 conf_supported /* Confirmation supported indication */; 598 u8 glbl_q_num /* Global RQ/CQ num to be used for sense data placement/completion */; 599 __le32 cid /* CID which that tasks associated to */; 600 __le32 fcp_cmd_trns_size /* IO size as reflected in FCP CMD */; 601 __le32 rsrv; 602 }; 603 604 /* 605 * The fcoe task storm context of Tstorm 606 */ 607 struct tstorm_fcoe_task_st_ctx 608 { 609 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write /* FW read- write (modifyable) part The fcoe task storm context of Tstorm */; 610 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only /* FW read only part The fcoe task storm context of Tstorm */; 611 }; 612 613 struct e4_mstorm_fcoe_task_ag_ctx 614 { 615 u8 byte0 /* cdu_validation */; 616 u8 byte1 /* state */; 617 __le16 icid /* icid */; 618 u8 flags0; 619 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 620 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 621 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 622 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 623 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 /* exist_in_qm1 */ 624 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 625 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 626 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 627 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 628 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 629 u8 flags1; 630 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */ 631 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 632 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 633 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 634 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 635 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 636 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf0en */ 637 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 638 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 639 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 640 u8 flags2; 641 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 642 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 643 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 644 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 645 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 646 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 647 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 648 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 649 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 650 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 651 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 652 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 653 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 /* rule5en */ 654 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 655 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 656 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 657 u8 cleanup_state /* byte2 */; 658 __le32 received_bytes /* reg0 */; 659 u8 byte3 /* byte3 */; 660 u8 glbl_q_num /* byte4 */; 661 __le16 word1 /* word1 */; 662 __le16 tid_to_xfer /* word2 */; 663 __le16 word3 /* word3 */; 664 __le16 word4 /* word4 */; 665 __le16 word5 /* word5 */; 666 __le32 expected_bytes /* reg1 */; 667 __le32 reg2 /* reg2 */; 668 }; 669 670 /* 671 * The fcoe task storm context of Mstorm 672 */ 673 struct mstorm_fcoe_task_st_ctx 674 { 675 struct regpair rsp_buf_addr /* Buffer to place the sense/response data attached to FCP_RSP frame */; 676 __le32 rsrv[2]; 677 struct scsi_sgl_params sgl_params; 678 __le32 data_2_trns_rem /* Entire SGL buffer size remainder */; 679 __le32 data_buffer_offset /* Buffer offset */; 680 __le16 parent_id /* Used for multiple continuation in Target mode */; 681 __le16 flags; 682 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 683 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0 684 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */ 685 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4 686 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1 /* 0=no, 1=yes */ 687 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6 688 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1 /* 0 = 24 Bytes FC Header not included in Middle-Path placement, 1 = 24 Bytes FC Header included in MP placement */ 689 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7 690 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3 /* DIX block size: can be 0:2B, 1:4B, 2:8B */ 691 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8 692 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 /* 0=no, 1=yes */ 693 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10 694 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1 /* Indication to a single cached DIX SGE instead of SGL */ 695 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11 696 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1 697 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12 698 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 /* use_enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 699 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13 700 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3 701 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14 702 struct scsi_cached_sges data_desc /* Union of Data SGL / cached sge */; 703 }; 704 705 struct e4_ustorm_fcoe_task_ag_ctx 706 { 707 u8 reserved /* cdu_validation */; 708 u8 byte1 /* state */; 709 __le16 icid /* icid */; 710 u8 flags0; 711 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 712 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 713 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 714 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 715 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 716 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 717 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 718 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 719 u8 flags1; 720 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 721 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 722 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 723 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 724 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 725 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 726 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */ 727 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 728 u8 flags2; 729 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 730 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 731 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 732 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 733 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 734 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 735 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 736 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 737 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 738 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 739 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 740 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 741 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 742 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 743 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 744 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 745 u8 flags3; 746 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 747 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 748 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 749 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 750 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 751 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 752 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 753 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 754 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */ 755 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 756 __le32 dif_err_intervals /* reg0 */; 757 __le32 dif_error_1st_interval /* reg1 */; 758 __le32 global_cq_num /* reg2 */; 759 __le32 reg3 /* reg3 */; 760 __le32 reg4 /* reg4 */; 761 __le32 reg5 /* reg5 */; 762 }; 763 764 /* 765 * fcoe task context 766 */ 767 struct fcoe_task_context 768 { 769 struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */; 770 struct regpair ystorm_st_padding[2] /* padding */; 771 struct tdif_task_context tdif_context /* tdif context */; 772 struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 773 struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 774 struct timers_context timer_context /* timer context */; 775 struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */; 776 struct regpair tstorm_st_padding[2] /* padding */; 777 struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 778 struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */; 779 struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 780 struct rdif_task_context rdif_context /* rdif context */; 781 }; 782 783 784 785 786 787 788 789 790 /* 791 * Per PF FCoE transmit path statistics - pStorm RAM structure 792 */ 793 struct fcoe_tx_stat 794 { 795 struct regpair fcoe_tx_byte_cnt /* Transmitted FCoE bytes count */; 796 struct regpair fcoe_tx_data_pkt_cnt /* Transmitted FCoE FCP DATA packets count */; 797 struct regpair fcoe_tx_xfer_pkt_cnt /* Transmitted FCoE XFER_RDY packets count */; 798 struct regpair fcoe_tx_other_pkt_cnt /* Transmitted FCoE packets which are not DATA/XFER_RDY count */; 799 }; 800 801 802 /* 803 * FCoE SQ/XferQ element 804 */ 805 struct fcoe_wqe 806 { 807 __le16 task_id /* Initiator - The task identifier (OX_ID). Target - Continuation tid or RX_ID in non-continuation mode */; 808 __le16 flags; 809 #define FCOE_WQE_REQ_TYPE_MASK 0xF /* Type of the wqe request. use enum fcoe_sqe_request_type (use enum fcoe_sqe_request_type) */ 810 #define FCOE_WQE_REQ_TYPE_SHIFT 0 811 #define FCOE_WQE_SGL_MODE_MASK 0x1 /* The driver will give a hint about sizes of SGEs for better credits evaluation at Xstorm. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 812 #define FCOE_WQE_SGL_MODE_SHIFT 4 813 #define FCOE_WQE_CONTINUATION_MASK 0x1 /* Indication if this wqe is a continuation to an existing task (Target only) */ 814 #define FCOE_WQE_CONTINUATION_SHIFT 5 815 #define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1 /* Indication to FW to send FCP_RSP after all data was sent - Target only */ 816 #define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6 817 #define FCOE_WQE_RESERVED_MASK 0x1 818 #define FCOE_WQE_RESERVED_SHIFT 7 819 #define FCOE_WQE_NUM_SGES_MASK 0xF /* Number of SGEs. 8 = at least 8 sges */ 820 #define FCOE_WQE_NUM_SGES_SHIFT 8 821 #define FCOE_WQE_RESERVED1_MASK 0xF 822 #define FCOE_WQE_RESERVED1_SHIFT 12 823 union fcoe_additional_info_union additional_info_union /* Additional wqe information (if needed) */; 824 }; 825 826 827 828 829 830 831 832 833 834 /* 835 * FCoE XFRQ element 836 */ 837 struct xfrqe_prot_flags 838 { 839 u8 flags; 840 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 841 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0 842 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1 /* If DIF protection is configured against target (0=no, 1=yes) */ 843 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4 844 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3 /* If DIF/DIX protection is configured against the host (0=none, 1=DIF, 2=DIX) */ 845 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5 846 #define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1 /* Must set to 0 */ 847 #define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7 848 }; 849 850 851 852 853 854 855 856 struct e5_mstorm_fcoe_task_ag_ctx 857 { 858 u8 byte0 /* cdu_validation */; 859 u8 byte1 /* state_and_core_id */; 860 __le16 icid /* icid */; 861 u8 flags0; 862 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 863 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 864 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 865 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 866 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 /* exist_in_qm1 */ 867 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 868 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 869 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 870 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 871 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 872 u8 flags1; 873 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */ 874 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 875 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 876 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 877 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 878 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 879 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf0en */ 880 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 881 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 882 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 883 u8 flags2; 884 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 885 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 886 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 887 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 888 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 889 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 890 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 891 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 892 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 893 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 894 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 895 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 896 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 /* rule5en */ 897 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 898 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 899 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 900 u8 flags3; 901 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */ 902 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 903 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 904 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 905 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 906 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 907 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 908 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 909 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 910 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 911 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 912 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 913 __le32 received_bytes /* reg0 */; 914 u8 cleanup_state /* byte2 */; 915 u8 byte3 /* byte3 */; 916 u8 glbl_q_num /* byte4 */; 917 u8 e4_reserved7 /* byte5 */; 918 __le16 word1 /* regpair0 */; 919 __le16 tid_to_xfer /* word2 */; 920 __le16 word3 /* word3 */; 921 __le16 word4 /* word4 */; 922 __le16 word5 /* regpair1 */; 923 __le16 e4_reserved8 /* word6 */; 924 __le32 expected_bytes /* reg1 */; 925 }; 926 927 928 struct e5_tstorm_fcoe_task_ag_ctx 929 { 930 u8 reserved /* cdu_validation */; 931 u8 byte1 /* state_and_core_id */; 932 __le16 icid /* icid */; 933 u8 flags0; 934 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 935 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 936 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 937 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 938 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 939 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 940 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 /* bit2 */ 941 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 942 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 /* bit3 */ 943 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 944 u8 flags1; 945 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 /* bit4 */ 946 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 947 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 948 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 949 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */ 950 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 951 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */ 952 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 953 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 954 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 955 u8 flags2; 956 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 957 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 958 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */ 959 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 960 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */ 961 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 962 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */ 963 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 964 u8 flags3; 965 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */ 966 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 967 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 /* cf0en */ 968 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 969 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 /* cf1en */ 970 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 971 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 972 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 973 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 974 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 975 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf4en */ 976 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 977 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 /* cf5en */ 978 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 979 u8 flags4; 980 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 /* cf6en */ 981 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 982 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 /* cf7en */ 983 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 984 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 985 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 986 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 987 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 988 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 989 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 990 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 991 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 992 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 993 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 994 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 995 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 996 u8 cleanup_state /* byte2 */; 997 __le16 last_sent_tid /* word1 */; 998 __le32 rec_rr_tov_exp_timeout /* reg0 */; 999 u8 byte3 /* regpair0 */; 1000 u8 byte4 /* byte4 */; 1001 __le16 word2 /* word2 */; 1002 __le16 word3 /* word3 */; 1003 __le16 word4 /* word4 */; 1004 __le32 data_offset_end_of_seq /* regpair1 */; 1005 __le32 data_offset_next /* reg2 */; 1006 }; 1007 1008 1009 struct e5_ustorm_fcoe_task_ag_ctx 1010 { 1011 u8 reserved /* cdu_validation */; 1012 u8 byte1 /* state_and_core_id */; 1013 __le16 icid /* icid */; 1014 u8 flags0; 1015 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 1016 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 1017 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1018 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 1019 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1020 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 1021 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1022 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 1023 u8 flags1; 1024 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1025 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 1026 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1027 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 1028 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1029 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 1030 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */ 1031 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 1032 u8 flags2; 1033 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1034 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 1035 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1036 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 1037 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1038 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 1039 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1040 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 1041 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 1042 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 1043 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1044 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 1045 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1046 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 1047 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1048 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 1049 u8 flags3; 1050 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1051 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 1052 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1053 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 1054 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1055 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 1056 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1057 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 1058 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1059 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 4 1060 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1061 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 5 1062 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */ 1063 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 6 1064 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */ 1065 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 7 1066 u8 flags4; 1067 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */ 1068 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 0 1069 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */ 1070 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 2 1071 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */ 1072 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_SHIFT 3 1073 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */ 1074 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 1075 u8 byte2 /* byte2 */; 1076 u8 byte3 /* byte3 */; 1077 u8 e4_reserved8 /* byte4 */; 1078 __le32 dif_err_intervals /* dif_err_intervals */; 1079 __le32 dif_error_1st_interval /* dif_error_1st_interval */; 1080 __le32 global_cq_num /* reg2 */; 1081 __le32 reg3 /* reg3 */; 1082 __le32 reg4 /* reg4 */; 1083 }; 1084 1085 1086 struct e5_ystorm_fcoe_task_ag_ctx 1087 { 1088 u8 byte0 /* cdu_validation */; 1089 u8 byte1 /* state_and_core_id */; 1090 __le16 word0 /* icid */; 1091 u8 flags0; 1092 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1093 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 1094 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1095 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 1096 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1097 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 1098 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1099 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 1100 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1101 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 1102 u8 flags1; 1103 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1104 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 1105 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1106 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 1107 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 1108 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 1109 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1110 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 1111 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1112 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 1113 u8 flags2; 1114 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1115 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 1116 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1117 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 1118 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1119 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 1120 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1121 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 1122 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1123 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 1124 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1125 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 1126 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1127 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 1128 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1129 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 1130 u8 flags3; 1131 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */ 1132 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 1133 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 1134 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 1135 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 1136 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 1137 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 1138 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 1139 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 1140 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 1141 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 1142 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 1143 __le32 reg0 /* reg0 */; 1144 u8 byte2 /* byte2 */; 1145 u8 byte3 /* byte3 */; 1146 u8 byte4 /* byte4 */; 1147 u8 e4_reserved7 /* byte5 */; 1148 __le16 rx_id /* word1 */; 1149 __le16 word2 /* word2 */; 1150 __le16 word3 /* word3 */; 1151 __le16 word4 /* word4 */; 1152 __le16 word5 /* word5 */; 1153 __le16 e4_reserved8 /* word6 */; 1154 __le32 reg1 /* reg1 */; 1155 }; 1156 1157 1158 /* 1159 * FCoE doorbell data 1160 */ 1161 struct fcoe_db_data 1162 { 1163 u8 params; 1164 #define FCOE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 1165 #define FCOE_DB_DATA_DEST_SHIFT 0 1166 #define FCOE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 1167 #define FCOE_DB_DATA_AGG_CMD_SHIFT 2 1168 #define FCOE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 1169 #define FCOE_DB_DATA_BYPASS_EN_SHIFT 4 1170 #define FCOE_DB_DATA_RESERVED_MASK 0x1 1171 #define FCOE_DB_DATA_RESERVED_SHIFT 5 1172 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 1173 #define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6 1174 u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 1175 __le16 sq_prod; 1176 }; 1177 1178 #endif /* __FCOE_COMMON__ */ 1179