1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __FCOE_COMMON__ 32 #define __FCOE_COMMON__ 33 /*********************/ 34 /* FCOE FW CONSTANTS */ 35 /*********************/ 36 37 #define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12 38 39 /* 40 * The fcoe storm task context protection-information of Ystorm 41 */ 42 struct protection_info_ctx 43 { 44 __le16 flags; 45 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */ 46 #define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0 47 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1 /* 0=no, 1=yes */ 48 #define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2 49 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1 /* 0=no, 1=yes */ 50 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3 51 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 52 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4 53 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 /* 0=no, 1=yes */ 54 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8 55 #define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F 56 #define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9 57 u8 dix_block_size /* Source protection data size */; 58 u8 dst_size /* Destination protection data size */; 59 }; 60 61 /* 62 * The fcoe storm task context protection-information of Ystorm 63 */ 64 union protection_info_union_ctx 65 { 66 struct protection_info_ctx info; 67 __le32 value /* If and only if this field is not 0 then protection is set */; 68 }; 69 70 /* 71 * FCP CMD payload 72 */ 73 struct fcoe_fcp_cmd_payload 74 { 75 __le32 opaque[8] /* The FCP_CMD payload */; 76 }; 77 78 /* 79 * FCP RSP payload 80 */ 81 struct fcoe_fcp_rsp_payload 82 { 83 __le32 opaque[6] /* The FCP_RSP payload */; 84 }; 85 86 /* 87 * FCP RSP payload 88 */ 89 struct fcp_rsp_payload_padded 90 { 91 struct fcoe_fcp_rsp_payload rsp_payload /* The FCP_RSP payload */; 92 __le32 reserved[2]; 93 }; 94 95 /* 96 * FCP RSP payload 97 */ 98 struct fcoe_fcp_xfer_payload 99 { 100 __le32 opaque[3] /* The FCP_XFER payload */; 101 }; 102 103 /* 104 * FCP RSP payload 105 */ 106 struct fcp_xfer_payload_padded 107 { 108 struct fcoe_fcp_xfer_payload xfer_payload /* The FCP_XFER payload */; 109 __le32 reserved[5]; 110 }; 111 112 /* 113 * Task params 114 */ 115 struct fcoe_tx_data_params 116 { 117 __le32 data_offset /* Data offset */; 118 __le32 offset_in_io /* For sequence cleanup */; 119 u8 flags; 120 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1 /* Should we send offset in IO */ 121 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0 122 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1 /* Should the PBF drop this data */ 123 #define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1 124 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1 /* Indication if the task after seqqence recovery flow */ 125 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2 126 #define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F 127 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3 128 u8 dif_residual /* Residual from protection interval */; 129 __le16 seq_cnt /* Sequence counter */; 130 __le16 single_sge_saved_offset /* Saved SGE length for single SGE case */; 131 __le16 next_dif_offset /* Tracking next DIF offset in FC payload */; 132 __le16 seq_id /* Sequence ID (Set [saved] upon seq_cnt==0 (start of sequence) and used throughout sequence) */; 133 __le16 reserved3; 134 }; 135 136 /* 137 * Middle path parameters: FC header fields provided by the driver 138 */ 139 struct fcoe_tx_mid_path_params 140 { 141 __le32 parameter; 142 u8 r_ctl; 143 u8 type; 144 u8 cs_ctl; 145 u8 df_ctl; 146 __le16 rx_id; 147 __le16 ox_id; 148 }; 149 150 /* 151 * Task params 152 */ 153 struct fcoe_tx_params 154 { 155 struct fcoe_tx_data_params data /* Data offset */; 156 struct fcoe_tx_mid_path_params mid_path; 157 }; 158 159 /* 160 * Union of FCP CMD payload \ TX params \ ABTS \ Cleanup 161 */ 162 union fcoe_tx_info_union_ctx 163 { 164 struct fcoe_fcp_cmd_payload fcp_cmd_payload /* FCP CMD payload */; 165 struct fcp_rsp_payload_padded fcp_rsp_payload /* FCP RSP payload */; 166 struct fcp_xfer_payload_padded fcp_xfer_payload /* FCP XFER payload */; 167 struct fcoe_tx_params tx_params /* Task TX params */; 168 }; 169 170 /* 171 * Data sgl 172 */ 173 struct fcoe_slow_sgl_ctx 174 { 175 struct regpair base_sgl_addr /* Address of first SGE in SGL */; 176 __le16 curr_sge_off /* Offset in current BD (in bytes) */; 177 __le16 remainder_num_sges /* Number of BDs */; 178 __le16 curr_sgl_index /* Index of current SGE */; 179 __le16 reserved; 180 }; 181 182 /* 183 * Union of DIX SGL \ cached DIX sges 184 */ 185 union fcoe_dix_desc_ctx 186 { 187 struct fcoe_slow_sgl_ctx dix_sgl /* DIX slow-SGL data base */; 188 struct scsi_sge cached_dix_sge /* Cached DIX sge */; 189 }; 190 191 /* 192 * The fcoe storm task context of Ystorm 193 */ 194 struct ystorm_fcoe_task_st_ctx 195 { 196 u8 task_type /* Task type. use enum fcoe_task_type (use enum fcoe_task_type) */; 197 u8 sgl_mode; 198 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 /* use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 199 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0 200 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F 201 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1 202 u8 cached_dix_sge /* Dix sge is cached on task context */; 203 u8 expect_first_xfer /* Will let Ystorm know when it should initialize fcp_cmd_payload_params_union.params */; 204 __le32 num_pbf_zero_write /* The amount of bytes that PBF should dummy write - Relevant for protection only. */; 205 union protection_info_union_ctx protection_info_union /* Protection information */; 206 __le32 data_2_trns_rem /* Entire SGL-buffer remainder */; 207 struct scsi_sgl_params sgl_params; 208 u8 reserved1[12]; 209 union fcoe_tx_info_union_ctx tx_info_union /* Union of FCP CMD payload / TX params / ABTS / Cleanup */; 210 union fcoe_dix_desc_ctx dix_desc /* Union of DIX SGL / cached DIX sges */; 211 struct scsi_cached_sges data_desc /* Data cached SGEs */; 212 __le16 ox_id /* OX-ID. Used in Target mode only */; 213 __le16 rx_id /* RX-ID. Used in Target mode only */; 214 __le32 task_rety_identifier /* Parameter field of the FCP CMDs FC header */; 215 u8 reserved2[8]; 216 }; 217 218 struct e4_ystorm_fcoe_task_ag_ctx 219 { 220 u8 byte0 /* cdu_validation */; 221 u8 byte1 /* state */; 222 __le16 word0 /* icid */; 223 u8 flags0; 224 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 225 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 226 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 227 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 228 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 229 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 230 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 231 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 232 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 233 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 234 u8 flags1; 235 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 236 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 237 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 238 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 239 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 240 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 241 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 242 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 243 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 244 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 245 u8 flags2; 246 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 247 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 248 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 249 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 250 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 251 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 252 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 253 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 254 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 255 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 256 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 257 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 258 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 259 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 260 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 261 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 262 u8 byte2 /* byte2 */; 263 __le32 reg0 /* reg0 */; 264 u8 byte3 /* byte3 */; 265 u8 byte4 /* byte4 */; 266 __le16 rx_id /* word1 */; 267 __le16 word2 /* word2 */; 268 __le16 word3 /* word3 */; 269 __le16 word4 /* word4 */; 270 __le16 word5 /* word5 */; 271 __le32 reg1 /* reg1 */; 272 __le32 reg2 /* reg2 */; 273 }; 274 275 struct e4_tstorm_fcoe_task_ag_ctx 276 { 277 u8 reserved /* cdu_validation */; 278 u8 byte1 /* state */; 279 __le16 icid /* icid */; 280 u8 flags0; 281 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 282 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 283 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 284 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 285 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 286 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 287 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 /* bit2 */ 288 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 289 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 /* bit3 */ 290 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 291 u8 flags1; 292 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 /* bit4 */ 293 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 294 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 295 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 296 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */ 297 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 298 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */ 299 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 300 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 301 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 302 u8 flags2; 303 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 304 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 305 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */ 306 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 307 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */ 308 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 309 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */ 310 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 311 u8 flags3; 312 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */ 313 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 314 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 /* cf0en */ 315 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 316 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 /* cf1en */ 317 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 318 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 319 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 320 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 321 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 322 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf4en */ 323 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 324 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 /* cf5en */ 325 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 326 u8 flags4; 327 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 /* cf6en */ 328 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 329 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 /* cf7en */ 330 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 331 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 332 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 333 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 334 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 335 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 336 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 337 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 338 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 339 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 340 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 341 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 342 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 343 u8 cleanup_state /* byte2 */; 344 __le16 last_sent_tid /* word1 */; 345 __le32 rec_rr_tov_exp_timeout /* reg0 */; 346 u8 byte3 /* byte3 */; 347 u8 byte4 /* byte4 */; 348 __le16 word2 /* word2 */; 349 __le16 word3 /* word3 */; 350 __le16 word4 /* word4 */; 351 __le32 data_offset_end_of_seq /* reg1 */; 352 __le32 data_offset_next /* reg2 */; 353 }; 354 355 /* 356 * Cached data sges 357 */ 358 struct fcoe_exp_ro 359 { 360 __le32 data_offset /* data-offset */; 361 __le32 reserved /* High data-offset */; 362 }; 363 364 /* 365 * Union of Cleanup address \ expected relative offsets 366 */ 367 union fcoe_cleanup_addr_exp_ro_union 368 { 369 struct regpair abts_rsp_fc_payload_hi /* Abts flow: first 64 bits of fcPayload, out of 96 */; 370 struct fcoe_exp_ro exp_ro /* Expected relative offsets */; 371 }; 372 373 /* 374 * fields coppied from ABTSrsp pckt 375 */ 376 struct fcoe_abts_pkt 377 { 378 __le32 abts_rsp_fc_payload_lo /* Abts flow: last 32 bits of fcPayload, out of 96 */; 379 __le16 abts_rsp_rx_id /* Abts flow: rxId parameter of the abts packet */; 380 u8 abts_rsp_rctl /* Abts flow: rctl parameter of the abts packet */; 381 u8 reserved2; 382 }; 383 384 /* 385 * FW read- write (modifyable) part The fcoe task storm context of Tstorm 386 */ 387 struct fcoe_tstorm_fcoe_task_st_ctx_read_write 388 { 389 union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union /* Union of Cleanup address / expected relative offsets */; 390 __le16 flags; 391 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1 /* Rx SGL type. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 392 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0 393 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1 /* Expected first frame flag */ 394 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1 395 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1 /* Sequence active */ 396 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2 397 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1 /* Sequence timeout for an active Sequence */ 398 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3 399 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1 /* Set by Data-in flow. Indicate that this exchange contains a single FCP DATA packet */ 400 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4 401 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1 /* The status of the current out of order received Sequence */ 402 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5 403 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3 /* number of additional CQE that will be produced for this task completion */ 404 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6 405 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF 406 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8 407 __le16 seq_cnt /* Sequence counter */; 408 u8 seq_id /* Sequence id */; 409 u8 ooo_rx_seq_id /* The last out of order received SEQ_ID */; 410 __le16 rx_id /* RX_ID of the exchange - should match each packet expect for the first */; 411 struct fcoe_abts_pkt abts_data /* The last out of order received SEQ_CNT */; 412 __le32 e_d_tov_exp_timeout_val /* E_D_TOV timer val (in msec) */; 413 __le16 ooo_rx_seq_cnt /* The last out of order received SEQ_CNT */; 414 __le16 reserved1; 415 }; 416 417 /* 418 * FW read only part The fcoe task storm context of Tstorm 419 */ 420 struct fcoe_tstorm_fcoe_task_st_ctx_read_only 421 { 422 u8 task_type /* Task type. use enum fcoe_task_type (use enum fcoe_task_type) */; 423 u8 dev_type /* Device type (disk or tape). use enum fcoe_device_type (use enum fcoe_device_type) */; 424 u8 conf_supported /* Confirmation supported indication */; 425 u8 glbl_q_num /* Global RQ/CQ num to be used for sense data placement/completion */; 426 __le32 cid /* CID which that tasks associated to */; 427 __le32 fcp_cmd_trns_size /* IO size as reflected in FCP CMD */; 428 __le32 rsrv; 429 }; 430 431 /* 432 * The fcoe task storm context of Tstorm 433 */ 434 struct tstorm_fcoe_task_st_ctx 435 { 436 struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write /* FW read- write (modifyable) part The fcoe task storm context of Tstorm */; 437 struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only /* FW read only part The fcoe task storm context of Tstorm */; 438 }; 439 440 struct e4_mstorm_fcoe_task_ag_ctx 441 { 442 u8 byte0 /* cdu_validation */; 443 u8 byte1 /* state */; 444 __le16 icid /* icid */; 445 u8 flags0; 446 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 447 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 448 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 449 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 450 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 /* exist_in_qm1 */ 451 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 452 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 453 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 454 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 455 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 456 u8 flags1; 457 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */ 458 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 459 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 460 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 461 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 462 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 463 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf0en */ 464 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 465 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 466 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 467 u8 flags2; 468 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 469 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 470 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 471 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 472 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 473 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 474 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 475 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 476 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 477 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 478 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 479 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 480 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 /* rule5en */ 481 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 482 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 483 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 484 u8 cleanup_state /* byte2 */; 485 __le32 received_bytes /* reg0 */; 486 u8 byte3 /* byte3 */; 487 u8 glbl_q_num /* byte4 */; 488 __le16 word1 /* word1 */; 489 __le16 tid_to_xfer /* word2 */; 490 __le16 word3 /* word3 */; 491 __le16 word4 /* word4 */; 492 __le16 word5 /* word5 */; 493 __le32 expected_bytes /* reg1 */; 494 __le32 reg2 /* reg2 */; 495 }; 496 497 /* 498 * The fcoe task storm context of Mstorm 499 */ 500 struct mstorm_fcoe_task_st_ctx 501 { 502 struct regpair rsp_buf_addr /* Buffer to place the sense/response data attached to FCP_RSP frame */; 503 __le32 rsrv[2]; 504 struct scsi_sgl_params sgl_params; 505 __le32 data_2_trns_rem /* Entire SGL buffer size remainder */; 506 __le32 data_buffer_offset /* Buffer offset */; 507 __le16 parent_id /* Used for multiple continuation in Target mode */; 508 __le16 flags; 509 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 510 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0 511 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */ 512 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4 513 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1 /* 0=no, 1=yes */ 514 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6 515 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1 /* 0 = 24 Bytes FC Header not included in Middle-Path placement, 1 = 24 Bytes FC Header included in MP placement */ 516 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7 517 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3 /* DIX block size: can be 0:2B, 1:4B, 2:8B */ 518 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8 519 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 /* 0=no, 1=yes */ 520 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10 521 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1 /* Indication to a single cached DIX SGE instead of SGL */ 522 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11 523 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1 524 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12 525 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 /* use_enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 526 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13 527 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3 528 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14 529 struct scsi_cached_sges data_desc /* Union of Data SGL / cached sge */; 530 }; 531 532 struct e4_ustorm_fcoe_task_ag_ctx 533 { 534 u8 reserved /* cdu_validation */; 535 u8 byte1 /* state */; 536 __le16 icid /* icid */; 537 u8 flags0; 538 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 539 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 540 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 541 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 542 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 543 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 544 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 545 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 546 u8 flags1; 547 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 548 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 549 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 550 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 551 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 552 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 553 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */ 554 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 555 u8 flags2; 556 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 557 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 558 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 559 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 560 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 561 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 562 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 563 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 564 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 565 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 566 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 567 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 568 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 569 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 570 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 571 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 572 u8 flags3; 573 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 574 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 575 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 576 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 577 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 578 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 579 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 580 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 581 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */ 582 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 583 __le32 dif_err_intervals /* reg0 */; 584 __le32 dif_error_1st_interval /* reg1 */; 585 __le32 global_cq_num /* reg2 */; 586 __le32 reg3 /* reg3 */; 587 __le32 reg4 /* reg4 */; 588 __le32 reg5 /* reg5 */; 589 }; 590 591 /* 592 * fcoe task context 593 */ 594 struct e4_fcoe_task_context 595 { 596 struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */; 597 struct regpair ystorm_st_padding[2] /* padding */; 598 struct tdif_task_context tdif_context /* tdif context */; 599 struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 600 struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 601 struct timers_context timer_context /* timer context */; 602 struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */; 603 struct regpair tstorm_st_padding[2] /* padding */; 604 struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 605 struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */; 606 struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 607 struct rdif_task_context rdif_context /* rdif context */; 608 }; 609 610 struct e5_ystorm_fcoe_task_ag_ctx 611 { 612 u8 byte0 /* cdu_validation */; 613 u8 byte1 /* state_and_core_id */; 614 __le16 word0 /* icid */; 615 u8 flags0; 616 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 617 #define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 618 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 619 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 620 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 621 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 622 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 623 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 624 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 625 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 626 u8 flags1; 627 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 628 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 629 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 630 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 631 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 632 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 633 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 634 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 635 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 636 #define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 637 u8 flags2; 638 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 639 #define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 640 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 641 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 642 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 643 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 644 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 645 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 646 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 647 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 648 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 649 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 650 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 651 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 652 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 653 #define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 654 u8 flags3; 655 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */ 656 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 657 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 658 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 659 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 660 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 661 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 662 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 663 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 664 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 665 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 666 #define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 667 __le32 reg0 /* reg0 */; 668 u8 byte2 /* byte2 */; 669 u8 byte3 /* byte3 */; 670 u8 byte4 /* byte4 */; 671 u8 e4_reserved7 /* byte5 */; 672 __le16 rx_id /* word1 */; 673 __le16 word2 /* word2 */; 674 __le16 word3 /* word3 */; 675 __le16 word4 /* word4 */; 676 __le16 word5 /* word5 */; 677 __le16 e4_reserved8 /* word6 */; 678 __le32 reg1 /* reg1 */; 679 }; 680 681 struct e5_tstorm_fcoe_task_ag_ctx 682 { 683 u8 reserved /* cdu_validation */; 684 u8 byte1 /* state_and_core_id */; 685 __le16 icid /* icid */; 686 u8 flags0; 687 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 688 #define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 689 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 690 #define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 691 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 692 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 693 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 /* bit2 */ 694 #define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 695 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 /* bit3 */ 696 #define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 697 u8 flags1; 698 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 /* bit4 */ 699 #define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 700 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 701 #define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 702 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */ 703 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 704 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */ 705 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 706 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 707 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 708 u8 flags2; 709 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 710 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 711 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */ 712 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 713 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */ 714 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 715 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */ 716 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 717 u8 flags3; 718 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */ 719 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 720 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 /* cf0en */ 721 #define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 722 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 /* cf1en */ 723 #define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 724 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 725 #define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 726 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 727 #define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 728 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf4en */ 729 #define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 730 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 /* cf5en */ 731 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 732 u8 flags4; 733 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 /* cf6en */ 734 #define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 735 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 /* cf7en */ 736 #define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 737 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 738 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 739 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 740 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 741 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 742 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 743 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 744 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 745 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 746 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 747 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 748 #define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 749 u8 cleanup_state /* byte2 */; 750 __le16 last_sent_tid /* word1 */; 751 __le32 rec_rr_tov_exp_timeout /* reg0 */; 752 u8 byte3 /* regpair0 */; 753 u8 byte4 /* byte4 */; 754 __le16 word2 /* word2 */; 755 __le16 word3 /* word3 */; 756 __le16 word4 /* word4 */; 757 __le32 data_offset_end_of_seq /* regpair1 */; 758 __le32 data_offset_next /* reg2 */; 759 }; 760 761 struct e5_mstorm_fcoe_task_ag_ctx 762 { 763 u8 byte0 /* cdu_validation */; 764 u8 byte1 /* state_and_core_id */; 765 __le16 icid /* icid */; 766 u8 flags0; 767 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 768 #define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 769 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 770 #define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 771 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 /* exist_in_qm1 */ 772 #define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 773 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 774 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 775 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 776 #define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 777 u8 flags1; 778 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */ 779 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 780 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 781 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 782 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 783 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 784 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf0en */ 785 #define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 786 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 787 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 788 u8 flags2; 789 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 790 #define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 791 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 792 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 793 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 794 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 795 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 796 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 797 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 798 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 799 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 800 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 801 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 /* rule5en */ 802 #define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 803 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 804 #define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 805 u8 flags3; 806 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */ 807 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 808 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 809 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 810 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 811 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 812 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 813 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 814 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 815 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 816 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 817 #define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 818 __le32 received_bytes /* reg0 */; 819 u8 cleanup_state /* byte2 */; 820 u8 byte3 /* byte3 */; 821 u8 glbl_q_num /* byte4 */; 822 u8 e4_reserved7 /* byte5 */; 823 __le16 word1 /* regpair0 */; 824 __le16 tid_to_xfer /* word2 */; 825 __le16 word3 /* word3 */; 826 __le16 word4 /* word4 */; 827 __le16 word5 /* regpair1 */; 828 __le16 e4_reserved8 /* word6 */; 829 __le32 expected_bytes /* reg1 */; 830 }; 831 832 struct e5_ustorm_fcoe_task_ag_ctx 833 { 834 u8 reserved /* cdu_validation */; 835 u8 byte1 /* state_and_core_id */; 836 __le16 icid /* icid */; 837 u8 flags0; 838 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 839 #define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 840 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 841 #define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 842 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 843 #define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 844 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 845 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 846 u8 flags1; 847 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 848 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 849 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 850 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 851 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 852 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 853 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */ 854 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 855 u8 flags2; 856 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 857 #define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 858 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 859 #define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 860 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 861 #define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 862 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 863 #define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 864 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 865 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 866 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 867 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 868 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 869 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 870 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 871 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 872 u8 flags3; 873 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 874 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 875 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 876 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 877 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 878 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 879 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 880 #define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 881 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 882 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 4 883 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 884 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 5 885 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */ 886 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 6 887 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */ 888 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 7 889 u8 flags4; 890 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */ 891 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 0 892 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */ 893 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 2 894 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */ 895 #define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_SHIFT 3 896 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */ 897 #define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 898 u8 byte2 /* byte2 */; 899 u8 byte3 /* byte3 */; 900 u8 e4_reserved8 /* byte4 */; 901 __le32 dif_err_intervals /* dif_err_intervals */; 902 __le32 dif_error_1st_interval /* dif_error_1st_interval */; 903 __le32 global_cq_num /* reg2 */; 904 __le32 reg3 /* reg3 */; 905 __le32 reg4 /* reg4 */; 906 }; 907 908 /* 909 * fcoe task context 910 */ 911 struct e5_fcoe_task_context 912 { 913 struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */; 914 struct regpair ystorm_st_padding[2] /* padding */; 915 struct tdif_task_context tdif_context /* tdif context */; 916 struct e5_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 917 struct e5_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 918 struct timers_context timer_context /* timer context */; 919 struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */; 920 struct regpair tstorm_st_padding[2] /* padding */; 921 struct e5_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 922 struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */; 923 struct e5_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 924 struct rdif_task_context rdif_context /* rdif context */; 925 }; 926 927 /* 928 * FCoE additional WQE (Sq/ XferQ) information 929 */ 930 union fcoe_additional_info_union 931 { 932 __le32 previous_tid /* Previous tid. Used for Send XFER WQEs in Multiple continuation mode - Target only. */; 933 __le32 parent_tid /* Parent tid. Used for write tasks in a continuation mode - Target only */; 934 __le32 burst_length /* The desired burst length. */; 935 __le32 seq_rec_updated_offset /* The updated offset in SGL - Used in sequence recovery */; 936 }; 937 938 /* 939 * FCoE Ramrod Command IDs 940 */ 941 enum fcoe_completion_status 942 { 943 FCOE_COMPLETION_STATUS_SUCCESS /* FCoE ramrod completed successfully */, 944 FCOE_COMPLETION_STATUS_FCOE_VER_ERR /* Wrong FCoE version */, 945 FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR /* src_mac_arr for the current physical port is full- allocation failed */, 946 MAX_FCOE_COMPLETION_STATUS 947 }; 948 949 /* 950 * FC address (SID/DID) network presentation 951 */ 952 struct fc_addr_nw 953 { 954 u8 addr_lo /* First byte of the SID/DID address that comes/goes from/to the NW (for example if SID is 11:22:33 - this is 0x11) */; 955 u8 addr_mid; 956 u8 addr_hi; 957 }; 958 959 /* 960 * FCoE connection offload 961 */ 962 struct fcoe_conn_offload_ramrod_data 963 { 964 struct regpair sq_pbl_addr /* SQ Pbl base address */; 965 struct regpair sq_curr_page_addr /* SQ current page address */; 966 struct regpair sq_next_page_addr /* SQ next page address */; 967 struct regpair xferq_pbl_addr /* XFERQ Pbl base address */; 968 struct regpair xferq_curr_page_addr /* XFERQ current page address */; 969 struct regpair xferq_next_page_addr /* XFERQ next page address */; 970 struct regpair respq_pbl_addr /* RESPQ Pbl base address */; 971 struct regpair respq_curr_page_addr /* RESPQ current page address */; 972 struct regpair respq_next_page_addr /* RESPQ next page address */; 973 __le16 dst_mac_addr_lo /* First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */; 974 __le16 dst_mac_addr_mid; 975 __le16 dst_mac_addr_hi; 976 __le16 src_mac_addr_lo /* Source MAC address in NW order - First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */; 977 __le16 src_mac_addr_mid; 978 __le16 src_mac_addr_hi; 979 __le16 tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */; 980 __le16 e_d_tov_timer_val /* E_D_TOV timeout value in resolution of 1 msec */; 981 __le16 rx_max_fc_pay_len /* Maximum acceptable FC payload size supported by us */; 982 __le16 vlan_tag; 983 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF /* Vlan id */ 984 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0 985 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1 /* Canonical format indicator */ 986 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12 987 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7 /* Vlan priority */ 988 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13 989 __le16 physical_q0 /* Physical QM queue to be linked to logical queue 0 (fastPath queue) */; 990 __le16 rec_rr_tov_timer_val /* REC_TOV timeout value in resolution of 1 msec */; 991 struct fc_addr_nw s_id /* Source ID in NW order, received during FLOGI */; 992 u8 max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by target, received during PLOGI */; 993 struct fc_addr_nw d_id /* Destination ID in NW order, received after inquiry of the fabric network */; 994 u8 flags; 995 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1 /* Continuously increasing SEQ_CNT indication, received during PLOGI */ 996 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0 997 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1 /* Confirmation request supported */ 998 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1 999 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1 /* REC allowed */ 1000 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2 1001 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1 /* Does inner vlan exist */ 1002 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3 1003 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_MASK 0x1 /* Does a single vlan (inner/outer) should be used. - UFP mode */ 1004 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_SHIFT 4 1005 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3 /* indication for conn mode: 0=Initiator, 1=Target, 2=Both Initiator and Traget */ 1006 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 5 1007 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x1 1008 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 7 1009 __le16 conn_id /* Drivers connection ID. Should be sent in EQs to speed-up drivers access to connection data. */; 1010 u8 def_q_idx /* Default queue number to be used for unsolicited traffic */; 1011 u8 reserved[5]; 1012 }; 1013 1014 /* 1015 * FCoE terminate connection request 1016 */ 1017 struct fcoe_conn_terminate_ramrod_data 1018 { 1019 struct regpair terminate_params_addr /* Terminate params ptr */; 1020 }; 1021 1022 /* 1023 * FCoE device type 1024 */ 1025 enum fcoe_device_type 1026 { 1027 FCOE_TASK_DEV_TYPE_DISK, 1028 FCOE_TASK_DEV_TYPE_TAPE, 1029 MAX_FCOE_DEVICE_TYPE 1030 }; 1031 1032 /* 1033 * Data sgl 1034 */ 1035 struct fcoe_fast_sgl_ctx 1036 { 1037 struct regpair sgl_start_addr /* Current sge address */; 1038 __le32 sgl_byte_offset /* Byte offset from the beginning of the first page in the SGL. In case SGL starts in the middle of page then driver should init this value with the start offset */; 1039 __le16 task_reuse_cnt /* The reuse count for that task. Wrap ion 4K value. */; 1040 __le16 init_offset_in_first_sge /* offset from the beginning of the first page in the SGL, never changed by FW */; 1041 }; 1042 1043 /* 1044 * FCoE firmware function init 1045 */ 1046 struct fcoe_init_func_ramrod_data 1047 { 1048 struct scsi_init_func_params func_params /* Common SCSI init params passed by driver to FW in function init ramrod */; 1049 struct scsi_init_func_queues q_params /* SCSI RQ/CQ/CMDQ firmware function init parameters */; 1050 __le16 mtu /* Max transmission unit */; 1051 __le16 sq_num_pages_in_pbl /* Number of pages at Send Queue */; 1052 __le32 reserved[3]; 1053 }; 1054 1055 /* 1056 * FCoE: Mode of the connection: Target or Initiator or both 1057 */ 1058 enum fcoe_mode_type 1059 { 1060 FCOE_INITIATOR_MODE=0x0, 1061 FCOE_TARGET_MODE=0x1, 1062 FCOE_BOTH_OR_NOT_CHOSEN=0x3, 1063 MAX_FCOE_MODE_TYPE 1064 }; 1065 1066 /* 1067 * Per PF FCoE receive path statistics - tStorm RAM structure 1068 */ 1069 struct fcoe_rx_stat 1070 { 1071 struct regpair fcoe_rx_byte_cnt /* Number of FCoE bytes that were received */; 1072 struct regpair fcoe_rx_data_pkt_cnt /* Number of FCoE FCP DATA packets that were received */; 1073 struct regpair fcoe_rx_xfer_pkt_cnt /* Number of FCoE FCP XFER RDY packets that were received */; 1074 struct regpair fcoe_rx_other_pkt_cnt /* Number of FCoE packets which are not DATA/XFER_RDY that were received */; 1075 __le32 fcoe_silent_drop_pkt_cmdq_full_cnt /* Number of packets that were silently dropped since CMDQ was full */; 1076 __le32 fcoe_silent_drop_pkt_rq_full_cnt /* Number of packets that were silently dropped since RQ (BDQ) was full */; 1077 __le32 fcoe_silent_drop_pkt_crc_error_cnt /* Number of packets that were silently dropped due to FC CRC error */; 1078 __le32 fcoe_silent_drop_pkt_task_invalid_cnt /* Number of packets that were silently dropped since task was not valid */; 1079 __le32 fcoe_silent_drop_total_pkt_cnt /* Number of FCoE packets that were silently dropped */; 1080 __le32 rsrv; 1081 }; 1082 1083 /* 1084 * FCoE SQE request type 1085 */ 1086 enum fcoe_sqe_request_type 1087 { 1088 SEND_FCOE_CMD, 1089 SEND_FCOE_MIDPATH, 1090 SEND_FCOE_ABTS_REQUEST, 1091 FCOE_EXCHANGE_CLEANUP, 1092 FCOE_SEQUENCE_RECOVERY, 1093 SEND_FCOE_XFER_RDY, 1094 SEND_FCOE_RSP, 1095 SEND_FCOE_RSP_WITH_SENSE_DATA, 1096 SEND_FCOE_TARGET_DATA, 1097 SEND_FCOE_INITIATOR_DATA, 1098 SEND_FCOE_XFER_CONTINUATION_RDY /* Xfer Continuation (==1) ready to be sent. Previous XFERs data received successfully. */, 1099 SEND_FCOE_TARGET_ABTS_RSP, 1100 MAX_FCOE_SQE_REQUEST_TYPE 1101 }; 1102 1103 /* 1104 * FCoe statistics request 1105 */ 1106 struct fcoe_stat_ramrod_data 1107 { 1108 struct regpair stat_params_addr /* Statistics host address */; 1109 }; 1110 1111 /* 1112 * FCoE task type 1113 */ 1114 enum fcoe_task_type 1115 { 1116 FCOE_TASK_TYPE_WRITE_INITIATOR, 1117 FCOE_TASK_TYPE_READ_INITIATOR, 1118 FCOE_TASK_TYPE_MIDPATH, 1119 FCOE_TASK_TYPE_UNSOLICITED, 1120 FCOE_TASK_TYPE_ABTS, 1121 FCOE_TASK_TYPE_EXCHANGE_CLEANUP, 1122 FCOE_TASK_TYPE_SEQUENCE_CLEANUP, 1123 FCOE_TASK_TYPE_WRITE_TARGET, 1124 FCOE_TASK_TYPE_READ_TARGET, 1125 FCOE_TASK_TYPE_RSP, 1126 FCOE_TASK_TYPE_RSP_SENSE_DATA, 1127 FCOE_TASK_TYPE_ABTS_TARGET, 1128 FCOE_TASK_TYPE_ENUM_SIZE, 1129 MAX_FCOE_TASK_TYPE 1130 }; 1131 1132 /* 1133 * Per PF FCoE transmit path statistics - pStorm RAM structure 1134 */ 1135 struct fcoe_tx_stat 1136 { 1137 struct regpair fcoe_tx_byte_cnt /* Transmitted FCoE bytes count */; 1138 struct regpair fcoe_tx_data_pkt_cnt /* Transmitted FCoE FCP DATA packets count */; 1139 struct regpair fcoe_tx_xfer_pkt_cnt /* Transmitted FCoE XFER_RDY packets count */; 1140 struct regpair fcoe_tx_other_pkt_cnt /* Transmitted FCoE packets which are not DATA/XFER_RDY count */; 1141 }; 1142 1143 /* 1144 * FCoE SQ/XferQ element 1145 */ 1146 struct fcoe_wqe 1147 { 1148 __le16 task_id /* Initiator - The task identifier (OX_ID). Target - Continuation tid or RX_ID in non-continuation mode */; 1149 __le16 flags; 1150 #define FCOE_WQE_REQ_TYPE_MASK 0xF /* Type of the wqe request. use enum fcoe_sqe_request_type (use enum fcoe_sqe_request_type) */ 1151 #define FCOE_WQE_REQ_TYPE_SHIFT 0 1152 #define FCOE_WQE_SGL_MODE_MASK 0x1 /* The driver will give a hint about sizes of SGEs for better credits evaluation at Xstorm. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 1153 #define FCOE_WQE_SGL_MODE_SHIFT 4 1154 #define FCOE_WQE_CONTINUATION_MASK 0x1 /* Indication if this wqe is a continuation to an existing task (Target only) */ 1155 #define FCOE_WQE_CONTINUATION_SHIFT 5 1156 #define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1 /* Indication to FW to send FCP_RSP after all data was sent - Target only */ 1157 #define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6 1158 #define FCOE_WQE_RESERVED_MASK 0x1 1159 #define FCOE_WQE_RESERVED_SHIFT 7 1160 #define FCOE_WQE_NUM_SGES_MASK 0xF /* Number of SGEs. 8 = at least 8 sges */ 1161 #define FCOE_WQE_NUM_SGES_SHIFT 8 1162 #define FCOE_WQE_RESERVED1_MASK 0xF 1163 #define FCOE_WQE_RESERVED1_SHIFT 12 1164 union fcoe_additional_info_union additional_info_union /* Additional wqe information (if needed) */; 1165 }; 1166 1167 /* 1168 * FCoE XFRQ element 1169 */ 1170 struct xfrqe_prot_flags 1171 { 1172 u8 flags; 1173 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 1174 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0 1175 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1 /* If DIF protection is configured against target (0=no, 1=yes) */ 1176 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4 1177 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3 /* If DIF/DIX protection is configured against the host (0=none, 1=DIF, 2=DIX) */ 1178 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5 1179 #define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1 /* Must set to 0 */ 1180 #define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7 1181 }; 1182 1183 /* 1184 * FCoE doorbell data 1185 */ 1186 struct fcoe_db_data 1187 { 1188 u8 params; 1189 #define FCOE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 1190 #define FCOE_DB_DATA_DEST_SHIFT 0 1191 #define FCOE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 1192 #define FCOE_DB_DATA_AGG_CMD_SHIFT 2 1193 #define FCOE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 1194 #define FCOE_DB_DATA_BYPASS_EN_SHIFT 4 1195 #define FCOE_DB_DATA_RESERVED_MASK 0x1 1196 #define FCOE_DB_DATA_RESERVED_SHIFT 5 1197 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 1198 #define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6 1199 u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 1200 __le16 sq_prod; 1201 }; 1202 1203 #endif /* __FCOE_COMMON__ */ 1204