1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * File : ecore_l2.c 30 */ 31 #include <sys/cdefs.h> 32 #include "bcm_osal.h" 33 34 #include "ecore.h" 35 #include "ecore_status.h" 36 #include "ecore_hsi_eth.h" 37 #include "ecore_chain.h" 38 #include "ecore_spq.h" 39 #include "ecore_init_fw_funcs.h" 40 #include "ecore_cxt.h" 41 #include "ecore_l2.h" 42 #include "ecore_sp_commands.h" 43 #include "ecore_gtt_reg_addr.h" 44 #include "ecore_iro.h" 45 #include "reg_addr.h" 46 #include "ecore_int.h" 47 #include "ecore_hw.h" 48 #include "ecore_vf.h" 49 #include "ecore_sriov.h" 50 #include "ecore_mcp.h" 51 52 #define ECORE_MAX_SGES_NUM 16 53 #define CRC32_POLY 0x1edc6f41 54 55 #ifdef _NTDDK_ 56 #pragma warning(push) 57 #pragma warning(disable : 28167) 58 #pragma warning(disable : 28123) 59 #pragma warning(disable : 28121) 60 #endif 61 62 struct ecore_l2_info { 63 u32 queues; 64 unsigned long **pp_qid_usage; 65 66 /* The lock is meant to synchronize access to the qid usage */ 67 osal_mutex_t lock; 68 }; 69 70 enum _ecore_status_t ecore_l2_alloc(struct ecore_hwfn *p_hwfn) 71 { 72 struct ecore_l2_info *p_l2_info; 73 unsigned long **pp_qids; 74 u32 i; 75 76 if (!ECORE_IS_L2_PERSONALITY(p_hwfn)) 77 return ECORE_SUCCESS; 78 79 p_l2_info = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_l2_info)); 80 if (!p_l2_info) 81 return ECORE_NOMEM; 82 p_hwfn->p_l2_info = p_l2_info; 83 84 if (IS_PF(p_hwfn->p_dev)) { 85 p_l2_info->queues = RESC_NUM(p_hwfn, ECORE_L2_QUEUE); 86 } else { 87 u8 rx = 0, tx = 0; 88 89 ecore_vf_get_num_rxqs(p_hwfn, &rx); 90 ecore_vf_get_num_txqs(p_hwfn, &tx); 91 92 p_l2_info->queues = (u32)OSAL_MAX_T(u8, rx, tx); 93 } 94 95 pp_qids = OSAL_VZALLOC(p_hwfn->p_dev, 96 sizeof(unsigned long *) * 97 p_l2_info->queues); 98 if (pp_qids == OSAL_NULL) 99 return ECORE_NOMEM; 100 p_l2_info->pp_qid_usage = pp_qids; 101 102 for (i = 0; i < p_l2_info->queues; i++) { 103 pp_qids[i] = OSAL_VZALLOC(p_hwfn->p_dev, 104 MAX_QUEUES_PER_QZONE / 8); 105 if (pp_qids[i] == OSAL_NULL) 106 return ECORE_NOMEM; 107 } 108 109 #ifdef CONFIG_ECORE_LOCK_ALLOC 110 if (OSAL_MUTEX_ALLOC(p_hwfn, &p_l2_info->lock)) 111 return ECORE_NOMEM; 112 #endif 113 114 return ECORE_SUCCESS; 115 } 116 117 void ecore_l2_setup(struct ecore_hwfn *p_hwfn) 118 { 119 if (!ECORE_IS_L2_PERSONALITY(p_hwfn)) 120 return; 121 122 OSAL_MUTEX_INIT(&p_hwfn->p_l2_info->lock); 123 } 124 125 void ecore_l2_free(struct ecore_hwfn *p_hwfn) 126 { 127 u32 i; 128 129 if (!ECORE_IS_L2_PERSONALITY(p_hwfn)) 130 return; 131 132 if (p_hwfn->p_l2_info == OSAL_NULL) 133 return; 134 135 if (p_hwfn->p_l2_info->pp_qid_usage == OSAL_NULL) 136 goto out_l2_info; 137 138 /* Free until hit first uninitialized entry */ 139 for (i = 0; i < p_hwfn->p_l2_info->queues; i++) { 140 if (p_hwfn->p_l2_info->pp_qid_usage[i] == OSAL_NULL) 141 break; 142 OSAL_VFREE(p_hwfn->p_dev, 143 p_hwfn->p_l2_info->pp_qid_usage[i]); 144 p_hwfn->p_l2_info->pp_qid_usage[i] = OSAL_NULL; 145 } 146 147 #ifdef CONFIG_ECORE_LOCK_ALLOC 148 /* Lock is last to initialize, if everything else was */ 149 if (i == p_hwfn->p_l2_info->queues) 150 OSAL_MUTEX_DEALLOC(&p_hwfn->p_l2_info->lock); 151 #endif 152 153 OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info->pp_qid_usage); 154 p_hwfn->p_l2_info->pp_qid_usage = OSAL_NULL; 155 156 out_l2_info: 157 OSAL_VFREE(p_hwfn->p_dev, p_hwfn->p_l2_info); 158 p_hwfn->p_l2_info = OSAL_NULL; 159 } 160 161 /* TODO - we'll need locking around these... */ 162 static bool ecore_eth_queue_qid_usage_add(struct ecore_hwfn *p_hwfn, 163 struct ecore_queue_cid *p_cid) 164 { 165 struct ecore_l2_info *p_l2_info = p_hwfn->p_l2_info; 166 u16 queue_id = p_cid->rel.queue_id; 167 bool b_rc = true; 168 u8 first; 169 170 OSAL_MUTEX_ACQUIRE(&p_l2_info->lock); 171 172 if (queue_id > p_l2_info->queues) { 173 DP_NOTICE(p_hwfn, true, 174 "Requested to increase usage for qzone %04x out of %08x\n", 175 queue_id, p_l2_info->queues); 176 b_rc = false; 177 goto out; 178 } 179 180 first = (u8)OSAL_FIND_FIRST_ZERO_BIT(p_l2_info->pp_qid_usage[queue_id], 181 MAX_QUEUES_PER_QZONE); 182 if (first >= MAX_QUEUES_PER_QZONE) { 183 b_rc = false; 184 goto out; 185 } 186 187 OSAL_SET_BIT(first, p_l2_info->pp_qid_usage[queue_id]); 188 p_cid->qid_usage_idx = first; 189 190 out: 191 OSAL_MUTEX_RELEASE(&p_l2_info->lock); 192 return b_rc; 193 } 194 195 static void ecore_eth_queue_qid_usage_del(struct ecore_hwfn *p_hwfn, 196 struct ecore_queue_cid *p_cid) 197 { 198 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_l2_info->lock); 199 200 OSAL_CLEAR_BIT(p_cid->qid_usage_idx, 201 p_hwfn->p_l2_info->pp_qid_usage[p_cid->rel.queue_id]); 202 203 OSAL_MUTEX_RELEASE(&p_hwfn->p_l2_info->lock); 204 } 205 206 void ecore_eth_queue_cid_release(struct ecore_hwfn *p_hwfn, 207 struct ecore_queue_cid *p_cid) 208 { 209 bool b_legacy_vf = !!(p_cid->vf_legacy & 210 ECORE_QCID_LEGACY_VF_CID); 211 212 /* VFs' CIDs are 0-based in PF-view, and uninitialized on VF. 213 * For legacy vf-queues, the CID doesn't go through here. 214 */ 215 if (IS_PF(p_hwfn->p_dev) && !b_legacy_vf) 216 _ecore_cxt_release_cid(p_hwfn, p_cid->cid, p_cid->vfid); 217 218 /* VFs maintain the index inside queue-zone on their own */ 219 if (p_cid->vfid == ECORE_QUEUE_CID_PF) 220 ecore_eth_queue_qid_usage_del(p_hwfn, p_cid); 221 222 OSAL_VFREE(p_hwfn->p_dev, p_cid); 223 } 224 225 /* The internal is only meant to be directly called by PFs initializeing CIDs 226 * for their VFs. 227 */ 228 static struct ecore_queue_cid * 229 _ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn, 230 u16 opaque_fid, u32 cid, 231 struct ecore_queue_start_common_params *p_params, 232 bool b_is_rx, 233 struct ecore_queue_cid_vf_params *p_vf_params) 234 { 235 struct ecore_queue_cid *p_cid; 236 enum _ecore_status_t rc; 237 238 p_cid = OSAL_VZALLOC(p_hwfn->p_dev, sizeof(*p_cid)); 239 if (p_cid == OSAL_NULL) 240 return OSAL_NULL; 241 242 p_cid->opaque_fid = opaque_fid; 243 p_cid->cid = cid; 244 p_cid->p_owner = p_hwfn; 245 246 /* Fill in parameters */ 247 p_cid->rel.vport_id = p_params->vport_id; 248 p_cid->rel.queue_id = p_params->queue_id; 249 p_cid->rel.stats_id = p_params->stats_id; 250 p_cid->sb_igu_id = p_params->p_sb->igu_sb_id; 251 p_cid->b_is_rx = b_is_rx; 252 p_cid->sb_idx = p_params->sb_idx; 253 254 /* Fill-in bits related to VFs' queues if information was provided */ 255 if (p_vf_params != OSAL_NULL) { 256 p_cid->vfid = p_vf_params->vfid; 257 p_cid->vf_qid = p_vf_params->vf_qid; 258 p_cid->vf_legacy = p_vf_params->vf_legacy; 259 } else { 260 p_cid->vfid = ECORE_QUEUE_CID_PF; 261 } 262 263 /* Don't try calculating the absolute indices for VFs */ 264 if (IS_VF(p_hwfn->p_dev)) { 265 p_cid->abs = p_cid->rel; 266 267 goto out; 268 } 269 270 /* Calculate the engine-absolute indices of the resources. 271 * This would guarantee they're valid later on. 272 * In some cases [SBs] we already have the right values. 273 */ 274 rc = ecore_fw_vport(p_hwfn, p_cid->rel.vport_id, &p_cid->abs.vport_id); 275 if (rc != ECORE_SUCCESS) 276 goto fail; 277 278 rc = ecore_fw_l2_queue(p_hwfn, p_cid->rel.queue_id, 279 &p_cid->abs.queue_id); 280 if (rc != ECORE_SUCCESS) 281 goto fail; 282 283 /* In case of a PF configuring its VF's queues, the stats-id is already 284 * absolute [since there's a single index that's suitable per-VF]. 285 */ 286 if (p_cid->vfid == ECORE_QUEUE_CID_PF) { 287 rc = ecore_fw_vport(p_hwfn, p_cid->rel.stats_id, 288 &p_cid->abs.stats_id); 289 if (rc != ECORE_SUCCESS) 290 goto fail; 291 } else { 292 p_cid->abs.stats_id = p_cid->rel.stats_id; 293 } 294 295 out: 296 /* VF-images have provided the qid_usage_idx on their own. 297 * Otherwise, we need to allocate a unique one. 298 */ 299 if (!p_vf_params) { 300 if (!ecore_eth_queue_qid_usage_add(p_hwfn, p_cid)) 301 goto fail; 302 } else { 303 p_cid->qid_usage_idx = p_vf_params->qid_usage_idx; 304 } 305 306 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 307 "opaque_fid: %04x CID %08x vport %02x [%02x] qzone %04x.%02x [%04x] stats %02x [%02x] SB %04x PI %02x\n", 308 p_cid->opaque_fid, p_cid->cid, 309 p_cid->rel.vport_id, p_cid->abs.vport_id, 310 p_cid->rel.queue_id, p_cid->qid_usage_idx, 311 p_cid->abs.queue_id, 312 p_cid->rel.stats_id, p_cid->abs.stats_id, 313 p_cid->sb_igu_id, p_cid->sb_idx); 314 315 return p_cid; 316 317 fail: 318 OSAL_VFREE(p_hwfn->p_dev, p_cid); 319 return OSAL_NULL; 320 } 321 322 struct ecore_queue_cid * 323 ecore_eth_queue_to_cid(struct ecore_hwfn *p_hwfn, u16 opaque_fid, 324 struct ecore_queue_start_common_params *p_params, 325 bool b_is_rx, 326 struct ecore_queue_cid_vf_params *p_vf_params) 327 { 328 struct ecore_queue_cid *p_cid; 329 u8 vfid = ECORE_CXT_PF_CID; 330 bool b_legacy_vf = false; 331 u32 cid = 0; 332 333 /* In case of legacy VFs, The CID can be derived from the additional 334 * VF parameters - the VF assumes queue X uses CID X, so we can simply 335 * use the vf_qid for this purpose as well. 336 */ 337 if (p_vf_params) { 338 vfid = p_vf_params->vfid; 339 340 if (p_vf_params->vf_legacy & 341 ECORE_QCID_LEGACY_VF_CID) { 342 b_legacy_vf = true; 343 cid = p_vf_params->vf_qid; 344 } 345 } 346 347 /* Get a unique firmware CID for this queue, in case it's a PF. 348 * VF's don't need a CID as the queue configuration will be done 349 * by PF. 350 */ 351 if (IS_PF(p_hwfn->p_dev) && !b_legacy_vf) { 352 if (_ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, 353 &cid, vfid) != ECORE_SUCCESS) { 354 DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n"); 355 return OSAL_NULL; 356 } 357 } 358 359 p_cid = _ecore_eth_queue_to_cid(p_hwfn, opaque_fid, cid, 360 p_params, b_is_rx, p_vf_params); 361 if ((p_cid == OSAL_NULL) && IS_PF(p_hwfn->p_dev) && !b_legacy_vf) 362 _ecore_cxt_release_cid(p_hwfn, cid, vfid); 363 364 return p_cid; 365 } 366 367 static struct ecore_queue_cid * 368 ecore_eth_queue_to_cid_pf(struct ecore_hwfn *p_hwfn, u16 opaque_fid, 369 bool b_is_rx, 370 struct ecore_queue_start_common_params *p_params) 371 { 372 return ecore_eth_queue_to_cid(p_hwfn, opaque_fid, p_params, b_is_rx, 373 OSAL_NULL); 374 } 375 376 enum _ecore_status_t ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn, 377 struct ecore_sp_vport_start_params *p_params) 378 { 379 struct vport_start_ramrod_data *p_ramrod = OSAL_NULL; 380 struct ecore_spq_entry *p_ent = OSAL_NULL; 381 struct ecore_sp_init_data init_data; 382 struct eth_vport_tpa_param *p_tpa; 383 u16 rx_mode = 0, tx_err = 0; 384 u8 abs_vport_id = 0; 385 enum _ecore_status_t rc = ECORE_NOTIMPL; 386 387 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 388 if (rc != ECORE_SUCCESS) 389 return rc; 390 391 /* Get SPQ entry */ 392 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 393 init_data.cid = ecore_spq_get_cid(p_hwfn); 394 init_data.opaque_fid = p_params->opaque_fid; 395 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 396 397 rc = ecore_sp_init_request(p_hwfn, &p_ent, 398 ETH_RAMROD_VPORT_START, 399 PROTOCOLID_ETH, &init_data); 400 if (rc != ECORE_SUCCESS) 401 return rc; 402 403 p_ramrod = &p_ent->ramrod.vport_start; 404 p_ramrod->vport_id = abs_vport_id; 405 406 p_ramrod->mtu = OSAL_CPU_TO_LE16(p_params->mtu); 407 p_ramrod->handle_ptp_pkts = p_params->handle_ptp_pkts; 408 p_ramrod->inner_vlan_removal_en = p_params->remove_inner_vlan; 409 p_ramrod->drop_ttl0_en = p_params->drop_ttl0; 410 p_ramrod->untagged = p_params->only_untagged; 411 p_ramrod->zero_placement_offset = p_params->zero_placement_offset; 412 413 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 1); 414 SET_FIELD(rx_mode, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 1); 415 416 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(rx_mode); 417 418 /* Handle requests for strict behavior on transmission errors */ 419 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE, 420 p_params->b_err_illegal_vlan_mode ? 421 ETH_TX_ERR_ASSERT_MALICIOUS : 0); 422 SET_FIELD(tx_err, ETH_TX_ERR_VALS_PACKET_TOO_SMALL, 423 p_params->b_err_small_pkt ? 424 ETH_TX_ERR_ASSERT_MALICIOUS : 0); 425 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR, 426 p_params->b_err_anti_spoof ? 427 ETH_TX_ERR_ASSERT_MALICIOUS : 0); 428 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS, 429 p_params->b_err_illegal_inband_mode ? 430 ETH_TX_ERR_ASSERT_MALICIOUS : 0); 431 SET_FIELD(tx_err, ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG, 432 p_params->b_err_vlan_insert_with_inband ? 433 ETH_TX_ERR_ASSERT_MALICIOUS : 0); 434 SET_FIELD(tx_err, ETH_TX_ERR_VALS_MTU_VIOLATION, 435 p_params->b_err_big_pkt ? 436 ETH_TX_ERR_ASSERT_MALICIOUS : 0); 437 SET_FIELD(tx_err, ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME, 438 p_params->b_err_ctrl_frame ? 439 ETH_TX_ERR_ASSERT_MALICIOUS : 0); 440 p_ramrod->tx_err_behav.values = OSAL_CPU_TO_LE16(tx_err); 441 442 /* TPA related fields */ 443 p_tpa = &p_ramrod->tpa_param; 444 OSAL_MEMSET(p_tpa, 0, sizeof(struct eth_vport_tpa_param)); 445 p_tpa->max_buff_num = p_params->max_buffers_per_cqe; 446 447 switch (p_params->tpa_mode) { 448 case ECORE_TPA_MODE_GRO: 449 p_tpa->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM; 450 p_tpa->tpa_max_size = (u16)-1; 451 p_tpa->tpa_min_size_to_cont = p_params->mtu/2; 452 p_tpa->tpa_min_size_to_start = p_params->mtu/2; 453 p_tpa->tpa_ipv4_en_flg = 1; 454 p_tpa->tpa_ipv6_en_flg = 1; 455 p_tpa->tpa_ipv4_tunn_en_flg = 1; 456 p_tpa->tpa_ipv6_tunn_en_flg = 1; 457 p_tpa->tpa_pkt_split_flg = 1; 458 p_tpa->tpa_gro_consistent_flg = 1; 459 break; 460 default: 461 break; 462 } 463 464 p_ramrod->tx_switching_en = p_params->tx_switching; 465 #ifndef ASIC_ONLY 466 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) 467 p_ramrod->tx_switching_en = 0; 468 #endif 469 470 p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac; 471 p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype; 472 473 /* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */ 474 p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_params->concrete_fid); 475 476 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 477 } 478 479 enum _ecore_status_t ecore_sp_vport_start(struct ecore_hwfn *p_hwfn, 480 struct ecore_sp_vport_start_params *p_params) 481 { 482 if (IS_VF(p_hwfn->p_dev)) 483 return ecore_vf_pf_vport_start(p_hwfn, p_params->vport_id, 484 p_params->mtu, 485 p_params->remove_inner_vlan, 486 p_params->tpa_mode, 487 p_params->max_buffers_per_cqe, 488 p_params->only_untagged, 489 p_params->zero_placement_offset); 490 491 return ecore_sp_eth_vport_start(p_hwfn, p_params); 492 } 493 494 static enum _ecore_status_t 495 ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn, 496 struct vport_update_ramrod_data *p_ramrod, 497 struct ecore_rss_params *p_rss) 498 { 499 struct eth_vport_rss_config *p_config; 500 u16 capabilities = 0; 501 int i, table_size; 502 enum _ecore_status_t rc = ECORE_SUCCESS; 503 504 if (!p_rss) { 505 p_ramrod->common.update_rss_flg = 0; 506 return rc; 507 } 508 p_config = &p_ramrod->rss_config; 509 510 OSAL_BUILD_BUG_ON(ECORE_RSS_IND_TABLE_SIZE != 511 ETH_RSS_IND_TABLE_ENTRIES_NUM); 512 513 rc = ecore_fw_rss_eng(p_hwfn, p_rss->rss_eng_id, 514 &p_config->rss_id); 515 if (rc != ECORE_SUCCESS) 516 return rc; 517 518 p_ramrod->common.update_rss_flg = p_rss->update_rss_config; 519 p_config->update_rss_capabilities = p_rss->update_rss_capabilities; 520 p_config->update_rss_ind_table = p_rss->update_rss_ind_table; 521 p_config->update_rss_key = p_rss->update_rss_key; 522 523 p_config->rss_mode = p_rss->rss_enable ? 524 ETH_VPORT_RSS_MODE_REGULAR : 525 ETH_VPORT_RSS_MODE_DISABLED; 526 527 p_config->capabilities = 0; 528 529 SET_FIELD(capabilities, 530 ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY, 531 !!(p_rss->rss_caps & ECORE_RSS_IPV4)); 532 SET_FIELD(capabilities, 533 ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY, 534 !!(p_rss->rss_caps & ECORE_RSS_IPV6)); 535 SET_FIELD(capabilities, 536 ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY, 537 !!(p_rss->rss_caps & ECORE_RSS_IPV4_TCP)); 538 SET_FIELD(capabilities, 539 ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY, 540 !!(p_rss->rss_caps & ECORE_RSS_IPV6_TCP)); 541 SET_FIELD(capabilities, 542 ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY, 543 !!(p_rss->rss_caps & ECORE_RSS_IPV4_UDP)); 544 SET_FIELD(capabilities, 545 ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY, 546 !!(p_rss->rss_caps & ECORE_RSS_IPV6_UDP)); 547 p_config->tbl_size = p_rss->rss_table_size_log; 548 p_config->capabilities = OSAL_CPU_TO_LE16(capabilities); 549 550 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, 551 "update rss flag %d, rss_mode = %d, update_caps = %d, capabilities = %d, update_ind = %d, update_rss_key = %d\n", 552 p_ramrod->common.update_rss_flg, 553 p_config->rss_mode, 554 p_config->update_rss_capabilities, 555 p_config->capabilities, 556 p_config->update_rss_ind_table, 557 p_config->update_rss_key); 558 559 table_size = OSAL_MIN_T(int, ECORE_RSS_IND_TABLE_SIZE, 560 1 << p_config->tbl_size); 561 for (i = 0; i < table_size; i++) { 562 struct ecore_queue_cid *p_queue = p_rss->rss_ind_table[i]; 563 564 if (!p_queue) 565 return ECORE_INVAL; 566 567 p_config->indirection_table[i] = 568 OSAL_CPU_TO_LE16(p_queue->abs.queue_id); 569 } 570 571 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, 572 "Configured RSS indirection table [%d entries]:\n", 573 table_size); 574 for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i += 0x10) { 575 DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP, 576 "%04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n", 577 OSAL_LE16_TO_CPU(p_config->indirection_table[i]), 578 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 1]), 579 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 2]), 580 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 3]), 581 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 4]), 582 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 5]), 583 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 6]), 584 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 7]), 585 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 8]), 586 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 9]), 587 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 10]), 588 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 11]), 589 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 12]), 590 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 13]), 591 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 14]), 592 OSAL_LE16_TO_CPU(p_config->indirection_table[i + 15])); 593 } 594 595 for (i = 0; i < 10; i++) 596 p_config->rss_key[i] = OSAL_CPU_TO_LE32(p_rss->rss_key[i]); 597 598 return rc; 599 } 600 601 static void 602 ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn, 603 struct vport_update_ramrod_data *p_ramrod, 604 struct ecore_filter_accept_flags accept_flags) 605 { 606 p_ramrod->common.update_rx_mode_flg = 607 accept_flags.update_rx_mode_config; 608 p_ramrod->common.update_tx_mode_flg = 609 accept_flags.update_tx_mode_config; 610 611 #ifndef ASIC_ONLY 612 /* On B0 emulation we cannot enable Tx, since this would cause writes 613 * to PVFC HW block which isn't implemented in emulation. 614 */ 615 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 616 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 617 "Non-Asic - prevent Tx mode in vport update\n"); 618 p_ramrod->common.update_tx_mode_flg = 0; 619 } 620 #endif 621 622 /* Set Rx mode accept flags */ 623 if (p_ramrod->common.update_rx_mode_flg) { 624 u8 accept_filter = accept_flags.rx_accept_filter; 625 u16 state = 0; 626 627 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL, 628 !(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) || 629 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED))); 630 631 SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED, 632 !!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)); 633 634 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL, 635 !(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) || 636 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED))); 637 638 SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL, 639 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) && 640 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED))); 641 642 SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL, 643 !!(accept_filter & ECORE_ACCEPT_BCAST)); 644 645 p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state); 646 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 647 "vport[%02x] p_ramrod->rx_mode.state = 0x%x\n", 648 p_ramrod->common.vport_id, state); 649 } 650 651 /* Set Tx mode accept flags */ 652 if (p_ramrod->common.update_tx_mode_flg) { 653 u8 accept_filter = accept_flags.tx_accept_filter; 654 u16 state = 0; 655 656 SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL, 657 !!(accept_filter & ECORE_ACCEPT_NONE)); 658 659 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL, 660 !!(accept_filter & ECORE_ACCEPT_NONE)); 661 662 SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL, 663 (!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) && 664 !!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED))); 665 666 SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL, 667 !!(accept_filter & ECORE_ACCEPT_BCAST)); 668 669 p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state); 670 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 671 "vport[%02x] p_ramrod->tx_mode.state = 0x%x\n", 672 p_ramrod->common.vport_id, state); 673 } 674 } 675 676 static void 677 ecore_sp_vport_update_sge_tpa(struct vport_update_ramrod_data *p_ramrod, 678 struct ecore_sge_tpa_params *p_params) 679 { 680 struct eth_vport_tpa_param *p_tpa; 681 u16 val; 682 683 if (!p_params) { 684 p_ramrod->common.update_tpa_param_flg = 0; 685 p_ramrod->common.update_tpa_en_flg = 0; 686 p_ramrod->common.update_tpa_param_flg = 0; 687 return; 688 } 689 690 p_ramrod->common.update_tpa_en_flg = p_params->update_tpa_en_flg; 691 p_tpa = &p_ramrod->tpa_param; 692 p_tpa->tpa_ipv4_en_flg = p_params->tpa_ipv4_en_flg; 693 p_tpa->tpa_ipv6_en_flg = p_params->tpa_ipv6_en_flg; 694 p_tpa->tpa_ipv4_tunn_en_flg = p_params->tpa_ipv4_tunn_en_flg; 695 p_tpa->tpa_ipv6_tunn_en_flg = p_params->tpa_ipv6_tunn_en_flg; 696 697 p_ramrod->common.update_tpa_param_flg = p_params->update_tpa_param_flg; 698 p_tpa->max_buff_num = p_params->max_buffers_per_cqe; 699 p_tpa->tpa_pkt_split_flg = p_params->tpa_pkt_split_flg; 700 p_tpa->tpa_hdr_data_split_flg = p_params->tpa_hdr_data_split_flg; 701 p_tpa->tpa_gro_consistent_flg = p_params->tpa_gro_consistent_flg; 702 p_tpa->tpa_max_aggs_num = p_params->tpa_max_aggs_num; 703 val = p_params->tpa_max_size; 704 p_tpa->tpa_max_size = OSAL_CPU_TO_LE16(val); 705 val = p_params->tpa_min_size_to_start; 706 p_tpa->tpa_min_size_to_start = OSAL_CPU_TO_LE16(val); 707 val = p_params->tpa_min_size_to_cont; 708 p_tpa->tpa_min_size_to_cont = OSAL_CPU_TO_LE16(val); 709 } 710 711 static void 712 ecore_sp_update_mcast_bin(struct vport_update_ramrod_data *p_ramrod, 713 struct ecore_sp_vport_update_params *p_params) 714 { 715 int i; 716 717 OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 0, 718 sizeof(p_ramrod->approx_mcast.bins)); 719 720 if (!p_params->update_approx_mcast_flg) 721 return; 722 723 p_ramrod->common.update_approx_mcast_flg = 1; 724 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 725 u32 *p_bins = p_params->bins; 726 727 p_ramrod->approx_mcast.bins[i] = OSAL_CPU_TO_LE32(p_bins[i]); 728 } 729 } 730 731 enum _ecore_status_t ecore_sp_vport_update(struct ecore_hwfn *p_hwfn, 732 struct ecore_sp_vport_update_params *p_params, 733 enum spq_mode comp_mode, 734 struct ecore_spq_comp_cb *p_comp_data) 735 { 736 struct ecore_rss_params *p_rss_params = p_params->rss_params; 737 struct vport_update_ramrod_data_cmn *p_cmn; 738 struct ecore_sp_init_data init_data; 739 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL; 740 struct ecore_spq_entry *p_ent = OSAL_NULL; 741 u8 abs_vport_id = 0, val; 742 enum _ecore_status_t rc = ECORE_NOTIMPL; 743 744 if (IS_VF(p_hwfn->p_dev)) { 745 rc = ecore_vf_pf_vport_update(p_hwfn, p_params); 746 return rc; 747 } 748 749 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 750 if (rc != ECORE_SUCCESS) 751 return rc; 752 753 /* Get SPQ entry */ 754 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 755 init_data.cid = ecore_spq_get_cid(p_hwfn); 756 init_data.opaque_fid = p_params->opaque_fid; 757 init_data.comp_mode = comp_mode; 758 init_data.p_comp_data = p_comp_data; 759 760 rc = ecore_sp_init_request(p_hwfn, &p_ent, 761 ETH_RAMROD_VPORT_UPDATE, 762 PROTOCOLID_ETH, &init_data); 763 if (rc != ECORE_SUCCESS) 764 return rc; 765 766 /* Copy input params to ramrod according to FW struct */ 767 p_ramrod = &p_ent->ramrod.vport_update; 768 p_cmn = &p_ramrod->common; 769 770 p_cmn->vport_id = abs_vport_id; 771 772 p_cmn->rx_active_flg = p_params->vport_active_rx_flg; 773 p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg; 774 p_cmn->tx_active_flg = p_params->vport_active_tx_flg; 775 p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg; 776 777 p_cmn->accept_any_vlan = p_params->accept_any_vlan; 778 val = p_params->update_accept_any_vlan_flg; 779 p_cmn->update_accept_any_vlan_flg = val; 780 781 p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg; 782 val = p_params->update_inner_vlan_removal_flg; 783 p_cmn->update_inner_vlan_removal_en_flg = val; 784 785 p_cmn->default_vlan_en = p_params->default_vlan_enable_flg; 786 val = p_params->update_default_vlan_enable_flg; 787 p_cmn->update_default_vlan_en_flg = val; 788 789 p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan); 790 p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg; 791 792 p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg; 793 794 p_ramrod->common.tx_switching_en = p_params->tx_switching_flg; 795 #ifndef ASIC_ONLY 796 if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) 797 if (p_ramrod->common.tx_switching_en || 798 p_ramrod->common.update_tx_switching_en_flg) { 799 DP_NOTICE(p_hwfn, false, "FPGA - why are we seeing tx-switching? Overriding it\n"); 800 p_ramrod->common.tx_switching_en = 0; 801 p_ramrod->common.update_tx_switching_en_flg = 1; 802 } 803 #endif 804 p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg; 805 806 p_cmn->anti_spoofing_en = p_params->anti_spoofing_en; 807 val = p_params->update_anti_spoofing_en_flg; 808 p_ramrod->common.update_anti_spoofing_en_flg = val; 809 810 rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params); 811 if (rc != ECORE_SUCCESS) { 812 /* Return spq entry which is taken in ecore_sp_init_request()*/ 813 ecore_spq_return_entry(p_hwfn, p_ent); 814 return rc; 815 } 816 817 /* Update mcast bins for VFs, PF doesn't use this functionality */ 818 ecore_sp_update_mcast_bin(p_ramrod, p_params); 819 820 ecore_sp_update_accept_mode(p_hwfn, p_ramrod, p_params->accept_flags); 821 ecore_sp_vport_update_sge_tpa(p_ramrod, p_params->sge_tpa_params); 822 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 823 } 824 825 enum _ecore_status_t ecore_sp_vport_stop(struct ecore_hwfn *p_hwfn, 826 u16 opaque_fid, 827 u8 vport_id) 828 { 829 struct vport_stop_ramrod_data *p_ramrod; 830 struct ecore_sp_init_data init_data; 831 struct ecore_spq_entry *p_ent; 832 u8 abs_vport_id = 0; 833 enum _ecore_status_t rc; 834 835 if (IS_VF(p_hwfn->p_dev)) 836 return ecore_vf_pf_vport_stop(p_hwfn); 837 838 rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id); 839 if (rc != ECORE_SUCCESS) 840 return rc; 841 842 /* Get SPQ entry */ 843 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 844 init_data.cid = ecore_spq_get_cid(p_hwfn); 845 init_data.opaque_fid = opaque_fid; 846 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 847 848 rc = ecore_sp_init_request(p_hwfn, &p_ent, 849 ETH_RAMROD_VPORT_STOP, 850 PROTOCOLID_ETH, &init_data); 851 if (rc != ECORE_SUCCESS) 852 return rc; 853 854 p_ramrod = &p_ent->ramrod.vport_stop; 855 p_ramrod->vport_id = abs_vport_id; 856 857 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 858 } 859 860 static enum _ecore_status_t 861 ecore_vf_pf_accept_flags(struct ecore_hwfn *p_hwfn, 862 struct ecore_filter_accept_flags *p_accept_flags) 863 { 864 struct ecore_sp_vport_update_params s_params; 865 866 OSAL_MEMSET(&s_params, 0, sizeof(s_params)); 867 OSAL_MEMCPY(&s_params.accept_flags, p_accept_flags, 868 sizeof(struct ecore_filter_accept_flags)); 869 870 return ecore_vf_pf_vport_update(p_hwfn, &s_params); 871 } 872 873 enum _ecore_status_t ecore_filter_accept_cmd(struct ecore_dev *p_dev, 874 u8 vport, 875 struct ecore_filter_accept_flags accept_flags, 876 u8 update_accept_any_vlan, 877 u8 accept_any_vlan, 878 enum spq_mode comp_mode, 879 struct ecore_spq_comp_cb *p_comp_data) 880 { 881 struct ecore_sp_vport_update_params vport_update_params; 882 int i, rc; 883 884 /* Prepare and send the vport rx_mode change */ 885 OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params)); 886 vport_update_params.vport_id = vport; 887 vport_update_params.accept_flags = accept_flags; 888 vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan; 889 vport_update_params.accept_any_vlan = accept_any_vlan; 890 891 for_each_hwfn(p_dev, i) { 892 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 893 894 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid; 895 896 if (IS_VF(p_dev)) { 897 rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags); 898 if (rc != ECORE_SUCCESS) 899 return rc; 900 continue; 901 } 902 903 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params, 904 comp_mode, p_comp_data); 905 if (rc != ECORE_SUCCESS) { 906 DP_ERR(p_dev, "Update rx_mode failed %d\n", rc); 907 return rc; 908 } 909 910 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 911 "Accept filter configured, flags = [Rx]%x [Tx]%x\n", 912 accept_flags.rx_accept_filter, 913 accept_flags.tx_accept_filter); 914 915 if (update_accept_any_vlan) 916 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 917 "accept_any_vlan=%d configured\n", 918 accept_any_vlan); 919 } 920 921 return 0; 922 } 923 924 enum _ecore_status_t 925 ecore_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn, 926 struct ecore_queue_cid *p_cid, 927 u16 bd_max_bytes, 928 dma_addr_t bd_chain_phys_addr, 929 dma_addr_t cqe_pbl_addr, 930 u16 cqe_pbl_size) 931 { 932 struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL; 933 struct ecore_spq_entry *p_ent = OSAL_NULL; 934 struct ecore_sp_init_data init_data; 935 enum _ecore_status_t rc = ECORE_NOTIMPL; 936 937 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "opaque_fid=0x%x, cid=0x%x, rx_qzone=0x%x, vport_id=0x%x, sb_id=0x%x\n", 938 p_cid->opaque_fid, p_cid->cid, p_cid->abs.queue_id, 939 p_cid->abs.vport_id, p_cid->sb_igu_id); 940 941 /* Get SPQ entry */ 942 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 943 init_data.cid = p_cid->cid; 944 init_data.opaque_fid = p_cid->opaque_fid; 945 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 946 947 rc = ecore_sp_init_request(p_hwfn, &p_ent, 948 ETH_RAMROD_RX_QUEUE_START, 949 PROTOCOLID_ETH, &init_data); 950 if (rc != ECORE_SUCCESS) 951 return rc; 952 953 p_ramrod = &p_ent->ramrod.rx_queue_start; 954 955 p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->sb_igu_id); 956 p_ramrod->sb_index = p_cid->sb_idx; 957 p_ramrod->vport_id = p_cid->abs.vport_id; 958 p_ramrod->stats_counter_id = p_cid->abs.stats_id; 959 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id); 960 p_ramrod->complete_cqe_flg = 0; 961 p_ramrod->complete_event_flg = 1; 962 963 p_ramrod->bd_max_bytes = OSAL_CPU_TO_LE16(bd_max_bytes); 964 DMA_REGPAIR_LE(p_ramrod->bd_base, bd_chain_phys_addr); 965 966 p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size); 967 DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr); 968 969 if (p_cid->vfid != ECORE_QUEUE_CID_PF) { 970 bool b_legacy_vf = !!(p_cid->vf_legacy & 971 ECORE_QCID_LEGACY_VF_RX_PROD); 972 973 p_ramrod->vf_rx_prod_index = p_cid->vf_qid; 974 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Queue%s is meant for VF rxq[%02x]\n", 975 b_legacy_vf ? " [legacy]" : "", 976 p_cid->vf_qid); 977 p_ramrod->vf_rx_prod_use_zone_a = b_legacy_vf; 978 } 979 980 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 981 } 982 983 static enum _ecore_status_t 984 ecore_eth_pf_rx_queue_start(struct ecore_hwfn *p_hwfn, 985 struct ecore_queue_cid *p_cid, 986 u16 bd_max_bytes, 987 dma_addr_t bd_chain_phys_addr, 988 dma_addr_t cqe_pbl_addr, 989 u16 cqe_pbl_size, 990 void OSAL_IOMEM **pp_prod) 991 { 992 u32 init_prod_val = 0; 993 994 *pp_prod = (u8 OSAL_IOMEM*) 995 p_hwfn->regview + 996 GTT_BAR0_MAP_REG_MSDM_RAM + 997 MSTORM_ETH_PF_PRODS_OFFSET(p_cid->abs.queue_id); 998 999 /* Init the rcq, rx bd and rx sge (if valid) producers to 0 */ 1000 __internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32), 1001 (u32 *)(&init_prod_val)); 1002 1003 return ecore_eth_rxq_start_ramrod(p_hwfn, p_cid, 1004 bd_max_bytes, 1005 bd_chain_phys_addr, 1006 cqe_pbl_addr, cqe_pbl_size); 1007 } 1008 1009 enum _ecore_status_t 1010 ecore_eth_rx_queue_start(struct ecore_hwfn *p_hwfn, 1011 u16 opaque_fid, 1012 struct ecore_queue_start_common_params *p_params, 1013 u16 bd_max_bytes, 1014 dma_addr_t bd_chain_phys_addr, 1015 dma_addr_t cqe_pbl_addr, 1016 u16 cqe_pbl_size, 1017 struct ecore_rxq_start_ret_params *p_ret_params) 1018 { 1019 struct ecore_queue_cid *p_cid; 1020 enum _ecore_status_t rc; 1021 1022 /* Allocate a CID for the queue */ 1023 p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, true, p_params); 1024 if (p_cid == OSAL_NULL) 1025 return ECORE_NOMEM; 1026 1027 if (IS_PF(p_hwfn->p_dev)) 1028 rc = ecore_eth_pf_rx_queue_start(p_hwfn, p_cid, 1029 bd_max_bytes, 1030 bd_chain_phys_addr, 1031 cqe_pbl_addr, cqe_pbl_size, 1032 &p_ret_params->p_prod); 1033 else 1034 rc = ecore_vf_pf_rxq_start(p_hwfn, p_cid, 1035 bd_max_bytes, 1036 bd_chain_phys_addr, 1037 cqe_pbl_addr, 1038 cqe_pbl_size, 1039 &p_ret_params->p_prod); 1040 1041 /* Provide the caller with a reference to as handler */ 1042 if (rc != ECORE_SUCCESS) 1043 ecore_eth_queue_cid_release(p_hwfn, p_cid); 1044 else 1045 p_ret_params->p_handle = (void *)p_cid; 1046 1047 return rc; 1048 } 1049 1050 enum _ecore_status_t ecore_sp_eth_rx_queues_update(struct ecore_hwfn *p_hwfn, 1051 void **pp_rxq_handles, 1052 u8 num_rxqs, 1053 u8 complete_cqe_flg, 1054 u8 complete_event_flg, 1055 enum spq_mode comp_mode, 1056 struct ecore_spq_comp_cb *p_comp_data) 1057 { 1058 struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL; 1059 struct ecore_spq_entry *p_ent = OSAL_NULL; 1060 struct ecore_sp_init_data init_data; 1061 struct ecore_queue_cid *p_cid; 1062 enum _ecore_status_t rc = ECORE_NOTIMPL; 1063 u8 i; 1064 1065 #ifndef LINUX_REMOVE 1066 if (IS_VF(p_hwfn->p_dev)) 1067 return ecore_vf_pf_rxqs_update(p_hwfn, 1068 (struct ecore_queue_cid **) 1069 pp_rxq_handles, 1070 num_rxqs, 1071 complete_cqe_flg, 1072 complete_event_flg); 1073 #endif 1074 1075 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 1076 init_data.comp_mode = comp_mode; 1077 init_data.p_comp_data = p_comp_data; 1078 1079 for (i = 0; i < num_rxqs; i++) { 1080 p_cid = ((struct ecore_queue_cid **)pp_rxq_handles)[i]; 1081 1082 /* Get SPQ entry */ 1083 init_data.cid = p_cid->cid; 1084 init_data.opaque_fid = p_cid->opaque_fid; 1085 1086 rc = ecore_sp_init_request(p_hwfn, &p_ent, 1087 ETH_RAMROD_RX_QUEUE_UPDATE, 1088 PROTOCOLID_ETH, &init_data); 1089 if (rc != ECORE_SUCCESS) 1090 return rc; 1091 1092 p_ramrod = &p_ent->ramrod.rx_queue_update; 1093 p_ramrod->vport_id = p_cid->abs.vport_id; 1094 1095 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id); 1096 p_ramrod->complete_cqe_flg = complete_cqe_flg; 1097 p_ramrod->complete_event_flg = complete_event_flg; 1098 1099 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 1100 if (rc != ECORE_SUCCESS) 1101 return rc; 1102 } 1103 1104 return rc; 1105 } 1106 1107 enum _ecore_status_t 1108 ecore_sp_eth_rx_queues_set_default(struct ecore_hwfn *p_hwfn, 1109 void *p_rxq_handler, 1110 enum spq_mode comp_mode, 1111 struct ecore_spq_comp_cb *p_comp_data) 1112 { 1113 struct rx_queue_update_ramrod_data *p_ramrod = OSAL_NULL; 1114 struct ecore_spq_entry *p_ent = OSAL_NULL; 1115 struct ecore_sp_init_data init_data; 1116 struct ecore_queue_cid *p_cid; 1117 enum _ecore_status_t rc = ECORE_SUCCESS; 1118 1119 if (IS_VF(p_hwfn->p_dev)) 1120 return ECORE_NOTIMPL; 1121 1122 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 1123 init_data.comp_mode = comp_mode; 1124 init_data.p_comp_data = p_comp_data; 1125 1126 p_cid = (struct ecore_queue_cid *)p_rxq_handler; 1127 1128 /* Get SPQ entry */ 1129 init_data.cid = p_cid->cid; 1130 init_data.opaque_fid = p_cid->opaque_fid; 1131 1132 rc = ecore_sp_init_request(p_hwfn, &p_ent, 1133 ETH_RAMROD_RX_QUEUE_UPDATE, 1134 PROTOCOLID_ETH, &init_data); 1135 if (rc != ECORE_SUCCESS) 1136 return rc; 1137 1138 p_ramrod = &p_ent->ramrod.rx_queue_update; 1139 p_ramrod->vport_id = p_cid->abs.vport_id; 1140 1141 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id); 1142 p_ramrod->complete_cqe_flg = 0; 1143 p_ramrod->complete_event_flg = 1; 1144 p_ramrod->set_default_rss_queue = 1; 1145 1146 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 1147 1148 return rc; 1149 } 1150 1151 static enum _ecore_status_t 1152 ecore_eth_pf_rx_queue_stop(struct ecore_hwfn *p_hwfn, 1153 struct ecore_queue_cid *p_cid, 1154 bool b_eq_completion_only, 1155 bool b_cqe_completion) 1156 { 1157 struct rx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL; 1158 struct ecore_spq_entry *p_ent = OSAL_NULL; 1159 struct ecore_sp_init_data init_data; 1160 enum _ecore_status_t rc; 1161 1162 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 1163 init_data.cid = p_cid->cid; 1164 init_data.opaque_fid = p_cid->opaque_fid; 1165 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 1166 1167 rc = ecore_sp_init_request(p_hwfn, &p_ent, 1168 ETH_RAMROD_RX_QUEUE_STOP, 1169 PROTOCOLID_ETH, &init_data); 1170 if (rc != ECORE_SUCCESS) 1171 return rc; 1172 1173 p_ramrod = &p_ent->ramrod.rx_queue_stop; 1174 p_ramrod->vport_id = p_cid->abs.vport_id; 1175 p_ramrod->rx_queue_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id); 1176 1177 /* Cleaning the queue requires the completion to arrive there. 1178 * In addition, VFs require the answer to come as eqe to PF. 1179 */ 1180 p_ramrod->complete_cqe_flg = ((p_cid->vfid == ECORE_QUEUE_CID_PF) && 1181 !b_eq_completion_only) || 1182 b_cqe_completion; 1183 p_ramrod->complete_event_flg = (p_cid->vfid != ECORE_QUEUE_CID_PF) || 1184 b_eq_completion_only; 1185 1186 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 1187 } 1188 1189 enum _ecore_status_t ecore_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn, 1190 void *p_rxq, 1191 bool eq_completion_only, 1192 bool cqe_completion) 1193 { 1194 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_rxq; 1195 enum _ecore_status_t rc = ECORE_NOTIMPL; 1196 1197 if (IS_PF(p_hwfn->p_dev)) 1198 rc = ecore_eth_pf_rx_queue_stop(p_hwfn, p_cid, 1199 eq_completion_only, 1200 cqe_completion); 1201 else 1202 rc = ecore_vf_pf_rxq_stop(p_hwfn, p_cid, cqe_completion); 1203 1204 if (rc == ECORE_SUCCESS) 1205 ecore_eth_queue_cid_release(p_hwfn, p_cid); 1206 return rc; 1207 } 1208 1209 enum _ecore_status_t 1210 ecore_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn, 1211 struct ecore_queue_cid *p_cid, 1212 dma_addr_t pbl_addr, u16 pbl_size, 1213 u16 pq_id) 1214 { 1215 struct tx_queue_start_ramrod_data *p_ramrod = OSAL_NULL; 1216 struct ecore_spq_entry *p_ent = OSAL_NULL; 1217 struct ecore_sp_init_data init_data; 1218 enum _ecore_status_t rc = ECORE_NOTIMPL; 1219 1220 /* Get SPQ entry */ 1221 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 1222 init_data.cid = p_cid->cid; 1223 init_data.opaque_fid = p_cid->opaque_fid; 1224 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 1225 1226 rc = ecore_sp_init_request(p_hwfn, &p_ent, 1227 ETH_RAMROD_TX_QUEUE_START, 1228 PROTOCOLID_ETH, &init_data); 1229 if (rc != ECORE_SUCCESS) 1230 return rc; 1231 1232 p_ramrod = &p_ent->ramrod.tx_queue_start; 1233 p_ramrod->vport_id = p_cid->abs.vport_id; 1234 1235 p_ramrod->sb_id = OSAL_CPU_TO_LE16(p_cid->sb_igu_id); 1236 p_ramrod->sb_index = p_cid->sb_idx; 1237 p_ramrod->stats_counter_id = p_cid->abs.stats_id; 1238 1239 p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id); 1240 p_ramrod->same_as_last_id = OSAL_CPU_TO_LE16(p_cid->abs.queue_id); 1241 1242 p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size); 1243 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr); 1244 1245 p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id); 1246 1247 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 1248 } 1249 1250 static enum _ecore_status_t 1251 ecore_eth_pf_tx_queue_start(struct ecore_hwfn *p_hwfn, 1252 struct ecore_queue_cid *p_cid, 1253 u8 tc, 1254 dma_addr_t pbl_addr, u16 pbl_size, 1255 void OSAL_IOMEM **pp_doorbell) 1256 { 1257 enum _ecore_status_t rc; 1258 1259 /* TODO - set tc in the pq_params for multi-cos */ 1260 rc = ecore_eth_txq_start_ramrod(p_hwfn, p_cid, 1261 pbl_addr, pbl_size, 1262 ecore_get_cm_pq_idx_mcos(p_hwfn, tc)); 1263 if (rc != ECORE_SUCCESS) 1264 return rc; 1265 1266 /* Provide the caller with the necessary return values */ 1267 *pp_doorbell = (u8 OSAL_IOMEM *) 1268 p_hwfn->doorbells + 1269 DB_ADDR(p_cid->cid, DQ_DEMS_LEGACY); 1270 1271 return ECORE_SUCCESS; 1272 } 1273 1274 enum _ecore_status_t 1275 ecore_eth_tx_queue_start(struct ecore_hwfn *p_hwfn, u16 opaque_fid, 1276 struct ecore_queue_start_common_params *p_params, 1277 u8 tc, 1278 dma_addr_t pbl_addr, u16 pbl_size, 1279 struct ecore_txq_start_ret_params *p_ret_params) 1280 { 1281 struct ecore_queue_cid *p_cid; 1282 enum _ecore_status_t rc; 1283 1284 p_cid = ecore_eth_queue_to_cid_pf(p_hwfn, opaque_fid, false, p_params); 1285 if (p_cid == OSAL_NULL) 1286 return ECORE_INVAL; 1287 1288 if (IS_PF(p_hwfn->p_dev)) 1289 rc = ecore_eth_pf_tx_queue_start(p_hwfn, p_cid, tc, 1290 pbl_addr, pbl_size, 1291 &p_ret_params->p_doorbell); 1292 else 1293 rc = ecore_vf_pf_txq_start(p_hwfn, p_cid, 1294 pbl_addr, pbl_size, 1295 &p_ret_params->p_doorbell); 1296 1297 if (rc != ECORE_SUCCESS) 1298 ecore_eth_queue_cid_release(p_hwfn, p_cid); 1299 else 1300 p_ret_params->p_handle = (void *)p_cid; 1301 1302 return rc; 1303 } 1304 1305 static enum _ecore_status_t 1306 ecore_eth_pf_tx_queue_stop(struct ecore_hwfn *p_hwfn, 1307 struct ecore_queue_cid *p_cid) 1308 { 1309 struct ecore_spq_entry *p_ent = OSAL_NULL; 1310 struct ecore_sp_init_data init_data; 1311 enum _ecore_status_t rc; 1312 1313 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 1314 init_data.cid = p_cid->cid; 1315 init_data.opaque_fid = p_cid->opaque_fid; 1316 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 1317 1318 rc = ecore_sp_init_request(p_hwfn, &p_ent, 1319 ETH_RAMROD_TX_QUEUE_STOP, 1320 PROTOCOLID_ETH, &init_data); 1321 if (rc != ECORE_SUCCESS) 1322 return rc; 1323 1324 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 1325 } 1326 1327 enum _ecore_status_t ecore_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn, 1328 void *p_handle) 1329 { 1330 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)p_handle; 1331 enum _ecore_status_t rc; 1332 1333 if (IS_PF(p_hwfn->p_dev)) 1334 rc = ecore_eth_pf_tx_queue_stop(p_hwfn, p_cid); 1335 else 1336 rc = ecore_vf_pf_txq_stop(p_hwfn, p_cid); 1337 1338 if (rc == ECORE_SUCCESS) 1339 ecore_eth_queue_cid_release(p_hwfn, p_cid); 1340 return rc; 1341 } 1342 1343 static enum eth_filter_action ecore_filter_action(enum ecore_filter_opcode opcode) 1344 { 1345 enum eth_filter_action action = MAX_ETH_FILTER_ACTION; 1346 1347 switch (opcode) { 1348 case ECORE_FILTER_ADD: 1349 action = ETH_FILTER_ACTION_ADD; 1350 break; 1351 case ECORE_FILTER_REMOVE: 1352 action = ETH_FILTER_ACTION_REMOVE; 1353 break; 1354 case ECORE_FILTER_FLUSH: 1355 action = ETH_FILTER_ACTION_REMOVE_ALL; 1356 break; 1357 default: 1358 action = MAX_ETH_FILTER_ACTION; 1359 } 1360 1361 return action; 1362 } 1363 1364 static enum _ecore_status_t 1365 ecore_filter_ucast_common(struct ecore_hwfn *p_hwfn, 1366 u16 opaque_fid, 1367 struct ecore_filter_ucast *p_filter_cmd, 1368 struct vport_filter_update_ramrod_data **pp_ramrod, 1369 struct ecore_spq_entry **pp_ent, 1370 enum spq_mode comp_mode, 1371 struct ecore_spq_comp_cb *p_comp_data) 1372 { 1373 u8 vport_to_add_to = 0, vport_to_remove_from = 0; 1374 struct vport_filter_update_ramrod_data *p_ramrod; 1375 struct eth_filter_cmd *p_first_filter; 1376 struct eth_filter_cmd *p_second_filter; 1377 struct ecore_sp_init_data init_data; 1378 enum eth_filter_action action; 1379 enum _ecore_status_t rc; 1380 1381 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1382 &vport_to_remove_from); 1383 if (rc != ECORE_SUCCESS) 1384 return rc; 1385 1386 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1387 &vport_to_add_to); 1388 if (rc != ECORE_SUCCESS) 1389 return rc; 1390 1391 /* Get SPQ entry */ 1392 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 1393 init_data.cid = ecore_spq_get_cid(p_hwfn); 1394 init_data.opaque_fid = opaque_fid; 1395 init_data.comp_mode = comp_mode; 1396 init_data.p_comp_data = p_comp_data; 1397 1398 rc = ecore_sp_init_request(p_hwfn, pp_ent, 1399 ETH_RAMROD_FILTERS_UPDATE, 1400 PROTOCOLID_ETH, &init_data); 1401 if (rc != ECORE_SUCCESS) 1402 return rc; 1403 1404 *pp_ramrod = &(*pp_ent)->ramrod.vport_filter_update; 1405 p_ramrod = *pp_ramrod; 1406 p_ramrod->filter_cmd_hdr.rx = p_filter_cmd->is_rx_filter ? 1 : 0; 1407 p_ramrod->filter_cmd_hdr.tx = p_filter_cmd->is_tx_filter ? 1 : 0; 1408 1409 #ifndef ASIC_ONLY 1410 if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) { 1411 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 1412 "Non-Asic - prevent Tx filters\n"); 1413 p_ramrod->filter_cmd_hdr.tx = 0; 1414 } 1415 1416 #endif 1417 1418 switch (p_filter_cmd->opcode) { 1419 case ECORE_FILTER_REPLACE: 1420 case ECORE_FILTER_MOVE: 1421 p_ramrod->filter_cmd_hdr.cmd_cnt = 2; break; 1422 default: 1423 p_ramrod->filter_cmd_hdr.cmd_cnt = 1; break; 1424 } 1425 1426 p_first_filter = &p_ramrod->filter_cmds[0]; 1427 p_second_filter = &p_ramrod->filter_cmds[1]; 1428 1429 switch (p_filter_cmd->type) { 1430 case ECORE_FILTER_MAC: 1431 p_first_filter->type = ETH_FILTER_TYPE_MAC; break; 1432 case ECORE_FILTER_VLAN: 1433 p_first_filter->type = ETH_FILTER_TYPE_VLAN; break; 1434 case ECORE_FILTER_MAC_VLAN: 1435 p_first_filter->type = ETH_FILTER_TYPE_PAIR; break; 1436 case ECORE_FILTER_INNER_MAC: 1437 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC; break; 1438 case ECORE_FILTER_INNER_VLAN: 1439 p_first_filter->type = ETH_FILTER_TYPE_INNER_VLAN; break; 1440 case ECORE_FILTER_INNER_PAIR: 1441 p_first_filter->type = ETH_FILTER_TYPE_INNER_PAIR; break; 1442 case ECORE_FILTER_INNER_MAC_VNI_PAIR: 1443 p_first_filter->type = ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR; 1444 break; 1445 case ECORE_FILTER_MAC_VNI_PAIR: 1446 p_first_filter->type = ETH_FILTER_TYPE_MAC_VNI_PAIR; break; 1447 case ECORE_FILTER_VNI: 1448 p_first_filter->type = ETH_FILTER_TYPE_VNI; break; 1449 } 1450 1451 if ((p_first_filter->type == ETH_FILTER_TYPE_MAC) || 1452 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1453 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC) || 1454 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR) || 1455 (p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1456 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR)) 1457 ecore_set_fw_mac_addr(&p_first_filter->mac_msb, 1458 &p_first_filter->mac_mid, 1459 &p_first_filter->mac_lsb, 1460 (u8 *)p_filter_cmd->mac); 1461 1462 if ((p_first_filter->type == ETH_FILTER_TYPE_VLAN) || 1463 (p_first_filter->type == ETH_FILTER_TYPE_PAIR) || 1464 (p_first_filter->type == ETH_FILTER_TYPE_INNER_VLAN) || 1465 (p_first_filter->type == ETH_FILTER_TYPE_INNER_PAIR)) 1466 p_first_filter->vlan_id = OSAL_CPU_TO_LE16(p_filter_cmd->vlan); 1467 1468 if ((p_first_filter->type == ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR) || 1469 (p_first_filter->type == ETH_FILTER_TYPE_MAC_VNI_PAIR) || 1470 (p_first_filter->type == ETH_FILTER_TYPE_VNI)) 1471 p_first_filter->vni = OSAL_CPU_TO_LE32(p_filter_cmd->vni); 1472 1473 if (p_filter_cmd->opcode == ECORE_FILTER_MOVE) { 1474 p_second_filter->type = p_first_filter->type; 1475 p_second_filter->mac_msb = p_first_filter->mac_msb; 1476 p_second_filter->mac_mid = p_first_filter->mac_mid; 1477 p_second_filter->mac_lsb = p_first_filter->mac_lsb; 1478 p_second_filter->vlan_id = p_first_filter->vlan_id; 1479 p_second_filter->vni = p_first_filter->vni; 1480 1481 p_first_filter->action = ETH_FILTER_ACTION_REMOVE; 1482 1483 p_first_filter->vport_id = vport_to_remove_from; 1484 1485 p_second_filter->action = ETH_FILTER_ACTION_ADD; 1486 p_second_filter->vport_id = vport_to_add_to; 1487 } else if (p_filter_cmd->opcode == ECORE_FILTER_REPLACE) { 1488 p_first_filter->vport_id = vport_to_add_to; 1489 OSAL_MEMCPY(p_second_filter, p_first_filter, 1490 sizeof(*p_second_filter)); 1491 p_first_filter->action = ETH_FILTER_ACTION_REMOVE_ALL; 1492 p_second_filter->action = ETH_FILTER_ACTION_ADD; 1493 } else { 1494 action = ecore_filter_action(p_filter_cmd->opcode); 1495 1496 if (action == MAX_ETH_FILTER_ACTION) { 1497 DP_NOTICE(p_hwfn, true, 1498 "%d is not supported yet\n", 1499 p_filter_cmd->opcode); 1500 return ECORE_NOTIMPL; 1501 } 1502 1503 p_first_filter->action = action; 1504 p_first_filter->vport_id = 1505 (p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ? 1506 vport_to_remove_from : vport_to_add_to; 1507 } 1508 1509 return ECORE_SUCCESS; 1510 } 1511 1512 enum _ecore_status_t ecore_sp_eth_filter_ucast(struct ecore_hwfn *p_hwfn, 1513 u16 opaque_fid, 1514 struct ecore_filter_ucast *p_filter_cmd, 1515 enum spq_mode comp_mode, 1516 struct ecore_spq_comp_cb *p_comp_data) 1517 { 1518 struct vport_filter_update_ramrod_data *p_ramrod = OSAL_NULL; 1519 struct ecore_spq_entry *p_ent = OSAL_NULL; 1520 struct eth_filter_cmd_header *p_header; 1521 enum _ecore_status_t rc; 1522 1523 rc = ecore_filter_ucast_common(p_hwfn, opaque_fid, p_filter_cmd, 1524 &p_ramrod, &p_ent, 1525 comp_mode, p_comp_data); 1526 if (rc != ECORE_SUCCESS) { 1527 DP_ERR(p_hwfn, "Uni. filter command failed %d\n", rc); 1528 return rc; 1529 } 1530 p_header = &p_ramrod->filter_cmd_hdr; 1531 p_header->assert_on_error = p_filter_cmd->assert_on_error; 1532 1533 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 1534 if (rc != ECORE_SUCCESS) { 1535 DP_ERR(p_hwfn, 1536 "Unicast filter ADD command failed %d\n", 1537 rc); 1538 return rc; 1539 } 1540 1541 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 1542 "Unicast filter configured, opcode = %s, type = %s, cmd_cnt = %d, is_rx_filter = %d, is_tx_filter = %d\n", 1543 (p_filter_cmd->opcode == ECORE_FILTER_ADD) ? "ADD" : 1544 ((p_filter_cmd->opcode == ECORE_FILTER_REMOVE) ? 1545 "REMOVE" : 1546 ((p_filter_cmd->opcode == ECORE_FILTER_MOVE) ? 1547 "MOVE" : "REPLACE")), 1548 (p_filter_cmd->type == ECORE_FILTER_MAC) ? "MAC" : 1549 ((p_filter_cmd->type == ECORE_FILTER_VLAN) ? 1550 "VLAN" : "MAC & VLAN"), 1551 p_ramrod->filter_cmd_hdr.cmd_cnt, 1552 p_filter_cmd->is_rx_filter, 1553 p_filter_cmd->is_tx_filter); 1554 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 1555 "vport_to_add_to = %d, vport_to_remove_from = %d, mac = %2x:%2x:%2x:%2x:%2x:%2x, vlan = %d\n", 1556 p_filter_cmd->vport_to_add_to, 1557 p_filter_cmd->vport_to_remove_from, 1558 p_filter_cmd->mac[0], p_filter_cmd->mac[1], 1559 p_filter_cmd->mac[2], p_filter_cmd->mac[3], 1560 p_filter_cmd->mac[4], p_filter_cmd->mac[5], 1561 p_filter_cmd->vlan); 1562 1563 return ECORE_SUCCESS; 1564 } 1565 1566 /******************************************************************************* 1567 * Description: 1568 * Calculates crc 32 on a buffer 1569 * Note: crc32_length MUST be aligned to 8 1570 * Return: 1571 ******************************************************************************/ 1572 static u32 ecore_calc_crc32c(u8 *crc32_packet, u32 crc32_length, u32 crc32_seed) 1573 { 1574 u32 byte = 0, bit = 0, crc32_result = crc32_seed; 1575 u8 msb = 0, current_byte = 0; 1576 1577 if ((crc32_packet == OSAL_NULL) || 1578 (crc32_length == 0) || 1579 ((crc32_length % 8) != 0)) { 1580 return crc32_result; 1581 } 1582 1583 for (byte = 0; byte < crc32_length; byte++) { 1584 current_byte = crc32_packet[byte]; 1585 for (bit = 0; bit < 8; bit++) { 1586 msb = (u8)(crc32_result >> 31); 1587 crc32_result = crc32_result << 1; 1588 if (msb != (0x1 & (current_byte >> bit))) { 1589 crc32_result = crc32_result ^ CRC32_POLY; 1590 crc32_result |= 1; /*crc32_result[0] = 1;*/ 1591 } 1592 } 1593 } 1594 1595 return crc32_result; 1596 } 1597 1598 static u32 ecore_crc32c_le(u32 seed, u8 *mac) 1599 { 1600 u32 packet_buf[2] = {0}; 1601 1602 OSAL_MEMCPY((u8 *)(&packet_buf[0]), &mac[0], 6); 1603 return ecore_calc_crc32c((u8 *)packet_buf, 8, seed); 1604 } 1605 1606 u8 ecore_mcast_bin_from_mac(u8 *mac) 1607 { 1608 u32 crc = ecore_crc32c_le(ETH_MULTICAST_BIN_FROM_MAC_SEED, mac); 1609 1610 return crc & 0xff; 1611 } 1612 1613 static enum _ecore_status_t 1614 ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn, 1615 struct ecore_filter_mcast *p_filter_cmd, 1616 enum spq_mode comp_mode, 1617 struct ecore_spq_comp_cb *p_comp_data) 1618 { 1619 struct vport_update_ramrod_data *p_ramrod = OSAL_NULL; 1620 u32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 1621 struct ecore_spq_entry *p_ent = OSAL_NULL; 1622 struct ecore_sp_init_data init_data; 1623 u8 abs_vport_id = 0; 1624 enum _ecore_status_t rc; 1625 int i; 1626 1627 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) 1628 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_add_to, 1629 &abs_vport_id); 1630 else 1631 rc = ecore_fw_vport(p_hwfn, p_filter_cmd->vport_to_remove_from, 1632 &abs_vport_id); 1633 if (rc != ECORE_SUCCESS) 1634 return rc; 1635 1636 /* Get SPQ entry */ 1637 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 1638 init_data.cid = ecore_spq_get_cid(p_hwfn); 1639 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1640 init_data.comp_mode = comp_mode; 1641 init_data.p_comp_data = p_comp_data; 1642 1643 rc = ecore_sp_init_request(p_hwfn, &p_ent, 1644 ETH_RAMROD_VPORT_UPDATE, 1645 PROTOCOLID_ETH, &init_data); 1646 if (rc != ECORE_SUCCESS) { 1647 DP_ERR(p_hwfn, "Multi-cast command failed %d\n", rc); 1648 return rc; 1649 } 1650 1651 p_ramrod = &p_ent->ramrod.vport_update; 1652 p_ramrod->common.update_approx_mcast_flg = 1; 1653 1654 /* explicitly clear out the entire vector */ 1655 OSAL_MEMSET(&p_ramrod->approx_mcast.bins, 1656 0, sizeof(p_ramrod->approx_mcast.bins)); 1657 OSAL_MEMSET(bins, 0, sizeof(u32) * ETH_MULTICAST_MAC_BINS_IN_REGS); 1658 /* filter ADD op is explicit set op and it removes 1659 * any existing filters for the vport. 1660 */ 1661 if (p_filter_cmd->opcode == ECORE_FILTER_ADD) { 1662 for (i = 0; i < p_filter_cmd->num_mc_addrs; i++) { 1663 u32 bit; 1664 1665 bit = ecore_mcast_bin_from_mac(p_filter_cmd->mac[i]); 1666 bins[bit / 32] |= 1 << (bit % 32); 1667 } 1668 1669 /* Convert to correct endianity */ 1670 for (i = 0; i < ETH_MULTICAST_MAC_BINS_IN_REGS; i++) { 1671 struct vport_update_ramrod_mcast *p_ramrod_bins; 1672 1673 p_ramrod_bins = &p_ramrod->approx_mcast; 1674 p_ramrod_bins->bins[i] = OSAL_CPU_TO_LE32(bins[i]); 1675 } 1676 } 1677 1678 p_ramrod->common.vport_id = abs_vport_id; 1679 1680 rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 1681 if (rc != ECORE_SUCCESS) 1682 DP_ERR(p_hwfn, "Multicast filter command failed %d\n", rc); 1683 1684 return rc; 1685 } 1686 1687 enum _ecore_status_t ecore_filter_mcast_cmd(struct ecore_dev *p_dev, 1688 struct ecore_filter_mcast *p_filter_cmd, 1689 enum spq_mode comp_mode, 1690 struct ecore_spq_comp_cb *p_comp_data) 1691 { 1692 enum _ecore_status_t rc = ECORE_SUCCESS; 1693 int i; 1694 1695 /* only ADD and REMOVE operations are supported for multi-cast */ 1696 if ((p_filter_cmd->opcode != ECORE_FILTER_ADD && 1697 (p_filter_cmd->opcode != ECORE_FILTER_REMOVE)) || 1698 (p_filter_cmd->num_mc_addrs > ECORE_MAX_MC_ADDRS)) { 1699 return ECORE_INVAL; 1700 } 1701 1702 for_each_hwfn(p_dev, i) { 1703 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1704 1705 if (IS_VF(p_dev)) { 1706 ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd); 1707 continue; 1708 } 1709 1710 rc = ecore_sp_eth_filter_mcast(p_hwfn, 1711 p_filter_cmd, 1712 comp_mode, 1713 p_comp_data); 1714 if (rc != ECORE_SUCCESS) 1715 break; 1716 } 1717 1718 return rc; 1719 } 1720 1721 enum _ecore_status_t ecore_filter_ucast_cmd(struct ecore_dev *p_dev, 1722 struct ecore_filter_ucast *p_filter_cmd, 1723 enum spq_mode comp_mode, 1724 struct ecore_spq_comp_cb *p_comp_data) 1725 { 1726 enum _ecore_status_t rc = ECORE_SUCCESS; 1727 int i; 1728 1729 for_each_hwfn(p_dev, i) { 1730 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 1731 u16 opaque_fid; 1732 1733 if (IS_VF(p_dev)) { 1734 rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd); 1735 continue; 1736 } 1737 1738 opaque_fid = p_hwfn->hw_info.opaque_fid; 1739 rc = ecore_sp_eth_filter_ucast(p_hwfn, 1740 opaque_fid, 1741 p_filter_cmd, 1742 comp_mode, 1743 p_comp_data); 1744 if (rc != ECORE_SUCCESS) 1745 break; 1746 } 1747 1748 return rc; 1749 } 1750 1751 /* Statistics related code */ 1752 static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn, 1753 u32 *p_addr, u32 *p_len, 1754 u16 statistics_bin) 1755 { 1756 if (IS_PF(p_hwfn->p_dev)) { 1757 *p_addr = BAR0_MAP_REG_PSDM_RAM + 1758 PSTORM_QUEUE_STAT_OFFSET(statistics_bin); 1759 *p_len = sizeof(struct eth_pstorm_per_queue_stat); 1760 } else { 1761 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info; 1762 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1763 1764 *p_addr = p_resp->pfdev_info.stats_info.pstats.address; 1765 *p_len = p_resp->pfdev_info.stats_info.pstats.len; 1766 } 1767 } 1768 1769 static void __ecore_get_vport_pstats(struct ecore_hwfn *p_hwfn, 1770 struct ecore_ptt *p_ptt, 1771 struct ecore_eth_stats *p_stats, 1772 u16 statistics_bin) 1773 { 1774 struct eth_pstorm_per_queue_stat pstats; 1775 u32 pstats_addr = 0, pstats_len = 0; 1776 1777 __ecore_get_vport_pstats_addrlen(p_hwfn, &pstats_addr, &pstats_len, 1778 statistics_bin); 1779 1780 OSAL_MEMSET(&pstats, 0, sizeof(pstats)); 1781 ecore_memcpy_from(p_hwfn, p_ptt, &pstats, 1782 pstats_addr, pstats_len); 1783 1784 p_stats->common.tx_ucast_bytes += 1785 HILO_64_REGPAIR(pstats.sent_ucast_bytes); 1786 p_stats->common.tx_mcast_bytes += 1787 HILO_64_REGPAIR(pstats.sent_mcast_bytes); 1788 p_stats->common.tx_bcast_bytes += 1789 HILO_64_REGPAIR(pstats.sent_bcast_bytes); 1790 p_stats->common.tx_ucast_pkts += 1791 HILO_64_REGPAIR(pstats.sent_ucast_pkts); 1792 p_stats->common.tx_mcast_pkts += 1793 HILO_64_REGPAIR(pstats.sent_mcast_pkts); 1794 p_stats->common.tx_bcast_pkts += 1795 HILO_64_REGPAIR(pstats.sent_bcast_pkts); 1796 p_stats->common.tx_err_drop_pkts += 1797 HILO_64_REGPAIR(pstats.error_drop_pkts); 1798 } 1799 1800 static void __ecore_get_vport_tstats(struct ecore_hwfn *p_hwfn, 1801 struct ecore_ptt *p_ptt, 1802 struct ecore_eth_stats *p_stats) 1803 { 1804 struct tstorm_per_port_stat tstats; 1805 u32 tstats_addr, tstats_len; 1806 1807 if (IS_PF(p_hwfn->p_dev)) { 1808 tstats_addr = BAR0_MAP_REG_TSDM_RAM + 1809 TSTORM_PORT_STAT_OFFSET(MFW_PORT(p_hwfn)); 1810 tstats_len = sizeof(struct tstorm_per_port_stat); 1811 } else { 1812 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info; 1813 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1814 1815 tstats_addr = p_resp->pfdev_info.stats_info.tstats.address; 1816 tstats_len = p_resp->pfdev_info.stats_info.tstats.len; 1817 } 1818 1819 OSAL_MEMSET(&tstats, 0, sizeof(tstats)); 1820 ecore_memcpy_from(p_hwfn, p_ptt, &tstats, 1821 tstats_addr, tstats_len); 1822 1823 p_stats->common.mftag_filter_discards += 1824 HILO_64_REGPAIR(tstats.mftag_filter_discard); 1825 p_stats->common.mac_filter_discards += 1826 HILO_64_REGPAIR(tstats.eth_mac_filter_discard); 1827 } 1828 1829 static void __ecore_get_vport_ustats_addrlen(struct ecore_hwfn *p_hwfn, 1830 u32 *p_addr, u32 *p_len, 1831 u16 statistics_bin) 1832 { 1833 if (IS_PF(p_hwfn->p_dev)) { 1834 *p_addr = BAR0_MAP_REG_USDM_RAM + 1835 USTORM_QUEUE_STAT_OFFSET(statistics_bin); 1836 *p_len = sizeof(struct eth_ustorm_per_queue_stat); 1837 } else { 1838 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info; 1839 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1840 1841 *p_addr = p_resp->pfdev_info.stats_info.ustats.address; 1842 *p_len = p_resp->pfdev_info.stats_info.ustats.len; 1843 } 1844 } 1845 1846 static void __ecore_get_vport_ustats(struct ecore_hwfn *p_hwfn, 1847 struct ecore_ptt *p_ptt, 1848 struct ecore_eth_stats *p_stats, 1849 u16 statistics_bin) 1850 { 1851 struct eth_ustorm_per_queue_stat ustats; 1852 u32 ustats_addr = 0, ustats_len = 0; 1853 1854 __ecore_get_vport_ustats_addrlen(p_hwfn, &ustats_addr, &ustats_len, 1855 statistics_bin); 1856 1857 OSAL_MEMSET(&ustats, 0, sizeof(ustats)); 1858 ecore_memcpy_from(p_hwfn, p_ptt, &ustats, 1859 ustats_addr, ustats_len); 1860 1861 p_stats->common.rx_ucast_bytes += 1862 HILO_64_REGPAIR(ustats.rcv_ucast_bytes); 1863 p_stats->common.rx_mcast_bytes += 1864 HILO_64_REGPAIR(ustats.rcv_mcast_bytes); 1865 p_stats->common.rx_bcast_bytes += 1866 HILO_64_REGPAIR(ustats.rcv_bcast_bytes); 1867 p_stats->common.rx_ucast_pkts += 1868 HILO_64_REGPAIR(ustats.rcv_ucast_pkts); 1869 p_stats->common.rx_mcast_pkts += 1870 HILO_64_REGPAIR(ustats.rcv_mcast_pkts); 1871 p_stats->common.rx_bcast_pkts += 1872 HILO_64_REGPAIR(ustats.rcv_bcast_pkts); 1873 } 1874 1875 static void __ecore_get_vport_mstats_addrlen(struct ecore_hwfn *p_hwfn, 1876 u32 *p_addr, u32 *p_len, 1877 u16 statistics_bin) 1878 { 1879 if (IS_PF(p_hwfn->p_dev)) { 1880 *p_addr = BAR0_MAP_REG_MSDM_RAM + 1881 MSTORM_QUEUE_STAT_OFFSET(statistics_bin); 1882 *p_len = sizeof(struct eth_mstorm_per_queue_stat); 1883 } else { 1884 struct ecore_vf_iov *p_iov = p_hwfn->vf_iov_info; 1885 struct pfvf_acquire_resp_tlv *p_resp = &p_iov->acquire_resp; 1886 1887 *p_addr = p_resp->pfdev_info.stats_info.mstats.address; 1888 *p_len = p_resp->pfdev_info.stats_info.mstats.len; 1889 } 1890 } 1891 1892 static void __ecore_get_vport_mstats(struct ecore_hwfn *p_hwfn, 1893 struct ecore_ptt *p_ptt, 1894 struct ecore_eth_stats *p_stats, 1895 u16 statistics_bin) 1896 { 1897 struct eth_mstorm_per_queue_stat mstats; 1898 u32 mstats_addr = 0, mstats_len = 0; 1899 1900 __ecore_get_vport_mstats_addrlen(p_hwfn, &mstats_addr, &mstats_len, 1901 statistics_bin); 1902 1903 OSAL_MEMSET(&mstats, 0, sizeof(mstats)); 1904 ecore_memcpy_from(p_hwfn, p_ptt, &mstats, 1905 mstats_addr, mstats_len); 1906 1907 p_stats->common.no_buff_discards += 1908 HILO_64_REGPAIR(mstats.no_buff_discard); 1909 p_stats->common.packet_too_big_discard += 1910 HILO_64_REGPAIR(mstats.packet_too_big_discard); 1911 p_stats->common.ttl0_discard += 1912 HILO_64_REGPAIR(mstats.ttl0_discard); 1913 p_stats->common.tpa_coalesced_pkts += 1914 HILO_64_REGPAIR(mstats.tpa_coalesced_pkts); 1915 p_stats->common.tpa_coalesced_events += 1916 HILO_64_REGPAIR(mstats.tpa_coalesced_events); 1917 p_stats->common.tpa_aborts_num += 1918 HILO_64_REGPAIR(mstats.tpa_aborts_num); 1919 p_stats->common.tpa_coalesced_bytes += 1920 HILO_64_REGPAIR(mstats.tpa_coalesced_bytes); 1921 } 1922 1923 static void __ecore_get_vport_port_stats(struct ecore_hwfn *p_hwfn, 1924 struct ecore_ptt *p_ptt, 1925 struct ecore_eth_stats *p_stats) 1926 { 1927 struct ecore_eth_stats_common *p_common = &p_stats->common; 1928 struct port_stats port_stats; 1929 int j; 1930 1931 OSAL_MEMSET(&port_stats, 0, sizeof(port_stats)); 1932 1933 ecore_memcpy_from(p_hwfn, p_ptt, &port_stats, 1934 p_hwfn->mcp_info->port_addr + 1935 OFFSETOF(struct public_port, stats), 1936 sizeof(port_stats)); 1937 1938 p_common->rx_64_byte_packets += port_stats.eth.r64; 1939 p_common->rx_65_to_127_byte_packets += port_stats.eth.r127; 1940 p_common->rx_128_to_255_byte_packets += port_stats.eth.r255; 1941 p_common->rx_256_to_511_byte_packets += port_stats.eth.r511; 1942 p_common->rx_512_to_1023_byte_packets += port_stats.eth.r1023; 1943 p_common->rx_1024_to_1518_byte_packets += port_stats.eth.r1518; 1944 p_common->rx_crc_errors += port_stats.eth.rfcs; 1945 p_common->rx_mac_crtl_frames += port_stats.eth.rxcf; 1946 p_common->rx_pause_frames += port_stats.eth.rxpf; 1947 p_common->rx_pfc_frames += port_stats.eth.rxpp; 1948 p_common->rx_align_errors += port_stats.eth.raln; 1949 p_common->rx_carrier_errors += port_stats.eth.rfcr; 1950 p_common->rx_oversize_packets += port_stats.eth.rovr; 1951 p_common->rx_jabbers += port_stats.eth.rjbr; 1952 p_common->rx_undersize_packets += port_stats.eth.rund; 1953 p_common->rx_fragments += port_stats.eth.rfrg; 1954 p_common->tx_64_byte_packets += port_stats.eth.t64; 1955 p_common->tx_65_to_127_byte_packets += port_stats.eth.t127; 1956 p_common->tx_128_to_255_byte_packets += port_stats.eth.t255; 1957 p_common->tx_256_to_511_byte_packets += port_stats.eth.t511; 1958 p_common->tx_512_to_1023_byte_packets += port_stats.eth.t1023; 1959 p_common->tx_1024_to_1518_byte_packets += port_stats.eth.t1518; 1960 p_common->tx_pause_frames += port_stats.eth.txpf; 1961 p_common->tx_pfc_frames += port_stats.eth.txpp; 1962 p_common->rx_mac_bytes += port_stats.eth.rbyte; 1963 p_common->rx_mac_uc_packets += port_stats.eth.rxuca; 1964 p_common->rx_mac_mc_packets += port_stats.eth.rxmca; 1965 p_common->rx_mac_bc_packets += port_stats.eth.rxbca; 1966 p_common->rx_mac_frames_ok += port_stats.eth.rxpok; 1967 p_common->tx_mac_bytes += port_stats.eth.tbyte; 1968 p_common->tx_mac_uc_packets += port_stats.eth.txuca; 1969 p_common->tx_mac_mc_packets += port_stats.eth.txmca; 1970 p_common->tx_mac_bc_packets += port_stats.eth.txbca; 1971 p_common->tx_mac_ctrl_frames += port_stats.eth.txcf; 1972 for (j = 0; j < 8; j++) { 1973 p_common->brb_truncates += port_stats.brb.brb_truncate[j]; 1974 p_common->brb_discards += port_stats.brb.brb_discard[j]; 1975 } 1976 1977 if (ECORE_IS_BB(p_hwfn->p_dev)) { 1978 struct ecore_eth_stats_bb *p_bb = &p_stats->bb; 1979 1980 p_bb->rx_1519_to_1522_byte_packets += 1981 port_stats.eth.u0.bb0.r1522; 1982 p_bb->rx_1519_to_2047_byte_packets += 1983 port_stats.eth.u0.bb0.r2047; 1984 p_bb->rx_2048_to_4095_byte_packets += 1985 port_stats.eth.u0.bb0.r4095; 1986 p_bb->rx_4096_to_9216_byte_packets += 1987 port_stats.eth.u0.bb0.r9216; 1988 p_bb->rx_9217_to_16383_byte_packets += 1989 port_stats.eth.u0.bb0.r16383; 1990 p_bb->tx_1519_to_2047_byte_packets += 1991 port_stats.eth.u1.bb1.t2047; 1992 p_bb->tx_2048_to_4095_byte_packets += 1993 port_stats.eth.u1.bb1.t4095; 1994 p_bb->tx_4096_to_9216_byte_packets += 1995 port_stats.eth.u1.bb1.t9216; 1996 p_bb->tx_9217_to_16383_byte_packets += 1997 port_stats.eth.u1.bb1.t16383; 1998 p_bb->tx_lpi_entry_count += port_stats.eth.u2.bb2.tlpiec; 1999 p_bb->tx_total_collisions += port_stats.eth.u2.bb2.tncl; 2000 } else { 2001 struct ecore_eth_stats_ah *p_ah = &p_stats->ah; 2002 2003 p_ah->rx_1519_to_max_byte_packets += 2004 port_stats.eth.u0.ah0.r1519_to_max; 2005 p_ah->tx_1519_to_max_byte_packets = 2006 port_stats.eth.u1.ah1.t1519_to_max; 2007 } 2008 2009 p_common->link_change_count = ecore_rd(p_hwfn, p_ptt, 2010 p_hwfn->mcp_info->port_addr + 2011 OFFSETOF(struct public_port, 2012 link_change_count)); 2013 } 2014 2015 void __ecore_get_vport_stats(struct ecore_hwfn *p_hwfn, 2016 struct ecore_ptt *p_ptt, 2017 struct ecore_eth_stats *stats, 2018 u16 statistics_bin, bool b_get_port_stats) 2019 { 2020 __ecore_get_vport_mstats(p_hwfn, p_ptt, stats, statistics_bin); 2021 __ecore_get_vport_ustats(p_hwfn, p_ptt, stats, statistics_bin); 2022 __ecore_get_vport_tstats(p_hwfn, p_ptt, stats); 2023 __ecore_get_vport_pstats(p_hwfn, p_ptt, stats, statistics_bin); 2024 2025 #ifndef ASIC_ONLY 2026 /* Avoid getting PORT stats for emulation.*/ 2027 if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) 2028 return; 2029 #endif 2030 2031 if (b_get_port_stats && p_hwfn->mcp_info) 2032 __ecore_get_vport_port_stats(p_hwfn, p_ptt, stats); 2033 } 2034 2035 static void _ecore_get_vport_stats(struct ecore_dev *p_dev, 2036 struct ecore_eth_stats *stats) 2037 { 2038 u8 fw_vport = 0; 2039 int i; 2040 2041 OSAL_MEMSET(stats, 0, sizeof(*stats)); 2042 2043 for_each_hwfn(p_dev, i) { 2044 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 2045 struct ecore_ptt *p_ptt = IS_PF(p_dev) ? 2046 ecore_ptt_acquire(p_hwfn) : OSAL_NULL; 2047 bool b_get_port_stats; 2048 2049 if (IS_PF(p_dev)) { 2050 /* The main vport index is relative first */ 2051 if (ecore_fw_vport(p_hwfn, 0, &fw_vport)) { 2052 DP_ERR(p_hwfn, "No vport available!\n"); 2053 goto out; 2054 } 2055 } 2056 2057 if (IS_PF(p_dev) && !p_ptt) { 2058 DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 2059 continue; 2060 } 2061 2062 b_get_port_stats = IS_PF(p_dev) && IS_LEAD_HWFN(p_hwfn); 2063 __ecore_get_vport_stats(p_hwfn, p_ptt, stats, fw_vport, 2064 b_get_port_stats); 2065 2066 out: 2067 if (IS_PF(p_dev) && p_ptt) 2068 ecore_ptt_release(p_hwfn, p_ptt); 2069 } 2070 } 2071 2072 void ecore_get_vport_stats(struct ecore_dev *p_dev, 2073 struct ecore_eth_stats *stats) 2074 { 2075 u32 i; 2076 2077 if (!p_dev) { 2078 OSAL_MEMSET(stats, 0, sizeof(*stats)); 2079 return; 2080 } 2081 2082 _ecore_get_vport_stats(p_dev, stats); 2083 2084 if (!p_dev->reset_stats) 2085 return; 2086 2087 /* Reduce the statistics baseline */ 2088 for (i = 0; i < sizeof(struct ecore_eth_stats) / sizeof(u64); i++) 2089 ((u64 *)stats)[i] -= ((u64 *)p_dev->reset_stats)[i]; 2090 } 2091 2092 /* zeroes V-PORT specific portion of stats (Port stats remains untouched) */ 2093 void ecore_reset_vport_stats(struct ecore_dev *p_dev) 2094 { 2095 int i; 2096 2097 for_each_hwfn(p_dev, i) { 2098 struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i]; 2099 struct eth_mstorm_per_queue_stat mstats; 2100 struct eth_ustorm_per_queue_stat ustats; 2101 struct eth_pstorm_per_queue_stat pstats; 2102 struct ecore_ptt *p_ptt = IS_PF(p_dev) ? 2103 ecore_ptt_acquire(p_hwfn) : OSAL_NULL; 2104 u32 addr = 0, len = 0; 2105 2106 if (IS_PF(p_dev) && !p_ptt) { 2107 DP_ERR(p_hwfn, "Failed to acquire ptt\n"); 2108 continue; 2109 } 2110 2111 OSAL_MEMSET(&mstats, 0, sizeof(mstats)); 2112 __ecore_get_vport_mstats_addrlen(p_hwfn, &addr, &len, 0); 2113 ecore_memcpy_to(p_hwfn, p_ptt, addr, &mstats, len); 2114 2115 OSAL_MEMSET(&ustats, 0, sizeof(ustats)); 2116 __ecore_get_vport_ustats_addrlen(p_hwfn, &addr, &len, 0); 2117 ecore_memcpy_to(p_hwfn, p_ptt, addr, &ustats, len); 2118 2119 OSAL_MEMSET(&pstats, 0, sizeof(pstats)); 2120 __ecore_get_vport_pstats_addrlen(p_hwfn, &addr, &len, 0); 2121 ecore_memcpy_to(p_hwfn, p_ptt, addr, &pstats, len); 2122 2123 if (IS_PF(p_dev)) 2124 ecore_ptt_release(p_hwfn, p_ptt); 2125 } 2126 2127 /* PORT statistics are not necessarily reset, so we need to 2128 * read and create a baseline for future statistics. 2129 * Link change stat is maintained by MFW, return its value as is. 2130 */ 2131 if (!p_dev->reset_stats) 2132 DP_INFO(p_dev, "Reset stats not allocated\n"); 2133 else { 2134 _ecore_get_vport_stats(p_dev, p_dev->reset_stats); 2135 p_dev->reset_stats->common.link_change_count = 0; 2136 } 2137 } 2138 2139 static enum gft_profile_type 2140 ecore_arfs_mode_to_hsi(enum ecore_filter_config_mode mode) 2141 { 2142 if (mode == ECORE_FILTER_CONFIG_MODE_5_TUPLE) 2143 return GFT_PROFILE_TYPE_4_TUPLE; 2144 if (mode == ECORE_FILTER_CONFIG_MODE_IP_DEST) 2145 return GFT_PROFILE_TYPE_IP_DST_ADDR; 2146 return GFT_PROFILE_TYPE_L4_DST_PORT; 2147 } 2148 2149 void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn, 2150 struct ecore_ptt *p_ptt, 2151 struct ecore_arfs_config_params *p_cfg_params) 2152 { 2153 if (OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits)) 2154 return; 2155 2156 if (p_cfg_params->mode != ECORE_FILTER_CONFIG_MODE_DISABLE) { 2157 ecore_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 2158 p_cfg_params->tcp, 2159 p_cfg_params->udp, 2160 p_cfg_params->ipv4, 2161 p_cfg_params->ipv6, 2162 ecore_arfs_mode_to_hsi(p_cfg_params->mode)); 2163 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 2164 "Configured Filtering: tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s mode=%08x\n", 2165 p_cfg_params->tcp ? "Enable" : "Disable", 2166 p_cfg_params->udp ? "Enable" : "Disable", 2167 p_cfg_params->ipv4 ? "Enable" : "Disable", 2168 p_cfg_params->ipv6 ? "Enable" : "Disable", 2169 (u32)p_cfg_params->mode); 2170 } else { 2171 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Disabled Filtering\n"); 2172 ecore_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2173 } 2174 } 2175 2176 enum _ecore_status_t 2177 ecore_configure_rfs_ntuple_filter(struct ecore_hwfn *p_hwfn, 2178 struct ecore_spq_comp_cb *p_cb, 2179 struct ecore_ntuple_filter_params *p_params) 2180 { 2181 struct rx_update_gft_filter_data *p_ramrod = OSAL_NULL; 2182 struct ecore_spq_entry *p_ent = OSAL_NULL; 2183 struct ecore_sp_init_data init_data; 2184 u16 abs_rx_q_id = 0; 2185 u8 abs_vport_id = 0; 2186 enum _ecore_status_t rc = ECORE_NOTIMPL; 2187 2188 rc = ecore_fw_vport(p_hwfn, p_params->vport_id, &abs_vport_id); 2189 if (rc != ECORE_SUCCESS) 2190 return rc; 2191 2192 if (p_params->qid != ECORE_RFS_NTUPLE_QID_RSS) { 2193 rc = ecore_fw_l2_queue(p_hwfn, p_params->qid, &abs_rx_q_id); 2194 if (rc != ECORE_SUCCESS) 2195 return rc; 2196 } 2197 2198 /* Get SPQ entry */ 2199 OSAL_MEMSET(&init_data, 0, sizeof(init_data)); 2200 init_data.cid = ecore_spq_get_cid(p_hwfn); 2201 2202 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 2203 2204 if (p_cb) { 2205 init_data.comp_mode = ECORE_SPQ_MODE_CB; 2206 init_data.p_comp_data = p_cb; 2207 } else { 2208 init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK; 2209 } 2210 2211 rc = ecore_sp_init_request(p_hwfn, &p_ent, 2212 ETH_RAMROD_GFT_UPDATE_FILTER, 2213 PROTOCOLID_ETH, &init_data); 2214 if (rc != ECORE_SUCCESS) 2215 return rc; 2216 2217 p_ramrod = &p_ent->ramrod.rx_update_gft; 2218 2219 DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_params->addr); 2220 p_ramrod->pkt_hdr_length = OSAL_CPU_TO_LE16(p_params->length); 2221 2222 if (p_params->qid != ECORE_RFS_NTUPLE_QID_RSS) { 2223 p_ramrod->rx_qid_valid = 1; 2224 p_ramrod->rx_qid = OSAL_CPU_TO_LE16(abs_rx_q_id); 2225 } 2226 2227 p_ramrod->flow_id_valid = 0; 2228 p_ramrod->flow_id = 0; 2229 2230 p_ramrod->vport_id = OSAL_CPU_TO_LE16 ((u16)abs_vport_id); 2231 p_ramrod->filter_action = p_params->b_is_add ? GFT_ADD_FILTER 2232 : GFT_DELETE_FILTER; 2233 2234 DP_VERBOSE(p_hwfn, ECORE_MSG_SP, 2235 "V[%0x], Q[%04x] - %s filter from 0x%llx [length %04xb]\n", 2236 abs_vport_id, abs_rx_q_id, 2237 p_params->b_is_add ? "Adding" : "Removing", 2238 (unsigned long long)p_params->addr, p_params->length); 2239 2240 return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL); 2241 } 2242 2243 int ecore_get_rxq_coalesce(struct ecore_hwfn *p_hwfn, 2244 struct ecore_ptt *p_ptt, 2245 struct ecore_queue_cid *p_cid, 2246 u16 *p_rx_coal) 2247 { 2248 u32 coalesce, address, is_valid; 2249 struct cau_sb_entry sb_entry; 2250 u8 timer_res; 2251 enum _ecore_status_t rc; 2252 2253 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2254 p_cid->sb_igu_id * sizeof(u64), 2255 (u64)(osal_uintptr_t)&sb_entry, 2, 2256 OSAL_NULL /* default parameters */); 2257 if (rc != ECORE_SUCCESS) { 2258 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2259 return rc; 2260 } 2261 2262 timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0); 2263 2264 address = BAR0_MAP_REG_USDM_RAM + 2265 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 2266 coalesce = ecore_rd(p_hwfn, p_ptt, address); 2267 2268 is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID); 2269 if (!is_valid) 2270 return ECORE_INVAL; 2271 2272 coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET); 2273 *p_rx_coal = (u16)(coalesce << timer_res); 2274 2275 return ECORE_SUCCESS; 2276 } 2277 2278 int ecore_get_txq_coalesce(struct ecore_hwfn *p_hwfn, 2279 struct ecore_ptt *p_ptt, 2280 struct ecore_queue_cid *p_cid, 2281 u16 *p_tx_coal) 2282 { 2283 u32 coalesce, address, is_valid; 2284 struct cau_sb_entry sb_entry; 2285 u8 timer_res; 2286 enum _ecore_status_t rc; 2287 2288 rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2289 p_cid->sb_igu_id * sizeof(u64), 2290 (u64)(osal_uintptr_t)&sb_entry, 2, 2291 OSAL_NULL /* default parameters */); 2292 if (rc != ECORE_SUCCESS) { 2293 DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2294 return rc; 2295 } 2296 2297 timer_res = GET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1); 2298 2299 address = BAR0_MAP_REG_XSDM_RAM + 2300 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 2301 coalesce = ecore_rd(p_hwfn, p_ptt, address); 2302 2303 is_valid = GET_FIELD(coalesce, COALESCING_TIMESET_VALID); 2304 if (!is_valid) 2305 return ECORE_INVAL; 2306 2307 coalesce = GET_FIELD(coalesce, COALESCING_TIMESET_TIMESET); 2308 *p_tx_coal = (u16)(coalesce << timer_res); 2309 2310 return ECORE_SUCCESS; 2311 } 2312 2313 enum _ecore_status_t 2314 ecore_get_queue_coalesce(struct ecore_hwfn *p_hwfn, u16 *p_coal, 2315 void *handle) 2316 { 2317 struct ecore_queue_cid *p_cid = (struct ecore_queue_cid *)handle; 2318 enum _ecore_status_t rc = ECORE_SUCCESS; 2319 struct ecore_ptt *p_ptt; 2320 2321 #ifdef CONFIG_ECORE_SRIOV 2322 if (IS_VF(p_hwfn->p_dev)) { 2323 rc = ecore_vf_pf_get_coalesce(p_hwfn, p_coal, p_cid); 2324 if (rc != ECORE_SUCCESS) 2325 DP_NOTICE(p_hwfn, false, 2326 "Unable to read queue calescing\n"); 2327 2328 return rc; 2329 } 2330 #endif 2331 2332 p_ptt = ecore_ptt_acquire(p_hwfn); 2333 if (!p_ptt) 2334 return ECORE_AGAIN; 2335 2336 if (p_cid->b_is_rx) { 2337 rc = ecore_get_rxq_coalesce(p_hwfn, p_ptt, p_cid, p_coal); 2338 if (rc != ECORE_SUCCESS) 2339 goto out; 2340 } else { 2341 rc = ecore_get_txq_coalesce(p_hwfn, p_ptt, p_cid, p_coal); 2342 if (rc != ECORE_SUCCESS) 2343 goto out; 2344 } 2345 2346 out: 2347 ecore_ptt_release(p_hwfn, p_ptt); 2348 2349 return rc; 2350 } 2351 #ifdef _NTDDK_ 2352 #pragma warning(pop) 2353 #endif 2354