1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * File : ecore_cxt.c 30 */ 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "bcm_osal.h" 35 #include "reg_addr.h" 36 #include "common_hsi.h" 37 #include "ecore_hsi_common.h" 38 #include "ecore_hsi_eth.h" 39 #include "tcp_common.h" 40 #include "ecore_hsi_iscsi.h" 41 #include "ecore_hsi_fcoe.h" 42 #include "ecore_hsi_roce.h" 43 #include "ecore_hsi_iwarp.h" 44 #include "ecore_rt_defs.h" 45 #include "ecore_status.h" 46 #include "ecore.h" 47 #include "ecore_init_ops.h" 48 #include "ecore_init_fw_funcs.h" 49 #include "ecore_cxt.h" 50 #include "ecore_hw.h" 51 #include "ecore_dev_api.h" 52 #include "ecore_sriov.h" 53 #include "ecore_rdma.h" 54 #include "ecore_mcp.h" 55 56 /* Max number of connection types in HW (DQ/CDU etc.) */ 57 #define MAX_CONN_TYPES PROTOCOLID_COMMON 58 #define NUM_TASK_TYPES 2 59 #define NUM_TASK_PF_SEGMENTS 4 60 #define NUM_TASK_VF_SEGMENTS 1 61 62 /* Doorbell-Queue constants */ 63 #define DQ_RANGE_SHIFT 4 64 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT) 65 66 /* Searcher constants */ 67 #define SRC_MIN_NUM_ELEMS 256 68 69 /* Timers constants */ 70 #define TM_SHIFT 7 71 #define TM_ALIGN (1 << TM_SHIFT) 72 #define TM_ELEM_SIZE 4 73 74 /* ILT constants */ 75 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12)) 76 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET 77 78 /* ILT entry structure */ 79 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL 80 #define ILT_ENTRY_PHY_ADDR_SHIFT 0 81 #define ILT_ENTRY_VALID_MASK 0x1ULL 82 #define ILT_ENTRY_VALID_SHIFT 52 83 #define ILT_ENTRY_IN_REGS 2 84 #define ILT_REG_SIZE_IN_BYTES 4 85 86 /* connection context union */ 87 union conn_context { 88 struct e4_core_conn_context core_ctx; 89 struct e4_eth_conn_context eth_ctx; 90 struct e4_iscsi_conn_context iscsi_ctx; 91 struct e4_fcoe_conn_context fcoe_ctx; 92 struct e4_roce_conn_context roce_ctx; 93 }; 94 95 /* TYPE-0 task context - iSCSI, FCOE */ 96 union type0_task_context { 97 struct e4_iscsi_task_context iscsi_ctx; 98 struct e4_fcoe_task_context fcoe_ctx; 99 }; 100 101 /* TYPE-1 task context - ROCE */ 102 union type1_task_context { 103 struct e4_rdma_task_context roce_ctx; 104 }; 105 106 struct src_ent { 107 u8 opaque[56]; 108 u64 next; 109 }; 110 111 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ 112 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12)) 113 114 #define CONN_CXT_SIZE(p_hwfn) \ 115 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn) 116 117 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context)) 118 #define XRC_SRQ_CXT_SIZE (sizeof(struct rdma_xrc_srq_context)) 119 120 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \ 121 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn) 122 123 /* Alignment is inherent to the type1_task_context structure */ 124 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context) 125 126 /* PF per protocl configuration object */ 127 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS) 128 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS) 129 130 struct ecore_tid_seg { 131 u32 count; 132 u8 type; 133 bool has_fl_mem; 134 }; 135 136 struct ecore_conn_type_cfg { 137 u32 cid_count; 138 u32 cids_per_vf; 139 struct ecore_tid_seg tid_seg[TASK_SEGMENTS]; 140 }; 141 142 /* ILT Client configuration, 143 * Per connection type (protocol) resources (cids, tis, vf cids etc.) 144 * 1 - for connection context (CDUC) and for each task context we need two 145 * values, for regular task context and for force load memory 146 */ 147 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2) 148 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2) 149 #define CDUC_BLK (0) 150 #define SRQ_BLK (0) 151 #define CDUT_SEG_BLK(n) (1 + (u8)(n)) 152 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS) 153 154 struct ilt_cfg_pair { 155 u32 reg; 156 u32 val; 157 }; 158 159 struct ecore_ilt_cli_blk { 160 u32 total_size; /* 0 means not active */ 161 u32 real_size_in_page; 162 u32 start_line; 163 u32 dynamic_line_cnt; 164 }; 165 166 struct ecore_ilt_client_cfg { 167 bool active; 168 169 /* ILT boundaries */ 170 struct ilt_cfg_pair first; 171 struct ilt_cfg_pair last; 172 struct ilt_cfg_pair p_size; 173 174 /* ILT client blocks for PF */ 175 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS]; 176 u32 pf_total_lines; 177 178 /* ILT client blocks for VFs */ 179 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS]; 180 u32 vf_total_lines; 181 }; 182 183 /* Per Path - 184 * ILT shadow table 185 * Protocol acquired CID lists 186 * PF start line in ILT 187 */ 188 struct ecore_dma_mem { 189 dma_addr_t p_phys; 190 void *p_virt; 191 osal_size_t size; 192 }; 193 194 #define MAP_WORD_SIZE sizeof(unsigned long) 195 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8) 196 197 struct ecore_cid_acquired_map { 198 u32 start_cid; 199 u32 max_count; 200 unsigned long *cid_map; 201 }; 202 203 struct ecore_cxt_mngr { 204 /* Per protocl configuration */ 205 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES]; 206 207 /* computed ILT structure */ 208 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX]; 209 210 /* Task type sizes */ 211 u32 task_type_size[NUM_TASK_TYPES]; 212 213 /* total number of VFs for this hwfn - 214 * ALL VFs are symmetric in terms of HW resources 215 */ 216 u32 vf_count; 217 218 /* Acquired CIDs */ 219 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES]; 220 /* TBD - do we want this allocated to reserve space? */ 221 struct ecore_cid_acquired_map acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS]; 222 223 /* ILT shadow table */ 224 struct ecore_dma_mem *ilt_shadow; 225 u32 pf_start_line; 226 227 /* Mutex for a dynamic ILT allocation */ 228 osal_mutex_t mutex; 229 230 /* SRC T2 */ 231 struct ecore_dma_mem *t2; 232 u32 t2_num_pages; 233 u64 first_free; 234 u64 last_free; 235 236 /* The infrastructure originally was very generic and context/task 237 * oriented - per connection-type we would set how many of those 238 * are needed, and later when determining how much memory we're 239 * needing for a given block we'd iterate over all the relevant 240 * connection-types. 241 * But since then we've had some additional resources, some of which 242 * require memory which is indepent of the general context/task 243 * scheme. We add those here explicitly per-feature. 244 */ 245 246 /* total number of SRQ's for this hwfn */ 247 u32 srq_count; 248 u32 xrc_srq_count; 249 250 /* Maximal number of L2 steering filters */ 251 u32 arfs_count; 252 253 /* TODO - VF arfs filters ? */ 254 }; 255 256 /* check if resources/configuration is required according to protocol type */ 257 static bool src_proto(enum protocol_type type) 258 { 259 return type == PROTOCOLID_ISCSI || 260 type == PROTOCOLID_FCOE || 261 type == PROTOCOLID_IWARP; 262 } 263 264 static bool tm_cid_proto(enum protocol_type type) 265 { 266 return type == PROTOCOLID_ISCSI || 267 type == PROTOCOLID_FCOE || 268 type == PROTOCOLID_ROCE || 269 type == PROTOCOLID_IWARP; 270 } 271 272 static bool tm_tid_proto(enum protocol_type type) 273 { 274 return type == PROTOCOLID_FCOE; 275 } 276 277 /* counts the iids for the CDU/CDUC ILT client configuration */ 278 struct ecore_cdu_iids { 279 u32 pf_cids; 280 u32 per_vf_cids; 281 }; 282 283 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr, 284 struct ecore_cdu_iids *iids) 285 { 286 u32 type; 287 288 for (type = 0; type < MAX_CONN_TYPES; type++) { 289 iids->pf_cids += p_mngr->conn_cfg[type].cid_count; 290 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 291 } 292 } 293 294 /* counts the iids for the Searcher block configuration */ 295 struct ecore_src_iids { 296 u32 pf_cids; 297 u32 per_vf_cids; 298 }; 299 300 static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr, 301 struct ecore_src_iids *iids) 302 { 303 u32 i; 304 305 for (i = 0; i < MAX_CONN_TYPES; i++) { 306 if (!src_proto(i)) 307 continue; 308 309 iids->pf_cids += p_mngr->conn_cfg[i].cid_count; 310 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf; 311 } 312 313 /* Add L2 filtering filters in addition */ 314 iids->pf_cids += p_mngr->arfs_count; 315 } 316 317 /* counts the iids for the Timers block configuration */ 318 struct ecore_tm_iids { 319 u32 pf_cids; 320 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */ 321 u32 pf_tids_total; 322 u32 per_vf_cids; 323 u32 per_vf_tids; 324 }; 325 326 static void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr, 327 struct ecore_tm_iids *iids) 328 { 329 bool tm_vf_required = false; 330 bool tm_required = false; 331 int i, j; 332 333 /* Timers is a special case -> we don't count how many cids require 334 * timers but what's the max cid that will be used by the timer block. 335 * therefore we traverse in reverse order, and once we hit a protocol 336 * that requires the timers memory, we'll sum all the protocols up 337 * to that one. 338 */ 339 for (i = MAX_CONN_TYPES - 1; i >= 0; i--) { 340 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i]; 341 342 if (tm_cid_proto(i) || tm_required) { 343 if (p_cfg->cid_count) 344 tm_required = true; 345 346 iids->pf_cids += p_cfg->cid_count; 347 } 348 349 if (tm_cid_proto(i) || tm_vf_required) { 350 if (p_cfg->cids_per_vf) 351 tm_vf_required = true; 352 353 iids->per_vf_cids += p_cfg->cids_per_vf; 354 } 355 356 if (tm_tid_proto(i)) { 357 struct ecore_tid_seg *segs = p_cfg->tid_seg; 358 359 /* for each segment there is at most one 360 * protocol for which count is not 0. 361 */ 362 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 363 iids->pf_tids[j] += segs[j].count; 364 365 /* The last array elelment is for the VFs. As for PF 366 * segments there can be only one protocol for 367 * which this value is not 0. 368 */ 369 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 370 } 371 } 372 373 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN); 374 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN); 375 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN); 376 377 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) { 378 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN); 379 iids->pf_tids_total += iids->pf_tids[j]; 380 } 381 } 382 383 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, 384 struct ecore_qm_iids *iids) 385 { 386 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 387 struct ecore_tid_seg *segs; 388 u32 vf_cids = 0, type, j; 389 u32 vf_tids = 0; 390 391 for (type = 0; type < MAX_CONN_TYPES; type++) { 392 iids->cids += p_mngr->conn_cfg[type].cid_count; 393 vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 394 395 segs = p_mngr->conn_cfg[type].tid_seg; 396 /* for each segment there is at most one 397 * protocol for which count is not 0. 398 */ 399 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 400 iids->tids += segs[j].count; 401 402 /* The last array elelment is for the VFs. As for PF 403 * segments there can be only one protocol for 404 * which this value is not 0. 405 */ 406 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 407 } 408 409 iids->vf_cids += vf_cids * p_mngr->vf_count; 410 iids->tids += vf_tids * p_mngr->vf_count; 411 412 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 413 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n", 414 iids->cids, iids->vf_cids, iids->tids, vf_tids); 415 } 416 417 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn, 418 u32 seg) 419 { 420 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr; 421 u32 i; 422 423 /* Find the protocol with tid count > 0 for this segment. 424 Note: there can only be one and this is already validated. 425 */ 426 for (i = 0; i < MAX_CONN_TYPES; i++) { 427 if (p_cfg->conn_cfg[i].tid_seg[seg].count) 428 return &p_cfg->conn_cfg[i].tid_seg[seg]; 429 } 430 return OSAL_NULL; 431 } 432 433 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, 434 u32 num_srqs, u32 num_xrc_srqs) 435 { 436 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 437 438 p_mgr->srq_count = num_srqs; 439 p_mgr->xrc_srq_count = num_xrc_srqs; 440 } 441 442 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn) 443 { 444 return p_hwfn->p_cxt_mngr->srq_count; 445 } 446 447 u32 ecore_cxt_get_xrc_srq_count(struct ecore_hwfn *p_hwfn) 448 { 449 return p_hwfn->p_cxt_mngr->xrc_srq_count; 450 } 451 452 u32 ecore_cxt_get_ilt_page_size(struct ecore_hwfn *p_hwfn, 453 enum ilt_clients ilt_client) 454 { 455 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 456 struct ecore_ilt_client_cfg *p_cli = &p_mngr->clients[ilt_client]; 457 458 return ILT_PAGE_IN_BYTES(p_cli->p_size.val); 459 } 460 461 static u32 ecore_cxt_srqs_per_page(struct ecore_hwfn *p_hwfn) 462 { 463 u32 page_size; 464 465 page_size = ecore_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM); 466 return page_size / SRQ_CXT_SIZE; 467 } 468 469 u32 ecore_cxt_get_total_srq_count(struct ecore_hwfn *p_hwfn) 470 { 471 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 472 u32 total_srqs; 473 474 total_srqs = p_mgr->srq_count; 475 476 /* XRC SRQs use the first and only the first SRQ ILT page. So if XRC 477 * SRQs are requested we need to allocate an extra SRQ ILT page for 478 * them. For that We increase the number of regular SRQs to cause the 479 * allocation of that extra page. 480 */ 481 if (p_mgr->xrc_srq_count) 482 total_srqs += ecore_cxt_srqs_per_page(p_hwfn); 483 484 return total_srqs; 485 } 486 487 /* set the iids (cid/tid) count per protocol */ 488 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn, 489 enum protocol_type type, 490 u32 cid_count, u32 vf_cid_cnt) 491 { 492 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 493 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type]; 494 495 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN); 496 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN); 497 498 if (type == PROTOCOLID_ROCE) { 499 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; 500 u32 cxt_size = CONN_CXT_SIZE(p_hwfn); 501 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 502 u32 align = elems_per_page * DQ_RANGE_ALIGN; 503 504 p_conn->cid_count = ROUNDUP(p_conn->cid_count, align); 505 } 506 } 507 508 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn, 509 enum protocol_type type, 510 u32 *vf_cid) 511 { 512 if (vf_cid) 513 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf; 514 515 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; 516 } 517 518 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn, 519 enum protocol_type type) 520 { 521 return p_hwfn->p_cxt_mngr->acquired[type].start_cid; 522 } 523 524 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn, 525 enum protocol_type type) 526 { 527 u32 cnt = 0; 528 int i; 529 530 for (i = 0; i < TASK_SEGMENTS; i++) 531 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count; 532 533 return cnt; 534 } 535 536 static void ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn, 537 enum protocol_type proto, 538 u8 seg, 539 u8 seg_type, 540 u32 count, 541 bool has_fl) 542 { 543 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 544 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg]; 545 546 p_seg->count = count; 547 p_seg->has_fl_mem = has_fl; 548 p_seg->type = seg_type; 549 } 550 551 /* the *p_line parameter must be either 0 for the first invocation or the 552 value returned in the previous invocation. 553 */ 554 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli, 555 struct ecore_ilt_cli_blk *p_blk, 556 u32 start_line, 557 u32 total_size, 558 u32 elem_size) 559 { 560 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 561 562 /* verify that it's called once for each block */ 563 if (p_blk->total_size) 564 return; 565 566 p_blk->total_size = total_size; 567 p_blk->real_size_in_page = 0; 568 if (elem_size) 569 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size; 570 p_blk->start_line = start_line; 571 } 572 573 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn, 574 struct ecore_ilt_client_cfg *p_cli, 575 struct ecore_ilt_cli_blk *p_blk, 576 u32 *p_line, 577 enum ilt_clients client_id) 578 { 579 if (!p_blk->total_size) 580 return; 581 582 if (!p_cli->active) 583 p_cli->first.val = *p_line; 584 585 p_cli->active = true; 586 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 587 p_cli->last.val = *p_line-1; 588 589 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 590 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n", 591 client_id, p_cli->first.val, p_cli->last.val, 592 p_blk->total_size, p_blk->real_size_in_page, 593 p_blk->start_line); 594 } 595 596 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn, 597 enum ilt_clients ilt_client) 598 { 599 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count; 600 struct ecore_ilt_client_cfg *p_cli; 601 u32 lines_to_skip = 0; 602 u32 cxts_per_p; 603 604 /* TBD MK: ILT code should be simplified once PROTO enum is changed */ 605 606 if (ilt_client == ILT_CLI_CDUC) { 607 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 608 609 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) / 610 (u32)CONN_CXT_SIZE(p_hwfn); 611 612 lines_to_skip = cid_count / cxts_per_p; 613 } 614 615 return lines_to_skip; 616 } 617 618 static struct ecore_ilt_client_cfg * 619 ecore_cxt_set_cli(struct ecore_ilt_client_cfg *p_cli) 620 { 621 p_cli->active = false; 622 p_cli->first.val = 0; 623 p_cli->last.val = 0; 624 return p_cli; 625 } 626 627 static struct ecore_ilt_cli_blk * 628 ecore_cxt_set_blk(struct ecore_ilt_cli_blk *p_blk) 629 { 630 p_blk->total_size = 0; 631 return p_blk; 632 } 633 634 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn, 635 u32 *line_count) 636 { 637 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 638 u32 curr_line, total, i, task_size, line; 639 struct ecore_ilt_client_cfg *p_cli; 640 struct ecore_ilt_cli_blk *p_blk; 641 struct ecore_cdu_iids cdu_iids; 642 struct ecore_src_iids src_iids; 643 struct ecore_qm_iids qm_iids; 644 struct ecore_tm_iids tm_iids; 645 struct ecore_tid_seg *p_seg; 646 647 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids)); 648 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids)); 649 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids)); 650 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids)); 651 652 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT); 653 654 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 655 "hwfn [%d] - Set context manager starting line to be 0x%08x\n", 656 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line); 657 658 /* CDUC */ 659 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]); 660 661 curr_line = p_mngr->pf_start_line; 662 663 /* CDUC PF */ 664 p_cli->pf_total_lines = 0; 665 666 /* get the counters for the CDUC,CDUC and QM clients */ 667 ecore_cxt_cdu_iids(p_mngr, &cdu_iids); 668 669 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]); 670 671 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn); 672 673 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 674 total, CONN_CXT_SIZE(p_hwfn)); 675 676 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 677 p_cli->pf_total_lines = curr_line - p_blk->start_line; 678 679 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn, 680 ILT_CLI_CDUC); 681 682 /* CDUC VF */ 683 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]); 684 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn); 685 686 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 687 total, CONN_CXT_SIZE(p_hwfn)); 688 689 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 690 p_cli->vf_total_lines = curr_line - p_blk->start_line; 691 692 for (i = 1; i < p_mngr->vf_count; i++) 693 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 694 ILT_CLI_CDUC); 695 696 /* CDUT PF */ 697 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]); 698 p_cli->first.val = curr_line; 699 700 /* first the 'working' task memory */ 701 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 702 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i); 703 if (!p_seg || p_seg->count == 0) 704 continue; 705 706 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]); 707 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 708 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total, 709 p_mngr->task_type_size[p_seg->type]); 710 711 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 712 ILT_CLI_CDUT); 713 } 714 715 /* next the 'init' task memory (forced load memory) */ 716 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 717 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i); 718 if (!p_seg || p_seg->count == 0) 719 continue; 720 721 p_blk = ecore_cxt_set_blk( 722 &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]); 723 724 if (!p_seg->has_fl_mem) { 725 /* The segment is active (total size pf 'working' 726 * memory is > 0) but has no FL (forced-load, Init) 727 * memory. Thus: 728 * 729 * 1. The total-size in the corrsponding FL block of 730 * the ILT client is set to 0 - No ILT line are 731 * provisioned and no ILT memory allocated. 732 * 733 * 2. The start-line of said block is set to the 734 * start line of the matching working memory 735 * block in the ILT client. This is later used to 736 * configure the CDU segment offset registers and 737 * results in an FL command for TIDs of this 738 * segement behaves as regular load commands 739 * (loading TIDs from the working memory). 740 */ 741 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line; 742 743 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 744 continue; 745 } 746 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 747 748 ecore_ilt_cli_blk_fill(p_cli, p_blk, 749 curr_line, total, 750 p_mngr->task_type_size[p_seg->type]); 751 752 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 753 ILT_CLI_CDUT); 754 } 755 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line; 756 757 /* CDUT VF */ 758 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF); 759 if (p_seg && p_seg->count) { 760 /* Stricly speaking we need to iterate over all VF 761 * task segment types, but a VF has only 1 segment 762 */ 763 764 /* 'working' memory */ 765 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 766 767 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]); 768 ecore_ilt_cli_blk_fill(p_cli, p_blk, 769 curr_line, total, 770 p_mngr->task_type_size[p_seg->type]); 771 772 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 773 ILT_CLI_CDUT); 774 775 /* 'init' memory */ 776 p_blk = ecore_cxt_set_blk( 777 &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]); 778 if (!p_seg->has_fl_mem) { 779 /* see comment above */ 780 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line; 781 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 782 } else { 783 task_size = p_mngr->task_type_size[p_seg->type]; 784 ecore_ilt_cli_blk_fill(p_cli, p_blk, 785 curr_line, total, 786 task_size); 787 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 788 ILT_CLI_CDUT); 789 } 790 p_cli->vf_total_lines = curr_line - 791 p_cli->vf_blks[0].start_line; 792 793 /* Now for the rest of the VFs */ 794 for (i = 1; i < p_mngr->vf_count; i++) { 795 /* don't set p_blk i.e. don't clear total_size */ 796 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)]; 797 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 798 ILT_CLI_CDUT); 799 800 /* don't set p_blk i.e. don't clear total_size */ 801 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]; 802 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 803 ILT_CLI_CDUT); 804 } 805 } 806 807 /* QM */ 808 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]); 809 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]); 810 811 ecore_cxt_qm_iids(p_hwfn, &qm_iids); 812 total = ecore_qm_pf_mem_size(qm_iids.cids, 813 qm_iids.vf_cids, qm_iids.tids, 814 p_hwfn->qm_info.num_pqs, 815 p_hwfn->qm_info.num_vf_pqs); 816 817 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 818 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n", 819 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids, 820 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total); 821 822 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000, 823 QM_PQ_ELEMENT_SIZE); 824 825 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM); 826 p_cli->pf_total_lines = curr_line - p_blk->start_line; 827 828 /* SRC */ 829 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]); 830 ecore_cxt_src_iids(p_mngr, &src_iids); 831 832 /* Both the PF and VFs searcher connections are stored in the per PF 833 * database. Thus sum the PF searcher cids and all the VFs searcher 834 * cids. 835 */ 836 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 837 if (total) { 838 u32 local_max = OSAL_MAX_T(u32, total, 839 SRC_MIN_NUM_ELEMS); 840 841 total = OSAL_ROUNDUP_POW_OF_TWO(local_max); 842 843 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]); 844 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 845 total * sizeof(struct src_ent), 846 sizeof(struct src_ent)); 847 848 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 849 ILT_CLI_SRC); 850 p_cli->pf_total_lines = curr_line - p_blk->start_line; 851 } 852 853 /* TM PF */ 854 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]); 855 ecore_cxt_tm_iids(p_mngr, &tm_iids); 856 total = tm_iids.pf_cids + tm_iids.pf_tids_total; 857 if (total) { 858 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]); 859 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 860 total * TM_ELEM_SIZE, 861 TM_ELEM_SIZE); 862 863 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 864 ILT_CLI_TM); 865 p_cli->pf_total_lines = curr_line - p_blk->start_line; 866 } 867 868 /* TM VF */ 869 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids; 870 if (total) { 871 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[0]); 872 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 873 total * TM_ELEM_SIZE, 874 TM_ELEM_SIZE); 875 876 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 877 ILT_CLI_TM); 878 879 p_cli->vf_total_lines = curr_line - p_blk->start_line; 880 for (i = 1; i < p_mngr->vf_count; i++) { 881 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 882 ILT_CLI_TM); 883 } 884 } 885 886 /* TSDM (SRQ CONTEXT) */ 887 total = ecore_cxt_get_total_srq_count(p_hwfn); 888 if (total) { 889 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]); 890 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]); 891 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 892 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE); 893 894 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 895 ILT_CLI_TSDM); 896 p_cli->pf_total_lines = curr_line - p_blk->start_line; 897 } 898 899 *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line; 900 901 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line > 902 RESC_NUM(p_hwfn, ECORE_ILT)) { 903 return ECORE_INVAL; 904 } 905 906 return ECORE_SUCCESS; 907 } 908 909 u32 ecore_cxt_cfg_ilt_compute_excess(struct ecore_hwfn *p_hwfn, u32 used_lines) 910 { 911 struct ecore_ilt_client_cfg *p_cli; 912 u32 excess_lines, available_lines; 913 struct ecore_cxt_mngr *p_mngr; 914 u32 ilt_page_size, elem_size; 915 struct ecore_tid_seg *p_seg; 916 int i; 917 918 available_lines = RESC_NUM(p_hwfn, ECORE_ILT); 919 excess_lines = used_lines - available_lines; 920 921 if (!excess_lines) 922 return 0; 923 924 if (!ECORE_IS_RDMA_PERSONALITY(p_hwfn)) 925 return 0; 926 927 p_mngr = p_hwfn->p_cxt_mngr; 928 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 929 ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 930 931 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 932 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i); 933 if (!p_seg || p_seg->count == 0) 934 continue; 935 936 elem_size = p_mngr->task_type_size[p_seg->type]; 937 if (!elem_size) 938 continue; 939 940 return (ilt_page_size / elem_size) * excess_lines; 941 } 942 943 DP_ERR(p_hwfn, "failed computing excess ILT lines\n"); 944 return 0; 945 } 946 947 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn) 948 { 949 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 950 u32 i; 951 952 if (!p_mngr->t2) 953 return; 954 955 for (i = 0; i < p_mngr->t2_num_pages; i++) 956 if (p_mngr->t2[i].p_virt) 957 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, 958 p_mngr->t2[i].p_virt, 959 p_mngr->t2[i].p_phys, 960 p_mngr->t2[i].size); 961 962 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2); 963 p_mngr->t2 = OSAL_NULL; 964 } 965 966 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn) 967 { 968 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 969 u32 conn_num, total_size, ent_per_page, psz, i; 970 struct ecore_ilt_client_cfg *p_src; 971 struct ecore_src_iids src_iids; 972 struct ecore_dma_mem *p_t2; 973 enum _ecore_status_t rc; 974 975 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids)); 976 977 /* if the SRC ILT client is inactive - there are no connection 978 * requiring the searcer, leave. 979 */ 980 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC]; 981 if (!p_src->active) 982 return ECORE_SUCCESS; 983 984 ecore_cxt_src_iids(p_mngr, &src_iids); 985 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 986 total_size = conn_num * sizeof(struct src_ent); 987 988 /* use the same page size as the SRC ILT client */ 989 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val); 990 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz); 991 992 /* allocate t2 */ 993 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 994 p_mngr->t2_num_pages * 995 sizeof(struct ecore_dma_mem)); 996 if (!p_mngr->t2) { 997 DP_NOTICE(p_hwfn, false, "Failed to allocate t2 table\n"); 998 rc = ECORE_NOMEM; 999 goto t2_fail; 1000 } 1001 1002 /* allocate t2 pages */ 1003 for (i = 0; i < p_mngr->t2_num_pages; i++) { 1004 u32 size = OSAL_MIN_T(u32, total_size, psz); 1005 void **p_virt = &p_mngr->t2[i].p_virt; 1006 1007 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, 1008 &p_mngr->t2[i].p_phys, 1009 size); 1010 if (!p_mngr->t2[i].p_virt) { 1011 rc = ECORE_NOMEM; 1012 goto t2_fail; 1013 } 1014 OSAL_MEM_ZERO(*p_virt, size); 1015 p_mngr->t2[i].size = size; 1016 total_size -= size; 1017 } 1018 1019 /* Set the t2 pointers */ 1020 1021 /* entries per page - must be a power of two */ 1022 ent_per_page = psz / sizeof(struct src_ent); 1023 1024 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys; 1025 1026 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page]; 1027 p_mngr->last_free = (u64)p_t2->p_phys + 1028 ((conn_num - 1) & (ent_per_page - 1)) * 1029 sizeof(struct src_ent); 1030 1031 for (i = 0; i < p_mngr->t2_num_pages; i++) { 1032 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num); 1033 struct src_ent *entries = p_mngr->t2[i].p_virt; 1034 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val; 1035 u32 j; 1036 1037 for (j = 0; j < ent_num - 1; j++) { 1038 val = p_ent_phys + 1039 (j + 1) * sizeof(struct src_ent); 1040 entries[j].next = OSAL_CPU_TO_BE64(val); 1041 } 1042 1043 if (i < p_mngr->t2_num_pages - 1) 1044 val = (u64)p_mngr->t2[i + 1].p_phys; 1045 else 1046 val = 0; 1047 entries[j].next = OSAL_CPU_TO_BE64(val); 1048 1049 conn_num -= ent_num; 1050 } 1051 1052 return ECORE_SUCCESS; 1053 1054 t2_fail: 1055 ecore_cxt_src_t2_free(p_hwfn); 1056 return rc; 1057 } 1058 1059 #define for_each_ilt_valid_client(pos, clients) \ 1060 for (pos = 0; pos < ILT_CLI_MAX; pos++) \ 1061 if (!clients[pos].active) { \ 1062 continue; \ 1063 } else \ 1064 1065 /* Total number of ILT lines used by this PF */ 1066 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients) 1067 { 1068 u32 size = 0; 1069 u32 i; 1070 1071 for_each_ilt_valid_client(i, ilt_clients) 1072 size += (ilt_clients[i].last.val - 1073 ilt_clients[i].first.val + 1); 1074 1075 return size; 1076 } 1077 1078 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn) 1079 { 1080 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients; 1081 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1082 u32 ilt_size, i; 1083 1084 if (p_mngr->ilt_shadow == OSAL_NULL) 1085 return; 1086 1087 ilt_size = ecore_cxt_ilt_shadow_size(p_cli); 1088 1089 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) { 1090 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i]; 1091 1092 if (p_dma->p_virt) 1093 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, 1094 p_dma->p_virt, 1095 p_dma->p_phys, 1096 p_dma->size); 1097 p_dma->p_virt = OSAL_NULL; 1098 } 1099 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow); 1100 p_mngr->ilt_shadow = OSAL_NULL; 1101 } 1102 1103 static enum _ecore_status_t ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn, 1104 struct ecore_ilt_cli_blk *p_blk, 1105 enum ilt_clients ilt_client, 1106 u32 start_line_offset) 1107 { 1108 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow; 1109 u32 lines, line, sz_left, lines_to_skip = 0; 1110 1111 /* Special handling for RoCE that supports dynamic allocation */ 1112 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn) && 1113 ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM)) 1114 return ECORE_SUCCESS; 1115 1116 lines_to_skip = p_blk->dynamic_line_cnt; 1117 1118 if (!p_blk->total_size) 1119 return ECORE_SUCCESS; 1120 1121 sz_left = p_blk->total_size; 1122 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - 1123 lines_to_skip; 1124 line = p_blk->start_line + start_line_offset - 1125 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip; 1126 1127 for (; lines; lines--) { 1128 dma_addr_t p_phys; 1129 void *p_virt; 1130 u32 size; 1131 1132 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page); 1133 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, 1134 &p_phys, size); 1135 if (!p_virt) 1136 return ECORE_NOMEM; 1137 OSAL_MEM_ZERO(p_virt, size); 1138 1139 ilt_shadow[line].p_phys = p_phys; 1140 ilt_shadow[line].p_virt = p_virt; 1141 ilt_shadow[line].size = size; 1142 1143 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 1144 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n", 1145 line, (unsigned long long)p_phys, p_virt, size); 1146 1147 sz_left -= size; 1148 line++; 1149 } 1150 1151 return ECORE_SUCCESS; 1152 } 1153 1154 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn) 1155 { 1156 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1157 struct ecore_ilt_client_cfg *clients = p_mngr->clients; 1158 struct ecore_ilt_cli_blk *p_blk; 1159 u32 size, i, j, k; 1160 enum _ecore_status_t rc; 1161 1162 size = ecore_cxt_ilt_shadow_size(clients); 1163 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 1164 size * sizeof(struct ecore_dma_mem)); 1165 1166 if (p_mngr->ilt_shadow == OSAL_NULL) { 1167 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt shadow table\n"); 1168 rc = ECORE_NOMEM; 1169 goto ilt_shadow_fail; 1170 } 1171 1172 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 1173 "Allocated 0x%x bytes for ilt shadow\n", 1174 (u32)(size * sizeof(struct ecore_dma_mem))); 1175 1176 for_each_ilt_valid_client(i, clients) { 1177 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) { 1178 p_blk = &clients[i].pf_blks[j]; 1179 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0); 1180 if (rc != ECORE_SUCCESS) 1181 goto ilt_shadow_fail; 1182 } 1183 for (k = 0; k < p_mngr->vf_count; k++) { 1184 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) { 1185 u32 lines = clients[i].vf_total_lines * k; 1186 1187 p_blk = &clients[i].vf_blks[j]; 1188 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, 1189 i, lines); 1190 if (rc != ECORE_SUCCESS) 1191 goto ilt_shadow_fail; 1192 } 1193 } 1194 } 1195 1196 return ECORE_SUCCESS; 1197 1198 ilt_shadow_fail: 1199 ecore_ilt_shadow_free(p_hwfn); 1200 return rc; 1201 } 1202 1203 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn) 1204 { 1205 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1206 u32 type, vf; 1207 1208 for (type = 0; type < MAX_CONN_TYPES; type++) { 1209 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map); 1210 p_mngr->acquired[type].cid_map = OSAL_NULL; 1211 p_mngr->acquired[type].max_count = 0; 1212 p_mngr->acquired[type].start_cid = 0; 1213 1214 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) { 1215 OSAL_FREE(p_hwfn->p_dev, 1216 p_mngr->acquired_vf[type][vf].cid_map); 1217 p_mngr->acquired_vf[type][vf].cid_map = OSAL_NULL; 1218 p_mngr->acquired_vf[type][vf].max_count = 0; 1219 p_mngr->acquired_vf[type][vf].start_cid = 0; 1220 } 1221 } 1222 } 1223 1224 static enum _ecore_status_t 1225 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type, 1226 u32 cid_start, u32 cid_count, 1227 struct ecore_cid_acquired_map *p_map) 1228 { 1229 u32 size; 1230 1231 if (!cid_count) 1232 return ECORE_SUCCESS; 1233 1234 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD); 1235 p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size); 1236 if (p_map->cid_map == OSAL_NULL) 1237 return ECORE_NOMEM; 1238 1239 p_map->max_count = cid_count; 1240 p_map->start_cid = cid_start; 1241 1242 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT, 1243 "Type %08x start: %08x count %08x\n", 1244 type, p_map->start_cid, p_map->max_count); 1245 1246 return ECORE_SUCCESS; 1247 } 1248 1249 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn) 1250 { 1251 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1252 u32 start_cid = 0, vf_start_cid = 0; 1253 u32 type, vf; 1254 1255 for (type = 0; type < MAX_CONN_TYPES; type++) { 1256 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type]; 1257 struct ecore_cid_acquired_map *p_map; 1258 1259 /* Handle PF maps */ 1260 p_map = &p_mngr->acquired[type]; 1261 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid, 1262 p_cfg->cid_count, p_map)) 1263 goto cid_map_fail; 1264 1265 /* Handle VF maps */ 1266 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) { 1267 p_map = &p_mngr->acquired_vf[type][vf]; 1268 if (ecore_cid_map_alloc_single(p_hwfn, type, 1269 vf_start_cid, 1270 p_cfg->cids_per_vf, 1271 p_map)) 1272 goto cid_map_fail; 1273 } 1274 1275 start_cid += p_cfg->cid_count; 1276 vf_start_cid += p_cfg->cids_per_vf; 1277 } 1278 1279 return ECORE_SUCCESS; 1280 1281 cid_map_fail: 1282 ecore_cid_map_free(p_hwfn); 1283 return ECORE_NOMEM; 1284 } 1285 1286 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn) 1287 { 1288 struct ecore_ilt_client_cfg *clients; 1289 struct ecore_cxt_mngr *p_mngr; 1290 u32 i; 1291 1292 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr)); 1293 if (!p_mngr) { 1294 DP_NOTICE(p_hwfn, false, "Failed to allocate `struct ecore_cxt_mngr'\n"); 1295 return ECORE_NOMEM; 1296 } 1297 1298 /* Initialize ILT client registers */ 1299 clients = p_mngr->clients; 1300 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT); 1301 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT); 1302 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE); 1303 1304 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT); 1305 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT); 1306 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE); 1307 1308 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT); 1309 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT); 1310 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE); 1311 1312 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT); 1313 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT); 1314 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE); 1315 1316 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT); 1317 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT); 1318 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE); 1319 1320 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT); 1321 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); 1322 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); 1323 1324 /* default ILT page size for all clients is 64K */ 1325 for (i = 0; i < ILT_CLI_MAX; i++) 1326 p_mngr->clients[i].p_size.val = p_hwfn->p_dev->ilt_page_size; 1327 1328 /* Initialize task sizes */ 1329 p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn); 1330 p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn); 1331 1332 if (p_hwfn->p_dev->p_iov_info) 1333 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs; 1334 1335 /* Initialize the dynamic ILT allocation mutex */ 1336 #ifdef CONFIG_ECORE_LOCK_ALLOC 1337 OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex); 1338 #endif 1339 OSAL_MUTEX_INIT(&p_mngr->mutex); 1340 1341 /* Set the cxt mangr pointer priori to further allocations */ 1342 p_hwfn->p_cxt_mngr = p_mngr; 1343 1344 return ECORE_SUCCESS; 1345 } 1346 1347 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn) 1348 { 1349 enum _ecore_status_t rc; 1350 1351 /* Allocate the ILT shadow table */ 1352 rc = ecore_ilt_shadow_alloc(p_hwfn); 1353 if (rc) { 1354 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt memory\n"); 1355 goto tables_alloc_fail; 1356 } 1357 1358 /* Allocate the T2 table */ 1359 rc = ecore_cxt_src_t2_alloc(p_hwfn); 1360 if (rc) { 1361 DP_NOTICE(p_hwfn, false, "Failed to allocate T2 memory\n"); 1362 goto tables_alloc_fail; 1363 } 1364 1365 /* Allocate and initialize the acquired cids bitmaps */ 1366 rc = ecore_cid_map_alloc(p_hwfn); 1367 if (rc) { 1368 DP_NOTICE(p_hwfn, false, "Failed to allocate cid maps\n"); 1369 goto tables_alloc_fail; 1370 } 1371 1372 return ECORE_SUCCESS; 1373 1374 tables_alloc_fail: 1375 ecore_cxt_mngr_free(p_hwfn); 1376 return rc; 1377 } 1378 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn) 1379 { 1380 if (!p_hwfn->p_cxt_mngr) 1381 return; 1382 1383 ecore_cid_map_free(p_hwfn); 1384 ecore_cxt_src_t2_free(p_hwfn); 1385 ecore_ilt_shadow_free(p_hwfn); 1386 #ifdef CONFIG_ECORE_LOCK_ALLOC 1387 OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex); 1388 #endif 1389 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr); 1390 1391 p_hwfn->p_cxt_mngr = OSAL_NULL; 1392 } 1393 1394 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn) 1395 { 1396 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1397 struct ecore_cid_acquired_map *p_map; 1398 struct ecore_conn_type_cfg *p_cfg; 1399 int type; 1400 u32 len; 1401 1402 /* Reset acquired cids */ 1403 for (type = 0; type < MAX_CONN_TYPES; type++) { 1404 u32 vf; 1405 1406 p_cfg = &p_mngr->conn_cfg[type]; 1407 if (p_cfg->cid_count) { 1408 p_map = &p_mngr->acquired[type]; 1409 len = DIV_ROUND_UP(p_map->max_count, 1410 BITS_PER_MAP_WORD) * 1411 MAP_WORD_SIZE; 1412 OSAL_MEM_ZERO(p_map->cid_map, len); 1413 } 1414 1415 if (!p_cfg->cids_per_vf) 1416 continue; 1417 1418 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) { 1419 p_map = &p_mngr->acquired_vf[type][vf]; 1420 len = DIV_ROUND_UP(p_map->max_count, 1421 BITS_PER_MAP_WORD) * 1422 MAP_WORD_SIZE; 1423 OSAL_MEM_ZERO(p_map->cid_map, len); 1424 } 1425 } 1426 } 1427 1428 /* HW initialization helper (per Block, per phase) */ 1429 1430 /* CDU Common */ 1431 #define CDUC_CXT_SIZE_SHIFT \ 1432 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT 1433 1434 #define CDUC_CXT_SIZE_MASK \ 1435 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT) 1436 1437 #define CDUC_BLOCK_WASTE_SHIFT \ 1438 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT 1439 1440 #define CDUC_BLOCK_WASTE_MASK \ 1441 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT) 1442 1443 #define CDUC_NCIB_SHIFT \ 1444 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT 1445 1446 #define CDUC_NCIB_MASK \ 1447 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT) 1448 1449 #define CDUT_TYPE0_CXT_SIZE_SHIFT \ 1450 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 1451 1452 #define CDUT_TYPE0_CXT_SIZE_MASK \ 1453 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \ 1454 CDUT_TYPE0_CXT_SIZE_SHIFT) 1455 1456 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \ 1457 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 1458 1459 #define CDUT_TYPE0_BLOCK_WASTE_MASK \ 1460 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \ 1461 CDUT_TYPE0_BLOCK_WASTE_SHIFT) 1462 1463 #define CDUT_TYPE0_NCIB_SHIFT \ 1464 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 1465 1466 #define CDUT_TYPE0_NCIB_MASK \ 1467 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \ 1468 CDUT_TYPE0_NCIB_SHIFT) 1469 1470 #define CDUT_TYPE1_CXT_SIZE_SHIFT \ 1471 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 1472 1473 #define CDUT_TYPE1_CXT_SIZE_MASK \ 1474 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \ 1475 CDUT_TYPE1_CXT_SIZE_SHIFT) 1476 1477 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \ 1478 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 1479 1480 #define CDUT_TYPE1_BLOCK_WASTE_MASK \ 1481 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \ 1482 CDUT_TYPE1_BLOCK_WASTE_SHIFT) 1483 1484 #define CDUT_TYPE1_NCIB_SHIFT \ 1485 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 1486 1487 #define CDUT_TYPE1_NCIB_MASK \ 1488 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \ 1489 CDUT_TYPE1_NCIB_SHIFT) 1490 1491 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn) 1492 { 1493 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0; 1494 1495 /* CDUC - connection configuration */ 1496 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1497 cxt_size = CONN_CXT_SIZE(p_hwfn); 1498 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1499 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1500 1501 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); 1502 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); 1503 SET_FIELD(cdu_params, (u32)CDUC_NCIB, elems_per_page); 1504 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params); 1505 1506 /* CDUT - type-0 tasks configuration */ 1507 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val; 1508 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0]; 1509 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1510 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1511 1512 /* cxt size and block-waste are multipes of 8 */ 1513 cdu_params = 0; 1514 SET_FIELD(cdu_params, (u32)CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3)); 1515 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3)); 1516 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page); 1517 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params); 1518 1519 /* CDUT - type-1 tasks configuration */ 1520 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1]; 1521 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1522 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1523 1524 /* cxt size and block-waste are multipes of 8 */ 1525 cdu_params = 0; 1526 SET_FIELD(cdu_params, (u32)CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3)); 1527 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3)); 1528 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page); 1529 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params); 1530 } 1531 1532 /* CDU PF */ 1533 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT 1534 #define CDU_SEG_REG_TYPE_MASK 0x1 1535 #define CDU_SEG_REG_OFFSET_SHIFT 0 1536 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK 1537 1538 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn) 1539 { 1540 struct ecore_ilt_client_cfg *p_cli; 1541 struct ecore_tid_seg *p_seg; 1542 u32 cdu_seg_params, offset; 1543 int i; 1544 1545 static const u32 rt_type_offset_arr[] = { 1546 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET, 1547 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET, 1548 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET, 1549 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 1550 }; 1551 1552 static const u32 rt_type_offset_fl_arr[] = { 1553 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET, 1554 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET, 1555 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET, 1556 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 1557 }; 1558 1559 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1560 1561 /* There are initializations only for CDUT during pf Phase */ 1562 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1563 /* Segment 0*/ 1564 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i); 1565 if (!p_seg) 1566 continue; 1567 1568 /* Note: start_line is already adjusted for the CDU 1569 * segment register granularity, so we just need to 1570 * divide. Adjustment is implicit as we assume ILT 1571 * Page size is larger than 32K! 1572 */ 1573 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1574 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line - 1575 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1576 1577 cdu_seg_params = 0; 1578 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1579 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1580 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], 1581 cdu_seg_params); 1582 1583 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1584 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line - 1585 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1586 1587 cdu_seg_params = 0; 1588 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1589 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1590 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], 1591 cdu_seg_params); 1592 } 1593 } 1594 1595 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1596 bool is_pf_loading) 1597 { 1598 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1599 struct ecore_mcp_link_state *p_link; 1600 struct ecore_qm_iids iids; 1601 1602 OSAL_MEM_ZERO(&iids, sizeof(iids)); 1603 ecore_cxt_qm_iids(p_hwfn, &iids); 1604 1605 p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output; 1606 1607 ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id, 1608 p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port, 1609 is_pf_loading, 1610 iids.cids, iids.vf_cids, iids.tids, 1611 qm_info->start_pq, 1612 qm_info->num_pqs - qm_info->num_vf_pqs, 1613 qm_info->num_vf_pqs, 1614 qm_info->start_vport, 1615 qm_info->num_vports, qm_info->pf_wfq, 1616 qm_info->pf_rl, p_link->speed, 1617 p_hwfn->qm_info.qm_pq_params, 1618 p_hwfn->qm_info.qm_vport_params); 1619 } 1620 1621 /* CM PF */ 1622 static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn) 1623 { 1624 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB)); 1625 } 1626 1627 /* DQ PF */ 1628 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn) 1629 { 1630 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1631 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0; 1632 1633 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT); 1634 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid); 1635 1636 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT); 1637 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid); 1638 1639 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT); 1640 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid); 1641 1642 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT); 1643 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid); 1644 1645 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT); 1646 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid); 1647 1648 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT); 1649 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid); 1650 1651 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT); 1652 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid); 1653 1654 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT); 1655 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid); 1656 1657 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT); 1658 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid); 1659 1660 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT); 1661 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid); 1662 1663 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT); 1664 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid); 1665 1666 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT); 1667 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid); 1668 1669 /* Connection types 6 & 7 are not in use, yet they must be configured 1670 * as the highest possible connection. Not configuring them means the 1671 * defaults will be used, and with a large number of cids a bug may 1672 * occur, if the defaults will be smaller than dq_pf_max_cid / 1673 * dq_vf_max_cid. 1674 */ 1675 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid); 1676 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid); 1677 1678 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid); 1679 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid); 1680 } 1681 1682 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn) 1683 { 1684 struct ecore_ilt_client_cfg *ilt_clients; 1685 int i; 1686 1687 ilt_clients = p_hwfn->p_cxt_mngr->clients; 1688 for_each_ilt_valid_client(i, ilt_clients) { 1689 STORE_RT_REG(p_hwfn, 1690 ilt_clients[i].first.reg, 1691 ilt_clients[i].first.val); 1692 STORE_RT_REG(p_hwfn, 1693 ilt_clients[i].last.reg, 1694 ilt_clients[i].last.val); 1695 STORE_RT_REG(p_hwfn, 1696 ilt_clients[i].p_size.reg, 1697 ilt_clients[i].p_size.val); 1698 } 1699 } 1700 1701 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn) 1702 { 1703 struct ecore_ilt_client_cfg *p_cli; 1704 u32 blk_factor; 1705 1706 /* For simplicty we set the 'block' to be an ILT page */ 1707 if (p_hwfn->p_dev->p_iov_info) { 1708 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info; 1709 1710 STORE_RT_REG(p_hwfn, 1711 PSWRQ2_REG_VF_BASE_RT_OFFSET, 1712 p_iov->first_vf_in_pf); 1713 STORE_RT_REG(p_hwfn, 1714 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, 1715 p_iov->first_vf_in_pf + p_iov->total_vfs); 1716 } 1717 1718 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 1719 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1720 if (p_cli->active) { 1721 STORE_RT_REG(p_hwfn, 1722 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET, 1723 blk_factor); 1724 STORE_RT_REG(p_hwfn, 1725 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1726 p_cli->pf_total_lines); 1727 STORE_RT_REG(p_hwfn, 1728 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET, 1729 p_cli->vf_total_lines); 1730 } 1731 1732 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1733 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1734 if (p_cli->active) { 1735 STORE_RT_REG(p_hwfn, 1736 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET, 1737 blk_factor); 1738 STORE_RT_REG(p_hwfn, 1739 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1740 p_cli->pf_total_lines); 1741 STORE_RT_REG(p_hwfn, 1742 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET, 1743 p_cli->vf_total_lines); 1744 } 1745 1746 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM]; 1747 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1748 if (p_cli->active) { 1749 STORE_RT_REG(p_hwfn, 1750 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, 1751 blk_factor); 1752 STORE_RT_REG(p_hwfn, 1753 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1754 p_cli->pf_total_lines); 1755 STORE_RT_REG(p_hwfn, 1756 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET, 1757 p_cli->vf_total_lines); 1758 } 1759 } 1760 1761 /* ILT (PSWRQ2) PF */ 1762 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn) 1763 { 1764 struct ecore_ilt_client_cfg *clients; 1765 struct ecore_cxt_mngr *p_mngr; 1766 struct ecore_dma_mem *p_shdw; 1767 u32 line, rt_offst, i; 1768 1769 ecore_ilt_bounds_init(p_hwfn); 1770 ecore_ilt_vf_bounds_init(p_hwfn); 1771 1772 p_mngr = p_hwfn->p_cxt_mngr; 1773 p_shdw = p_mngr->ilt_shadow; 1774 clients = p_hwfn->p_cxt_mngr->clients; 1775 1776 for_each_ilt_valid_client(i, clients) { 1777 /* Client's 1st val and RT array are absolute, ILT shadows' 1778 * lines are relative. 1779 */ 1780 line = clients[i].first.val - p_mngr->pf_start_line; 1781 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET + 1782 clients[i].first.val * ILT_ENTRY_IN_REGS; 1783 1784 for (; line <= clients[i].last.val - p_mngr->pf_start_line; 1785 line++, rt_offst += ILT_ENTRY_IN_REGS) { 1786 u64 ilt_hw_entry = 0; 1787 1788 /** p_virt could be OSAL_NULL incase of dynamic 1789 * allocation 1790 */ 1791 if (p_shdw[line].p_virt != OSAL_NULL) { 1792 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 1793 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 1794 (unsigned long long)(p_shdw[line].p_phys >> 12)); 1795 1796 DP_VERBOSE( 1797 p_hwfn, ECORE_MSG_ILT, 1798 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n", 1799 rt_offst, line, i, 1800 (unsigned long long)(p_shdw[line].p_phys >> 12)); 1801 } 1802 1803 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry); 1804 } 1805 } 1806 } 1807 1808 /* SRC (Searcher) PF */ 1809 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn) 1810 { 1811 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1812 u32 rounded_conn_num, conn_num, conn_max; 1813 struct ecore_src_iids src_iids; 1814 1815 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids)); 1816 ecore_cxt_src_iids(p_mngr, &src_iids); 1817 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 1818 if (!conn_num) 1819 return; 1820 1821 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS); 1822 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max); 1823 1824 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num); 1825 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET, 1826 OSAL_LOG2(rounded_conn_num)); 1827 1828 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET, 1829 p_hwfn->p_cxt_mngr->first_free); 1830 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET, 1831 p_hwfn->p_cxt_mngr->last_free); 1832 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 1833 "Configured SEARCHER for 0x%08x connections\n", 1834 conn_num); 1835 } 1836 1837 /* Timers PF */ 1838 #define TM_CFG_NUM_IDS_SHIFT 0 1839 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL 1840 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16 1841 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL 1842 #define TM_CFG_PARENT_PF_SHIFT 25 1843 #define TM_CFG_PARENT_PF_MASK 0x7ULL 1844 1845 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30 1846 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL 1847 1848 #define TM_CFG_TID_OFFSET_SHIFT 30 1849 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL 1850 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49 1851 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL 1852 1853 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn) 1854 { 1855 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1856 u32 active_seg_mask = 0, tm_offset, rt_reg; 1857 struct ecore_tm_iids tm_iids; 1858 u64 cfg_word; 1859 u8 i; 1860 1861 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids)); 1862 ecore_cxt_tm_iids(p_mngr, &tm_iids); 1863 1864 /* @@@TBD No pre-scan for now */ 1865 1866 /* Note: We assume consecutive VFs for a PF */ 1867 for (i = 0; i < p_mngr->vf_count; i++) { 1868 cfg_word = 0; 1869 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids); 1870 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1871 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1872 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ 1873 1874 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1875 (sizeof(cfg_word) / sizeof(u32)) * 1876 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i); 1877 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1878 } 1879 1880 cfg_word = 0; 1881 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids); 1882 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1883 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */ 1884 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ 1885 1886 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1887 (sizeof(cfg_word) / sizeof(u32)) * 1888 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id); 1889 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1890 1891 /* enale scan */ 1892 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET, 1893 tm_iids.pf_cids ? 0x1 : 0x0); 1894 1895 /* @@@TBD how to enable the scan for the VFs */ 1896 1897 tm_offset = tm_iids.per_vf_cids; 1898 1899 /* Note: We assume consecutive VFs for a PF */ 1900 for (i = 0; i < p_mngr->vf_count; i++) { 1901 cfg_word = 0; 1902 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids); 1903 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1904 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1905 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1906 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0); 1907 1908 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1909 (sizeof(cfg_word) / sizeof(u32)) * 1910 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i); 1911 1912 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1913 } 1914 1915 tm_offset = tm_iids.pf_cids; 1916 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1917 cfg_word = 0; 1918 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]); 1919 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1920 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); 1921 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1922 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0); 1923 1924 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1925 (sizeof(cfg_word) / sizeof(u32)) * 1926 (NUM_OF_VFS(p_hwfn->p_dev) + 1927 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i); 1928 1929 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1930 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0); 1931 1932 tm_offset += tm_iids.pf_tids[i]; 1933 } 1934 1935 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) 1936 active_seg_mask = 0; 1937 1938 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask); 1939 1940 /* @@@TBD how to enable the scan for the VFs */ 1941 } 1942 1943 static void ecore_prs_init_common(struct ecore_hwfn *p_hwfn) 1944 { 1945 if ((p_hwfn->hw_info.personality == ECORE_PCI_FCOE) && 1946 p_hwfn->pf_params.fcoe_pf_params.is_target) 1947 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0); 1948 } 1949 1950 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn) 1951 { 1952 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1953 struct ecore_conn_type_cfg *p_fcoe; 1954 struct ecore_tid_seg *p_tid; 1955 1956 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE]; 1957 1958 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */ 1959 if (!p_fcoe->cid_count) 1960 return; 1961 1962 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG]; 1963 if (p_hwfn->pf_params.fcoe_pf_params.is_target) { 1964 STORE_RT_REG_AGG(p_hwfn, 1965 PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET, 1966 p_tid->count); 1967 } else { 1968 STORE_RT_REG_AGG(p_hwfn, 1969 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET, 1970 p_tid->count); 1971 } 1972 } 1973 1974 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn) 1975 { 1976 /* CDU configuration */ 1977 ecore_cdu_init_common(p_hwfn); 1978 ecore_prs_init_common(p_hwfn); 1979 } 1980 1981 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 1982 { 1983 ecore_qm_init_pf(p_hwfn, p_ptt, true); 1984 ecore_cm_init_pf(p_hwfn); 1985 ecore_dq_init_pf(p_hwfn); 1986 ecore_cdu_init_pf(p_hwfn); 1987 ecore_ilt_init_pf(p_hwfn); 1988 ecore_src_init_pf(p_hwfn); 1989 ecore_tm_init_pf(p_hwfn); 1990 ecore_prs_init_pf(p_hwfn); 1991 } 1992 1993 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn, 1994 enum protocol_type type, 1995 u32 *p_cid, u8 vfid) 1996 { 1997 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1998 struct ecore_cid_acquired_map *p_map; 1999 u32 rel_cid; 2000 2001 if (type >= MAX_CONN_TYPES) { 2002 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type); 2003 return ECORE_INVAL; 2004 } 2005 2006 if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) { 2007 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid); 2008 return ECORE_INVAL; 2009 } 2010 2011 /* Determine the right map to take this CID from */ 2012 if (vfid == ECORE_CXT_PF_CID) 2013 p_map = &p_mngr->acquired[type]; 2014 else 2015 p_map = &p_mngr->acquired_vf[type][vfid]; 2016 2017 if (p_map->cid_map == OSAL_NULL) { 2018 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type); 2019 return ECORE_INVAL; 2020 } 2021 2022 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map, 2023 p_map->max_count); 2024 2025 if (rel_cid >= p_map->max_count) { 2026 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n", 2027 type); 2028 return ECORE_NORESOURCES; 2029 } 2030 2031 OSAL_SET_BIT(rel_cid, p_map->cid_map); 2032 2033 *p_cid = rel_cid + p_map->start_cid; 2034 2035 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT, 2036 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n", 2037 *p_cid, rel_cid, vfid, type); 2038 2039 return ECORE_SUCCESS; 2040 } 2041 2042 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn, 2043 enum protocol_type type, 2044 u32 *p_cid) 2045 { 2046 return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID); 2047 } 2048 2049 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn, 2050 u32 cid, u8 vfid, 2051 enum protocol_type *p_type, 2052 struct ecore_cid_acquired_map **pp_map) 2053 { 2054 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2055 u32 rel_cid; 2056 2057 /* Iterate over protocols and find matching cid range */ 2058 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) { 2059 if (vfid == ECORE_CXT_PF_CID) 2060 *pp_map = &p_mngr->acquired[*p_type]; 2061 else 2062 *pp_map = &p_mngr->acquired_vf[*p_type][vfid]; 2063 2064 if (!((*pp_map)->cid_map)) 2065 continue; 2066 if (cid >= (*pp_map)->start_cid && 2067 cid < (*pp_map)->start_cid + (*pp_map)->max_count) { 2068 break; 2069 } 2070 } 2071 2072 if (*p_type == MAX_CONN_TYPES) { 2073 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid); 2074 goto fail; 2075 } 2076 2077 rel_cid = cid - (*pp_map)->start_cid; 2078 if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) { 2079 DP_NOTICE(p_hwfn, true, 2080 "CID %d [vifd %02x] not acquired", cid, vfid); 2081 goto fail; 2082 } 2083 2084 return true; 2085 fail: 2086 *p_type = MAX_CONN_TYPES; 2087 *pp_map = OSAL_NULL; 2088 return false; 2089 } 2090 2091 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid) 2092 { 2093 struct ecore_cid_acquired_map *p_map = OSAL_NULL; 2094 enum protocol_type type; 2095 bool b_acquired; 2096 u32 rel_cid; 2097 2098 if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) { 2099 DP_NOTICE(p_hwfn, true, 2100 "Trying to return incorrect CID belonging to VF %02x\n", 2101 vfid); 2102 return; 2103 } 2104 2105 /* Test acquired and find matching per-protocol map */ 2106 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid, 2107 &type, &p_map); 2108 2109 if (!b_acquired) 2110 return; 2111 2112 rel_cid = cid - p_map->start_cid; 2113 OSAL_CLEAR_BIT(rel_cid, p_map->cid_map); 2114 2115 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT, 2116 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n", 2117 cid, rel_cid, vfid, type); 2118 } 2119 2120 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid) 2121 { 2122 _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID); 2123 } 2124 2125 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn, 2126 struct ecore_cxt_info *p_info) 2127 { 2128 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2129 struct ecore_cid_acquired_map *p_map = OSAL_NULL; 2130 u32 conn_cxt_size, hw_p_size, cxts_per_p, line; 2131 enum protocol_type type; 2132 bool b_acquired; 2133 2134 /* Test acquired and find matching per-protocol map */ 2135 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, 2136 ECORE_CXT_PF_CID, 2137 &type, &p_map); 2138 2139 if (!b_acquired) 2140 return ECORE_INVAL; 2141 2142 /* set the protocl type */ 2143 p_info->type = type; 2144 2145 /* compute context virtual pointer */ 2146 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 2147 2148 conn_cxt_size = CONN_CXT_SIZE(p_hwfn); 2149 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size; 2150 line = p_info->iid / cxts_per_p; 2151 2152 /* Make sure context is allocated (dynamic allocation) */ 2153 if (!p_mngr->ilt_shadow[line].p_virt) 2154 return ECORE_INVAL; 2155 2156 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt + 2157 p_info->iid % cxts_per_p * conn_cxt_size; 2158 2159 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT), 2160 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n", 2161 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid); 2162 2163 return ECORE_SUCCESS; 2164 } 2165 2166 static void ecore_rdma_set_pf_params(struct ecore_hwfn *p_hwfn, 2167 struct ecore_rdma_pf_params *p_params, 2168 u32 num_tasks) 2169 { 2170 u32 num_cons, num_qps; 2171 enum protocol_type proto; 2172 2173 /* The only case RDMA personality can be overriden is if NVRAM is 2174 * configured with ETH_RDMA or if no rdma protocol was requested 2175 */ 2176 switch (p_params->rdma_protocol) { 2177 case ECORE_RDMA_PROTOCOL_DEFAULT: 2178 if (p_hwfn->mcp_info->func_info.protocol == 2179 ECORE_PCI_ETH_RDMA) { 2180 DP_NOTICE(p_hwfn, false, 2181 "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n"); 2182 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE; 2183 } 2184 break; 2185 case ECORE_RDMA_PROTOCOL_NONE: 2186 p_hwfn->hw_info.personality = ECORE_PCI_ETH; 2187 return; /* intentional... nothing left to do... */ 2188 case ECORE_RDMA_PROTOCOL_ROCE: 2189 if (p_hwfn->mcp_info->func_info.protocol == ECORE_PCI_ETH_RDMA) 2190 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE; 2191 break; 2192 case ECORE_RDMA_PROTOCOL_IWARP: 2193 if (p_hwfn->mcp_info->func_info.protocol == ECORE_PCI_ETH_RDMA) 2194 p_hwfn->hw_info.personality = ECORE_PCI_ETH_IWARP; 2195 break; 2196 } 2197 2198 switch (p_hwfn->hw_info.personality) { 2199 case ECORE_PCI_ETH_IWARP: 2200 /* Each QP requires one connection */ 2201 num_cons = OSAL_MIN_T(u32, IWARP_MAX_QPS, p_params->num_qps); 2202 #ifdef CONFIG_ECORE_IWARP /* required for the define */ 2203 /* additional connections required for passive tcp handling */ 2204 num_cons += ECORE_IWARP_PREALLOC_CNT; 2205 #endif 2206 proto = PROTOCOLID_IWARP; 2207 break; 2208 case ECORE_PCI_ETH_ROCE: 2209 num_qps = OSAL_MIN_T(u32, ROCE_MAX_QPS, p_params->num_qps); 2210 num_cons = num_qps * 2; /* each QP requires two connections */ 2211 proto = PROTOCOLID_ROCE; 2212 break; 2213 default: 2214 return; 2215 } 2216 2217 if (num_cons && num_tasks) { 2218 u32 num_srqs, num_xrc_srqs, max_xrc_srqs, page_size; 2219 2220 ecore_cxt_set_proto_cid_count(p_hwfn, proto, 2221 num_cons, 0); 2222 2223 /* Deliberatly passing ROCE for tasks id. This is because 2224 * iWARP / RoCE share the task id. 2225 */ 2226 ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE, 2227 ECORE_CXT_ROCE_TID_SEG, 2228 1, /* RoCE segment type */ 2229 num_tasks, 2230 false); /* !force load */ 2231 2232 num_srqs = OSAL_MIN_T(u32, ECORE_RDMA_MAX_SRQS, 2233 p_params->num_srqs); 2234 2235 /* XRC SRQs populate a single ILT page */ 2236 page_size = ecore_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM); 2237 max_xrc_srqs = page_size / XRC_SRQ_CXT_SIZE; 2238 max_xrc_srqs = OSAL_MIN_T(u32, max_xrc_srqs, ECORE_RDMA_MAX_XRC_SRQS); 2239 2240 num_xrc_srqs = OSAL_MIN_T(u32, p_params->num_xrc_srqs, 2241 max_xrc_srqs); 2242 ecore_cxt_set_srq_count(p_hwfn, num_srqs, num_xrc_srqs); 2243 2244 } else { 2245 DP_INFO(p_hwfn->p_dev, 2246 "RDMA personality used without setting params!\n"); 2247 } 2248 } 2249 2250 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn, 2251 u32 rdma_tasks) 2252 { 2253 /* Set the number of required CORE connections */ 2254 u32 core_cids = 1; /* SPQ */ 2255 2256 if (p_hwfn->using_ll2) 2257 core_cids += 4; /* @@@TBD Use the proper #define */ 2258 2259 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0); 2260 2261 switch (p_hwfn->hw_info.personality) { 2262 case ECORE_PCI_ETH_RDMA: 2263 case ECORE_PCI_ETH_IWARP: 2264 case ECORE_PCI_ETH_ROCE: 2265 { 2266 ecore_rdma_set_pf_params(p_hwfn, 2267 &p_hwfn->pf_params.rdma_pf_params, 2268 rdma_tasks); 2269 2270 /* no need for break since RoCE coexist with Ethernet */ 2271 } 2272 case ECORE_PCI_ETH: 2273 { 2274 u32 count = 0; 2275 2276 struct ecore_eth_pf_params *p_params = 2277 &p_hwfn->pf_params.eth_pf_params; 2278 2279 if (!p_params->num_vf_cons) 2280 p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT; 2281 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 2282 p_params->num_cons, 2283 p_params->num_vf_cons); 2284 2285 count = p_params->num_arfs_filters; 2286 2287 if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, 2288 &p_hwfn->p_dev->mf_bits)) 2289 p_hwfn->p_cxt_mngr->arfs_count = count; 2290 2291 break; 2292 } 2293 case ECORE_PCI_FCOE: 2294 { 2295 struct ecore_fcoe_pf_params *p_params; 2296 2297 p_params = &p_hwfn->pf_params.fcoe_pf_params; 2298 2299 if (p_params->num_cons && p_params->num_tasks) { 2300 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_FCOE, 2301 p_params->num_cons, 0); 2302 2303 ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE, 2304 ECORE_CXT_FCOE_TID_SEG, 2305 0, /* segment type */ 2306 p_params->num_tasks, 2307 true); 2308 } else { 2309 DP_INFO(p_hwfn->p_dev, 2310 "Fcoe personality used without setting params!\n"); 2311 } 2312 break; 2313 } 2314 case ECORE_PCI_ISCSI: 2315 { 2316 struct ecore_iscsi_pf_params *p_params; 2317 2318 p_params = &p_hwfn->pf_params.iscsi_pf_params; 2319 2320 if (p_params->num_cons && p_params->num_tasks) { 2321 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ISCSI, 2322 p_params->num_cons, 0); 2323 2324 ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ISCSI, 2325 ECORE_CXT_ISCSI_TID_SEG, 2326 0, /* segment type */ 2327 p_params->num_tasks, 2328 true); 2329 } else { 2330 DP_INFO(p_hwfn->p_dev, 2331 "Iscsi personality used without setting params!\n"); 2332 } 2333 break; 2334 } 2335 default: 2336 return ECORE_INVAL; 2337 } 2338 2339 return ECORE_SUCCESS; 2340 } 2341 2342 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn, 2343 struct ecore_tid_mem *p_info) 2344 { 2345 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2346 u32 proto, seg, total_lines, i, shadow_line; 2347 struct ecore_ilt_client_cfg *p_cli; 2348 struct ecore_ilt_cli_blk *p_fl_seg; 2349 struct ecore_tid_seg *p_seg_info; 2350 2351 /* Verify the personality */ 2352 switch (p_hwfn->hw_info.personality) { 2353 case ECORE_PCI_FCOE: 2354 proto = PROTOCOLID_FCOE; 2355 seg = ECORE_CXT_FCOE_TID_SEG; 2356 break; 2357 case ECORE_PCI_ISCSI: 2358 proto = PROTOCOLID_ISCSI; 2359 seg = ECORE_CXT_ISCSI_TID_SEG; 2360 break; 2361 default: 2362 return ECORE_INVAL; 2363 } 2364 2365 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2366 if (!p_cli->active) { 2367 return ECORE_INVAL; 2368 } 2369 2370 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2371 if (!p_seg_info->has_fl_mem) 2372 return ECORE_INVAL; 2373 2374 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2375 total_lines = DIV_ROUND_UP(p_fl_seg->total_size, 2376 p_fl_seg->real_size_in_page); 2377 2378 for (i = 0; i < total_lines; i++) { 2379 shadow_line = i + p_fl_seg->start_line - 2380 p_hwfn->p_cxt_mngr->pf_start_line; 2381 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt; 2382 } 2383 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) - 2384 p_fl_seg->real_size_in_page; 2385 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type]; 2386 p_info->num_tids_per_block = p_fl_seg->real_size_in_page / 2387 p_info->tid_size; 2388 2389 return ECORE_SUCCESS; 2390 } 2391 2392 /* This function is very RoCE oriented, if another protocol in the future 2393 * will want this feature we'll need to modify the function to be more generic 2394 */ 2395 enum _ecore_status_t 2396 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn, 2397 enum ecore_cxt_elem_type elem_type, 2398 u32 iid) 2399 { 2400 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; 2401 struct ecore_ilt_client_cfg *p_cli; 2402 struct ecore_ilt_cli_blk *p_blk; 2403 struct ecore_ptt *p_ptt; 2404 dma_addr_t p_phys; 2405 u64 ilt_hw_entry; 2406 void *p_virt; 2407 enum _ecore_status_t rc = ECORE_SUCCESS; 2408 2409 switch (elem_type) { 2410 case ECORE_ELEM_CXT: 2411 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2412 elem_size = CONN_CXT_SIZE(p_hwfn); 2413 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2414 break; 2415 case ECORE_ELEM_SRQ: 2416 /* The first ILT page is not used for regular SRQs. Skip it. */ 2417 iid += ecore_cxt_srqs_per_page(p_hwfn); 2418 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2419 elem_size = SRQ_CXT_SIZE; 2420 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2421 break; 2422 case ECORE_ELEM_XRC_SRQ: 2423 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2424 elem_size = XRC_SRQ_CXT_SIZE; 2425 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2426 break; 2427 case ECORE_ELEM_TASK: 2428 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2429 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2430 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)]; 2431 break; 2432 default: 2433 DP_NOTICE(p_hwfn, false, 2434 "ECORE_INVALID elem type = %d", elem_type); 2435 return ECORE_INVAL; 2436 } 2437 2438 /* Calculate line in ilt */ 2439 hw_p_size = p_cli->p_size.val; 2440 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2441 line = p_blk->start_line + (iid / elems_per_p); 2442 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line; 2443 2444 /* If line is already allocated, do nothing, otherwise allocate it and 2445 * write it to the PSWRQ2 registers. 2446 * This section can be run in parallel from different contexts and thus 2447 * a mutex protection is needed. 2448 */ 2449 #ifdef _NTDDK_ 2450 #pragma warning(suppress : 28121) 2451 #endif 2452 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex); 2453 2454 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt) 2455 goto out0; 2456 2457 p_ptt = ecore_ptt_acquire(p_hwfn); 2458 if (!p_ptt) { 2459 DP_NOTICE(p_hwfn, false, 2460 "ECORE_TIME_OUT on ptt acquire - dynamic allocation"); 2461 rc = ECORE_TIMEOUT; 2462 goto out0; 2463 } 2464 2465 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, 2466 &p_phys, 2467 p_blk->real_size_in_page); 2468 if (!p_virt) { 2469 rc = ECORE_NOMEM; 2470 goto out1; 2471 } 2472 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page); 2473 2474 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only, 2475 * to compensate for a HW bug, but it is configured even if DIF is not 2476 * enabled. This is harmless and allows us to avoid a dedicated API. We 2477 * configure the field for all of the contexts on the newly allocated 2478 * page. 2479 */ 2480 if (elem_type == ECORE_ELEM_TASK) { 2481 u32 elem_i; 2482 u8 *elem_start = (u8 *)p_virt; 2483 union type1_task_context *elem; 2484 2485 for (elem_i = 0; elem_i < elems_per_p; elem_i++) { 2486 elem = (union type1_task_context *)elem_start; 2487 SET_FIELD(elem->roce_ctx.tdif_context.flags1, 2488 TDIF_TASK_CONTEXT_REF_TAG_MASK , 0xf); 2489 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); 2490 } 2491 } 2492 2493 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt; 2494 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys; 2495 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size = 2496 p_blk->real_size_in_page; 2497 2498 /* compute absolute offset */ 2499 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2500 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS); 2501 2502 ilt_hw_entry = 0; 2503 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 2504 SET_FIELD(ilt_hw_entry, 2505 ILT_ENTRY_PHY_ADDR, 2506 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12)); 2507 2508 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */ 2509 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry, 2510 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 2511 OSAL_NULL /* default parameters */); 2512 2513 if (elem_type == ECORE_ELEM_CXT) { 2514 u32 last_cid_allocated = (1 + (iid / elems_per_p)) * 2515 elems_per_p; 2516 2517 /* Update the relevant register in the parser */ 2518 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 2519 last_cid_allocated - 1); 2520 2521 /* RoCE w/a -> we don't write to the prs search reg until first 2522 * cid is allocated. This is because the prs checks 2523 * last_cid-1 >=0 making 0 a valid value... this will cause 2524 * the a context load to occur on a RoCE packet received with 2525 * cid=0 even before context was initialized, can happen with a 2526 * stray packet from switch or a packet with crc-error 2527 */ 2528 2529 if (!p_hwfn->b_rdma_enabled_in_prs) { 2530 /* Enable Rdma search */ 2531 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1); 2532 p_hwfn->b_rdma_enabled_in_prs = true; 2533 } 2534 } 2535 2536 out1: 2537 ecore_ptt_release(p_hwfn, p_ptt); 2538 out0: 2539 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex); 2540 2541 return rc; 2542 } 2543 2544 /* This function is very RoCE oriented, if another protocol in the future 2545 * will want this feature we'll need to modify the function to be more generic 2546 */ 2547 enum _ecore_status_t 2548 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn, 2549 enum ecore_cxt_elem_type elem_type, 2550 u32 start_iid, u32 count) 2551 { 2552 u32 start_line, end_line, shadow_start_line, shadow_end_line; 2553 u32 reg_offset, elem_size, hw_p_size, elems_per_p; 2554 struct ecore_ilt_client_cfg *p_cli; 2555 struct ecore_ilt_cli_blk *p_blk; 2556 u32 end_iid = start_iid + count; 2557 struct ecore_ptt *p_ptt; 2558 u64 ilt_hw_entry = 0; 2559 u32 i; 2560 2561 switch (elem_type) { 2562 case ECORE_ELEM_CXT: 2563 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2564 elem_size = CONN_CXT_SIZE(p_hwfn); 2565 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2566 break; 2567 case ECORE_ELEM_SRQ: 2568 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2569 elem_size = SRQ_CXT_SIZE; 2570 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2571 break; 2572 case ECORE_ELEM_TASK: 2573 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2574 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2575 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)]; 2576 break; 2577 default: 2578 DP_NOTICE(p_hwfn, false, 2579 "ECORE_INVALID elem type = %d", elem_type); 2580 return ECORE_INVAL; 2581 } 2582 2583 /* Calculate line in ilt */ 2584 hw_p_size = p_cli->p_size.val; 2585 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2586 start_line = p_blk->start_line + (start_iid / elems_per_p); 2587 end_line = p_blk->start_line + (end_iid / elems_per_p); 2588 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p)) 2589 end_line--; 2590 2591 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line; 2592 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line; 2593 2594 p_ptt = ecore_ptt_acquire(p_hwfn); 2595 if (!p_ptt) { 2596 DP_NOTICE(p_hwfn, false, "ECORE_TIME_OUT on ptt acquire - dynamic allocation"); 2597 return ECORE_TIMEOUT; 2598 } 2599 2600 for (i = shadow_start_line; i < shadow_end_line; i++) { 2601 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt) 2602 continue; 2603 2604 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, 2605 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt, 2606 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys, 2607 p_hwfn->p_cxt_mngr->ilt_shadow[i].size); 2608 2609 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL; 2610 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0; 2611 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0; 2612 2613 /* compute absolute offset */ 2614 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2615 ((start_line++) * ILT_REG_SIZE_IN_BYTES * 2616 ILT_ENTRY_IN_REGS); 2617 2618 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a 2619 * wide-bus. 2620 */ 2621 ecore_dmae_host2grc(p_hwfn, p_ptt, 2622 (u64)(osal_uintptr_t)&ilt_hw_entry, 2623 reg_offset, 2624 sizeof(ilt_hw_entry) / sizeof(u32), 2625 OSAL_NULL /* default parameters */); 2626 } 2627 2628 ecore_ptt_release(p_hwfn, p_ptt); 2629 2630 return ECORE_SUCCESS; 2631 } 2632 2633 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn, 2634 u32 tid, 2635 u8 ctx_type, 2636 void **pp_task_ctx) 2637 { 2638 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2639 struct ecore_ilt_client_cfg *p_cli; 2640 struct ecore_tid_seg *p_seg_info; 2641 struct ecore_ilt_cli_blk *p_seg; 2642 u32 num_tids_per_block; 2643 u32 tid_size, ilt_idx; 2644 u32 total_lines; 2645 u32 proto, seg; 2646 2647 /* Verify the personality */ 2648 switch (p_hwfn->hw_info.personality) { 2649 case ECORE_PCI_FCOE: 2650 proto = PROTOCOLID_FCOE; 2651 seg = ECORE_CXT_FCOE_TID_SEG; 2652 break; 2653 case ECORE_PCI_ISCSI: 2654 proto = PROTOCOLID_ISCSI; 2655 seg = ECORE_CXT_ISCSI_TID_SEG; 2656 break; 2657 default: 2658 return ECORE_INVAL; 2659 } 2660 2661 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2662 if (!p_cli->active) { 2663 return ECORE_INVAL; 2664 } 2665 2666 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2667 2668 if (ctx_type == ECORE_CTX_WORKING_MEM) { 2669 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)]; 2670 } else if (ctx_type == ECORE_CTX_FL_MEM) { 2671 if (!p_seg_info->has_fl_mem) { 2672 return ECORE_INVAL; 2673 } 2674 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2675 } else { 2676 return ECORE_INVAL; 2677 } 2678 total_lines = DIV_ROUND_UP(p_seg->total_size, 2679 p_seg->real_size_in_page); 2680 tid_size = p_mngr->task_type_size[p_seg_info->type]; 2681 num_tids_per_block = p_seg->real_size_in_page / tid_size; 2682 2683 if (total_lines < tid/num_tids_per_block) 2684 return ECORE_INVAL; 2685 2686 ilt_idx = tid / num_tids_per_block + p_seg->start_line - 2687 p_mngr->pf_start_line; 2688 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt + 2689 (tid % num_tids_per_block) * tid_size; 2690 2691 return ECORE_SUCCESS; 2692 } 2693