1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * File : ecore_cxt.c 30 */ 31 #include <sys/cdefs.h> 32 #include "bcm_osal.h" 33 #include "reg_addr.h" 34 #include "common_hsi.h" 35 #include "ecore_hsi_common.h" 36 #include "ecore_hsi_eth.h" 37 #include "tcp_common.h" 38 #include "ecore_hsi_iscsi.h" 39 #include "ecore_hsi_fcoe.h" 40 #include "ecore_hsi_roce.h" 41 #include "ecore_hsi_iwarp.h" 42 #include "ecore_rt_defs.h" 43 #include "ecore_status.h" 44 #include "ecore.h" 45 #include "ecore_init_ops.h" 46 #include "ecore_init_fw_funcs.h" 47 #include "ecore_cxt.h" 48 #include "ecore_hw.h" 49 #include "ecore_dev_api.h" 50 #include "ecore_sriov.h" 51 #include "ecore_rdma.h" 52 #include "ecore_mcp.h" 53 54 /* Max number of connection types in HW (DQ/CDU etc.) */ 55 #define MAX_CONN_TYPES PROTOCOLID_COMMON 56 #define NUM_TASK_TYPES 2 57 #define NUM_TASK_PF_SEGMENTS 4 58 #define NUM_TASK_VF_SEGMENTS 1 59 60 /* Doorbell-Queue constants */ 61 #define DQ_RANGE_SHIFT 4 62 #define DQ_RANGE_ALIGN (1 << DQ_RANGE_SHIFT) 63 64 /* Searcher constants */ 65 #define SRC_MIN_NUM_ELEMS 256 66 67 /* Timers constants */ 68 #define TM_SHIFT 7 69 #define TM_ALIGN (1 << TM_SHIFT) 70 #define TM_ELEM_SIZE 4 71 72 /* ILT constants */ 73 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12)) 74 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_##cli##_##reg##_RT_OFFSET 75 76 /* ILT entry structure */ 77 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL 78 #define ILT_ENTRY_PHY_ADDR_SHIFT 0 79 #define ILT_ENTRY_VALID_MASK 0x1ULL 80 #define ILT_ENTRY_VALID_SHIFT 52 81 #define ILT_ENTRY_IN_REGS 2 82 #define ILT_REG_SIZE_IN_BYTES 4 83 84 /* connection context union */ 85 union conn_context { 86 struct e4_core_conn_context core_ctx; 87 struct e4_eth_conn_context eth_ctx; 88 struct e4_iscsi_conn_context iscsi_ctx; 89 struct e4_fcoe_conn_context fcoe_ctx; 90 struct e4_roce_conn_context roce_ctx; 91 }; 92 93 /* TYPE-0 task context - iSCSI, FCOE */ 94 union type0_task_context { 95 struct e4_iscsi_task_context iscsi_ctx; 96 struct e4_fcoe_task_context fcoe_ctx; 97 }; 98 99 /* TYPE-1 task context - ROCE */ 100 union type1_task_context { 101 struct e4_rdma_task_context roce_ctx; 102 }; 103 104 struct src_ent { 105 u8 opaque[56]; 106 u64 next; 107 }; 108 109 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ 110 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12)) 111 112 #define CONN_CXT_SIZE(p_hwfn) \ 113 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn) 114 115 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context)) 116 #define XRC_SRQ_CXT_SIZE (sizeof(struct rdma_xrc_srq_context)) 117 118 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \ 119 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn) 120 121 /* Alignment is inherent to the type1_task_context structure */ 122 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context) 123 124 /* PF per protocl configuration object */ 125 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS) 126 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS) 127 128 struct ecore_tid_seg { 129 u32 count; 130 u8 type; 131 bool has_fl_mem; 132 }; 133 134 struct ecore_conn_type_cfg { 135 u32 cid_count; 136 u32 cids_per_vf; 137 struct ecore_tid_seg tid_seg[TASK_SEGMENTS]; 138 }; 139 140 /* ILT Client configuration, 141 * Per connection type (protocol) resources (cids, tis, vf cids etc.) 142 * 1 - for connection context (CDUC) and for each task context we need two 143 * values, for regular task context and for force load memory 144 */ 145 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2) 146 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2) 147 #define CDUC_BLK (0) 148 #define SRQ_BLK (0) 149 #define CDUT_SEG_BLK(n) (1 + (u8)(n)) 150 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS) 151 152 struct ilt_cfg_pair { 153 u32 reg; 154 u32 val; 155 }; 156 157 struct ecore_ilt_cli_blk { 158 u32 total_size; /* 0 means not active */ 159 u32 real_size_in_page; 160 u32 start_line; 161 u32 dynamic_line_cnt; 162 }; 163 164 struct ecore_ilt_client_cfg { 165 bool active; 166 167 /* ILT boundaries */ 168 struct ilt_cfg_pair first; 169 struct ilt_cfg_pair last; 170 struct ilt_cfg_pair p_size; 171 172 /* ILT client blocks for PF */ 173 struct ecore_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS]; 174 u32 pf_total_lines; 175 176 /* ILT client blocks for VFs */ 177 struct ecore_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS]; 178 u32 vf_total_lines; 179 }; 180 181 /* Per Path - 182 * ILT shadow table 183 * Protocol acquired CID lists 184 * PF start line in ILT 185 */ 186 struct ecore_dma_mem { 187 dma_addr_t p_phys; 188 void *p_virt; 189 osal_size_t size; 190 }; 191 192 #define MAP_WORD_SIZE sizeof(unsigned long) 193 #define BITS_PER_MAP_WORD (MAP_WORD_SIZE * 8) 194 195 struct ecore_cid_acquired_map { 196 u32 start_cid; 197 u32 max_count; 198 unsigned long *cid_map; 199 }; 200 201 struct ecore_cxt_mngr { 202 /* Per protocl configuration */ 203 struct ecore_conn_type_cfg conn_cfg[MAX_CONN_TYPES]; 204 205 /* computed ILT structure */ 206 struct ecore_ilt_client_cfg clients[ILT_CLI_MAX]; 207 208 /* Task type sizes */ 209 u32 task_type_size[NUM_TASK_TYPES]; 210 211 /* total number of VFs for this hwfn - 212 * ALL VFs are symmetric in terms of HW resources 213 */ 214 u32 vf_count; 215 216 /* Acquired CIDs */ 217 struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES]; 218 /* TBD - do we want this allocated to reserve space? */ 219 struct ecore_cid_acquired_map acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS]; 220 221 /* ILT shadow table */ 222 struct ecore_dma_mem *ilt_shadow; 223 u32 pf_start_line; 224 225 /* Mutex for a dynamic ILT allocation */ 226 osal_mutex_t mutex; 227 228 /* SRC T2 */ 229 struct ecore_dma_mem *t2; 230 u32 t2_num_pages; 231 u64 first_free; 232 u64 last_free; 233 234 /* The infrastructure originally was very generic and context/task 235 * oriented - per connection-type we would set how many of those 236 * are needed, and later when determining how much memory we're 237 * needing for a given block we'd iterate over all the relevant 238 * connection-types. 239 * But since then we've had some additional resources, some of which 240 * require memory which is independent of the general context/task 241 * scheme. We add those here explicitly per-feature. 242 */ 243 244 /* total number of SRQ's for this hwfn */ 245 u32 srq_count; 246 u32 xrc_srq_count; 247 248 /* Maximal number of L2 steering filters */ 249 u32 arfs_count; 250 251 /* TODO - VF arfs filters ? */ 252 }; 253 254 /* check if resources/configuration is required according to protocol type */ 255 static bool src_proto(enum protocol_type type) 256 { 257 return type == PROTOCOLID_ISCSI || 258 type == PROTOCOLID_FCOE || 259 type == PROTOCOLID_IWARP; 260 } 261 262 static bool tm_cid_proto(enum protocol_type type) 263 { 264 return type == PROTOCOLID_ISCSI || 265 type == PROTOCOLID_FCOE || 266 type == PROTOCOLID_ROCE || 267 type == PROTOCOLID_IWARP; 268 } 269 270 static bool tm_tid_proto(enum protocol_type type) 271 { 272 return type == PROTOCOLID_FCOE; 273 } 274 275 /* counts the iids for the CDU/CDUC ILT client configuration */ 276 struct ecore_cdu_iids { 277 u32 pf_cids; 278 u32 per_vf_cids; 279 }; 280 281 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr *p_mngr, 282 struct ecore_cdu_iids *iids) 283 { 284 u32 type; 285 286 for (type = 0; type < MAX_CONN_TYPES; type++) { 287 iids->pf_cids += p_mngr->conn_cfg[type].cid_count; 288 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 289 } 290 } 291 292 /* counts the iids for the Searcher block configuration */ 293 struct ecore_src_iids { 294 u32 pf_cids; 295 u32 per_vf_cids; 296 }; 297 298 static void ecore_cxt_src_iids(struct ecore_cxt_mngr *p_mngr, 299 struct ecore_src_iids *iids) 300 { 301 u32 i; 302 303 for (i = 0; i < MAX_CONN_TYPES; i++) { 304 if (!src_proto(i)) 305 continue; 306 307 iids->pf_cids += p_mngr->conn_cfg[i].cid_count; 308 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf; 309 } 310 311 /* Add L2 filtering filters in addition */ 312 iids->pf_cids += p_mngr->arfs_count; 313 } 314 315 /* counts the iids for the Timers block configuration */ 316 struct ecore_tm_iids { 317 u32 pf_cids; 318 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */ 319 u32 pf_tids_total; 320 u32 per_vf_cids; 321 u32 per_vf_tids; 322 }; 323 324 static void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr, 325 struct ecore_tm_iids *iids) 326 { 327 bool tm_vf_required = false; 328 bool tm_required = false; 329 int i, j; 330 331 /* Timers is a special case -> we don't count how many cids require 332 * timers but what's the max cid that will be used by the timer block. 333 * therefore we traverse in reverse order, and once we hit a protocol 334 * that requires the timers memory, we'll sum all the protocols up 335 * to that one. 336 */ 337 for (i = MAX_CONN_TYPES - 1; i >= 0; i--) { 338 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i]; 339 340 if (tm_cid_proto(i) || tm_required) { 341 if (p_cfg->cid_count) 342 tm_required = true; 343 344 iids->pf_cids += p_cfg->cid_count; 345 } 346 347 if (tm_cid_proto(i) || tm_vf_required) { 348 if (p_cfg->cids_per_vf) 349 tm_vf_required = true; 350 351 iids->per_vf_cids += p_cfg->cids_per_vf; 352 } 353 354 if (tm_tid_proto(i)) { 355 struct ecore_tid_seg *segs = p_cfg->tid_seg; 356 357 /* for each segment there is at most one 358 * protocol for which count is not 0. 359 */ 360 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 361 iids->pf_tids[j] += segs[j].count; 362 363 /* The last array elelment is for the VFs. As for PF 364 * segments there can be only one protocol for 365 * which this value is not 0. 366 */ 367 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 368 } 369 } 370 371 iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN); 372 iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN); 373 iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN); 374 375 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) { 376 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN); 377 iids->pf_tids_total += iids->pf_tids[j]; 378 } 379 } 380 381 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, 382 struct ecore_qm_iids *iids) 383 { 384 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 385 struct ecore_tid_seg *segs; 386 u32 vf_cids = 0, type, j; 387 u32 vf_tids = 0; 388 389 for (type = 0; type < MAX_CONN_TYPES; type++) { 390 iids->cids += p_mngr->conn_cfg[type].cid_count; 391 vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 392 393 segs = p_mngr->conn_cfg[type].tid_seg; 394 /* for each segment there is at most one 395 * protocol for which count is not 0. 396 */ 397 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 398 iids->tids += segs[j].count; 399 400 /* The last array elelment is for the VFs. As for PF 401 * segments there can be only one protocol for 402 * which this value is not 0. 403 */ 404 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 405 } 406 407 iids->vf_cids += vf_cids * p_mngr->vf_count; 408 iids->tids += vf_tids * p_mngr->vf_count; 409 410 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 411 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n", 412 iids->cids, iids->vf_cids, iids->tids, vf_tids); 413 } 414 415 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn, 416 u32 seg) 417 { 418 struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr; 419 u32 i; 420 421 /* Find the protocol with tid count > 0 for this segment. 422 Note: there can only be one and this is already validated. 423 */ 424 for (i = 0; i < MAX_CONN_TYPES; i++) { 425 if (p_cfg->conn_cfg[i].tid_seg[seg].count) 426 return &p_cfg->conn_cfg[i].tid_seg[seg]; 427 } 428 return OSAL_NULL; 429 } 430 431 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, 432 u32 num_srqs, u32 num_xrc_srqs) 433 { 434 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 435 436 p_mgr->srq_count = num_srqs; 437 p_mgr->xrc_srq_count = num_xrc_srqs; 438 } 439 440 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn) 441 { 442 return p_hwfn->p_cxt_mngr->srq_count; 443 } 444 445 u32 ecore_cxt_get_xrc_srq_count(struct ecore_hwfn *p_hwfn) 446 { 447 return p_hwfn->p_cxt_mngr->xrc_srq_count; 448 } 449 450 u32 ecore_cxt_get_ilt_page_size(struct ecore_hwfn *p_hwfn, 451 enum ilt_clients ilt_client) 452 { 453 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 454 struct ecore_ilt_client_cfg *p_cli = &p_mngr->clients[ilt_client]; 455 456 return ILT_PAGE_IN_BYTES(p_cli->p_size.val); 457 } 458 459 static u32 ecore_cxt_srqs_per_page(struct ecore_hwfn *p_hwfn) 460 { 461 u32 page_size; 462 463 page_size = ecore_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM); 464 return page_size / SRQ_CXT_SIZE; 465 } 466 467 u32 ecore_cxt_get_total_srq_count(struct ecore_hwfn *p_hwfn) 468 { 469 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 470 u32 total_srqs; 471 472 total_srqs = p_mgr->srq_count; 473 474 /* XRC SRQs use the first and only the first SRQ ILT page. So if XRC 475 * SRQs are requested we need to allocate an extra SRQ ILT page for 476 * them. For that We increase the number of regular SRQs to cause the 477 * allocation of that extra page. 478 */ 479 if (p_mgr->xrc_srq_count) 480 total_srqs += ecore_cxt_srqs_per_page(p_hwfn); 481 482 return total_srqs; 483 } 484 485 /* set the iids (cid/tid) count per protocol */ 486 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn, 487 enum protocol_type type, 488 u32 cid_count, u32 vf_cid_cnt) 489 { 490 struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 491 struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type]; 492 493 p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN); 494 p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN); 495 496 if (type == PROTOCOLID_ROCE) { 497 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; 498 u32 cxt_size = CONN_CXT_SIZE(p_hwfn); 499 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 500 u32 align = elems_per_page * DQ_RANGE_ALIGN; 501 502 p_conn->cid_count = ROUNDUP(p_conn->cid_count, align); 503 } 504 } 505 506 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn, 507 enum protocol_type type, 508 u32 *vf_cid) 509 { 510 if (vf_cid) 511 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf; 512 513 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; 514 } 515 516 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn, 517 enum protocol_type type) 518 { 519 return p_hwfn->p_cxt_mngr->acquired[type].start_cid; 520 } 521 522 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn, 523 enum protocol_type type) 524 { 525 u32 cnt = 0; 526 int i; 527 528 for (i = 0; i < TASK_SEGMENTS; i++) 529 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count; 530 531 return cnt; 532 } 533 534 static void ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn, 535 enum protocol_type proto, 536 u8 seg, 537 u8 seg_type, 538 u32 count, 539 bool has_fl) 540 { 541 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 542 struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg]; 543 544 p_seg->count = count; 545 p_seg->has_fl_mem = has_fl; 546 p_seg->type = seg_type; 547 } 548 549 /* the *p_line parameter must be either 0 for the first invocation or the 550 value returned in the previous invocation. 551 */ 552 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg *p_cli, 553 struct ecore_ilt_cli_blk *p_blk, 554 u32 start_line, 555 u32 total_size, 556 u32 elem_size) 557 { 558 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 559 560 /* verify that it's called once for each block */ 561 if (p_blk->total_size) 562 return; 563 564 p_blk->total_size = total_size; 565 p_blk->real_size_in_page = 0; 566 if (elem_size) 567 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size; 568 p_blk->start_line = start_line; 569 } 570 571 static void ecore_ilt_cli_adv_line(struct ecore_hwfn *p_hwfn, 572 struct ecore_ilt_client_cfg *p_cli, 573 struct ecore_ilt_cli_blk *p_blk, 574 u32 *p_line, 575 enum ilt_clients client_id) 576 { 577 if (!p_blk->total_size) 578 return; 579 580 if (!p_cli->active) 581 p_cli->first.val = *p_line; 582 583 p_cli->active = true; 584 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 585 p_cli->last.val = *p_line-1; 586 587 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 588 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n", 589 client_id, p_cli->first.val, p_cli->last.val, 590 p_blk->total_size, p_blk->real_size_in_page, 591 p_blk->start_line); 592 } 593 594 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn, 595 enum ilt_clients ilt_client) 596 { 597 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count; 598 struct ecore_ilt_client_cfg *p_cli; 599 u32 lines_to_skip = 0; 600 u32 cxts_per_p; 601 602 /* TBD MK: ILT code should be simplified once PROTO enum is changed */ 603 604 if (ilt_client == ILT_CLI_CDUC) { 605 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 606 607 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) / 608 (u32)CONN_CXT_SIZE(p_hwfn); 609 610 lines_to_skip = cid_count / cxts_per_p; 611 } 612 613 return lines_to_skip; 614 } 615 616 static struct ecore_ilt_client_cfg * 617 ecore_cxt_set_cli(struct ecore_ilt_client_cfg *p_cli) 618 { 619 p_cli->active = false; 620 p_cli->first.val = 0; 621 p_cli->last.val = 0; 622 return p_cli; 623 } 624 625 static struct ecore_ilt_cli_blk * 626 ecore_cxt_set_blk(struct ecore_ilt_cli_blk *p_blk) 627 { 628 p_blk->total_size = 0; 629 return p_blk; 630 } 631 632 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn, 633 u32 *line_count) 634 { 635 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 636 u32 curr_line, total, i, task_size, line; 637 struct ecore_ilt_client_cfg *p_cli; 638 struct ecore_ilt_cli_blk *p_blk; 639 struct ecore_cdu_iids cdu_iids; 640 struct ecore_src_iids src_iids; 641 struct ecore_qm_iids qm_iids; 642 struct ecore_tm_iids tm_iids; 643 struct ecore_tid_seg *p_seg; 644 645 OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids)); 646 OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids)); 647 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids)); 648 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids)); 649 650 p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT); 651 652 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 653 "hwfn [%d] - Set context manager starting line to be 0x%08x\n", 654 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line); 655 656 /* CDUC */ 657 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]); 658 659 curr_line = p_mngr->pf_start_line; 660 661 /* CDUC PF */ 662 p_cli->pf_total_lines = 0; 663 664 /* get the counters for the CDUC,CDUC and QM clients */ 665 ecore_cxt_cdu_iids(p_mngr, &cdu_iids); 666 667 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]); 668 669 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn); 670 671 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 672 total, CONN_CXT_SIZE(p_hwfn)); 673 674 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 675 p_cli->pf_total_lines = curr_line - p_blk->start_line; 676 677 p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn, 678 ILT_CLI_CDUC); 679 680 /* CDUC VF */ 681 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]); 682 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn); 683 684 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 685 total, CONN_CXT_SIZE(p_hwfn)); 686 687 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 688 p_cli->vf_total_lines = curr_line - p_blk->start_line; 689 690 for (i = 1; i < p_mngr->vf_count; i++) 691 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 692 ILT_CLI_CDUC); 693 694 /* CDUT PF */ 695 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]); 696 p_cli->first.val = curr_line; 697 698 /* first the 'working' task memory */ 699 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 700 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i); 701 if (!p_seg || p_seg->count == 0) 702 continue; 703 704 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]); 705 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 706 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total, 707 p_mngr->task_type_size[p_seg->type]); 708 709 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 710 ILT_CLI_CDUT); 711 } 712 713 /* next the 'init' task memory (forced load memory) */ 714 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 715 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i); 716 if (!p_seg || p_seg->count == 0) 717 continue; 718 719 p_blk = ecore_cxt_set_blk( 720 &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]); 721 722 if (!p_seg->has_fl_mem) { 723 /* The segment is active (total size pf 'working' 724 * memory is > 0) but has no FL (forced-load, Init) 725 * memory. Thus: 726 * 727 * 1. The total-size in the corrsponding FL block of 728 * the ILT client is set to 0 - No ILT line are 729 * provisioned and no ILT memory allocated. 730 * 731 * 2. The start-line of said block is set to the 732 * start line of the matching working memory 733 * block in the ILT client. This is later used to 734 * configure the CDU segment offset registers and 735 * results in an FL command for TIDs of this 736 * segement behaves as regular load commands 737 * (loading TIDs from the working memory). 738 */ 739 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line; 740 741 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 742 continue; 743 } 744 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 745 746 ecore_ilt_cli_blk_fill(p_cli, p_blk, 747 curr_line, total, 748 p_mngr->task_type_size[p_seg->type]); 749 750 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 751 ILT_CLI_CDUT); 752 } 753 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line; 754 755 /* CDUT VF */ 756 p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF); 757 if (p_seg && p_seg->count) { 758 /* Stricly speaking we need to iterate over all VF 759 * task segment types, but a VF has only 1 segment 760 */ 761 762 /* 'working' memory */ 763 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 764 765 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]); 766 ecore_ilt_cli_blk_fill(p_cli, p_blk, 767 curr_line, total, 768 p_mngr->task_type_size[p_seg->type]); 769 770 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 771 ILT_CLI_CDUT); 772 773 /* 'init' memory */ 774 p_blk = ecore_cxt_set_blk( 775 &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]); 776 if (!p_seg->has_fl_mem) { 777 /* see comment above */ 778 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line; 779 ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 780 } else { 781 task_size = p_mngr->task_type_size[p_seg->type]; 782 ecore_ilt_cli_blk_fill(p_cli, p_blk, 783 curr_line, total, 784 task_size); 785 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 786 ILT_CLI_CDUT); 787 } 788 p_cli->vf_total_lines = curr_line - 789 p_cli->vf_blks[0].start_line; 790 791 /* Now for the rest of the VFs */ 792 for (i = 1; i < p_mngr->vf_count; i++) { 793 /* don't set p_blk i.e. don't clear total_size */ 794 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)]; 795 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 796 ILT_CLI_CDUT); 797 798 /* don't set p_blk i.e. don't clear total_size */ 799 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]; 800 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 801 ILT_CLI_CDUT); 802 } 803 } 804 805 /* QM */ 806 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]); 807 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]); 808 809 ecore_cxt_qm_iids(p_hwfn, &qm_iids); 810 total = ecore_qm_pf_mem_size(qm_iids.cids, 811 qm_iids.vf_cids, qm_iids.tids, 812 p_hwfn->qm_info.num_pqs, 813 p_hwfn->qm_info.num_vf_pqs); 814 815 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 816 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n", 817 qm_iids.cids, qm_iids.vf_cids, qm_iids.tids, 818 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total); 819 820 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000, 821 QM_PQ_ELEMENT_SIZE); 822 823 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM); 824 p_cli->pf_total_lines = curr_line - p_blk->start_line; 825 826 /* SRC */ 827 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]); 828 ecore_cxt_src_iids(p_mngr, &src_iids); 829 830 /* Both the PF and VFs searcher connections are stored in the per PF 831 * database. Thus sum the PF searcher cids and all the VFs searcher 832 * cids. 833 */ 834 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 835 if (total) { 836 u32 local_max = OSAL_MAX_T(u32, total, 837 SRC_MIN_NUM_ELEMS); 838 839 total = OSAL_ROUNDUP_POW_OF_TWO(local_max); 840 841 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]); 842 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 843 total * sizeof(struct src_ent), 844 sizeof(struct src_ent)); 845 846 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 847 ILT_CLI_SRC); 848 p_cli->pf_total_lines = curr_line - p_blk->start_line; 849 } 850 851 /* TM PF */ 852 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]); 853 ecore_cxt_tm_iids(p_mngr, &tm_iids); 854 total = tm_iids.pf_cids + tm_iids.pf_tids_total; 855 if (total) { 856 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]); 857 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 858 total * TM_ELEM_SIZE, 859 TM_ELEM_SIZE); 860 861 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 862 ILT_CLI_TM); 863 p_cli->pf_total_lines = curr_line - p_blk->start_line; 864 } 865 866 /* TM VF */ 867 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids; 868 if (total) { 869 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[0]); 870 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 871 total * TM_ELEM_SIZE, 872 TM_ELEM_SIZE); 873 874 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 875 ILT_CLI_TM); 876 877 p_cli->vf_total_lines = curr_line - p_blk->start_line; 878 for (i = 1; i < p_mngr->vf_count; i++) { 879 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 880 ILT_CLI_TM); 881 } 882 } 883 884 /* TSDM (SRQ CONTEXT) */ 885 total = ecore_cxt_get_total_srq_count(p_hwfn); 886 if (total) { 887 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]); 888 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]); 889 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 890 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE); 891 892 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 893 ILT_CLI_TSDM); 894 p_cli->pf_total_lines = curr_line - p_blk->start_line; 895 } 896 897 *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line; 898 899 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line > 900 RESC_NUM(p_hwfn, ECORE_ILT)) { 901 return ECORE_INVAL; 902 } 903 904 return ECORE_SUCCESS; 905 } 906 907 u32 ecore_cxt_cfg_ilt_compute_excess(struct ecore_hwfn *p_hwfn, u32 used_lines) 908 { 909 struct ecore_ilt_client_cfg *p_cli; 910 u32 excess_lines, available_lines; 911 struct ecore_cxt_mngr *p_mngr; 912 u32 ilt_page_size, elem_size; 913 struct ecore_tid_seg *p_seg; 914 int i; 915 916 available_lines = RESC_NUM(p_hwfn, ECORE_ILT); 917 excess_lines = used_lines - available_lines; 918 919 if (!excess_lines) 920 return 0; 921 922 if (!ECORE_IS_RDMA_PERSONALITY(p_hwfn)) 923 return 0; 924 925 p_mngr = p_hwfn->p_cxt_mngr; 926 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 927 ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 928 929 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 930 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i); 931 if (!p_seg || p_seg->count == 0) 932 continue; 933 934 elem_size = p_mngr->task_type_size[p_seg->type]; 935 if (!elem_size) 936 continue; 937 938 return (ilt_page_size / elem_size) * excess_lines; 939 } 940 941 DP_ERR(p_hwfn, "failed computing excess ILT lines\n"); 942 return 0; 943 } 944 945 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn) 946 { 947 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 948 u32 i; 949 950 if (!p_mngr->t2) 951 return; 952 953 for (i = 0; i < p_mngr->t2_num_pages; i++) 954 if (p_mngr->t2[i].p_virt) 955 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, 956 p_mngr->t2[i].p_virt, 957 p_mngr->t2[i].p_phys, 958 p_mngr->t2[i].size); 959 960 OSAL_FREE(p_hwfn->p_dev, p_mngr->t2); 961 p_mngr->t2 = OSAL_NULL; 962 } 963 964 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn) 965 { 966 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 967 u32 conn_num, total_size, ent_per_page, psz, i; 968 struct ecore_ilt_client_cfg *p_src; 969 struct ecore_src_iids src_iids; 970 struct ecore_dma_mem *p_t2; 971 enum _ecore_status_t rc; 972 973 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids)); 974 975 /* if the SRC ILT client is inactive - there are no connection 976 * requiring the searcer, leave. 977 */ 978 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC]; 979 if (!p_src->active) 980 return ECORE_SUCCESS; 981 982 ecore_cxt_src_iids(p_mngr, &src_iids); 983 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 984 total_size = conn_num * sizeof(struct src_ent); 985 986 /* use the same page size as the SRC ILT client */ 987 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val); 988 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz); 989 990 /* allocate t2 */ 991 p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 992 p_mngr->t2_num_pages * 993 sizeof(struct ecore_dma_mem)); 994 if (!p_mngr->t2) { 995 DP_NOTICE(p_hwfn, false, "Failed to allocate t2 table\n"); 996 rc = ECORE_NOMEM; 997 goto t2_fail; 998 } 999 1000 /* allocate t2 pages */ 1001 for (i = 0; i < p_mngr->t2_num_pages; i++) { 1002 u32 size = OSAL_MIN_T(u32, total_size, psz); 1003 void **p_virt = &p_mngr->t2[i].p_virt; 1004 1005 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, 1006 &p_mngr->t2[i].p_phys, 1007 size); 1008 if (!p_mngr->t2[i].p_virt) { 1009 rc = ECORE_NOMEM; 1010 goto t2_fail; 1011 } 1012 OSAL_MEM_ZERO(*p_virt, size); 1013 p_mngr->t2[i].size = size; 1014 total_size -= size; 1015 } 1016 1017 /* Set the t2 pointers */ 1018 1019 /* entries per page - must be a power of two */ 1020 ent_per_page = psz / sizeof(struct src_ent); 1021 1022 p_mngr->first_free = (u64)p_mngr->t2[0].p_phys; 1023 1024 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page]; 1025 p_mngr->last_free = (u64)p_t2->p_phys + 1026 ((conn_num - 1) & (ent_per_page - 1)) * 1027 sizeof(struct src_ent); 1028 1029 for (i = 0; i < p_mngr->t2_num_pages; i++) { 1030 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num); 1031 struct src_ent *entries = p_mngr->t2[i].p_virt; 1032 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val; 1033 u32 j; 1034 1035 for (j = 0; j < ent_num - 1; j++) { 1036 val = p_ent_phys + 1037 (j + 1) * sizeof(struct src_ent); 1038 entries[j].next = OSAL_CPU_TO_BE64(val); 1039 } 1040 1041 if (i < p_mngr->t2_num_pages - 1) 1042 val = (u64)p_mngr->t2[i + 1].p_phys; 1043 else 1044 val = 0; 1045 entries[j].next = OSAL_CPU_TO_BE64(val); 1046 1047 conn_num -= ent_num; 1048 } 1049 1050 return ECORE_SUCCESS; 1051 1052 t2_fail: 1053 ecore_cxt_src_t2_free(p_hwfn); 1054 return rc; 1055 } 1056 1057 #define for_each_ilt_valid_client(pos, clients) \ 1058 for (pos = 0; pos < ILT_CLI_MAX; pos++) \ 1059 if (!clients[pos].active) { \ 1060 continue; \ 1061 } else \ 1062 1063 /* Total number of ILT lines used by this PF */ 1064 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients) 1065 { 1066 u32 size = 0; 1067 u32 i; 1068 1069 for_each_ilt_valid_client(i, ilt_clients) 1070 size += (ilt_clients[i].last.val - 1071 ilt_clients[i].first.val + 1); 1072 1073 return size; 1074 } 1075 1076 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn) 1077 { 1078 struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients; 1079 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1080 u32 ilt_size, i; 1081 1082 if (p_mngr->ilt_shadow == OSAL_NULL) 1083 return; 1084 1085 ilt_size = ecore_cxt_ilt_shadow_size(p_cli); 1086 1087 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) { 1088 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i]; 1089 1090 if (p_dma->p_virt) 1091 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, 1092 p_dma->p_virt, 1093 p_dma->p_phys, 1094 p_dma->size); 1095 p_dma->p_virt = OSAL_NULL; 1096 } 1097 OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow); 1098 p_mngr->ilt_shadow = OSAL_NULL; 1099 } 1100 1101 static enum _ecore_status_t ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn, 1102 struct ecore_ilt_cli_blk *p_blk, 1103 enum ilt_clients ilt_client, 1104 u32 start_line_offset) 1105 { 1106 struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow; 1107 u32 lines, line, sz_left, lines_to_skip = 0; 1108 1109 /* Special handling for RoCE that supports dynamic allocation */ 1110 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn) && 1111 ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM)) 1112 return ECORE_SUCCESS; 1113 1114 lines_to_skip = p_blk->dynamic_line_cnt; 1115 1116 if (!p_blk->total_size) 1117 return ECORE_SUCCESS; 1118 1119 sz_left = p_blk->total_size; 1120 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - 1121 lines_to_skip; 1122 line = p_blk->start_line + start_line_offset - 1123 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip; 1124 1125 for (; lines; lines--) { 1126 dma_addr_t p_phys; 1127 void *p_virt; 1128 u32 size; 1129 1130 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page); 1131 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, 1132 &p_phys, size); 1133 if (!p_virt) 1134 return ECORE_NOMEM; 1135 OSAL_MEM_ZERO(p_virt, size); 1136 1137 ilt_shadow[line].p_phys = p_phys; 1138 ilt_shadow[line].p_virt = p_virt; 1139 ilt_shadow[line].size = size; 1140 1141 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 1142 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n", 1143 line, (unsigned long long)p_phys, p_virt, size); 1144 1145 sz_left -= size; 1146 line++; 1147 } 1148 1149 return ECORE_SUCCESS; 1150 } 1151 1152 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn) 1153 { 1154 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1155 struct ecore_ilt_client_cfg *clients = p_mngr->clients; 1156 struct ecore_ilt_cli_blk *p_blk; 1157 u32 size, i, j, k; 1158 enum _ecore_status_t rc; 1159 1160 size = ecore_cxt_ilt_shadow_size(clients); 1161 p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, 1162 size * sizeof(struct ecore_dma_mem)); 1163 1164 if (p_mngr->ilt_shadow == OSAL_NULL) { 1165 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt shadow table\n"); 1166 rc = ECORE_NOMEM; 1167 goto ilt_shadow_fail; 1168 } 1169 1170 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 1171 "Allocated 0x%x bytes for ilt shadow\n", 1172 (u32)(size * sizeof(struct ecore_dma_mem))); 1173 1174 for_each_ilt_valid_client(i, clients) { 1175 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) { 1176 p_blk = &clients[i].pf_blks[j]; 1177 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0); 1178 if (rc != ECORE_SUCCESS) 1179 goto ilt_shadow_fail; 1180 } 1181 for (k = 0; k < p_mngr->vf_count; k++) { 1182 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) { 1183 u32 lines = clients[i].vf_total_lines * k; 1184 1185 p_blk = &clients[i].vf_blks[j]; 1186 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, 1187 i, lines); 1188 if (rc != ECORE_SUCCESS) 1189 goto ilt_shadow_fail; 1190 } 1191 } 1192 } 1193 1194 return ECORE_SUCCESS; 1195 1196 ilt_shadow_fail: 1197 ecore_ilt_shadow_free(p_hwfn); 1198 return rc; 1199 } 1200 1201 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn) 1202 { 1203 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1204 u32 type, vf; 1205 1206 for (type = 0; type < MAX_CONN_TYPES; type++) { 1207 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map); 1208 p_mngr->acquired[type].cid_map = OSAL_NULL; 1209 p_mngr->acquired[type].max_count = 0; 1210 p_mngr->acquired[type].start_cid = 0; 1211 1212 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) { 1213 OSAL_FREE(p_hwfn->p_dev, 1214 p_mngr->acquired_vf[type][vf].cid_map); 1215 p_mngr->acquired_vf[type][vf].cid_map = OSAL_NULL; 1216 p_mngr->acquired_vf[type][vf].max_count = 0; 1217 p_mngr->acquired_vf[type][vf].start_cid = 0; 1218 } 1219 } 1220 } 1221 1222 static enum _ecore_status_t 1223 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type, 1224 u32 cid_start, u32 cid_count, 1225 struct ecore_cid_acquired_map *p_map) 1226 { 1227 u32 size; 1228 1229 if (!cid_count) 1230 return ECORE_SUCCESS; 1231 1232 size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD); 1233 p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size); 1234 if (p_map->cid_map == OSAL_NULL) 1235 return ECORE_NOMEM; 1236 1237 p_map->max_count = cid_count; 1238 p_map->start_cid = cid_start; 1239 1240 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT, 1241 "Type %08x start: %08x count %08x\n", 1242 type, p_map->start_cid, p_map->max_count); 1243 1244 return ECORE_SUCCESS; 1245 } 1246 1247 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn) 1248 { 1249 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1250 u32 start_cid = 0, vf_start_cid = 0; 1251 u32 type, vf; 1252 1253 for (type = 0; type < MAX_CONN_TYPES; type++) { 1254 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type]; 1255 struct ecore_cid_acquired_map *p_map; 1256 1257 /* Handle PF maps */ 1258 p_map = &p_mngr->acquired[type]; 1259 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid, 1260 p_cfg->cid_count, p_map)) 1261 goto cid_map_fail; 1262 1263 /* Handle VF maps */ 1264 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) { 1265 p_map = &p_mngr->acquired_vf[type][vf]; 1266 if (ecore_cid_map_alloc_single(p_hwfn, type, 1267 vf_start_cid, 1268 p_cfg->cids_per_vf, 1269 p_map)) 1270 goto cid_map_fail; 1271 } 1272 1273 start_cid += p_cfg->cid_count; 1274 vf_start_cid += p_cfg->cids_per_vf; 1275 } 1276 1277 return ECORE_SUCCESS; 1278 1279 cid_map_fail: 1280 ecore_cid_map_free(p_hwfn); 1281 return ECORE_NOMEM; 1282 } 1283 1284 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn) 1285 { 1286 struct ecore_ilt_client_cfg *clients; 1287 struct ecore_cxt_mngr *p_mngr; 1288 u32 i; 1289 1290 p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr)); 1291 if (!p_mngr) { 1292 DP_NOTICE(p_hwfn, false, "Failed to allocate `struct ecore_cxt_mngr'\n"); 1293 return ECORE_NOMEM; 1294 } 1295 1296 /* Initialize ILT client registers */ 1297 clients = p_mngr->clients; 1298 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT); 1299 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT); 1300 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE); 1301 1302 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT); 1303 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT); 1304 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE); 1305 1306 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT); 1307 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT); 1308 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE); 1309 1310 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT); 1311 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT); 1312 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE); 1313 1314 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT); 1315 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT); 1316 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE); 1317 1318 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT); 1319 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); 1320 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); 1321 1322 /* default ILT page size for all clients is 64K */ 1323 for (i = 0; i < ILT_CLI_MAX; i++) 1324 p_mngr->clients[i].p_size.val = p_hwfn->p_dev->ilt_page_size; 1325 1326 /* Initialize task sizes */ 1327 p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn); 1328 p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn); 1329 1330 if (p_hwfn->p_dev->p_iov_info) 1331 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs; 1332 1333 /* Initialize the dynamic ILT allocation mutex */ 1334 #ifdef CONFIG_ECORE_LOCK_ALLOC 1335 OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex); 1336 #endif 1337 OSAL_MUTEX_INIT(&p_mngr->mutex); 1338 1339 /* Set the cxt mangr pointer priori to further allocations */ 1340 p_hwfn->p_cxt_mngr = p_mngr; 1341 1342 return ECORE_SUCCESS; 1343 } 1344 1345 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn) 1346 { 1347 enum _ecore_status_t rc; 1348 1349 /* Allocate the ILT shadow table */ 1350 rc = ecore_ilt_shadow_alloc(p_hwfn); 1351 if (rc) { 1352 DP_NOTICE(p_hwfn, false, "Failed to allocate ilt memory\n"); 1353 goto tables_alloc_fail; 1354 } 1355 1356 /* Allocate the T2 table */ 1357 rc = ecore_cxt_src_t2_alloc(p_hwfn); 1358 if (rc) { 1359 DP_NOTICE(p_hwfn, false, "Failed to allocate T2 memory\n"); 1360 goto tables_alloc_fail; 1361 } 1362 1363 /* Allocate and initialize the acquired cids bitmaps */ 1364 rc = ecore_cid_map_alloc(p_hwfn); 1365 if (rc) { 1366 DP_NOTICE(p_hwfn, false, "Failed to allocate cid maps\n"); 1367 goto tables_alloc_fail; 1368 } 1369 1370 return ECORE_SUCCESS; 1371 1372 tables_alloc_fail: 1373 ecore_cxt_mngr_free(p_hwfn); 1374 return rc; 1375 } 1376 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn) 1377 { 1378 if (!p_hwfn->p_cxt_mngr) 1379 return; 1380 1381 ecore_cid_map_free(p_hwfn); 1382 ecore_cxt_src_t2_free(p_hwfn); 1383 ecore_ilt_shadow_free(p_hwfn); 1384 #ifdef CONFIG_ECORE_LOCK_ALLOC 1385 OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex); 1386 #endif 1387 OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr); 1388 1389 p_hwfn->p_cxt_mngr = OSAL_NULL; 1390 } 1391 1392 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn) 1393 { 1394 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1395 struct ecore_cid_acquired_map *p_map; 1396 struct ecore_conn_type_cfg *p_cfg; 1397 int type; 1398 u32 len; 1399 1400 /* Reset acquired cids */ 1401 for (type = 0; type < MAX_CONN_TYPES; type++) { 1402 u32 vf; 1403 1404 p_cfg = &p_mngr->conn_cfg[type]; 1405 if (p_cfg->cid_count) { 1406 p_map = &p_mngr->acquired[type]; 1407 len = DIV_ROUND_UP(p_map->max_count, 1408 BITS_PER_MAP_WORD) * 1409 MAP_WORD_SIZE; 1410 OSAL_MEM_ZERO(p_map->cid_map, len); 1411 } 1412 1413 if (!p_cfg->cids_per_vf) 1414 continue; 1415 1416 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) { 1417 p_map = &p_mngr->acquired_vf[type][vf]; 1418 len = DIV_ROUND_UP(p_map->max_count, 1419 BITS_PER_MAP_WORD) * 1420 MAP_WORD_SIZE; 1421 OSAL_MEM_ZERO(p_map->cid_map, len); 1422 } 1423 } 1424 } 1425 1426 /* HW initialization helper (per Block, per phase) */ 1427 1428 /* CDU Common */ 1429 #define CDUC_CXT_SIZE_SHIFT \ 1430 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT 1431 1432 #define CDUC_CXT_SIZE_MASK \ 1433 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT) 1434 1435 #define CDUC_BLOCK_WASTE_SHIFT \ 1436 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT 1437 1438 #define CDUC_BLOCK_WASTE_MASK \ 1439 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT) 1440 1441 #define CDUC_NCIB_SHIFT \ 1442 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT 1443 1444 #define CDUC_NCIB_MASK \ 1445 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT) 1446 1447 #define CDUT_TYPE0_CXT_SIZE_SHIFT \ 1448 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 1449 1450 #define CDUT_TYPE0_CXT_SIZE_MASK \ 1451 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \ 1452 CDUT_TYPE0_CXT_SIZE_SHIFT) 1453 1454 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \ 1455 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 1456 1457 #define CDUT_TYPE0_BLOCK_WASTE_MASK \ 1458 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \ 1459 CDUT_TYPE0_BLOCK_WASTE_SHIFT) 1460 1461 #define CDUT_TYPE0_NCIB_SHIFT \ 1462 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 1463 1464 #define CDUT_TYPE0_NCIB_MASK \ 1465 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \ 1466 CDUT_TYPE0_NCIB_SHIFT) 1467 1468 #define CDUT_TYPE1_CXT_SIZE_SHIFT \ 1469 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 1470 1471 #define CDUT_TYPE1_CXT_SIZE_MASK \ 1472 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \ 1473 CDUT_TYPE1_CXT_SIZE_SHIFT) 1474 1475 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \ 1476 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 1477 1478 #define CDUT_TYPE1_BLOCK_WASTE_MASK \ 1479 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \ 1480 CDUT_TYPE1_BLOCK_WASTE_SHIFT) 1481 1482 #define CDUT_TYPE1_NCIB_SHIFT \ 1483 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 1484 1485 #define CDUT_TYPE1_NCIB_MASK \ 1486 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \ 1487 CDUT_TYPE1_NCIB_SHIFT) 1488 1489 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn) 1490 { 1491 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0; 1492 1493 /* CDUC - connection configuration */ 1494 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1495 cxt_size = CONN_CXT_SIZE(p_hwfn); 1496 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1497 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1498 1499 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); 1500 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); 1501 SET_FIELD(cdu_params, (u32)CDUC_NCIB, elems_per_page); 1502 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params); 1503 1504 /* CDUT - type-0 tasks configuration */ 1505 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val; 1506 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0]; 1507 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1508 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1509 1510 /* cxt size and block-waste are multipes of 8 */ 1511 cdu_params = 0; 1512 SET_FIELD(cdu_params, (u32)CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3)); 1513 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3)); 1514 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page); 1515 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params); 1516 1517 /* CDUT - type-1 tasks configuration */ 1518 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1]; 1519 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1520 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1521 1522 /* cxt size and block-waste are multipes of 8 */ 1523 cdu_params = 0; 1524 SET_FIELD(cdu_params, (u32)CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3)); 1525 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3)); 1526 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page); 1527 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params); 1528 } 1529 1530 /* CDU PF */ 1531 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT 1532 #define CDU_SEG_REG_TYPE_MASK 0x1 1533 #define CDU_SEG_REG_OFFSET_SHIFT 0 1534 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK 1535 1536 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn) 1537 { 1538 struct ecore_ilt_client_cfg *p_cli; 1539 struct ecore_tid_seg *p_seg; 1540 u32 cdu_seg_params, offset; 1541 int i; 1542 1543 static const u32 rt_type_offset_arr[] = { 1544 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET, 1545 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET, 1546 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET, 1547 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 1548 }; 1549 1550 static const u32 rt_type_offset_fl_arr[] = { 1551 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET, 1552 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET, 1553 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET, 1554 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 1555 }; 1556 1557 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1558 1559 /* There are initializations only for CDUT during pf Phase */ 1560 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1561 /* Segment 0*/ 1562 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i); 1563 if (!p_seg) 1564 continue; 1565 1566 /* Note: start_line is already adjusted for the CDU 1567 * segment register granularity, so we just need to 1568 * divide. Adjustment is implicit as we assume ILT 1569 * Page size is larger than 32K! 1570 */ 1571 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1572 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line - 1573 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1574 1575 cdu_seg_params = 0; 1576 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1577 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1578 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], 1579 cdu_seg_params); 1580 1581 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1582 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line - 1583 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1584 1585 cdu_seg_params = 0; 1586 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1587 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1588 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], 1589 cdu_seg_params); 1590 } 1591 } 1592 1593 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, 1594 bool is_pf_loading) 1595 { 1596 struct ecore_qm_info *qm_info = &p_hwfn->qm_info; 1597 struct ecore_mcp_link_state *p_link; 1598 struct ecore_qm_iids iids; 1599 1600 OSAL_MEM_ZERO(&iids, sizeof(iids)); 1601 ecore_cxt_qm_iids(p_hwfn, &iids); 1602 1603 p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output; 1604 1605 ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id, 1606 p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port, 1607 is_pf_loading, 1608 iids.cids, iids.vf_cids, iids.tids, 1609 qm_info->start_pq, 1610 qm_info->num_pqs - qm_info->num_vf_pqs, 1611 qm_info->num_vf_pqs, 1612 qm_info->start_vport, 1613 qm_info->num_vports, qm_info->pf_wfq, 1614 qm_info->pf_rl, p_link->speed, 1615 p_hwfn->qm_info.qm_pq_params, 1616 p_hwfn->qm_info.qm_vport_params); 1617 } 1618 1619 /* CM PF */ 1620 static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn) 1621 { 1622 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB)); 1623 } 1624 1625 /* DQ PF */ 1626 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn) 1627 { 1628 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1629 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0; 1630 1631 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT); 1632 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid); 1633 1634 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT); 1635 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid); 1636 1637 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT); 1638 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid); 1639 1640 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT); 1641 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid); 1642 1643 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT); 1644 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid); 1645 1646 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT); 1647 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid); 1648 1649 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT); 1650 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid); 1651 1652 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT); 1653 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid); 1654 1655 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT); 1656 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid); 1657 1658 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT); 1659 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid); 1660 1661 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT); 1662 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid); 1663 1664 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT); 1665 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid); 1666 1667 /* Connection types 6 & 7 are not in use, yet they must be configured 1668 * as the highest possible connection. Not configuring them means the 1669 * defaults will be used, and with a large number of cids a bug may 1670 * occur, if the defaults will be smaller than dq_pf_max_cid / 1671 * dq_vf_max_cid. 1672 */ 1673 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid); 1674 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid); 1675 1676 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid); 1677 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid); 1678 } 1679 1680 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn) 1681 { 1682 struct ecore_ilt_client_cfg *ilt_clients; 1683 int i; 1684 1685 ilt_clients = p_hwfn->p_cxt_mngr->clients; 1686 for_each_ilt_valid_client(i, ilt_clients) { 1687 STORE_RT_REG(p_hwfn, 1688 ilt_clients[i].first.reg, 1689 ilt_clients[i].first.val); 1690 STORE_RT_REG(p_hwfn, 1691 ilt_clients[i].last.reg, 1692 ilt_clients[i].last.val); 1693 STORE_RT_REG(p_hwfn, 1694 ilt_clients[i].p_size.reg, 1695 ilt_clients[i].p_size.val); 1696 } 1697 } 1698 1699 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn) 1700 { 1701 struct ecore_ilt_client_cfg *p_cli; 1702 u32 blk_factor; 1703 1704 /* For simplicty we set the 'block' to be an ILT page */ 1705 if (p_hwfn->p_dev->p_iov_info) { 1706 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info; 1707 1708 STORE_RT_REG(p_hwfn, 1709 PSWRQ2_REG_VF_BASE_RT_OFFSET, 1710 p_iov->first_vf_in_pf); 1711 STORE_RT_REG(p_hwfn, 1712 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, 1713 p_iov->first_vf_in_pf + p_iov->total_vfs); 1714 } 1715 1716 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 1717 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1718 if (p_cli->active) { 1719 STORE_RT_REG(p_hwfn, 1720 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET, 1721 blk_factor); 1722 STORE_RT_REG(p_hwfn, 1723 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1724 p_cli->pf_total_lines); 1725 STORE_RT_REG(p_hwfn, 1726 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET, 1727 p_cli->vf_total_lines); 1728 } 1729 1730 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1731 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1732 if (p_cli->active) { 1733 STORE_RT_REG(p_hwfn, 1734 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET, 1735 blk_factor); 1736 STORE_RT_REG(p_hwfn, 1737 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1738 p_cli->pf_total_lines); 1739 STORE_RT_REG(p_hwfn, 1740 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET, 1741 p_cli->vf_total_lines); 1742 } 1743 1744 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM]; 1745 blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1746 if (p_cli->active) { 1747 STORE_RT_REG(p_hwfn, 1748 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, 1749 blk_factor); 1750 STORE_RT_REG(p_hwfn, 1751 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1752 p_cli->pf_total_lines); 1753 STORE_RT_REG(p_hwfn, 1754 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET, 1755 p_cli->vf_total_lines); 1756 } 1757 } 1758 1759 /* ILT (PSWRQ2) PF */ 1760 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn) 1761 { 1762 struct ecore_ilt_client_cfg *clients; 1763 struct ecore_cxt_mngr *p_mngr; 1764 struct ecore_dma_mem *p_shdw; 1765 u32 line, rt_offst, i; 1766 1767 ecore_ilt_bounds_init(p_hwfn); 1768 ecore_ilt_vf_bounds_init(p_hwfn); 1769 1770 p_mngr = p_hwfn->p_cxt_mngr; 1771 p_shdw = p_mngr->ilt_shadow; 1772 clients = p_hwfn->p_cxt_mngr->clients; 1773 1774 for_each_ilt_valid_client(i, clients) { 1775 /* Client's 1st val and RT array are absolute, ILT shadows' 1776 * lines are relative. 1777 */ 1778 line = clients[i].first.val - p_mngr->pf_start_line; 1779 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET + 1780 clients[i].first.val * ILT_ENTRY_IN_REGS; 1781 1782 for (; line <= clients[i].last.val - p_mngr->pf_start_line; 1783 line++, rt_offst += ILT_ENTRY_IN_REGS) { 1784 u64 ilt_hw_entry = 0; 1785 1786 /** p_virt could be OSAL_NULL incase of dynamic 1787 * allocation 1788 */ 1789 if (p_shdw[line].p_virt != OSAL_NULL) { 1790 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 1791 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 1792 (unsigned long long)(p_shdw[line].p_phys >> 12)); 1793 1794 DP_VERBOSE( 1795 p_hwfn, ECORE_MSG_ILT, 1796 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n", 1797 rt_offst, line, i, 1798 (unsigned long long)(p_shdw[line].p_phys >> 12)); 1799 } 1800 1801 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry); 1802 } 1803 } 1804 } 1805 1806 /* SRC (Searcher) PF */ 1807 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn) 1808 { 1809 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1810 u32 rounded_conn_num, conn_num, conn_max; 1811 struct ecore_src_iids src_iids; 1812 1813 OSAL_MEM_ZERO(&src_iids, sizeof(src_iids)); 1814 ecore_cxt_src_iids(p_mngr, &src_iids); 1815 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 1816 if (!conn_num) 1817 return; 1818 1819 conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS); 1820 rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max); 1821 1822 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num); 1823 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET, 1824 OSAL_LOG2(rounded_conn_num)); 1825 1826 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET, 1827 p_hwfn->p_cxt_mngr->first_free); 1828 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET, 1829 p_hwfn->p_cxt_mngr->last_free); 1830 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT, 1831 "Configured SEARCHER for 0x%08x connections\n", 1832 conn_num); 1833 } 1834 1835 /* Timers PF */ 1836 #define TM_CFG_NUM_IDS_SHIFT 0 1837 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL 1838 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16 1839 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL 1840 #define TM_CFG_PARENT_PF_SHIFT 25 1841 #define TM_CFG_PARENT_PF_MASK 0x7ULL 1842 1843 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30 1844 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL 1845 1846 #define TM_CFG_TID_OFFSET_SHIFT 30 1847 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL 1848 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49 1849 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL 1850 1851 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn) 1852 { 1853 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1854 u32 active_seg_mask = 0, tm_offset, rt_reg; 1855 struct ecore_tm_iids tm_iids; 1856 u64 cfg_word; 1857 u8 i; 1858 1859 OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids)); 1860 ecore_cxt_tm_iids(p_mngr, &tm_iids); 1861 1862 /* @@@TBD No pre-scan for now */ 1863 1864 /* Note: We assume consecutive VFs for a PF */ 1865 for (i = 0; i < p_mngr->vf_count; i++) { 1866 cfg_word = 0; 1867 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids); 1868 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1869 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1870 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ 1871 1872 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1873 (sizeof(cfg_word) / sizeof(u32)) * 1874 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i); 1875 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1876 } 1877 1878 cfg_word = 0; 1879 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids); 1880 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1881 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */ 1882 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ 1883 1884 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1885 (sizeof(cfg_word) / sizeof(u32)) * 1886 (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id); 1887 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1888 1889 /* enale scan */ 1890 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET, 1891 tm_iids.pf_cids ? 0x1 : 0x0); 1892 1893 /* @@@TBD how to enable the scan for the VFs */ 1894 1895 tm_offset = tm_iids.per_vf_cids; 1896 1897 /* Note: We assume consecutive VFs for a PF */ 1898 for (i = 0; i < p_mngr->vf_count; i++) { 1899 cfg_word = 0; 1900 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids); 1901 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1902 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1903 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1904 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0); 1905 1906 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1907 (sizeof(cfg_word) / sizeof(u32)) * 1908 (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i); 1909 1910 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1911 } 1912 1913 tm_offset = tm_iids.pf_cids; 1914 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1915 cfg_word = 0; 1916 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]); 1917 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1918 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); 1919 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1920 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0); 1921 1922 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1923 (sizeof(cfg_word) / sizeof(u32)) * 1924 (NUM_OF_VFS(p_hwfn->p_dev) + 1925 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i); 1926 1927 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1928 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0); 1929 1930 tm_offset += tm_iids.pf_tids[i]; 1931 } 1932 1933 if (ECORE_IS_RDMA_PERSONALITY(p_hwfn)) 1934 active_seg_mask = 0; 1935 1936 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask); 1937 1938 /* @@@TBD how to enable the scan for the VFs */ 1939 } 1940 1941 static void ecore_prs_init_common(struct ecore_hwfn *p_hwfn) 1942 { 1943 if ((p_hwfn->hw_info.personality == ECORE_PCI_FCOE) && 1944 p_hwfn->pf_params.fcoe_pf_params.is_target) 1945 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0); 1946 } 1947 1948 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn) 1949 { 1950 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1951 struct ecore_conn_type_cfg *p_fcoe; 1952 struct ecore_tid_seg *p_tid; 1953 1954 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE]; 1955 1956 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */ 1957 if (!p_fcoe->cid_count) 1958 return; 1959 1960 p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG]; 1961 if (p_hwfn->pf_params.fcoe_pf_params.is_target) { 1962 STORE_RT_REG_AGG(p_hwfn, 1963 PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET, 1964 p_tid->count); 1965 } else { 1966 STORE_RT_REG_AGG(p_hwfn, 1967 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET, 1968 p_tid->count); 1969 } 1970 } 1971 1972 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn) 1973 { 1974 /* CDU configuration */ 1975 ecore_cdu_init_common(p_hwfn); 1976 ecore_prs_init_common(p_hwfn); 1977 } 1978 1979 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt) 1980 { 1981 ecore_qm_init_pf(p_hwfn, p_ptt, true); 1982 ecore_cm_init_pf(p_hwfn); 1983 ecore_dq_init_pf(p_hwfn); 1984 ecore_cdu_init_pf(p_hwfn); 1985 ecore_ilt_init_pf(p_hwfn); 1986 ecore_src_init_pf(p_hwfn); 1987 ecore_tm_init_pf(p_hwfn); 1988 ecore_prs_init_pf(p_hwfn); 1989 } 1990 1991 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn, 1992 enum protocol_type type, 1993 u32 *p_cid, u8 vfid) 1994 { 1995 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1996 struct ecore_cid_acquired_map *p_map; 1997 u32 rel_cid; 1998 1999 if (type >= MAX_CONN_TYPES) { 2000 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type); 2001 return ECORE_INVAL; 2002 } 2003 2004 if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) { 2005 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid); 2006 return ECORE_INVAL; 2007 } 2008 2009 /* Determine the right map to take this CID from */ 2010 if (vfid == ECORE_CXT_PF_CID) 2011 p_map = &p_mngr->acquired[type]; 2012 else 2013 p_map = &p_mngr->acquired_vf[type][vfid]; 2014 2015 if (p_map->cid_map == OSAL_NULL) { 2016 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type); 2017 return ECORE_INVAL; 2018 } 2019 2020 rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map, 2021 p_map->max_count); 2022 2023 if (rel_cid >= p_map->max_count) { 2024 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n", 2025 type); 2026 return ECORE_NORESOURCES; 2027 } 2028 2029 OSAL_SET_BIT(rel_cid, p_map->cid_map); 2030 2031 *p_cid = rel_cid + p_map->start_cid; 2032 2033 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT, 2034 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n", 2035 *p_cid, rel_cid, vfid, type); 2036 2037 return ECORE_SUCCESS; 2038 } 2039 2040 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn, 2041 enum protocol_type type, 2042 u32 *p_cid) 2043 { 2044 return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID); 2045 } 2046 2047 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn, 2048 u32 cid, u8 vfid, 2049 enum protocol_type *p_type, 2050 struct ecore_cid_acquired_map **pp_map) 2051 { 2052 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2053 u32 rel_cid; 2054 2055 /* Iterate over protocols and find matching cid range */ 2056 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) { 2057 if (vfid == ECORE_CXT_PF_CID) 2058 *pp_map = &p_mngr->acquired[*p_type]; 2059 else 2060 *pp_map = &p_mngr->acquired_vf[*p_type][vfid]; 2061 2062 if (!((*pp_map)->cid_map)) 2063 continue; 2064 if (cid >= (*pp_map)->start_cid && 2065 cid < (*pp_map)->start_cid + (*pp_map)->max_count) { 2066 break; 2067 } 2068 } 2069 2070 if (*p_type == MAX_CONN_TYPES) { 2071 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid); 2072 goto fail; 2073 } 2074 2075 rel_cid = cid - (*pp_map)->start_cid; 2076 if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) { 2077 DP_NOTICE(p_hwfn, true, 2078 "CID %d [vifd %02x] not acquired", cid, vfid); 2079 goto fail; 2080 } 2081 2082 return true; 2083 fail: 2084 *p_type = MAX_CONN_TYPES; 2085 *pp_map = OSAL_NULL; 2086 return false; 2087 } 2088 2089 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid) 2090 { 2091 struct ecore_cid_acquired_map *p_map = OSAL_NULL; 2092 enum protocol_type type; 2093 bool b_acquired; 2094 u32 rel_cid; 2095 2096 if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) { 2097 DP_NOTICE(p_hwfn, true, 2098 "Trying to return incorrect CID belonging to VF %02x\n", 2099 vfid); 2100 return; 2101 } 2102 2103 /* Test acquired and find matching per-protocol map */ 2104 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid, 2105 &type, &p_map); 2106 2107 if (!b_acquired) 2108 return; 2109 2110 rel_cid = cid - p_map->start_cid; 2111 OSAL_CLEAR_BIT(rel_cid, p_map->cid_map); 2112 2113 DP_VERBOSE(p_hwfn, ECORE_MSG_CXT, 2114 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n", 2115 cid, rel_cid, vfid, type); 2116 } 2117 2118 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid) 2119 { 2120 _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID); 2121 } 2122 2123 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn, 2124 struct ecore_cxt_info *p_info) 2125 { 2126 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2127 struct ecore_cid_acquired_map *p_map = OSAL_NULL; 2128 u32 conn_cxt_size, hw_p_size, cxts_per_p, line; 2129 enum protocol_type type; 2130 bool b_acquired; 2131 2132 /* Test acquired and find matching per-protocol map */ 2133 b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid, 2134 ECORE_CXT_PF_CID, 2135 &type, &p_map); 2136 2137 if (!b_acquired) 2138 return ECORE_INVAL; 2139 2140 /* set the protocl type */ 2141 p_info->type = type; 2142 2143 /* compute context virtual pointer */ 2144 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 2145 2146 conn_cxt_size = CONN_CXT_SIZE(p_hwfn); 2147 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size; 2148 line = p_info->iid / cxts_per_p; 2149 2150 /* Make sure context is allocated (dynamic allocation) */ 2151 if (!p_mngr->ilt_shadow[line].p_virt) 2152 return ECORE_INVAL; 2153 2154 p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt + 2155 p_info->iid % cxts_per_p * conn_cxt_size; 2156 2157 DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT), 2158 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n", 2159 (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid); 2160 2161 return ECORE_SUCCESS; 2162 } 2163 2164 static void ecore_rdma_set_pf_params(struct ecore_hwfn *p_hwfn, 2165 struct ecore_rdma_pf_params *p_params, 2166 u32 num_tasks) 2167 { 2168 u32 num_cons, num_qps; 2169 enum protocol_type proto; 2170 2171 /* The only case RDMA personality can be overriden is if NVRAM is 2172 * configured with ETH_RDMA or if no rdma protocol was requested 2173 */ 2174 switch (p_params->rdma_protocol) { 2175 case ECORE_RDMA_PROTOCOL_DEFAULT: 2176 if (p_hwfn->mcp_info->func_info.protocol == 2177 ECORE_PCI_ETH_RDMA) { 2178 DP_NOTICE(p_hwfn, false, 2179 "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n"); 2180 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE; 2181 } 2182 break; 2183 case ECORE_RDMA_PROTOCOL_NONE: 2184 p_hwfn->hw_info.personality = ECORE_PCI_ETH; 2185 return; /* intentional... nothing left to do... */ 2186 case ECORE_RDMA_PROTOCOL_ROCE: 2187 if (p_hwfn->mcp_info->func_info.protocol == ECORE_PCI_ETH_RDMA) 2188 p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE; 2189 break; 2190 case ECORE_RDMA_PROTOCOL_IWARP: 2191 if (p_hwfn->mcp_info->func_info.protocol == ECORE_PCI_ETH_RDMA) 2192 p_hwfn->hw_info.personality = ECORE_PCI_ETH_IWARP; 2193 break; 2194 } 2195 2196 switch (p_hwfn->hw_info.personality) { 2197 case ECORE_PCI_ETH_IWARP: 2198 /* Each QP requires one connection */ 2199 num_cons = OSAL_MIN_T(u32, IWARP_MAX_QPS, p_params->num_qps); 2200 #ifdef CONFIG_ECORE_IWARP /* required for the define */ 2201 /* additional connections required for passive tcp handling */ 2202 num_cons += ECORE_IWARP_PREALLOC_CNT; 2203 #endif 2204 proto = PROTOCOLID_IWARP; 2205 break; 2206 case ECORE_PCI_ETH_ROCE: 2207 num_qps = OSAL_MIN_T(u32, ROCE_MAX_QPS, p_params->num_qps); 2208 num_cons = num_qps * 2; /* each QP requires two connections */ 2209 proto = PROTOCOLID_ROCE; 2210 break; 2211 default: 2212 return; 2213 } 2214 2215 if (num_cons && num_tasks) { 2216 u32 num_srqs, num_xrc_srqs, max_xrc_srqs, page_size; 2217 2218 ecore_cxt_set_proto_cid_count(p_hwfn, proto, 2219 num_cons, 0); 2220 2221 /* Deliberatly passing ROCE for tasks id. This is because 2222 * iWARP / RoCE share the task id. 2223 */ 2224 ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE, 2225 ECORE_CXT_ROCE_TID_SEG, 2226 1, /* RoCE segment type */ 2227 num_tasks, 2228 false); /* !force load */ 2229 2230 num_srqs = OSAL_MIN_T(u32, ECORE_RDMA_MAX_SRQS, 2231 p_params->num_srqs); 2232 2233 /* XRC SRQs populate a single ILT page */ 2234 page_size = ecore_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM); 2235 max_xrc_srqs = page_size / XRC_SRQ_CXT_SIZE; 2236 max_xrc_srqs = OSAL_MIN_T(u32, max_xrc_srqs, ECORE_RDMA_MAX_XRC_SRQS); 2237 2238 num_xrc_srqs = OSAL_MIN_T(u32, p_params->num_xrc_srqs, 2239 max_xrc_srqs); 2240 ecore_cxt_set_srq_count(p_hwfn, num_srqs, num_xrc_srqs); 2241 2242 } else { 2243 DP_INFO(p_hwfn->p_dev, 2244 "RDMA personality used without setting params!\n"); 2245 } 2246 } 2247 2248 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn, 2249 u32 rdma_tasks) 2250 { 2251 /* Set the number of required CORE connections */ 2252 u32 core_cids = 1; /* SPQ */ 2253 2254 if (p_hwfn->using_ll2) 2255 core_cids += 4; /* @@@TBD Use the proper #define */ 2256 2257 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0); 2258 2259 switch (p_hwfn->hw_info.personality) { 2260 case ECORE_PCI_ETH_RDMA: 2261 case ECORE_PCI_ETH_IWARP: 2262 case ECORE_PCI_ETH_ROCE: 2263 { 2264 ecore_rdma_set_pf_params(p_hwfn, 2265 &p_hwfn->pf_params.rdma_pf_params, 2266 rdma_tasks); 2267 2268 /* no need for break since RoCE coexist with Ethernet */ 2269 } 2270 case ECORE_PCI_ETH: 2271 { 2272 u32 count = 0; 2273 2274 struct ecore_eth_pf_params *p_params = 2275 &p_hwfn->pf_params.eth_pf_params; 2276 2277 if (!p_params->num_vf_cons) 2278 p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT; 2279 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 2280 p_params->num_cons, 2281 p_params->num_vf_cons); 2282 2283 count = p_params->num_arfs_filters; 2284 2285 if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, 2286 &p_hwfn->p_dev->mf_bits)) 2287 p_hwfn->p_cxt_mngr->arfs_count = count; 2288 2289 break; 2290 } 2291 case ECORE_PCI_FCOE: 2292 { 2293 struct ecore_fcoe_pf_params *p_params; 2294 2295 p_params = &p_hwfn->pf_params.fcoe_pf_params; 2296 2297 if (p_params->num_cons && p_params->num_tasks) { 2298 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_FCOE, 2299 p_params->num_cons, 0); 2300 2301 ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE, 2302 ECORE_CXT_FCOE_TID_SEG, 2303 0, /* segment type */ 2304 p_params->num_tasks, 2305 true); 2306 } else { 2307 DP_INFO(p_hwfn->p_dev, 2308 "Fcoe personality used without setting params!\n"); 2309 } 2310 break; 2311 } 2312 case ECORE_PCI_ISCSI: 2313 { 2314 struct ecore_iscsi_pf_params *p_params; 2315 2316 p_params = &p_hwfn->pf_params.iscsi_pf_params; 2317 2318 if (p_params->num_cons && p_params->num_tasks) { 2319 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ISCSI, 2320 p_params->num_cons, 0); 2321 2322 ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ISCSI, 2323 ECORE_CXT_ISCSI_TID_SEG, 2324 0, /* segment type */ 2325 p_params->num_tasks, 2326 true); 2327 } else { 2328 DP_INFO(p_hwfn->p_dev, 2329 "Iscsi personality used without setting params!\n"); 2330 } 2331 break; 2332 } 2333 default: 2334 return ECORE_INVAL; 2335 } 2336 2337 return ECORE_SUCCESS; 2338 } 2339 2340 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn, 2341 struct ecore_tid_mem *p_info) 2342 { 2343 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2344 u32 proto, seg, total_lines, i, shadow_line; 2345 struct ecore_ilt_client_cfg *p_cli; 2346 struct ecore_ilt_cli_blk *p_fl_seg; 2347 struct ecore_tid_seg *p_seg_info; 2348 2349 /* Verify the personality */ 2350 switch (p_hwfn->hw_info.personality) { 2351 case ECORE_PCI_FCOE: 2352 proto = PROTOCOLID_FCOE; 2353 seg = ECORE_CXT_FCOE_TID_SEG; 2354 break; 2355 case ECORE_PCI_ISCSI: 2356 proto = PROTOCOLID_ISCSI; 2357 seg = ECORE_CXT_ISCSI_TID_SEG; 2358 break; 2359 default: 2360 return ECORE_INVAL; 2361 } 2362 2363 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2364 if (!p_cli->active) { 2365 return ECORE_INVAL; 2366 } 2367 2368 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2369 if (!p_seg_info->has_fl_mem) 2370 return ECORE_INVAL; 2371 2372 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2373 total_lines = DIV_ROUND_UP(p_fl_seg->total_size, 2374 p_fl_seg->real_size_in_page); 2375 2376 for (i = 0; i < total_lines; i++) { 2377 shadow_line = i + p_fl_seg->start_line - 2378 p_hwfn->p_cxt_mngr->pf_start_line; 2379 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt; 2380 } 2381 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) - 2382 p_fl_seg->real_size_in_page; 2383 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type]; 2384 p_info->num_tids_per_block = p_fl_seg->real_size_in_page / 2385 p_info->tid_size; 2386 2387 return ECORE_SUCCESS; 2388 } 2389 2390 /* This function is very RoCE oriented, if another protocol in the future 2391 * will want this feature we'll need to modify the function to be more generic 2392 */ 2393 enum _ecore_status_t 2394 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn, 2395 enum ecore_cxt_elem_type elem_type, 2396 u32 iid) 2397 { 2398 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; 2399 struct ecore_ilt_client_cfg *p_cli; 2400 struct ecore_ilt_cli_blk *p_blk; 2401 struct ecore_ptt *p_ptt; 2402 dma_addr_t p_phys; 2403 u64 ilt_hw_entry; 2404 void *p_virt; 2405 enum _ecore_status_t rc = ECORE_SUCCESS; 2406 2407 switch (elem_type) { 2408 case ECORE_ELEM_CXT: 2409 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2410 elem_size = CONN_CXT_SIZE(p_hwfn); 2411 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2412 break; 2413 case ECORE_ELEM_SRQ: 2414 /* The first ILT page is not used for regular SRQs. Skip it. */ 2415 iid += ecore_cxt_srqs_per_page(p_hwfn); 2416 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2417 elem_size = SRQ_CXT_SIZE; 2418 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2419 break; 2420 case ECORE_ELEM_XRC_SRQ: 2421 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2422 elem_size = XRC_SRQ_CXT_SIZE; 2423 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2424 break; 2425 case ECORE_ELEM_TASK: 2426 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2427 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2428 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)]; 2429 break; 2430 default: 2431 DP_NOTICE(p_hwfn, false, 2432 "ECORE_INVALID elem type = %d", elem_type); 2433 return ECORE_INVAL; 2434 } 2435 2436 /* Calculate line in ilt */ 2437 hw_p_size = p_cli->p_size.val; 2438 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2439 line = p_blk->start_line + (iid / elems_per_p); 2440 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line; 2441 2442 /* If line is already allocated, do nothing, otherwise allocate it and 2443 * write it to the PSWRQ2 registers. 2444 * This section can be run in parallel from different contexts and thus 2445 * a mutex protection is needed. 2446 */ 2447 #ifdef _NTDDK_ 2448 #pragma warning(suppress : 28121) 2449 #endif 2450 OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex); 2451 2452 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt) 2453 goto out0; 2454 2455 p_ptt = ecore_ptt_acquire(p_hwfn); 2456 if (!p_ptt) { 2457 DP_NOTICE(p_hwfn, false, 2458 "ECORE_TIME_OUT on ptt acquire - dynamic allocation"); 2459 rc = ECORE_TIMEOUT; 2460 goto out0; 2461 } 2462 2463 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev, 2464 &p_phys, 2465 p_blk->real_size_in_page); 2466 if (!p_virt) { 2467 rc = ECORE_NOMEM; 2468 goto out1; 2469 } 2470 OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page); 2471 2472 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only, 2473 * to compensate for a HW bug, but it is configured even if DIF is not 2474 * enabled. This is harmless and allows us to avoid a dedicated API. We 2475 * configure the field for all of the contexts on the newly allocated 2476 * page. 2477 */ 2478 if (elem_type == ECORE_ELEM_TASK) { 2479 u32 elem_i; 2480 u8 *elem_start = (u8 *)p_virt; 2481 union type1_task_context *elem; 2482 2483 for (elem_i = 0; elem_i < elems_per_p; elem_i++) { 2484 elem = (union type1_task_context *)elem_start; 2485 SET_FIELD(elem->roce_ctx.tdif_context.flags1, 2486 TDIF_TASK_CONTEXT_REF_TAG_MASK , 0xf); 2487 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); 2488 } 2489 } 2490 2491 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt; 2492 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys; 2493 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size = 2494 p_blk->real_size_in_page; 2495 2496 /* compute absolute offset */ 2497 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2498 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS); 2499 2500 ilt_hw_entry = 0; 2501 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 2502 SET_FIELD(ilt_hw_entry, 2503 ILT_ENTRY_PHY_ADDR, 2504 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12)); 2505 2506 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */ 2507 ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry, 2508 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 2509 OSAL_NULL /* default parameters */); 2510 2511 if (elem_type == ECORE_ELEM_CXT) { 2512 u32 last_cid_allocated = (1 + (iid / elems_per_p)) * 2513 elems_per_p; 2514 2515 /* Update the relevant register in the parser */ 2516 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 2517 last_cid_allocated - 1); 2518 2519 /* RoCE w/a -> we don't write to the prs search reg until first 2520 * cid is allocated. This is because the prs checks 2521 * last_cid-1 >=0 making 0 a valid value... this will cause 2522 * the a context load to occur on a RoCE packet received with 2523 * cid=0 even before context was initialized, can happen with a 2524 * stray packet from switch or a packet with crc-error 2525 */ 2526 2527 if (!p_hwfn->b_rdma_enabled_in_prs) { 2528 /* Enable Rdma search */ 2529 ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1); 2530 p_hwfn->b_rdma_enabled_in_prs = true; 2531 } 2532 } 2533 2534 out1: 2535 ecore_ptt_release(p_hwfn, p_ptt); 2536 out0: 2537 OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex); 2538 2539 return rc; 2540 } 2541 2542 /* This function is very RoCE oriented, if another protocol in the future 2543 * will want this feature we'll need to modify the function to be more generic 2544 */ 2545 enum _ecore_status_t 2546 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn, 2547 enum ecore_cxt_elem_type elem_type, 2548 u32 start_iid, u32 count) 2549 { 2550 u32 start_line, end_line, shadow_start_line, shadow_end_line; 2551 u32 reg_offset, elem_size, hw_p_size, elems_per_p; 2552 struct ecore_ilt_client_cfg *p_cli; 2553 struct ecore_ilt_cli_blk *p_blk; 2554 u32 end_iid = start_iid + count; 2555 struct ecore_ptt *p_ptt; 2556 u64 ilt_hw_entry = 0; 2557 u32 i; 2558 2559 switch (elem_type) { 2560 case ECORE_ELEM_CXT: 2561 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2562 elem_size = CONN_CXT_SIZE(p_hwfn); 2563 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2564 break; 2565 case ECORE_ELEM_SRQ: 2566 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2567 elem_size = SRQ_CXT_SIZE; 2568 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2569 break; 2570 case ECORE_ELEM_TASK: 2571 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2572 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2573 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)]; 2574 break; 2575 default: 2576 DP_NOTICE(p_hwfn, false, 2577 "ECORE_INVALID elem type = %d", elem_type); 2578 return ECORE_INVAL; 2579 } 2580 2581 /* Calculate line in ilt */ 2582 hw_p_size = p_cli->p_size.val; 2583 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2584 start_line = p_blk->start_line + (start_iid / elems_per_p); 2585 end_line = p_blk->start_line + (end_iid / elems_per_p); 2586 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p)) 2587 end_line--; 2588 2589 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line; 2590 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line; 2591 2592 p_ptt = ecore_ptt_acquire(p_hwfn); 2593 if (!p_ptt) { 2594 DP_NOTICE(p_hwfn, false, "ECORE_TIME_OUT on ptt acquire - dynamic allocation"); 2595 return ECORE_TIMEOUT; 2596 } 2597 2598 for (i = shadow_start_line; i < shadow_end_line; i++) { 2599 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt) 2600 continue; 2601 2602 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, 2603 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt, 2604 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys, 2605 p_hwfn->p_cxt_mngr->ilt_shadow[i].size); 2606 2607 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL; 2608 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0; 2609 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0; 2610 2611 /* compute absolute offset */ 2612 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2613 ((start_line++) * ILT_REG_SIZE_IN_BYTES * 2614 ILT_ENTRY_IN_REGS); 2615 2616 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a 2617 * wide-bus. 2618 */ 2619 ecore_dmae_host2grc(p_hwfn, p_ptt, 2620 (u64)(osal_uintptr_t)&ilt_hw_entry, 2621 reg_offset, 2622 sizeof(ilt_hw_entry) / sizeof(u32), 2623 OSAL_NULL /* default parameters */); 2624 } 2625 2626 ecore_ptt_release(p_hwfn, p_ptt); 2627 2628 return ECORE_SUCCESS; 2629 } 2630 2631 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn, 2632 u32 tid, 2633 u8 ctx_type, 2634 void **pp_task_ctx) 2635 { 2636 struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2637 struct ecore_ilt_client_cfg *p_cli; 2638 struct ecore_tid_seg *p_seg_info; 2639 struct ecore_ilt_cli_blk *p_seg; 2640 u32 num_tids_per_block; 2641 u32 tid_size, ilt_idx; 2642 u32 total_lines; 2643 u32 proto, seg; 2644 2645 /* Verify the personality */ 2646 switch (p_hwfn->hw_info.personality) { 2647 case ECORE_PCI_FCOE: 2648 proto = PROTOCOLID_FCOE; 2649 seg = ECORE_CXT_FCOE_TID_SEG; 2650 break; 2651 case ECORE_PCI_ISCSI: 2652 proto = PROTOCOLID_ISCSI; 2653 seg = ECORE_CXT_ISCSI_TID_SEG; 2654 break; 2655 default: 2656 return ECORE_INVAL; 2657 } 2658 2659 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2660 if (!p_cli->active) { 2661 return ECORE_INVAL; 2662 } 2663 2664 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2665 2666 if (ctx_type == ECORE_CTX_WORKING_MEM) { 2667 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)]; 2668 } else if (ctx_type == ECORE_CTX_FL_MEM) { 2669 if (!p_seg_info->has_fl_mem) { 2670 return ECORE_INVAL; 2671 } 2672 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2673 } else { 2674 return ECORE_INVAL; 2675 } 2676 total_lines = DIV_ROUND_UP(p_seg->total_size, 2677 p_seg->real_size_in_page); 2678 tid_size = p_mngr->task_type_size[p_seg_info->type]; 2679 num_tids_per_block = p_seg->real_size_in_page / tid_size; 2680 2681 if (total_lines < tid/num_tids_per_block) 2682 return ECORE_INVAL; 2683 2684 ilt_idx = tid / num_tids_per_block + p_seg->start_line - 2685 p_mngr->pf_start_line; 2686 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt + 2687 (tid % num_tids_per_block) * tid_size; 2688 2689 return ECORE_SUCCESS; 2690 } 2691