1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_H 32 #define __ECORE_H 33 34 #include "ecore_hsi_common.h" 35 #include "ecore_hsi_debug_tools.h" 36 #include "ecore_hsi_init_func.h" 37 #include "ecore_hsi_init_tool.h" 38 #include "ecore_proto_if.h" 39 #include "mcp_public.h" 40 41 #define ECORE_MAJOR_VERSION 8 42 #define ECORE_MINOR_VERSION 30 43 #define ECORE_REVISION_VERSION 0 44 #define ECORE_ENGINEERING_VERSION 0 45 46 #define ECORE_VERSION \ 47 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \ 48 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION) 49 50 #define STORM_FW_VERSION \ 51 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 52 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 53 54 #define MAX_HWFNS_PER_DEVICE 2 55 #define NAME_SIZE 16 56 #define ARRAY_DECL static const 57 #define ECORE_WFQ_UNIT 100 58 59 /* Constants */ 60 #define ECORE_WID_SIZE (1024) 61 62 /* Configurable */ 63 #define ECORE_PF_DEMS_SIZE (4) 64 65 /* cau states */ 66 enum ecore_coalescing_mode { 67 ECORE_COAL_MODE_DISABLE, 68 ECORE_COAL_MODE_ENABLE 69 }; 70 71 enum ecore_nvm_cmd { 72 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, 73 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, 74 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM, 75 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, 76 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE, 77 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE, 78 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE, 79 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ, 80 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE, 81 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ, 82 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE, 83 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00 84 }; 85 86 #if !defined(CONFIG_ECORE_L2) && !defined(CONFIG_ECORE_ROCE) && \ 87 !defined(CONFIG_ECORE_FCOE) && !defined(CONFIG_ECORE_ISCSI) 88 #define CONFIG_ECORE_L2 89 #define CONFIG_ECORE_SRIOV 90 #define CONFIG_ECORE_ROCE 91 #define CONFIG_ECORE_IWARP 92 #define CONFIG_ECORE_FCOE 93 #define CONFIG_ECORE_ISCSI 94 #define CONFIG_ECORE_LL2 95 #endif 96 97 /* helpers */ 98 #define MASK_FIELD(_name, _value) \ 99 ((_value) &= (_name##_MASK)) 100 101 #define FIELD_VALUE(_name, _value) \ 102 ((_value & _name##_MASK) << _name##_SHIFT) 103 104 #define SET_FIELD(value, name, flag) \ 105 do { \ 106 (value) &= ~(name##_MASK << name##_SHIFT); \ 107 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\ 108 } while (0) 109 110 #define GET_FIELD(value, name) \ 111 (((value) >> (name##_SHIFT)) & name##_MASK) 112 113 #define GET_MFW_FIELD(name, field) \ 114 (((name) & (field ## _MASK)) >> (field ## _OFFSET)) 115 116 #define SET_MFW_FIELD(name, field, value) \ 117 do { \ 118 (name) &= ~((field ## _MASK) << (field ## _OFFSET)); \ 119 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \ 120 } while (0) 121 122 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS) 123 { 124 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 125 (cid * ECORE_PF_DEMS_SIZE); 126 127 return db_addr; 128 } 129 130 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS) 131 { 132 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 133 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 134 135 return db_addr; 136 } 137 138 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 139 ((sizeof(type_name) + (u32)(1<<(p_hwfn->p_dev->cache_shift))-1) & \ 140 ~((1<<(p_hwfn->p_dev->cache_shift))-1)) 141 142 #ifndef U64_HI 143 #define U64_HI(val) ((u32)(((u64)(val)) >> 32)) 144 #endif 145 146 #ifndef U64_LO 147 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff)) 148 #endif 149 150 #ifndef UEFI 151 /* Debug print definitions */ 152 #define DP_ERR(p_dev, fmt, ...) \ 153 do { \ 154 PRINT_ERR((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 155 __func__, __LINE__, \ 156 (p_dev)->name ? (p_dev)->name : "", \ 157 ##__VA_ARGS__); \ 158 } while (0) 159 160 #define DP_NOTICE(p_dev, is_assert, fmt, ...) \ 161 do { \ 162 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_NOTICE)) { \ 163 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 164 __func__, __LINE__, \ 165 (p_dev)->name ? (p_dev)->name : "", \ 166 ##__VA_ARGS__); \ 167 OSAL_ASSERT(!is_assert); \ 168 } \ 169 } while (0) 170 171 #define DP_INFO(p_dev, fmt, ...) \ 172 do { \ 173 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_INFO)) { \ 174 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 175 __func__, __LINE__, \ 176 (p_dev)->name ? (p_dev)->name : "", \ 177 ##__VA_ARGS__); \ 178 } \ 179 } while (0) 180 181 #define DP_VERBOSE(p_dev, module, fmt, ...) \ 182 do { \ 183 if (OSAL_UNLIKELY(((p_dev)->dp_level <= ECORE_LEVEL_VERBOSE) && \ 184 ((p_dev)->dp_module & module))) { \ 185 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 186 __func__, __LINE__, \ 187 (p_dev)->name ? (p_dev)->name : "", \ 188 ##__VA_ARGS__); \ 189 } \ 190 } while (0) 191 #endif 192 193 enum DP_LEVEL { 194 ECORE_LEVEL_VERBOSE = 0x0, 195 ECORE_LEVEL_INFO = 0x1, 196 ECORE_LEVEL_NOTICE = 0x2, 197 ECORE_LEVEL_ERR = 0x3, 198 }; 199 200 #define ECORE_LOG_LEVEL_SHIFT (30) 201 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff) 202 #define ECORE_LOG_INFO_MASK (0x40000000) 203 #define ECORE_LOG_NOTICE_MASK (0x80000000) 204 205 enum DP_MODULE { 206 ECORE_MSG_DRV = 0x0001, 207 ECORE_MSG_PROBE = 0x0002, 208 ECORE_MSG_LINK = 0x0004, 209 ECORE_MSG_TIMER = 0x0008, 210 ECORE_MSG_IFDOWN = 0x0010, 211 ECORE_MSG_IFUP = 0x0020, 212 ECORE_MSG_RX_ERR = 0x0040, 213 ECORE_MSG_TX_ERR = 0x0080, 214 ECORE_MSG_TX_QUEUED = 0x0100, 215 ECORE_MSG_INTR = 0x0200, 216 ECORE_MSG_TX_DONE = 0x0400, 217 ECORE_MSG_RX_STATUS = 0x0800, 218 ECORE_MSG_PKTDATA = 0x1000, 219 ECORE_MSG_HW = 0x2000, 220 ECORE_MSG_WOL = 0x4000, 221 ECORE_MSG_SPQ = 0x10000, 222 ECORE_MSG_STATS = 0x20000, 223 ECORE_MSG_DCB = 0x40000, 224 ECORE_MSG_IOV = 0x80000, 225 ECORE_MSG_SP = 0x100000, 226 ECORE_MSG_STORAGE = 0x200000, 227 ECORE_MSG_OOO = 0x200000, 228 ECORE_MSG_CXT = 0x800000, 229 ECORE_MSG_LL2 = 0x1000000, 230 ECORE_MSG_ILT = 0x2000000, 231 ECORE_MSG_RDMA = 0x4000000, 232 ECORE_MSG_DEBUG = 0x8000000, 233 /* to be added...up to 0x8000000 */ 234 }; 235 236 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++) 237 238 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 239 (val == (cond1) ? true1 : \ 240 (val == (cond2) ? true2 : def)) 241 242 /* forward */ 243 struct ecore_ptt_pool; 244 struct ecore_spq; 245 struct ecore_sb_info; 246 struct ecore_sb_attn_info; 247 struct ecore_cxt_mngr; 248 struct ecore_dma_mem; 249 struct ecore_sb_sp_info; 250 struct ecore_ll2_info; 251 struct ecore_l2_info; 252 struct ecore_igu_info; 253 struct ecore_mcp_info; 254 struct ecore_dcbx_info; 255 256 struct ecore_rt_data { 257 u32 *init_val; 258 bool *b_valid; 259 }; 260 261 enum ecore_tunn_mode { 262 ECORE_MODE_L2GENEVE_TUNN, 263 ECORE_MODE_IPGENEVE_TUNN, 264 ECORE_MODE_L2GRE_TUNN, 265 ECORE_MODE_IPGRE_TUNN, 266 ECORE_MODE_VXLAN_TUNN, 267 }; 268 269 enum ecore_tunn_clss { 270 ECORE_TUNN_CLSS_MAC_VLAN, 271 ECORE_TUNN_CLSS_MAC_VNI, 272 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 273 ECORE_TUNN_CLSS_INNER_MAC_VNI, 274 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 275 MAX_ECORE_TUNN_CLSS, 276 }; 277 278 struct ecore_tunn_update_type { 279 bool b_update_mode; 280 bool b_mode_enabled; 281 enum ecore_tunn_clss tun_cls; 282 }; 283 284 struct ecore_tunn_update_udp_port { 285 bool b_update_port; 286 u16 port; 287 }; 288 289 struct ecore_tunnel_info { 290 struct ecore_tunn_update_type vxlan; 291 struct ecore_tunn_update_type l2_geneve; 292 struct ecore_tunn_update_type ip_geneve; 293 struct ecore_tunn_update_type l2_gre; 294 struct ecore_tunn_update_type ip_gre; 295 296 struct ecore_tunn_update_udp_port vxlan_port; 297 struct ecore_tunn_update_udp_port geneve_port; 298 299 bool b_update_rx_cls; 300 bool b_update_tx_cls; 301 }; 302 303 /* The PCI personality is not quite synonymous to protocol ID: 304 * 1. All personalities need CORE connections 305 * 2. The Ethernet personality may support also the RoCE/iWARP protocol 306 */ 307 enum ecore_pci_personality { 308 ECORE_PCI_ETH, 309 ECORE_PCI_FCOE, 310 ECORE_PCI_ISCSI, 311 ECORE_PCI_ETH_ROCE, 312 ECORE_PCI_ETH_IWARP, 313 ECORE_PCI_ETH_RDMA, 314 ECORE_PCI_DEFAULT /* default in shmem */ 315 }; 316 317 /* All VFs are symetric, all counters are PF + all VFs */ 318 struct ecore_qm_iids { 319 u32 cids; 320 u32 vf_cids; 321 u32 tids; 322 }; 323 324 #define MAX_PF_PER_PORT 8 325 326 /* HW / FW resources, output of features supported below, most information 327 * is received from MFW. 328 */ 329 enum ecore_resources { 330 ECORE_L2_QUEUE, 331 ECORE_VPORT, 332 ECORE_RSS_ENG, 333 ECORE_PQ, 334 ECORE_RL, 335 ECORE_MAC, 336 ECORE_VLAN, 337 ECORE_RDMA_CNQ_RAM, 338 ECORE_ILT, 339 ECORE_LL2_QUEUE, 340 ECORE_CMDQS_CQS, 341 ECORE_RDMA_STATS_QUEUE, 342 ECORE_BDQ, 343 344 /* This is needed only internally for matching against the IGU. 345 * In case of legacy MFW, would be set to `0'. 346 */ 347 ECORE_SB, 348 349 ECORE_MAX_RESC, 350 }; 351 352 /* Features that require resources, given as input to the resource management 353 * algorithm, the output are the resources above 354 */ 355 enum ecore_feature { 356 ECORE_PF_L2_QUE, 357 ECORE_PF_TC, 358 ECORE_VF, 359 ECORE_EXTRA_VF_QUE, 360 ECORE_VMQ, 361 ECORE_RDMA_CNQ, 362 ECORE_ISCSI_CQ, 363 ECORE_FCOE_CQ, 364 ECORE_VF_L2_QUE, 365 ECORE_MAX_FEATURES, 366 }; 367 368 enum ecore_port_mode { 369 ECORE_PORT_MODE_DE_2X40G, 370 ECORE_PORT_MODE_DE_2X50G, 371 ECORE_PORT_MODE_DE_1X100G, 372 ECORE_PORT_MODE_DE_4X10G_F, 373 ECORE_PORT_MODE_DE_4X10G_E, 374 ECORE_PORT_MODE_DE_4X20G, 375 ECORE_PORT_MODE_DE_1X40G, 376 ECORE_PORT_MODE_DE_2X25G, 377 ECORE_PORT_MODE_DE_1X25G, 378 ECORE_PORT_MODE_DE_4X25G, 379 ECORE_PORT_MODE_DE_2X10G, 380 }; 381 382 enum ecore_dev_cap { 383 ECORE_DEV_CAP_ETH, 384 ECORE_DEV_CAP_FCOE, 385 ECORE_DEV_CAP_ISCSI, 386 ECORE_DEV_CAP_ROCE, 387 ECORE_DEV_CAP_IWARP 388 }; 389 390 enum ecore_hw_err_type { 391 ECORE_HW_ERR_FAN_FAIL, 392 ECORE_HW_ERR_MFW_RESP_FAIL, 393 ECORE_HW_ERR_HW_ATTN, 394 ECORE_HW_ERR_DMAE_FAIL, 395 ECORE_HW_ERR_RAMROD_FAIL, 396 ECORE_HW_ERR_FW_ASSERT, 397 }; 398 399 enum ecore_wol_support { 400 ECORE_WOL_SUPPORT_NONE, 401 ECORE_WOL_SUPPORT_PME, 402 }; 403 404 enum ecore_db_rec_exec { 405 DB_REC_DRY_RUN, 406 DB_REC_REAL_DEAL, 407 }; 408 409 struct ecore_hw_info { 410 /* PCI personality */ 411 enum ecore_pci_personality personality; 412 #define ECORE_IS_RDMA_PERSONALITY(dev) \ 413 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 414 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 415 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 416 #define ECORE_IS_ROCE_PERSONALITY(dev) \ 417 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 418 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 419 #define ECORE_IS_IWARP_PERSONALITY(dev) \ 420 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 421 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 422 #define ECORE_IS_L2_PERSONALITY(dev) \ 423 ((dev)->hw_info.personality == ECORE_PCI_ETH || \ 424 ECORE_IS_RDMA_PERSONALITY(dev)) 425 #define ECORE_IS_FCOE_PERSONALITY(dev) \ 426 ((dev)->hw_info.personality == ECORE_PCI_FCOE) 427 #define ECORE_IS_ISCSI_PERSONALITY(dev) \ 428 ((dev)->hw_info.personality == ECORE_PCI_ISCSI) 429 430 /* Resource Allocation scheme results */ 431 u32 resc_start[ECORE_MAX_RESC]; 432 u32 resc_num[ECORE_MAX_RESC]; 433 u32 feat_num[ECORE_MAX_FEATURES]; 434 435 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 436 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 437 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 438 RESC_NUM(_p_hwfn, resc)) 439 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 440 441 /* Amount of traffic classes HW supports */ 442 u8 num_hw_tc; 443 444 /* Amount of TCs which should be active according to DCBx or upper layer driver configuration */ 445 u8 num_active_tc; 446 447 /* The traffic class used by PF for it's offloaded protocol */ 448 u8 offload_tc; 449 450 u32 concrete_fid; 451 u16 opaque_fid; 452 u16 ovlan; 453 u32 part_num[4]; 454 455 #ifndef ETH_ALEN 456 #define ETH_ALEN 6 /* @@@ TBD - define somewhere else for Windows */ 457 #endif 458 unsigned char hw_mac_addr[ETH_ALEN]; 459 460 u16 num_iscsi_conns; 461 u16 num_fcoe_conns; 462 463 struct ecore_igu_info *p_igu_info; 464 /* Sriov */ 465 u8 max_chains_per_vf; 466 467 u32 port_mode; 468 u32 hw_mode; 469 unsigned long device_capabilities; 470 471 /* Default DCBX mode */ 472 u8 dcbx_mode; 473 474 u16 mtu; 475 476 enum ecore_wol_support b_wol_support; 477 }; 478 479 /* maximun size of read/write commands (HW limit) */ 480 #define DMAE_MAX_RW_SIZE 0x2000 481 482 struct ecore_dmae_info { 483 /* Mutex for synchronizing access to functions */ 484 osal_mutex_t mutex; 485 486 u8 channel; 487 488 dma_addr_t completion_word_phys_addr; 489 490 /* The memory location where the DMAE writes the completion 491 * value when an operation is finished on this context. 492 */ 493 u32 *p_completion_word; 494 495 dma_addr_t intermediate_buffer_phys_addr; 496 497 /* An intermediate buffer for DMAE operations that use virtual 498 * addresses - data is DMA'd to/from this buffer and then 499 * memcpy'd to/from the virtual address 500 */ 501 u32 *p_intermediate_buffer; 502 503 dma_addr_t dmae_cmd_phys_addr; 504 struct dmae_cmd *p_dmae_cmd; 505 }; 506 507 struct ecore_wfq_data { 508 u32 default_min_speed; /* When wfq feature is not configured */ 509 u32 min_speed; /* when feature is configured for any 1 vport */ 510 bool configured; 511 }; 512 513 struct ecore_qm_info { 514 struct init_qm_pq_params *qm_pq_params; 515 struct init_qm_vport_params *qm_vport_params; 516 struct init_qm_port_params *qm_port_params; 517 u16 start_pq; 518 u8 start_vport; 519 u16 pure_lb_pq; 520 u16 offload_pq; 521 u16 low_latency_pq; 522 u16 pure_ack_pq; 523 u16 ooo_pq; 524 u16 first_vf_pq; 525 u16 first_mcos_pq; 526 u16 first_rl_pq; 527 u16 num_pqs; 528 u16 num_vf_pqs; 529 u8 num_vports; 530 u8 max_phys_tcs_per_port; 531 u8 ooo_tc; 532 bool pf_rl_en; 533 bool pf_wfq_en; 534 bool vport_rl_en; 535 bool vport_wfq_en; 536 u8 pf_wfq; 537 u32 pf_rl; 538 struct ecore_wfq_data *wfq_data; 539 u8 num_pf_rls; 540 }; 541 542 struct ecore_db_recovery_info { 543 osal_list_t list; 544 osal_spinlock_t lock; 545 u32 db_recovery_counter; 546 }; 547 548 struct storm_stats { 549 u32 address; 550 u32 len; 551 }; 552 553 struct ecore_fw_data { 554 #ifdef CONFIG_ECORE_BINARY_FW 555 struct fw_ver_info *fw_ver_info; 556 #endif 557 const u8 *modes_tree_buf; 558 union init_op *init_ops; 559 const u32 *arr_data; 560 u32 init_ops_size; 561 }; 562 563 struct ecore_hwfn { 564 struct ecore_dev *p_dev; 565 u8 my_id; /* ID inside the PF */ 566 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 567 u8 rel_pf_id; /* Relative to engine*/ 568 u8 abs_pf_id; 569 #define ECORE_PATH_ID(_p_hwfn) \ 570 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 571 u8 port_id; 572 bool b_active; 573 574 u32 dp_module; 575 u8 dp_level; 576 char name[NAME_SIZE]; 577 void *dp_ctx; 578 579 bool first_on_engine; 580 bool hw_init_done; 581 582 u8 num_funcs_on_engine; 583 u8 enabled_func_idx; 584 585 /* BAR access */ 586 void OSAL_IOMEM *regview; 587 void OSAL_IOMEM *doorbells; 588 u64 db_phys_addr; 589 unsigned long db_size; 590 591 /* PTT pool */ 592 struct ecore_ptt_pool *p_ptt_pool; 593 594 /* HW info */ 595 struct ecore_hw_info hw_info; 596 597 /* rt_array (for init-tool) */ 598 struct ecore_rt_data rt_data; 599 600 /* SPQ */ 601 struct ecore_spq *p_spq; 602 603 /* EQ */ 604 struct ecore_eq *p_eq; 605 606 /* Consolidate Q*/ 607 struct ecore_consq *p_consq; 608 609 /* Slow-Path definitions */ 610 osal_dpc_t sp_dpc; 611 bool b_sp_dpc_enabled; 612 613 struct ecore_ptt *p_main_ptt; 614 struct ecore_ptt *p_dpc_ptt; 615 616 /* PTP will be used only by the leading funtion. 617 * Usage of all PTP-apis should be synchronized as result. 618 */ 619 struct ecore_ptt *p_ptp_ptt; 620 621 struct ecore_sb_sp_info *p_sp_sb; 622 struct ecore_sb_attn_info *p_sb_attn; 623 624 /* Protocol related */ 625 bool using_ll2; 626 struct ecore_ll2_info *p_ll2_info; 627 struct ecore_ooo_info *p_ooo_info; 628 struct ecore_iscsi_info *p_iscsi_info; 629 struct ecore_fcoe_info *p_fcoe_info; 630 struct ecore_rdma_info *p_rdma_info; 631 struct ecore_pf_params pf_params; 632 633 bool b_rdma_enabled_in_prs; 634 u32 rdma_prs_search_reg; 635 636 struct ecore_cxt_mngr *p_cxt_mngr; 637 638 /* Flag indicating whether interrupts are enabled or not*/ 639 bool b_int_enabled; 640 bool b_int_requested; 641 642 /* True if the driver requests for the link */ 643 bool b_drv_link_init; 644 645 struct ecore_vf_iov *vf_iov_info; 646 struct ecore_pf_iov *pf_iov_info; 647 struct ecore_mcp_info *mcp_info; 648 struct ecore_dcbx_info *p_dcbx_info; 649 650 struct ecore_dmae_info dmae_info; 651 652 /* QM init */ 653 struct ecore_qm_info qm_info; 654 655 /* Buffer for unzipping firmware data */ 656 #ifdef CONFIG_ECORE_ZIPPED_FW 657 void *unzip_buf; 658 #endif 659 660 struct dbg_tools_data dbg_info; 661 662 /* PWM region specific data */ 663 u16 wid_count; 664 u32 dpi_size; 665 u32 dpi_count; 666 u32 dpi_start_offset; /* this is used to 667 * calculate th 668 * doorbell address 669 */ 670 671 /* If one of the following is set then EDPM shouldn't be used */ 672 u8 dcbx_no_edpm; 673 u8 db_bar_no_edpm; 674 675 /* L2-related */ 676 struct ecore_l2_info *p_l2_info; 677 678 /* Mechanism for recovering from doorbell drop */ 679 struct ecore_db_recovery_info db_recovery_info; 680 }; 681 682 enum ecore_mf_mode { 683 ECORE_MF_DEFAULT, 684 ECORE_MF_OVLAN, 685 ECORE_MF_NPAR, 686 }; 687 688 enum ecore_dev_type { 689 ECORE_DEV_TYPE_BB, 690 ECORE_DEV_TYPE_AH, 691 ECORE_DEV_TYPE_E5, 692 }; 693 694 struct ecore_dev { 695 u32 dp_module; 696 u8 dp_level; 697 char name[NAME_SIZE]; 698 void *dp_ctx; 699 700 enum ecore_dev_type type; 701 /* Translate type/revision combo into the proper conditions */ 702 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB) 703 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev)) 704 #ifndef ASIC_ONLY 705 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \ 706 (CHIP_REV_IS_TEDIBEAR(dev))) 707 #else 708 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) 709 #endif 710 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH) 711 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev) 712 713 #define ECORE_IS_E5(dev) ((dev)->type == ECORE_DEV_TYPE_E5) 714 715 #define ECORE_E5_MISSING_CODE OSAL_BUILD_BUG_ON(false) 716 717 u16 vendor_id; 718 u16 device_id; 719 #define ECORE_DEV_ID_MASK 0xff00 720 #define ECORE_DEV_ID_MASK_BB 0x1600 721 #define ECORE_DEV_ID_MASK_AH 0x8000 722 #define ECORE_DEV_ID_MASK_E5 0x8100 723 724 u16 chip_num; 725 #define CHIP_NUM_MASK 0xffff 726 #define CHIP_NUM_SHIFT 16 727 728 u16 chip_rev; 729 #define CHIP_REV_MASK 0xf 730 #define CHIP_REV_SHIFT 12 731 #ifndef ASIC_ONLY 732 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) 733 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) 734 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) 735 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \ 736 CHIP_REV_IS_EMUL_B0(_p_dev)) 737 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) 738 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) 739 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \ 740 CHIP_REV_IS_FPGA_B0(_p_dev)) 741 #define CHIP_REV_IS_SLOW(_p_dev) \ 742 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) 743 #define CHIP_REV_IS_A0(_p_dev) \ 744 (CHIP_REV_IS_EMUL_A0(_p_dev) || \ 745 CHIP_REV_IS_FPGA_A0(_p_dev) || \ 746 !(_p_dev)->chip_rev) 747 #define CHIP_REV_IS_B0(_p_dev) \ 748 (CHIP_REV_IS_EMUL_B0(_p_dev) || \ 749 CHIP_REV_IS_FPGA_B0(_p_dev) || \ 750 (_p_dev)->chip_rev == 1) 751 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) 752 #else 753 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev) 754 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1) 755 #endif 756 757 u16 chip_metal; 758 #define CHIP_METAL_MASK 0xff 759 #define CHIP_METAL_SHIFT 4 760 761 u16 chip_bond_id; 762 #define CHIP_BOND_ID_MASK 0xf 763 #define CHIP_BOND_ID_SHIFT 0 764 765 u8 num_engines; 766 u8 num_ports_in_engine; 767 u8 num_funcs_in_port; 768 769 u8 path_id; 770 enum ecore_mf_mode mf_mode; 771 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) 772 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) 773 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) 774 775 int pcie_width; 776 int pcie_speed; 777 778 /* Add MF related configuration */ 779 u8 mcp_rev; 780 u8 boot_mode; 781 782 /* WoL related configurations */ 783 u8 wol_config; 784 u8 wol_mac[ETH_ALEN]; 785 786 u32 int_mode; 787 enum ecore_coalescing_mode int_coalescing_mode; 788 u16 rx_coalesce_usecs; 789 u16 tx_coalesce_usecs; 790 791 /* Start Bar offset of first hwfn */ 792 void OSAL_IOMEM *regview; 793 void OSAL_IOMEM *doorbells; 794 u64 db_phys_addr; 795 unsigned long db_size; 796 797 /* PCI */ 798 u8 cache_shift; 799 800 /* Init */ 801 const struct iro *iro_arr; 802 #define IRO (p_hwfn->p_dev->iro_arr) 803 804 /* HW functions */ 805 u8 num_hwfns; 806 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 807 808 /* SRIOV */ 809 struct ecore_hw_sriov_info *p_iov_info; 810 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info) 811 #ifdef CONFIG_ECORE_SW_CHANNEL 812 bool b_hw_channel; 813 #endif 814 struct ecore_tunnel_info tunnel; 815 bool b_is_vf; 816 bool b_dont_override_vf_msix; 817 818 u32 drv_type; 819 820 u32 rdma_max_sge; 821 u32 rdma_max_inline; 822 u32 rdma_max_srq_sge; 823 824 struct ecore_eth_stats *reset_stats; 825 struct ecore_fw_data *fw_data; 826 827 u32 mcp_nvm_resp; 828 829 /* Recovery */ 830 bool recov_in_prog; 831 832 /* Indicates whether should prevent attentions from being reasserted */ 833 bool attn_clr_en; 834 835 /* Indicates whether allowing the MFW to collect a crash dump */ 836 bool allow_mdump; 837 838 /* Indicates if the reg_fifo is checked after any register access */ 839 bool chk_reg_fifo; 840 841 #ifndef ASIC_ONLY 842 bool b_is_emul_full; 843 #endif 844 }; 845 846 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \ 847 : MAX_NUM_VFS_K2) 848 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 849 : MAX_NUM_L2_QUEUES_K2) 850 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 851 : MAX_NUM_PORTS_K2) 852 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 853 : MAX_SB_PER_PATH_K2) 854 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \ 855 : MAX_NUM_PFS_K2) 856 857 #define CRC8_TABLE_SIZE 256 858 859 /** 860 * @brief ecore_concrete_to_sw_fid - get the sw function id from 861 * the concrete value. 862 * 863 * @param concrete_fid 864 * 865 * @return OSAL_INLINE u8 866 */ 867 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid) 868 { 869 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 870 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 871 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID); 872 u8 sw_fid; 873 874 if (vf_valid) 875 sw_fid = vfid + MAX_NUM_PFS; 876 else 877 sw_fid = pfid; 878 879 return sw_fid; 880 } 881 882 #define PKT_LB_TC 9 883 #define MAX_NUM_VOQS_E4 20 884 885 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate); 886 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, 887 struct ecore_ptt *p_ptt, 888 u32 min_pf_rate); 889 890 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw); 891 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw); 892 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); 893 int ecore_device_num_engines(struct ecore_dev *p_dev); 894 int ecore_device_num_ports(struct ecore_dev *p_dev); 895 int ecore_device_get_port_id(struct ecore_dev *p_dev); 896 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb, 897 u8 *mac); 898 899 /* Flags for indication of required queues */ 900 #define PQ_FLAGS_RLS (1 << 0) 901 #define PQ_FLAGS_MCOS (1 << 1) 902 #define PQ_FLAGS_LB (1 << 2) 903 #define PQ_FLAGS_OOO (1 << 3) 904 #define PQ_FLAGS_ACK (1 << 4) 905 #define PQ_FLAGS_OFLD (1 << 5) 906 #define PQ_FLAGS_VFS (1 << 6) 907 #define PQ_FLAGS_LLT (1 << 7) 908 909 /* physical queue index for cm context intialization */ 910 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags); 911 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc); 912 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf); 913 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid); 914 915 const char *ecore_hw_get_resc_name(enum ecore_resources res_id); 916 917 /* doorbell recovery mechanism */ 918 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn); 919 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn, 920 enum ecore_db_rec_exec); 921 922 /* amount of resources used in qm init */ 923 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn); 924 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn); 925 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn); 926 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn); 927 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn); 928 929 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0]) 930 931 #endif /* __ECORE_H */ 932