1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_H 32 #define __ECORE_H 33 34 #include "ecore_status.h" 35 #include "ecore_hsi_common.h" 36 #include "ecore_hsi_debug_tools.h" 37 #include "ecore_hsi_init_func.h" 38 #include "ecore_hsi_init_tool.h" 39 #include "ecore_proto_if.h" 40 #include "mcp_public.h" 41 42 #define ECORE_MAJOR_VERSION 8 43 #define ECORE_MINOR_VERSION 33 44 #define ECORE_REVISION_VERSION 5 45 #define ECORE_ENGINEERING_VERSION 0 46 47 #define ECORE_VERSION \ 48 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \ 49 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION) 50 51 #define STORM_FW_VERSION \ 52 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 53 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 54 55 #define MAX_HWFNS_PER_DEVICE 2 56 #define NAME_SIZE 16 57 #define ARRAY_DECL static const 58 #define ECORE_WFQ_UNIT 100 59 60 /* Constants */ 61 #define ECORE_WID_SIZE (1024) 62 #define ECORE_MIN_WIDS (4) 63 64 /* Configurable */ 65 #define ECORE_PF_DEMS_SIZE (4) 66 67 /* cau states */ 68 enum ecore_coalescing_mode { 69 ECORE_COAL_MODE_DISABLE, 70 ECORE_COAL_MODE_ENABLE 71 }; 72 73 enum ecore_nvm_cmd { 74 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, 75 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, 76 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM, 77 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, 78 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE, 79 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE, 80 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE, 81 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ, 82 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE, 83 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ, 84 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE, 85 ECORE_ENCRYPT_PASSWORD = DRV_MSG_CODE_ENCRYPT_PASSWORD, 86 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00 87 }; 88 89 #ifndef LINUX_REMOVE 90 #if !defined(CONFIG_ECORE_L2) && !defined(CONFIG_ECORE_ROCE) && \ 91 !defined(CONFIG_ECORE_FCOE) && !defined(CONFIG_ECORE_ISCSI) && \ 92 !defined(CONFIG_ECORE_IWARP) 93 #define CONFIG_ECORE_L2 94 #define CONFIG_ECORE_SRIOV 95 #define CONFIG_ECORE_ROCE 96 #define CONFIG_ECORE_IWARP 97 #define CONFIG_ECORE_LL2 98 #define CONFIG_ECORE_RDMA 99 #define ECORE_CONFIG_DIRECT_HWFN 100 #define QLNX_ENABLE_IWARP 101 #endif 102 #endif 103 104 /* helpers */ 105 #ifndef __EXTRACT__LINUX__IF__ 106 #define MASK_FIELD(_name, _value) \ 107 ((_value) &= (_name##_MASK)) 108 109 #define FIELD_VALUE(_name, _value) \ 110 ((_value & _name##_MASK) << _name##_SHIFT) 111 112 #define SET_FIELD(value, name, flag) \ 113 do { \ 114 (value) &= ~(name##_MASK << name##_SHIFT); \ 115 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\ 116 } while (0) 117 118 #define GET_FIELD(value, name) \ 119 (((value) >> (name##_SHIFT)) & name##_MASK) 120 121 #define GET_MFW_FIELD(name, field) \ 122 (((name) & (field ## _MASK)) >> (field ## _OFFSET)) 123 124 #define SET_MFW_FIELD(name, field, value) \ 125 do { \ 126 (name) &= ~(field ## _MASK); \ 127 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK)); \ 128 } while (0) 129 #endif 130 131 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS) 132 { 133 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 134 (cid * ECORE_PF_DEMS_SIZE); 135 136 return db_addr; 137 } 138 139 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS) 140 { 141 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 142 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 143 144 return db_addr; 145 } 146 147 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 148 ((sizeof(type_name) + (u32)(1<<(p_hwfn->p_dev->cache_shift))-1) & \ 149 ~((1<<(p_hwfn->p_dev->cache_shift))-1)) 150 151 #ifndef LINUX_REMOVE 152 #ifndef U64_HI 153 #define U64_HI(val) ((u32)(((u64)(val)) >> 32)) 154 #endif 155 156 #ifndef U64_LO 157 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff)) 158 #endif 159 #endif 160 161 #ifndef __EXTRACT__LINUX__IF__ 162 #ifndef UEFI 163 /* Debug print definitions */ 164 #define DP_ERR(p_dev, fmt, ...) \ 165 do { \ 166 PRINT_ERR((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 167 __func__, __LINE__, \ 168 (p_dev)->name ? (p_dev)->name : "", \ 169 ##__VA_ARGS__); \ 170 } while (0) 171 172 #define DP_NOTICE(p_dev, is_assert, fmt, ...) \ 173 do { \ 174 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_NOTICE)) { \ 175 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 176 __func__, __LINE__, \ 177 (p_dev)->name ? (p_dev)->name : "", \ 178 ##__VA_ARGS__); \ 179 OSAL_ASSERT(!is_assert); \ 180 } \ 181 } while (0) 182 183 #define DP_INFO(p_dev, fmt, ...) \ 184 do { \ 185 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_INFO)) { \ 186 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 187 __func__, __LINE__, \ 188 (p_dev)->name ? (p_dev)->name : "", \ 189 ##__VA_ARGS__); \ 190 } \ 191 } while (0) 192 193 #define DP_VERBOSE(p_dev, module, fmt, ...) \ 194 do { \ 195 if (OSAL_UNLIKELY(((p_dev)->dp_level <= ECORE_LEVEL_VERBOSE) && \ 196 ((p_dev)->dp_module & module))) { \ 197 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 198 __func__, __LINE__, \ 199 (p_dev)->name ? (p_dev)->name : "", \ 200 ##__VA_ARGS__); \ 201 } \ 202 } while (0) 203 #endif 204 205 enum DP_LEVEL { 206 ECORE_LEVEL_VERBOSE = 0x0, 207 ECORE_LEVEL_INFO = 0x1, 208 ECORE_LEVEL_NOTICE = 0x2, 209 ECORE_LEVEL_ERR = 0x3, 210 }; 211 212 #define ECORE_LOG_LEVEL_SHIFT (30) 213 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff) 214 #define ECORE_LOG_INFO_MASK (0x40000000) 215 #define ECORE_LOG_NOTICE_MASK (0x80000000) 216 217 enum DP_MODULE { 218 #ifndef LINUX_REMOVE 219 ECORE_MSG_DRV = 0x0001, 220 ECORE_MSG_PROBE = 0x0002, 221 ECORE_MSG_LINK = 0x0004, 222 ECORE_MSG_TIMER = 0x0008, 223 ECORE_MSG_IFDOWN = 0x0010, 224 ECORE_MSG_IFUP = 0x0020, 225 ECORE_MSG_RX_ERR = 0x0040, 226 ECORE_MSG_TX_ERR = 0x0080, 227 ECORE_MSG_TX_QUEUED = 0x0100, 228 ECORE_MSG_INTR = 0x0200, 229 ECORE_MSG_TX_DONE = 0x0400, 230 ECORE_MSG_RX_STATUS = 0x0800, 231 ECORE_MSG_PKTDATA = 0x1000, 232 ECORE_MSG_HW = 0x2000, 233 ECORE_MSG_WOL = 0x4000, 234 #endif 235 ECORE_MSG_SPQ = 0x10000, 236 ECORE_MSG_STATS = 0x20000, 237 ECORE_MSG_DCB = 0x40000, 238 ECORE_MSG_IOV = 0x80000, 239 ECORE_MSG_SP = 0x100000, 240 ECORE_MSG_STORAGE = 0x200000, 241 ECORE_MSG_OOO = 0x200000, 242 ECORE_MSG_CXT = 0x800000, 243 ECORE_MSG_LL2 = 0x1000000, 244 ECORE_MSG_ILT = 0x2000000, 245 ECORE_MSG_RDMA = 0x4000000, 246 ECORE_MSG_DEBUG = 0x8000000, 247 /* to be added...up to 0x8000000 */ 248 }; 249 #endif 250 251 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++) 252 253 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 254 (val == (cond1) ? true1 : \ 255 (val == (cond2) ? true2 : def)) 256 257 /* forward */ 258 struct ecore_ptt_pool; 259 struct ecore_spq; 260 struct ecore_sb_info; 261 struct ecore_sb_attn_info; 262 struct ecore_cxt_mngr; 263 struct ecore_dma_mem; 264 struct ecore_sb_sp_info; 265 struct ecore_ll2_info; 266 struct ecore_l2_info; 267 struct ecore_igu_info; 268 struct ecore_mcp_info; 269 struct ecore_dcbx_info; 270 struct ecore_llh_info; 271 272 struct ecore_rt_data { 273 u32 *init_val; 274 bool *b_valid; 275 }; 276 277 enum ecore_tunn_mode { 278 ECORE_MODE_L2GENEVE_TUNN, 279 ECORE_MODE_IPGENEVE_TUNN, 280 ECORE_MODE_L2GRE_TUNN, 281 ECORE_MODE_IPGRE_TUNN, 282 ECORE_MODE_VXLAN_TUNN, 283 }; 284 285 enum ecore_tunn_clss { 286 ECORE_TUNN_CLSS_MAC_VLAN, 287 ECORE_TUNN_CLSS_MAC_VNI, 288 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 289 ECORE_TUNN_CLSS_INNER_MAC_VNI, 290 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 291 MAX_ECORE_TUNN_CLSS, 292 }; 293 294 struct ecore_tunn_update_type { 295 bool b_update_mode; 296 bool b_mode_enabled; 297 enum ecore_tunn_clss tun_cls; 298 }; 299 300 struct ecore_tunn_update_udp_port { 301 bool b_update_port; 302 u16 port; 303 }; 304 305 struct ecore_tunnel_info { 306 struct ecore_tunn_update_type vxlan; 307 struct ecore_tunn_update_type l2_geneve; 308 struct ecore_tunn_update_type ip_geneve; 309 struct ecore_tunn_update_type l2_gre; 310 struct ecore_tunn_update_type ip_gre; 311 312 struct ecore_tunn_update_udp_port vxlan_port; 313 struct ecore_tunn_update_udp_port geneve_port; 314 315 bool b_update_rx_cls; 316 bool b_update_tx_cls; 317 }; 318 319 /* The PCI personality is not quite synonymous to protocol ID: 320 * 1. All personalities need CORE connections 321 * 2. The Ethernet personality may support also the RoCE/iWARP protocol 322 */ 323 enum ecore_pci_personality { 324 ECORE_PCI_ETH, 325 ECORE_PCI_FCOE, 326 ECORE_PCI_ISCSI, 327 ECORE_PCI_ETH_ROCE, 328 ECORE_PCI_ETH_IWARP, 329 ECORE_PCI_ETH_RDMA, 330 ECORE_PCI_DEFAULT /* default in shmem */ 331 }; 332 333 /* All VFs are symetric, all counters are PF + all VFs */ 334 struct ecore_qm_iids { 335 u32 cids; 336 u32 vf_cids; 337 u32 tids; 338 }; 339 340 /* The PCI relax ordering is either taken care by management FW or can be 341 * enable/disable by ecore client. 342 */ 343 enum ecore_pci_rlx_odr { 344 ECORE_DEFAULT_RLX_ODR, 345 ECORE_ENABLE_RLX_ODR, 346 ECORE_DISABLE_RLX_ODR 347 }; 348 349 #define MAX_PF_PER_PORT 8 350 351 /* HW / FW resources, output of features supported below, most information 352 * is received from MFW. 353 */ 354 enum ecore_resources { 355 ECORE_L2_QUEUE, 356 ECORE_VPORT, 357 ECORE_RSS_ENG, 358 ECORE_PQ, 359 ECORE_RL, 360 ECORE_MAC, 361 ECORE_VLAN, 362 ECORE_RDMA_CNQ_RAM, 363 ECORE_ILT, 364 ECORE_LL2_QUEUE, 365 ECORE_CMDQS_CQS, 366 ECORE_RDMA_STATS_QUEUE, 367 ECORE_BDQ, 368 369 /* This is needed only internally for matching against the IGU. 370 * In case of legacy MFW, would be set to `0'. 371 */ 372 ECORE_SB, 373 374 ECORE_MAX_RESC, 375 }; 376 377 /* Features that require resources, given as input to the resource management 378 * algorithm, the output are the resources above 379 */ 380 enum ecore_feature { 381 ECORE_PF_L2_QUE, 382 ECORE_PF_TC, 383 ECORE_VF, 384 ECORE_EXTRA_VF_QUE, 385 ECORE_VMQ, 386 ECORE_RDMA_CNQ, 387 ECORE_ISCSI_CQ, 388 ECORE_FCOE_CQ, 389 ECORE_VF_L2_QUE, 390 ECORE_MAX_FEATURES, 391 }; 392 393 enum ecore_port_mode { 394 ECORE_PORT_MODE_DE_2X40G, 395 ECORE_PORT_MODE_DE_2X50G, 396 ECORE_PORT_MODE_DE_1X100G, 397 ECORE_PORT_MODE_DE_4X10G_F, 398 ECORE_PORT_MODE_DE_4X10G_E, 399 ECORE_PORT_MODE_DE_4X20G, 400 ECORE_PORT_MODE_DE_1X40G, 401 ECORE_PORT_MODE_DE_2X25G, 402 ECORE_PORT_MODE_DE_1X25G, 403 ECORE_PORT_MODE_DE_4X25G, 404 ECORE_PORT_MODE_DE_2X10G, 405 }; 406 407 enum ecore_dev_cap { 408 ECORE_DEV_CAP_ETH, 409 ECORE_DEV_CAP_FCOE, 410 ECORE_DEV_CAP_ISCSI, 411 ECORE_DEV_CAP_ROCE, 412 ECORE_DEV_CAP_IWARP 413 }; 414 415 #ifndef __EXTRACT__LINUX__IF__ 416 enum ecore_hw_err_type { 417 ECORE_HW_ERR_FAN_FAIL, 418 ECORE_HW_ERR_MFW_RESP_FAIL, 419 ECORE_HW_ERR_HW_ATTN, 420 ECORE_HW_ERR_DMAE_FAIL, 421 ECORE_HW_ERR_RAMROD_FAIL, 422 ECORE_HW_ERR_FW_ASSERT, 423 }; 424 #endif 425 426 enum ecore_wol_support { 427 ECORE_WOL_SUPPORT_NONE, 428 ECORE_WOL_SUPPORT_PME, 429 }; 430 431 enum ecore_db_rec_exec { 432 DB_REC_DRY_RUN, 433 DB_REC_REAL_DEAL, 434 DB_REC_ONCE, 435 }; 436 437 struct ecore_hw_info { 438 /* PCI personality */ 439 enum ecore_pci_personality personality; 440 #define ECORE_IS_RDMA_PERSONALITY(dev) \ 441 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 442 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 443 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 444 #define ECORE_IS_ROCE_PERSONALITY(dev) \ 445 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 446 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 447 #define ECORE_IS_IWARP_PERSONALITY(dev) \ 448 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 449 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 450 #define ECORE_IS_L2_PERSONALITY(dev) \ 451 ((dev)->hw_info.personality == ECORE_PCI_ETH || \ 452 ECORE_IS_RDMA_PERSONALITY(dev)) 453 #define ECORE_IS_FCOE_PERSONALITY(dev) \ 454 ((dev)->hw_info.personality == ECORE_PCI_FCOE) 455 #define ECORE_IS_ISCSI_PERSONALITY(dev) \ 456 ((dev)->hw_info.personality == ECORE_PCI_ISCSI) 457 458 /* Resource Allocation scheme results */ 459 u32 resc_start[ECORE_MAX_RESC]; 460 u32 resc_num[ECORE_MAX_RESC]; 461 u32 feat_num[ECORE_MAX_FEATURES]; 462 463 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 464 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 465 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 466 RESC_NUM(_p_hwfn, resc)) 467 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 468 469 /* Amount of traffic classes HW supports */ 470 u8 num_hw_tc; 471 472 /* Amount of TCs which should be active according to DCBx or upper layer driver configuration */ 473 u8 num_active_tc; 474 475 /* The traffic class used by PF for it's offloaded protocol */ 476 u8 offload_tc; 477 478 u32 concrete_fid; 479 u16 opaque_fid; 480 u16 ovlan; 481 u32 part_num[4]; 482 483 #ifndef ETH_ALEN 484 #define ETH_ALEN 6 /* @@@ TBD - define somewhere else for Windows */ 485 #endif 486 unsigned char hw_mac_addr[ETH_ALEN]; 487 488 u16 num_iscsi_conns; 489 u16 num_fcoe_conns; 490 491 struct ecore_igu_info *p_igu_info; 492 /* Sriov */ 493 u8 max_chains_per_vf; 494 495 u32 port_mode; 496 u32 hw_mode; 497 unsigned long device_capabilities; 498 499 #ifndef __EXTRACT__LINUX__THROW__ 500 /* Default DCBX mode */ 501 u8 dcbx_mode; 502 #endif 503 504 u16 mtu; 505 506 enum ecore_wol_support b_wol_support; 507 }; 508 509 /* maximun size of read/write commands (HW limit) */ 510 #define DMAE_MAX_RW_SIZE 0x2000 511 512 struct ecore_dmae_info { 513 /* Spinlock for synchronizing access to functions */ 514 osal_spinlock_t lock; 515 516 bool b_mem_ready; 517 518 u8 channel; 519 520 dma_addr_t completion_word_phys_addr; 521 522 /* The memory location where the DMAE writes the completion 523 * value when an operation is finished on this context. 524 */ 525 u32 *p_completion_word; 526 527 dma_addr_t intermediate_buffer_phys_addr; 528 529 /* An intermediate buffer for DMAE operations that use virtual 530 * addresses - data is DMA'd to/from this buffer and then 531 * memcpy'd to/from the virtual address 532 */ 533 u32 *p_intermediate_buffer; 534 535 dma_addr_t dmae_cmd_phys_addr; 536 struct dmae_cmd *p_dmae_cmd; 537 }; 538 539 struct ecore_wfq_data { 540 u32 default_min_speed; /* When wfq feature is not configured */ 541 u32 min_speed; /* when feature is configured for any 1 vport */ 542 bool configured; 543 }; 544 545 struct ecore_qm_info { 546 struct init_qm_pq_params *qm_pq_params; 547 struct init_qm_vport_params *qm_vport_params; 548 struct init_qm_port_params *qm_port_params; 549 u16 start_pq; 550 u8 start_vport; 551 u16 pure_lb_pq; 552 u16 offload_pq; 553 u16 low_latency_pq; 554 u16 pure_ack_pq; 555 u16 ooo_pq; 556 u16 first_vf_pq; 557 u16 first_mcos_pq; 558 u16 first_rl_pq; 559 u16 num_pqs; 560 u16 num_vf_pqs; 561 u8 num_vports; 562 u8 max_phys_tcs_per_port; 563 u8 ooo_tc; 564 bool pf_rl_en; 565 bool pf_wfq_en; 566 bool vport_rl_en; 567 bool vport_wfq_en; 568 u8 pf_wfq; 569 u32 pf_rl; 570 struct ecore_wfq_data *wfq_data; 571 u8 num_pf_rls; 572 }; 573 574 struct ecore_db_recovery_info { 575 osal_list_t list; 576 osal_spinlock_t lock; 577 u32 db_recovery_counter; 578 }; 579 580 struct storm_stats { 581 u32 address; 582 u32 len; 583 }; 584 585 struct ecore_fw_data { 586 #ifdef CONFIG_ECORE_BINARY_FW 587 struct fw_ver_info *fw_ver_info; 588 #endif 589 const u8 *modes_tree_buf; 590 const union init_op *init_ops; 591 const u32 *arr_data; 592 u32 init_ops_size; 593 }; 594 595 enum ecore_mf_mode_bit { 596 /* Supports PF-classification based on tag */ 597 ECORE_MF_OVLAN_CLSS, 598 599 /* Supports PF-classification based on MAC */ 600 ECORE_MF_LLH_MAC_CLSS, 601 602 /* Supports PF-classification based on protocol type */ 603 ECORE_MF_LLH_PROTO_CLSS, 604 605 /* Requires a default PF to be set */ 606 ECORE_MF_NEED_DEF_PF, 607 608 /* Allow LL2 to multicast/broadcast */ 609 ECORE_MF_LL2_NON_UNICAST, 610 611 /* Allow Cross-PF [& child VFs] Tx-switching */ 612 ECORE_MF_INTER_PF_SWITCH, 613 614 /* TODO - if we ever re-utilize any of this logic, we can rename */ 615 ECORE_MF_UFP_SPECIFIC, 616 617 ECORE_MF_DISABLE_ARFS, 618 619 /* Use vlan for steering */ 620 ECORE_MF_8021Q_TAGGING, 621 622 /* Use stag for steering */ 623 ECORE_MF_8021AD_TAGGING, 624 }; 625 626 enum ecore_ufp_mode { 627 ECORE_UFP_MODE_ETS, 628 ECORE_UFP_MODE_VNIC_BW, 629 ECORE_UFP_MODE_UNKNOWN 630 }; 631 632 enum ecore_ufp_pri_type { 633 ECORE_UFP_PRI_OS, 634 ECORE_UFP_PRI_VNIC, 635 ECORE_UFP_PRI_UNKNOWN 636 }; 637 638 struct ecore_ufp_info { 639 enum ecore_ufp_pri_type pri_type; 640 enum ecore_ufp_mode mode; 641 u8 tc; 642 }; 643 644 enum BAR_ID { 645 BAR_ID_0, /* used for GRC */ 646 BAR_ID_1 /* Used for doorbells */ 647 }; 648 649 struct ecore_hwfn { 650 struct ecore_dev *p_dev; 651 u8 my_id; /* ID inside the PF */ 652 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 653 u8 rel_pf_id; /* Relative to engine*/ 654 u8 abs_pf_id; 655 #define ECORE_PATH_ID(_p_hwfn) \ 656 (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0) 657 u8 port_id; 658 bool b_active; 659 660 u32 dp_module; 661 u8 dp_level; 662 char name[NAME_SIZE]; 663 void *dp_ctx; 664 665 bool hw_init_done; 666 667 u8 num_funcs_on_engine; 668 u8 enabled_func_idx; 669 670 /* BAR access */ 671 void OSAL_IOMEM *regview; 672 void OSAL_IOMEM *doorbells; 673 u64 db_phys_addr; 674 unsigned long db_size; 675 676 #ifndef LINUX_REMOVE 677 u64 reg_offset; 678 u64 db_offset; 679 #endif 680 681 /* PTT pool */ 682 struct ecore_ptt_pool *p_ptt_pool; 683 684 /* HW info */ 685 struct ecore_hw_info hw_info; 686 687 /* rt_array (for init-tool) */ 688 struct ecore_rt_data rt_data; 689 690 /* SPQ */ 691 struct ecore_spq *p_spq; 692 693 /* EQ */ 694 struct ecore_eq *p_eq; 695 696 /* Consolidate Q*/ 697 struct ecore_consq *p_consq; 698 699 /* Slow-Path definitions */ 700 osal_dpc_t sp_dpc; 701 bool b_sp_dpc_enabled; 702 703 struct ecore_ptt *p_main_ptt; 704 struct ecore_ptt *p_dpc_ptt; 705 706 /* PTP will be used only by the leading function. 707 * Usage of all PTP-apis should be synchronized as result. 708 */ 709 struct ecore_ptt *p_ptp_ptt; 710 711 struct ecore_sb_sp_info *p_sp_sb; 712 struct ecore_sb_attn_info *p_sb_attn; 713 714 /* Protocol related */ 715 bool using_ll2; 716 struct ecore_ll2_info *p_ll2_info; 717 struct ecore_ooo_info *p_ooo_info; 718 struct ecore_iscsi_info *p_iscsi_info; 719 struct ecore_fcoe_info *p_fcoe_info; 720 struct ecore_rdma_info *p_rdma_info; 721 struct ecore_pf_params pf_params; 722 723 bool b_rdma_enabled_in_prs; 724 u32 rdma_prs_search_reg; 725 726 struct ecore_cxt_mngr *p_cxt_mngr; 727 728 /* Flag indicating whether interrupts are enabled or not*/ 729 bool b_int_enabled; 730 bool b_int_requested; 731 732 /* True if the driver requests for the link */ 733 bool b_drv_link_init; 734 735 struct ecore_vf_iov *vf_iov_info; 736 struct ecore_pf_iov *pf_iov_info; 737 struct ecore_mcp_info *mcp_info; 738 struct ecore_dcbx_info *p_dcbx_info; 739 struct ecore_ufp_info ufp_info; 740 741 struct ecore_dmae_info dmae_info; 742 743 /* QM init */ 744 struct ecore_qm_info qm_info; 745 746 /* Buffer for unzipping firmware data */ 747 #ifdef CONFIG_ECORE_ZIPPED_FW 748 void *unzip_buf; 749 #endif 750 751 struct dbg_tools_data dbg_info; 752 753 /* PWM region specific data */ 754 u16 wid_count; 755 u32 dpi_size; 756 u32 dpi_count; 757 u32 dpi_start_offset; /* this is used to 758 * calculate th 759 * doorbell address 760 */ 761 762 /* If one of the following is set then EDPM shouldn't be used */ 763 u8 dcbx_no_edpm; 764 u8 db_bar_no_edpm; 765 766 /* L2-related */ 767 struct ecore_l2_info *p_l2_info; 768 769 /* Mechanism for recovering from doorbell drop */ 770 struct ecore_db_recovery_info db_recovery_info; 771 }; 772 773 #ifndef __EXTRACT__LINUX__THROW__ 774 enum ecore_mf_mode { 775 ECORE_MF_DEFAULT, 776 ECORE_MF_OVLAN, 777 ECORE_MF_NPAR, 778 ECORE_MF_UFP, 779 }; 780 #endif 781 782 #ifndef __EXTRACT__LINUX__IF__ 783 enum ecore_dev_type { 784 ECORE_DEV_TYPE_BB, 785 ECORE_DEV_TYPE_AH, 786 ECORE_DEV_TYPE_E5, 787 }; 788 #endif 789 790 struct ecore_dev { 791 u32 dp_module; 792 u8 dp_level; 793 char name[NAME_SIZE]; 794 void *dp_ctx; 795 796 enum ecore_dev_type type; 797 /* Translate type/revision combo into the proper conditions */ 798 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB) 799 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev)) 800 #ifndef ASIC_ONLY 801 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \ 802 (CHIP_REV_IS_TEDIBEAR(dev))) 803 #else 804 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) 805 #endif 806 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH) 807 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev) 808 #define ECORE_IS_E4(dev) (ECORE_IS_BB(dev) || ECORE_IS_AH(dev)) 809 #define ECORE_IS_E5(dev) ((dev)->type == ECORE_DEV_TYPE_E5) 810 811 #define ECORE_E5_MISSING_CODE OSAL_BUILD_BUG_ON(false) 812 813 u16 vendor_id; 814 u16 device_id; 815 #define ECORE_DEV_ID_MASK 0xff00 816 #define ECORE_DEV_ID_MASK_BB 0x1600 817 #define ECORE_DEV_ID_MASK_AH 0x8000 818 #define ECORE_DEV_ID_MASK_E5 0x8100 819 820 u16 chip_num; 821 #define CHIP_NUM_MASK 0xffff 822 #define CHIP_NUM_SHIFT 0 823 824 u8 chip_rev; 825 #define CHIP_REV_MASK 0xf 826 #define CHIP_REV_SHIFT 0 827 #ifndef ASIC_ONLY 828 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) 829 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) 830 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) 831 #define CHIP_REV_IS_EMUL(_p_dev) \ 832 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_EMUL_B0(_p_dev)) 833 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) 834 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) 835 #define CHIP_REV_IS_FPGA(_p_dev) \ 836 (CHIP_REV_IS_FPGA_A0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev)) 837 #define CHIP_REV_IS_SLOW(_p_dev) \ 838 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) 839 #define CHIP_REV_IS_A0(_p_dev) \ 840 (CHIP_REV_IS_EMUL_A0(_p_dev) || CHIP_REV_IS_FPGA_A0(_p_dev) || \ 841 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal)) 842 #define CHIP_REV_IS_B0(_p_dev) \ 843 (CHIP_REV_IS_EMUL_B0(_p_dev) || CHIP_REV_IS_FPGA_B0(_p_dev) || \ 844 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal)) 845 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) 846 #else 847 #define CHIP_REV_IS_A0(_p_dev) \ 848 (!(_p_dev)->chip_rev && !(_p_dev)->chip_metal) 849 #define CHIP_REV_IS_B0(_p_dev) \ 850 ((_p_dev)->chip_rev == 1 && !(_p_dev)->chip_metal) 851 #endif 852 853 u8 chip_metal; 854 #define CHIP_METAL_MASK 0xff 855 #define CHIP_METAL_SHIFT 0 856 857 u8 chip_bond_id; 858 #define CHIP_BOND_ID_MASK 0xff 859 #define CHIP_BOND_ID_SHIFT 0 860 861 u8 num_engines; 862 u8 num_ports; 863 u8 num_ports_in_engine; 864 u8 num_funcs_in_port; 865 866 u8 path_id; 867 868 unsigned long mf_bits; 869 #ifndef __EXTRACT__LINUX__THROW__ 870 enum ecore_mf_mode mf_mode; 871 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) 872 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) 873 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) 874 #endif 875 876 int pcie_width; 877 int pcie_speed; 878 879 /* Add MF related configuration */ 880 u8 mcp_rev; 881 u8 boot_mode; 882 883 /* WoL related configurations */ 884 u8 wol_config; 885 u8 wol_mac[ETH_ALEN]; 886 887 u32 int_mode; 888 enum ecore_coalescing_mode int_coalescing_mode; 889 u16 rx_coalesce_usecs; 890 u16 tx_coalesce_usecs; 891 892 /* Start Bar offset of first hwfn */ 893 void OSAL_IOMEM *regview; 894 void OSAL_IOMEM *doorbells; 895 u64 db_phys_addr; 896 unsigned long db_size; 897 898 /* PCI */ 899 u8 cache_shift; 900 901 /* Init */ 902 const struct iro *iro_arr; 903 #define IRO (p_hwfn->p_dev->iro_arr) 904 905 /* HW functions */ 906 u8 num_hwfns; 907 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 908 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0]) 909 #define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1) 910 911 /* Engine affinity */ 912 u8 l2_affin_hint; 913 u8 fir_affin; 914 u8 iwarp_affin; 915 /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */ 916 #define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin]) 917 /* Macro for getting the engine-affinitized hwfn for iWARP */ 918 #define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin]) 919 /* Generic macro for getting the engine-affinitized hwfn */ 920 #define ECORE_AFFIN_HWFN(dev) \ 921 (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \ 922 ECORE_IWARP_AFFIN_HWFN(dev) : \ 923 ECORE_FIR_AFFIN_HWFN(dev)) 924 /* Macro for getting the index (0/1) of the engine-affinitized hwfn */ 925 #define ECORE_AFFIN_HWFN_IDX(dev) \ 926 (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1) 927 928 /* SRIOV */ 929 struct ecore_hw_sriov_info *p_iov_info; 930 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info) 931 struct ecore_tunnel_info tunnel; 932 bool b_is_vf; 933 bool b_dont_override_vf_msix; 934 935 u32 drv_type; 936 937 u32 rdma_max_sge; 938 u32 rdma_max_inline; 939 u32 rdma_max_srq_sge; 940 u8 ilt_page_size; 941 942 struct ecore_eth_stats *reset_stats; 943 struct ecore_fw_data *fw_data; 944 945 u32 mcp_nvm_resp; 946 947 /* Recovery */ 948 bool recov_in_prog; 949 950 /* Indicates whether should prevent attentions from being reasserted */ 951 bool attn_clr_en; 952 953 /* Indicates whether allowing the MFW to collect a crash dump */ 954 bool allow_mdump; 955 956 /* Indicates if the reg_fifo is checked after any register access */ 957 bool chk_reg_fifo; 958 959 #ifndef ASIC_ONLY 960 bool b_is_emul_full; 961 #endif 962 /* LLH info */ 963 u8 ppfid_bitmap; 964 struct ecore_llh_info *p_llh_info; 965 }; 966 967 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \ 968 : MAX_NUM_VFS_K2) 969 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 970 : MAX_NUM_L2_QUEUES_K2) 971 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 972 : MAX_NUM_PORTS_K2) 973 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 974 : MAX_SB_PER_PATH_K2) 975 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \ 976 : MAX_NUM_PFS_K2) 977 978 #ifndef LINUX_REMOVE 979 #define CRC8_TABLE_SIZE 256 980 #endif 981 982 /** 983 * @brief ecore_concrete_to_sw_fid - get the sw function id from 984 * the concrete value. 985 * 986 * @param concrete_fid 987 * 988 * @return OSAL_INLINE u8 989 */ 990 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid) 991 { 992 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 993 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 994 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID); 995 u8 sw_fid; 996 997 if (vf_valid) 998 sw_fid = vfid + MAX_NUM_PFS; 999 else 1000 sw_fid = pfid; 1001 1002 return sw_fid; 1003 } 1004 1005 #define PKT_LB_TC 9 1006 #define MAX_NUM_VOQS_E4 20 1007 1008 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate); 1009 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, 1010 struct ecore_ptt *p_ptt, 1011 u32 min_pf_rate); 1012 1013 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw); 1014 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw); 1015 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); 1016 int ecore_device_num_engines(struct ecore_dev *p_dev); 1017 int ecore_device_num_ports(struct ecore_dev *p_dev); 1018 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb, 1019 u8 *mac); 1020 1021 /* Flags for indication of required queues */ 1022 #define PQ_FLAGS_RLS (1 << 0) 1023 #define PQ_FLAGS_MCOS (1 << 1) 1024 #define PQ_FLAGS_LB (1 << 2) 1025 #define PQ_FLAGS_OOO (1 << 3) 1026 #define PQ_FLAGS_ACK (1 << 4) 1027 #define PQ_FLAGS_OFLD (1 << 5) 1028 #define PQ_FLAGS_VFS (1 << 6) 1029 #define PQ_FLAGS_LLT (1 << 7) 1030 1031 /* physical queue index for cm context intialization */ 1032 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags); 1033 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc); 1034 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf); 1035 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid); 1036 1037 const char *ecore_hw_get_resc_name(enum ecore_resources res_id); 1038 1039 /* doorbell recovery mechanism */ 1040 void ecore_db_recovery_dp(struct ecore_hwfn *p_hwfn); 1041 void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn, 1042 enum ecore_db_rec_exec db_exec); 1043 1044 /* amount of resources used in qm init */ 1045 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn); 1046 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn); 1047 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn); 1048 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn); 1049 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn); 1050 1051 #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \ 1052 ecore_device_num_ports((_p_hwfn)->p_dev)) 1053 1054 /* The PFID<->PPFID calculation is based on the relative index of a PF on its 1055 * port. In BB there is a bug in the LLH in which the PPFID is actually engine 1056 * based, and thus it equals the PFID. 1057 */ 1058 #define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \ 1059 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \ 1060 (abs_ppfid) : \ 1061 (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \ 1062 MFW_PORT(_p_hwfn)) 1063 #define ECORE_PPFID_BY_PFID(_p_hwfn) \ 1064 (ECORE_IS_BB((_p_hwfn)->p_dev) ? \ 1065 (_p_hwfn)->rel_pf_id : \ 1066 (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine) 1067 1068 enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn, 1069 struct ecore_ptt *p_ptt, u32 addr, 1070 u32 val); 1071 1072 /* Utility functions for dumping the content of the NIG LLH filters */ 1073 enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid); 1074 enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev); 1075 1076 #endif /* __ECORE_H */ 1077