1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __ECORE_H 32 #define __ECORE_H 33 34 #include "ecore_hsi_common.h" 35 #include "ecore_hsi_debug_tools.h" 36 #include "ecore_hsi_init_func.h" 37 #include "ecore_hsi_init_tool.h" 38 #include "ecore_proto_if.h" 39 #include "mcp_public.h" 40 41 #define ECORE_MAJOR_VERSION 8 42 #define ECORE_MINOR_VERSION 18 43 #define ECORE_REVISION_VERSION 13 44 #define ECORE_ENGINEERING_VERSION 0 45 46 #define ECORE_VERSION \ 47 ((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \ 48 (ECORE_REVISION_VERSION << 8) | ECORE_ENGINEERING_VERSION) 49 50 #define STORM_FW_VERSION \ 51 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 52 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 53 54 #define MAX_HWFNS_PER_DEVICE 2 55 #define NAME_SIZE 16 56 #define ARRAY_DECL static const 57 #define ECORE_WFQ_UNIT 100 58 59 /* Constants */ 60 #define ECORE_WID_SIZE (1024) 61 62 /* Configurable */ 63 #define ECORE_PF_DEMS_SIZE (4) 64 65 /* cau states */ 66 enum ecore_coalescing_mode { 67 ECORE_COAL_MODE_DISABLE, 68 ECORE_COAL_MODE_ENABLE 69 }; 70 71 enum ecore_nvm_cmd { 72 ECORE_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, 73 ECORE_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, 74 ECORE_NVM_READ_NVRAM = DRV_MSG_CODE_NVM_READ_NVRAM, 75 ECORE_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, 76 ECORE_NVM_DEL_FILE = DRV_MSG_CODE_NVM_DEL_FILE, 77 ECORE_EXT_PHY_FW_UPGRADE = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE, 78 ECORE_NVM_SET_SECURE_MODE = DRV_MSG_CODE_SET_SECURE_MODE, 79 ECORE_PHY_RAW_READ = DRV_MSG_CODE_PHY_RAW_READ, 80 ECORE_PHY_RAW_WRITE = DRV_MSG_CODE_PHY_RAW_WRITE, 81 ECORE_PHY_CORE_READ = DRV_MSG_CODE_PHY_CORE_READ, 82 ECORE_PHY_CORE_WRITE = DRV_MSG_CODE_PHY_CORE_WRITE, 83 ECORE_GET_MCP_NVM_RESP = 0xFFFFFF00 84 }; 85 86 #if !defined(CONFIG_ECORE_L2) && !defined(CONFIG_ECORE_ROCE) && \ 87 !defined(CONFIG_ECORE_FCOE) && !defined(CONFIG_ECORE_ISCSI) 88 #define CONFIG_ECORE_L2 89 #define CONFIG_ECORE_SRIOV 90 #define CONFIG_ECORE_ROCE 91 #define CONFIG_ECORE_IWARP 92 #define CONFIG_ECORE_FCOE 93 #define CONFIG_ECORE_ISCSI 94 #define CONFIG_ECORE_LL2 95 #endif 96 97 /* helpers */ 98 #define MASK_FIELD(_name, _value) \ 99 ((_value) &= (_name##_MASK)) 100 101 #define FIELD_VALUE(_name, _value) \ 102 ((_value & _name##_MASK) << _name##_SHIFT) 103 104 #define SET_FIELD(value, name, flag) \ 105 do { \ 106 (value) &= ~(name##_MASK << name##_SHIFT); \ 107 (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\ 108 } while (0) 109 110 #define GET_FIELD(value, name) \ 111 (((value) >> (name##_SHIFT)) & name##_MASK) 112 113 #define ECORE_MFW_GET_FIELD(name, field) \ 114 (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 115 116 #define ECORE_MFW_SET_FIELD(name, field, value) \ 117 do { \ 118 (name) &= ~((field ## _MASK) << (field ## _SHIFT)); \ 119 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK)); \ 120 } while (0) 121 122 static OSAL_INLINE u32 DB_ADDR(u32 cid, u32 DEMS) 123 { 124 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 125 (cid * ECORE_PF_DEMS_SIZE); 126 127 return db_addr; 128 } 129 130 static OSAL_INLINE u32 DB_ADDR_VF(u32 cid, u32 DEMS) 131 { 132 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 133 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 134 135 return db_addr; 136 } 137 138 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 139 ((sizeof(type_name) + (u32)(1<<(p_hwfn->p_dev->cache_shift))-1) & \ 140 ~((1<<(p_hwfn->p_dev->cache_shift))-1)) 141 142 #ifndef U64_HI 143 #define U64_HI(val) ((u32)(((u64)(val)) >> 32)) 144 #endif 145 146 #ifndef U64_LO 147 #define U64_LO(val) ((u32)(((u64)(val)) & 0xffffffff)) 148 #endif 149 150 #ifndef UEFI 151 /* Debug print definitions */ 152 #define DP_ERR(p_dev, fmt, ...) \ 153 do { \ 154 PRINT_ERR((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 155 __func__, __LINE__, \ 156 (p_dev)->name ? (p_dev)->name : "", \ 157 ##__VA_ARGS__); \ 158 } while (0) 159 160 #define DP_NOTICE(p_dev, is_assert, fmt, ...) \ 161 do { \ 162 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_NOTICE)) { \ 163 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 164 __func__, __LINE__, \ 165 (p_dev)->name ? (p_dev)->name : "", \ 166 ##__VA_ARGS__); \ 167 OSAL_ASSERT(!is_assert); \ 168 } \ 169 } while (0) 170 171 #define DP_INFO(p_dev, fmt, ...) \ 172 do { \ 173 if (OSAL_UNLIKELY((p_dev)->dp_level <= ECORE_LEVEL_INFO)) { \ 174 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 175 __func__, __LINE__, \ 176 (p_dev)->name ? (p_dev)->name : "", \ 177 ##__VA_ARGS__); \ 178 } \ 179 } while (0) 180 181 #define DP_VERBOSE(p_dev, module, fmt, ...) \ 182 do { \ 183 if (OSAL_UNLIKELY(((p_dev)->dp_level <= ECORE_LEVEL_VERBOSE) && \ 184 ((p_dev)->dp_module & module))) { \ 185 PRINT((p_dev)->dp_ctx, "[%s:%d(%s)]" fmt, \ 186 __func__, __LINE__, \ 187 (p_dev)->name ? (p_dev)->name : "", \ 188 ##__VA_ARGS__); \ 189 } \ 190 } while (0) 191 #endif 192 193 enum DP_LEVEL { 194 ECORE_LEVEL_VERBOSE = 0x0, 195 ECORE_LEVEL_INFO = 0x1, 196 ECORE_LEVEL_NOTICE = 0x2, 197 ECORE_LEVEL_ERR = 0x3, 198 }; 199 200 #define ECORE_LOG_LEVEL_SHIFT (30) 201 #define ECORE_LOG_VERBOSE_MASK (0x3fffffff) 202 #define ECORE_LOG_INFO_MASK (0x40000000) 203 #define ECORE_LOG_NOTICE_MASK (0x80000000) 204 205 enum DP_MODULE { 206 ECORE_MSG_DRV = 0x0001, 207 ECORE_MSG_PROBE = 0x0002, 208 ECORE_MSG_LINK = 0x0004, 209 ECORE_MSG_TIMER = 0x0008, 210 ECORE_MSG_IFDOWN = 0x0010, 211 ECORE_MSG_IFUP = 0x0020, 212 ECORE_MSG_RX_ERR = 0x0040, 213 ECORE_MSG_TX_ERR = 0x0080, 214 ECORE_MSG_TX_QUEUED = 0x0100, 215 ECORE_MSG_INTR = 0x0200, 216 ECORE_MSG_TX_DONE = 0x0400, 217 ECORE_MSG_RX_STATUS = 0x0800, 218 ECORE_MSG_PKTDATA = 0x1000, 219 ECORE_MSG_HW = 0x2000, 220 ECORE_MSG_WOL = 0x4000, 221 ECORE_MSG_SPQ = 0x10000, 222 ECORE_MSG_STATS = 0x20000, 223 ECORE_MSG_DCB = 0x40000, 224 ECORE_MSG_IOV = 0x80000, 225 ECORE_MSG_SP = 0x100000, 226 ECORE_MSG_STORAGE = 0x200000, 227 ECORE_MSG_OOO = 0x200000, 228 ECORE_MSG_CXT = 0x800000, 229 ECORE_MSG_LL2 = 0x1000000, 230 ECORE_MSG_ILT = 0x2000000, 231 ECORE_MSG_RDMA = 0x4000000, 232 ECORE_MSG_DEBUG = 0x8000000, 233 /* to be added...up to 0x8000000 */ 234 }; 235 236 #define for_each_hwfn(p_dev, i) for (i = 0; i < p_dev->num_hwfns; i++) 237 238 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 239 (val == (cond1) ? true1 : \ 240 (val == (cond2) ? true2 : def)) 241 242 /* forward */ 243 struct ecore_ptt_pool; 244 struct ecore_spq; 245 struct ecore_sb_info; 246 struct ecore_sb_attn_info; 247 struct ecore_cxt_mngr; 248 struct ecore_dma_mem; 249 struct ecore_sb_sp_info; 250 struct ecore_ll2_info; 251 struct ecore_l2_info; 252 struct ecore_igu_info; 253 struct ecore_mcp_info; 254 struct ecore_dcbx_info; 255 256 struct ecore_rt_data { 257 u32 *init_val; 258 bool *b_valid; 259 }; 260 261 enum ecore_tunn_mode { 262 ECORE_MODE_L2GENEVE_TUNN, 263 ECORE_MODE_IPGENEVE_TUNN, 264 ECORE_MODE_L2GRE_TUNN, 265 ECORE_MODE_IPGRE_TUNN, 266 ECORE_MODE_VXLAN_TUNN, 267 }; 268 269 enum ecore_tunn_clss { 270 ECORE_TUNN_CLSS_MAC_VLAN, 271 ECORE_TUNN_CLSS_MAC_VNI, 272 ECORE_TUNN_CLSS_INNER_MAC_VLAN, 273 ECORE_TUNN_CLSS_INNER_MAC_VNI, 274 ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 275 MAX_ECORE_TUNN_CLSS, 276 }; 277 278 struct ecore_tunn_update_type { 279 bool b_update_mode; 280 bool b_mode_enabled; 281 enum ecore_tunn_clss tun_cls; 282 }; 283 284 struct ecore_tunn_update_udp_port { 285 bool b_update_port; 286 u16 port; 287 }; 288 289 struct ecore_tunnel_info { 290 struct ecore_tunn_update_type vxlan; 291 struct ecore_tunn_update_type l2_geneve; 292 struct ecore_tunn_update_type ip_geneve; 293 struct ecore_tunn_update_type l2_gre; 294 struct ecore_tunn_update_type ip_gre; 295 296 struct ecore_tunn_update_udp_port vxlan_port; 297 struct ecore_tunn_update_udp_port geneve_port; 298 299 bool b_update_rx_cls; 300 bool b_update_tx_cls; 301 }; 302 303 /* The PCI personality is not quite synonymous to protocol ID: 304 * 1. All personalities need CORE connections 305 * 2. The Ethernet personality may support also the RoCE/iWARP protocol 306 */ 307 enum ecore_pci_personality { 308 ECORE_PCI_ETH, 309 ECORE_PCI_FCOE, 310 ECORE_PCI_ISCSI, 311 ECORE_PCI_ETH_ROCE, 312 ECORE_PCI_ETH_IWARP, 313 ECORE_PCI_ETH_RDMA, 314 ECORE_PCI_DEFAULT /* default in shmem */ 315 }; 316 317 /* All VFs are symetric, all counters are PF + all VFs */ 318 struct ecore_qm_iids { 319 u32 cids; 320 u32 vf_cids; 321 u32 tids; 322 }; 323 324 #define MAX_PF_PER_PORT 8 325 326 /* HW / FW resources, output of features supported below, most information 327 * is received from MFW. 328 */ 329 enum ecore_resources { 330 ECORE_L2_QUEUE, 331 ECORE_VPORT, 332 ECORE_RSS_ENG, 333 ECORE_PQ, 334 ECORE_RL, 335 ECORE_MAC, 336 ECORE_VLAN, 337 ECORE_RDMA_CNQ_RAM, 338 ECORE_ILT, 339 ECORE_LL2_QUEUE, 340 ECORE_CMDQS_CQS, 341 ECORE_RDMA_STATS_QUEUE, 342 ECORE_BDQ, 343 344 /* This is needed only internally for matching against the IGU. 345 * In case of legacy MFW, would be set to `0'. 346 */ 347 ECORE_SB, 348 349 ECORE_MAX_RESC, 350 }; 351 352 /* Features that require resources, given as input to the resource management 353 * algorithm, the output are the resources above 354 */ 355 enum ecore_feature { 356 ECORE_PF_L2_QUE, 357 ECORE_PF_TC, 358 ECORE_VF, 359 ECORE_EXTRA_VF_QUE, 360 ECORE_VMQ, 361 ECORE_RDMA_CNQ, 362 ECORE_ISCSI_CQ, 363 ECORE_FCOE_CQ, 364 ECORE_VF_L2_QUE, 365 ECORE_MAX_FEATURES, 366 }; 367 368 enum ecore_port_mode { 369 ECORE_PORT_MODE_DE_2X40G, 370 ECORE_PORT_MODE_DE_2X50G, 371 ECORE_PORT_MODE_DE_1X100G, 372 ECORE_PORT_MODE_DE_4X10G_F, 373 ECORE_PORT_MODE_DE_4X10G_E, 374 ECORE_PORT_MODE_DE_4X20G, 375 ECORE_PORT_MODE_DE_1X40G, 376 ECORE_PORT_MODE_DE_2X25G, 377 ECORE_PORT_MODE_DE_1X25G, 378 ECORE_PORT_MODE_DE_4X25G, 379 ECORE_PORT_MODE_DE_2X10G, 380 }; 381 382 enum ecore_dev_cap { 383 ECORE_DEV_CAP_ETH, 384 ECORE_DEV_CAP_FCOE, 385 ECORE_DEV_CAP_ISCSI, 386 ECORE_DEV_CAP_ROCE, 387 ECORE_DEV_CAP_IWARP 388 }; 389 390 enum ecore_hw_err_type { 391 ECORE_HW_ERR_FAN_FAIL, 392 ECORE_HW_ERR_MFW_RESP_FAIL, 393 ECORE_HW_ERR_HW_ATTN, 394 ECORE_HW_ERR_DMAE_FAIL, 395 ECORE_HW_ERR_RAMROD_FAIL, 396 ECORE_HW_ERR_FW_ASSERT, 397 }; 398 399 enum ecore_wol_support { 400 ECORE_WOL_SUPPORT_NONE, 401 ECORE_WOL_SUPPORT_PME, 402 }; 403 404 struct ecore_hw_info { 405 /* PCI personality */ 406 enum ecore_pci_personality personality; 407 #define ECORE_IS_RDMA_PERSONALITY(dev) \ 408 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 409 (dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 410 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 411 #define ECORE_IS_ROCE_PERSONALITY(dev) \ 412 ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \ 413 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 414 #define ECORE_IS_IWARP_PERSONALITY(dev) \ 415 ((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \ 416 (dev)->hw_info.personality == ECORE_PCI_ETH_RDMA) 417 #define ECORE_IS_L2_PERSONALITY(dev) \ 418 ((dev)->hw_info.personality == ECORE_PCI_ETH || \ 419 ECORE_IS_RDMA_PERSONALITY(dev)) 420 #define ECORE_IS_FCOE_PERSONALITY(dev) \ 421 ((dev)->hw_info.personality == ECORE_PCI_FCOE) 422 #define ECORE_IS_ISCSI_PERSONALITY(dev) \ 423 ((dev)->hw_info.personality == ECORE_PCI_ISCSI) 424 425 /* Resource Allocation scheme results */ 426 u32 resc_start[ECORE_MAX_RESC]; 427 u32 resc_num[ECORE_MAX_RESC]; 428 u32 feat_num[ECORE_MAX_FEATURES]; 429 430 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 431 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 432 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 433 RESC_NUM(_p_hwfn, resc)) 434 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 435 436 /* Amount of traffic classes HW supports */ 437 u8 num_hw_tc; 438 439 /* Amount of TCs which should be active according to DCBx or upper layer driver configuration */ 440 u8 num_active_tc; 441 442 /* The traffic class used by PF for it's offloaded protocol */ 443 u8 offload_tc; 444 445 u32 concrete_fid; 446 u16 opaque_fid; 447 u16 ovlan; 448 u32 part_num[4]; 449 450 #ifndef ETH_ALEN 451 #define ETH_ALEN 6 /* @@@ TBD - define somewhere else for Windows */ 452 #endif 453 454 unsigned char hw_mac_addr[ETH_ALEN]; 455 u64 node_wwn; /* For FCoE only */ 456 u64 port_wwn; /* For FCoE only */ 457 458 u16 num_iscsi_conns; 459 u16 num_fcoe_conns; 460 461 struct ecore_igu_info *p_igu_info; 462 /* Sriov */ 463 u8 max_chains_per_vf; 464 465 u32 port_mode; 466 u32 hw_mode; 467 unsigned long device_capabilities; 468 469 /* Default DCBX mode */ 470 u8 dcbx_mode; 471 472 u16 mtu; 473 474 enum ecore_wol_support b_wol_support; 475 }; 476 477 /* maximun size of read/write commands (HW limit) */ 478 #define DMAE_MAX_RW_SIZE 0x2000 479 480 struct ecore_dmae_info { 481 /* Mutex for synchronizing access to functions */ 482 osal_mutex_t mutex; 483 484 u8 channel; 485 486 dma_addr_t completion_word_phys_addr; 487 488 /* The memory location where the DMAE writes the completion 489 * value when an operation is finished on this context. 490 */ 491 u32 *p_completion_word; 492 493 dma_addr_t intermediate_buffer_phys_addr; 494 495 /* An intermediate buffer for DMAE operations that use virtual 496 * addresses - data is DMA'd to/from this buffer and then 497 * memcpy'd to/from the virtual address 498 */ 499 u32 *p_intermediate_buffer; 500 501 dma_addr_t dmae_cmd_phys_addr; 502 struct dmae_cmd *p_dmae_cmd; 503 }; 504 505 struct ecore_wfq_data { 506 u32 default_min_speed; /* When wfq feature is not configured */ 507 u32 min_speed; /* when feature is configured for any 1 vport */ 508 bool configured; 509 }; 510 511 struct ecore_qm_info { 512 struct init_qm_pq_params *qm_pq_params; 513 struct init_qm_vport_params *qm_vport_params; 514 struct init_qm_port_params *qm_port_params; 515 u16 start_pq; 516 u8 start_vport; 517 u16 pure_lb_pq; 518 u16 offload_pq; 519 u16 low_latency_pq; 520 u16 pure_ack_pq; 521 u16 ooo_pq; 522 u16 first_vf_pq; 523 u16 first_mcos_pq; 524 u16 first_rl_pq; 525 u16 num_pqs; 526 u16 num_vf_pqs; 527 u8 num_vports; 528 u8 max_phys_tcs_per_port; 529 u8 ooo_tc; 530 bool pf_rl_en; 531 bool pf_wfq_en; 532 bool vport_rl_en; 533 bool vport_wfq_en; 534 u8 pf_wfq; 535 u32 pf_rl; 536 struct ecore_wfq_data *wfq_data; 537 u8 num_pf_rls; 538 }; 539 540 struct storm_stats { 541 u32 address; 542 u32 len; 543 }; 544 545 struct ecore_fw_data { 546 #ifdef CONFIG_ECORE_BINARY_FW 547 struct fw_ver_info *fw_ver_info; 548 #endif 549 const u8 *modes_tree_buf; 550 union init_op *init_ops; 551 const u32 *arr_data; 552 u32 init_ops_size; 553 }; 554 555 struct ecore_hwfn { 556 struct ecore_dev *p_dev; 557 u8 my_id; /* ID inside the PF */ 558 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 559 u8 rel_pf_id; /* Relative to engine*/ 560 u8 abs_pf_id; 561 #define ECORE_PATH_ID(_p_hwfn) \ 562 (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 563 u8 port_id; 564 bool b_active; 565 566 u32 dp_module; 567 u8 dp_level; 568 char name[NAME_SIZE]; 569 void *dp_ctx; 570 571 bool first_on_engine; 572 bool hw_init_done; 573 574 u8 num_funcs_on_engine; 575 u8 enabled_func_idx; 576 577 /* BAR access */ 578 void OSAL_IOMEM *regview; 579 void OSAL_IOMEM *doorbells; 580 u64 db_phys_addr; 581 unsigned long db_size; 582 583 /* PTT pool */ 584 struct ecore_ptt_pool *p_ptt_pool; 585 586 /* HW info */ 587 struct ecore_hw_info hw_info; 588 589 /* rt_array (for init-tool) */ 590 struct ecore_rt_data rt_data; 591 592 /* SPQ */ 593 struct ecore_spq *p_spq; 594 595 /* EQ */ 596 struct ecore_eq *p_eq; 597 598 /* Consolidate Q*/ 599 struct ecore_consq *p_consq; 600 601 /* Slow-Path definitions */ 602 osal_dpc_t sp_dpc; 603 bool b_sp_dpc_enabled; 604 605 struct ecore_ptt *p_main_ptt; 606 struct ecore_ptt *p_dpc_ptt; 607 608 struct ecore_sb_sp_info *p_sp_sb; 609 struct ecore_sb_attn_info *p_sb_attn; 610 611 /* Protocol related */ 612 bool using_ll2; 613 struct ecore_ll2_info *p_ll2_info; 614 struct ecore_ooo_info *p_ooo_info; 615 struct ecore_iscsi_info *p_iscsi_info; 616 struct ecore_fcoe_info *p_fcoe_info; 617 struct ecore_rdma_info *p_rdma_info; 618 struct ecore_pf_params pf_params; 619 620 bool b_rdma_enabled_in_prs; 621 u32 rdma_prs_search_reg; 622 623 struct ecore_cxt_mngr *p_cxt_mngr; 624 625 /* Flag indicating whether interrupts are enabled or not*/ 626 bool b_int_enabled; 627 bool b_int_requested; 628 629 /* True if the driver requests for the link */ 630 bool b_drv_link_init; 631 632 struct ecore_vf_iov *vf_iov_info; 633 struct ecore_pf_iov *pf_iov_info; 634 struct ecore_mcp_info *mcp_info; 635 struct ecore_dcbx_info *p_dcbx_info; 636 637 struct ecore_dmae_info dmae_info; 638 639 /* QM init */ 640 struct ecore_qm_info qm_info; 641 642 /* Buffer for unzipping firmware data */ 643 #ifdef CONFIG_ECORE_ZIPPED_FW 644 void *unzip_buf; 645 #endif 646 647 struct dbg_tools_data dbg_info; 648 649 /* PWM region specific data */ 650 u16 wid_count; 651 u32 dpi_size; 652 u32 dpi_count; 653 u32 dpi_start_offset; /* this is used to 654 * calculate th 655 * doorbell address 656 */ 657 658 /* If one of the following is set then EDPM shouldn't be used */ 659 u8 dcbx_no_edpm; 660 u8 db_bar_no_edpm; 661 662 /* L2-related */ 663 struct ecore_l2_info *p_l2_info; 664 }; 665 666 enum ecore_mf_mode { 667 ECORE_MF_DEFAULT, 668 ECORE_MF_OVLAN, 669 ECORE_MF_NPAR, 670 }; 671 672 enum ecore_dev_type { 673 ECORE_DEV_TYPE_BB, 674 ECORE_DEV_TYPE_AH, 675 ECORE_DEV_TYPE_E5, 676 }; 677 678 struct ecore_dev { 679 u32 dp_module; 680 u8 dp_level; 681 char name[NAME_SIZE]; 682 void *dp_ctx; 683 684 enum ecore_dev_type type; 685 /* Translate type/revision combo into the proper conditions */ 686 #define ECORE_IS_BB(dev) ((dev)->type == ECORE_DEV_TYPE_BB) 687 #define ECORE_IS_BB_A0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_A0(dev)) 688 #ifndef ASIC_ONLY 689 #define ECORE_IS_BB_B0(dev) ((ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) || \ 690 (CHIP_REV_IS_TEDIBEAR(dev))) 691 #else 692 #define ECORE_IS_BB_B0(dev) (ECORE_IS_BB(dev) && CHIP_REV_IS_B0(dev)) 693 #endif 694 #define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH) 695 #define ECORE_IS_K2(dev) ECORE_IS_AH(dev) 696 697 #define ECORE_IS_E5(dev) false 698 699 #define ECORE_E5_MISSING_CODE OSAL_BUILD_BUG_ON(false) 700 701 u16 vendor_id; 702 u16 device_id; 703 #define ECORE_DEV_ID_MASK 0xff00 704 #define ECORE_DEV_ID_MASK_BB 0x1600 705 #define ECORE_DEV_ID_MASK_AH 0x8000 706 707 u16 chip_num; 708 #define CHIP_NUM_MASK 0xffff 709 #define CHIP_NUM_SHIFT 16 710 711 u16 chip_rev; 712 #define CHIP_REV_MASK 0xf 713 #define CHIP_REV_SHIFT 12 714 #ifndef ASIC_ONLY 715 #define CHIP_REV_IS_TEDIBEAR(_p_dev) ((_p_dev)->chip_rev == 0x5) 716 #define CHIP_REV_IS_EMUL_A0(_p_dev) ((_p_dev)->chip_rev == 0xe) 717 #define CHIP_REV_IS_EMUL_B0(_p_dev) ((_p_dev)->chip_rev == 0xc) 718 #define CHIP_REV_IS_EMUL(_p_dev) (CHIP_REV_IS_EMUL_A0(_p_dev) || \ 719 CHIP_REV_IS_EMUL_B0(_p_dev)) 720 #define CHIP_REV_IS_FPGA_A0(_p_dev) ((_p_dev)->chip_rev == 0xf) 721 #define CHIP_REV_IS_FPGA_B0(_p_dev) ((_p_dev)->chip_rev == 0xd) 722 #define CHIP_REV_IS_FPGA(_p_dev) (CHIP_REV_IS_FPGA_A0(_p_dev) || \ 723 CHIP_REV_IS_FPGA_B0(_p_dev)) 724 #define CHIP_REV_IS_SLOW(_p_dev) \ 725 (CHIP_REV_IS_EMUL(_p_dev) || CHIP_REV_IS_FPGA(_p_dev)) 726 #define CHIP_REV_IS_A0(_p_dev) \ 727 (CHIP_REV_IS_EMUL_A0(_p_dev) || \ 728 CHIP_REV_IS_FPGA_A0(_p_dev) || \ 729 !(_p_dev)->chip_rev) 730 #define CHIP_REV_IS_B0(_p_dev) \ 731 (CHIP_REV_IS_EMUL_B0(_p_dev) || \ 732 CHIP_REV_IS_FPGA_B0(_p_dev) || \ 733 (_p_dev)->chip_rev == 1) 734 #define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev) 735 #else 736 #define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev) 737 #define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1) 738 #endif 739 740 u16 chip_metal; 741 #define CHIP_METAL_MASK 0xff 742 #define CHIP_METAL_SHIFT 4 743 744 u16 chip_bond_id; 745 #define CHIP_BOND_ID_MASK 0xf 746 #define CHIP_BOND_ID_SHIFT 0 747 748 u8 num_engines; 749 u8 num_ports_in_engines; 750 u8 num_funcs_in_port; 751 752 u8 path_id; 753 enum ecore_mf_mode mf_mode; 754 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT) 755 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR) 756 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN) 757 758 int pcie_width; 759 int pcie_speed; 760 761 /* Add MF related configuration */ 762 u8 mcp_rev; 763 u8 boot_mode; 764 765 /* WoL related configurations */ 766 u8 wol_config; 767 u8 wol_mac[ETH_ALEN]; 768 769 u32 int_mode; 770 enum ecore_coalescing_mode int_coalescing_mode; 771 u16 rx_coalesce_usecs; 772 u16 tx_coalesce_usecs; 773 774 /* Start Bar offset of first hwfn */ 775 void OSAL_IOMEM *regview; 776 void OSAL_IOMEM *doorbells; 777 u64 db_phys_addr; 778 unsigned long db_size; 779 780 /* PCI */ 781 u8 cache_shift; 782 783 /* Init */ 784 const struct iro *iro_arr; 785 #define IRO (p_hwfn->p_dev->iro_arr) 786 787 /* HW functions */ 788 u8 num_hwfns; 789 struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 790 791 /* SRIOV */ 792 struct ecore_hw_sriov_info *p_iov_info; 793 #define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info) 794 #ifdef CONFIG_ECORE_SW_CHANNEL 795 bool b_hw_channel; 796 #endif 797 struct ecore_tunnel_info tunnel; 798 bool b_is_vf; 799 bool b_dont_override_vf_msix; 800 801 u32 drv_type; 802 803 u32 rdma_max_sge; 804 u32 rdma_max_inline; 805 u32 rdma_max_srq_sge; 806 807 struct ecore_eth_stats *reset_stats; 808 struct ecore_fw_data *fw_data; 809 810 u32 mcp_nvm_resp; 811 812 /* Recovery */ 813 bool recov_in_prog; 814 815 /* Indicates whether should prevent attentions from being reasserted */ 816 bool attn_clr_en; 817 818 /* Indicates whether allowing the MFW to collect a crash dump */ 819 bool allow_mdump; 820 821 /* Indicates if the reg_fifo is checked after any register access */ 822 bool chk_reg_fifo; 823 824 #ifndef ASIC_ONLY 825 bool b_is_emul_full; 826 #endif 827 }; 828 829 #define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \ 830 : MAX_NUM_VFS_K2) 831 #define NUM_OF_L2_QUEUES(dev) (ECORE_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 832 : MAX_NUM_L2_QUEUES_K2) 833 #define NUM_OF_PORTS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 834 : MAX_NUM_PORTS_K2) 835 #define NUM_OF_SBS(dev) (ECORE_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 836 : MAX_SB_PER_PATH_K2) 837 #define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \ 838 : MAX_NUM_PFS_K2) 839 /** 840 * @brief ecore_concrete_to_sw_fid - get the sw function id from 841 * the concrete value. 842 * 843 * @param concrete_fid 844 * 845 * @return OSAL_INLINE u8 846 */ 847 static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev, 848 u32 concrete_fid) 849 { 850 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 851 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 852 u8 vf_valid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID); 853 u8 sw_fid; 854 855 if (vf_valid) 856 sw_fid = vfid + MAX_NUM_PFS; 857 else 858 sw_fid = pfid; 859 860 return sw_fid; 861 } 862 863 #define PURE_LB_TC 8 864 #define PKT_LB_TC 9 865 866 int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate); 867 void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev, 868 struct ecore_ptt *p_ptt, 869 u32 min_pf_rate); 870 871 int ecore_configure_pf_max_bandwidth(struct ecore_dev *p_dev, u8 max_bw); 872 int ecore_configure_pf_min_bandwidth(struct ecore_dev *p_dev, u8 min_bw); 873 void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt); 874 int ecore_device_num_engines(struct ecore_dev *p_dev); 875 int ecore_device_num_ports(struct ecore_dev *p_dev); 876 void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb, 877 u8 *mac); 878 879 /* Flags for indication of required queues */ 880 #define PQ_FLAGS_RLS (1 << 0) 881 #define PQ_FLAGS_MCOS (1 << 1) 882 #define PQ_FLAGS_LB (1 << 2) 883 #define PQ_FLAGS_OOO (1 << 3) 884 #define PQ_FLAGS_ACK (1 << 4) 885 #define PQ_FLAGS_OFLD (1 << 5) 886 #define PQ_FLAGS_VFS (1 << 6) 887 #define PQ_FLAGS_LLT (1 << 7) 888 889 /* physical queue index for cm context intialization */ 890 u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags); 891 u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc); 892 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf); 893 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid); 894 895 /* amount of resources used in qm init */ 896 u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn); 897 u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn); 898 u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn); 899 u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn); 900 u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn); 901 902 #define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0]) 903 904 const char *ecore_hw_get_resc_name(enum ecore_resources res_id); 905 906 #endif /* __ECORE_H */ 907