1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __COMMON_HSI__ 32 #define __COMMON_HSI__ 33 /********************************/ 34 /* PROTOCOL COMMON FW CONSTANTS */ 35 /********************************/ 36 37 /* Temporarily here should be added to HSI automatically by resource allocation tool.*/ 38 #define T_TEST_AGG_INT_TEMP 6 39 #define M_TEST_AGG_INT_TEMP 8 40 #define U_TEST_AGG_INT_TEMP 6 41 #define X_TEST_AGG_INT_TEMP 14 42 #define Y_TEST_AGG_INT_TEMP 4 43 #define P_TEST_AGG_INT_TEMP 4 44 45 #define X_FINAL_CLEANUP_AGG_INT 1 46 47 #define EVENT_RING_PAGE_SIZE_BYTES 4096 48 49 #define NUM_OF_GLOBAL_QUEUES 128 50 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 51 52 #define ISCSI_CDU_TASK_SEG_TYPE 0 53 #define FCOE_CDU_TASK_SEG_TYPE 0 54 #define RDMA_CDU_TASK_SEG_TYPE 1 55 56 #define FW_ASSERT_GENERAL_ATTN_IDX 32 57 58 #define MAX_PINNED_CCFC 32 59 60 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 61 62 /* Queue Zone sizes in bytes */ 63 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/ 64 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX producer of VFs in backward compatibility mode.*/ 65 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/ 66 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ 67 #define YSTORM_QZONE_SIZE 0 68 #define PSTORM_QZONE_SIZE 0 69 70 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 /*Log of mstorm default VF zone size.*/ 71 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 /*Maximum number of RX queues that can be allocated to VF by default*/ 72 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone size. Up to 96 VF supported in this mode*/ 73 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. Up to 48 VF supported in this mode*/ 74 75 76 /********************************/ 77 /* CORE (LIGHT L2) FW CONSTANTS */ 78 /********************************/ 79 80 #define CORE_LL2_MAX_RAMROD_PER_CON 8 81 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 82 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 83 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 84 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 85 86 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 87 88 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 89 90 /* 91 * Usually LL2 queues are opened in pairs � TX-RX. 92 * There is a hard restriction on number of RX queues (limited by Tstorm RAM) and TX counters (Pstorm RAM). 93 * Number of TX queues is almost unlimited. 94 * The constants are different so as to allow asymmetric LL2 connections 95 */ 96 97 #define MAX_NUM_LL2_RX_QUEUES 48 98 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 99 100 101 /////////////////////////////////////////////////////////////////////////////////////////////////// 102 // Include firmware verison number only- do not add constants here to avoid redundunt compilations 103 /////////////////////////////////////////////////////////////////////////////////////////////////// 104 105 106 #define FW_MAJOR_VERSION 8 107 #define FW_MINOR_VERSION 33 108 #define FW_REVISION_VERSION 7 109 #define FW_ENGINEERING_VERSION 0 110 111 /***********************/ 112 /* COMMON HW CONSTANTS */ 113 /***********************/ 114 115 /* PCI functions */ 116 #define MAX_NUM_PORTS_BB (2) 117 #define MAX_NUM_PORTS_K2 (4) 118 #define MAX_NUM_PORTS_E5 (4) 119 #define MAX_NUM_PORTS (MAX_NUM_PORTS_E5) 120 121 #define MAX_NUM_PFS_BB (8) 122 #define MAX_NUM_PFS_K2 (16) 123 #define MAX_NUM_PFS_E5 (16) 124 #define MAX_NUM_PFS (MAX_NUM_PFS_E5) 125 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 126 127 #define MAX_NUM_VFS_BB (120) 128 #define MAX_NUM_VFS_K2 (192) 129 #define MAX_NUM_VFS_E4 (MAX_NUM_VFS_K2) 130 #define MAX_NUM_VFS_E5 (240) 131 #define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_E5) 132 133 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 134 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) 135 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS_E4) 136 137 /* in both BB and K2, the VF number starts from 16. so for arrays containing all */ 138 /* possible PFs and VFs - we need a constant for this size */ 139 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 140 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 141 #define MAX_FUNCTION_NUMBER_E4 (MAX_NUM_PFS + MAX_NUM_VFS_E4) 142 #define MAX_FUNCTION_NUMBER_E5 (MAX_NUM_PFS + MAX_NUM_VFS_E5) 143 #define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_E5) 144 145 #define MAX_NUM_VPORTS_K2 (208) 146 #define MAX_NUM_VPORTS_BB (160) 147 #define MAX_NUM_VPORTS_E4 (MAX_NUM_VPORTS_K2) 148 #define MAX_NUM_VPORTS_E5 (256) 149 #define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_E5) 150 151 #define MAX_NUM_L2_QUEUES_BB (256) 152 #define MAX_NUM_L2_QUEUES_K2 (320) 153 #define MAX_NUM_L2_QUEUES_E5 (320) /* TODO_E5_VITALY - fix to 512 */ 154 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_E5) 155 156 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 157 #define NUM_PHYS_TCS_4PORT_K2 4 158 #define NUM_PHYS_TCS_4PORT_TX_E5 6 159 #define NUM_PHYS_TCS_4PORT_RX_E5 4 160 #define NUM_OF_PHYS_TCS 8 161 #define PURE_LB_TC NUM_OF_PHYS_TCS 162 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 163 #define NUM_TCS_4PORT_TX_E5 (NUM_PHYS_TCS_4PORT_TX_E5 + 1) 164 #define NUM_TCS_4PORT_RX_E5 (NUM_PHYS_TCS_4PORT_RX_E5 + 1) 165 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 166 167 /* CIDs */ 168 #define NUM_OF_CONNECTION_TYPES_E4 (8) 169 #define NUM_OF_CONNECTION_TYPES_E5 (16) 170 #define NUM_OF_TASK_TYPES (8) 171 #define NUM_OF_LCIDS (320) 172 #define NUM_OF_LTIDS (320) 173 174 /* Global PXP windows (GTT) */ 175 #define NUM_OF_GTT 19 176 #define GTT_DWORD_SIZE_BITS 10 177 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 178 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) 179 180 /* Tools Version */ 181 #define TOOLS_VERSION 10 182 /*****************/ 183 /* CDU CONSTANTS */ 184 /*****************/ 185 186 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 187 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 188 189 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 190 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 191 192 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 193 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 194 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 195 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 196 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 197 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 198 199 200 /*****************/ 201 /* DQ CONSTANTS */ 202 /*****************/ 203 204 /* DEMS */ 205 #define DQ_DEMS_LEGACY 0 206 #define DQ_DEMS_TOE_MORE_TO_SEND 3 207 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 208 #define DQ_DEMS_ROCE_CQ_CONS 7 209 210 /* XCM agg val selection (HW) */ 211 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 212 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 213 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 214 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 215 #define DQ_XCM_AGG_VAL_SEL_REG3 4 216 #define DQ_XCM_AGG_VAL_SEL_REG4 5 217 #define DQ_XCM_AGG_VAL_SEL_REG5 6 218 #define DQ_XCM_AGG_VAL_SEL_REG6 7 219 220 /* XCM agg val selection (FW) */ 221 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 222 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 223 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 224 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 225 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 226 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 227 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 228 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 229 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 230 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 231 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 232 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 233 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 234 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 235 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 236 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 237 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 238 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 239 240 /* UCM agg val selection (HW) */ 241 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 242 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 243 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 244 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 245 #define DQ_UCM_AGG_VAL_SEL_REG0 4 246 #define DQ_UCM_AGG_VAL_SEL_REG1 5 247 #define DQ_UCM_AGG_VAL_SEL_REG2 6 248 #define DQ_UCM_AGG_VAL_SEL_REG3 7 249 250 /* UCM agg val selection (FW) */ 251 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 252 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 253 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 254 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 255 256 /* TCM agg val selection (HW) */ 257 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 258 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 259 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 260 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 261 #define DQ_TCM_AGG_VAL_SEL_REG1 4 262 #define DQ_TCM_AGG_VAL_SEL_REG2 5 263 #define DQ_TCM_AGG_VAL_SEL_REG6 6 264 #define DQ_TCM_AGG_VAL_SEL_REG9 7 265 266 /* TCM agg val selection (FW) */ 267 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 268 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 269 270 /* XCM agg counter flag selection (HW) */ 271 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 272 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 273 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 274 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 275 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 276 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 277 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 278 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 279 280 /* XCM agg counter flag selection (FW) */ 281 #define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 282 #define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 283 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 284 #define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 285 #define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 286 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 287 #define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 288 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 289 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 290 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 291 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 292 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 293 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 294 295 /* UCM agg counter flag selection (HW) */ 296 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 297 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 298 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 299 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 300 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 301 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 302 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 303 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 304 305 /* UCM agg counter flag selection (FW) */ 306 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 307 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 308 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 309 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 310 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) 311 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 312 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 313 314 /* TCM agg counter flag selection (HW) */ 315 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 316 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 317 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 318 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 319 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 320 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 321 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 322 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 323 324 /* TCM agg counter flag selection (FW) */ 325 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 326 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2) 327 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 328 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 329 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 330 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 331 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 332 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 333 334 /* PWM address mapping */ 335 #define DQ_PWM_OFFSET_DPM_BASE 0x0 336 #define DQ_PWM_OFFSET_DPM_END 0x27 337 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 338 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 339 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 340 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 341 #define DQ_PWM_OFFSET_UCM16_4 0x50 342 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 343 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 344 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 345 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 346 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 347 348 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 349 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 350 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 351 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 352 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 353 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 354 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 355 356 #define DQ_REGION_SHIFT (12) 357 358 /* DPM */ 359 #define DQ_DPM_WQE_BUFF_SIZE (320) 360 361 // Conn type ranges 362 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 363 364 /*****************/ 365 /* QM CONSTANTS */ 366 /*****************/ 367 368 /* number of TX queues in the QM */ 369 #define MAX_QM_TX_QUEUES_K2 512 370 #define MAX_QM_TX_QUEUES_BB 448 371 #define MAX_QM_TX_QUEUES_E5 MAX_QM_TX_QUEUES_K2 372 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 373 374 /* number of Other queues in the QM */ 375 #define MAX_QM_OTHER_QUEUES_BB 64 376 #define MAX_QM_OTHER_QUEUES_K2 128 377 #define MAX_QM_OTHER_QUEUES_E5 MAX_QM_OTHER_QUEUES_K2 378 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 379 380 /* number of queues in a PF queue group */ 381 #define QM_PF_QUEUE_GROUP_SIZE 8 382 383 /* the size of a single queue element in bytes */ 384 #define QM_PQ_ELEMENT_SIZE 4 385 386 /* base number of Tx PQs in the CM PQ representation. 387 should be used when storing PQ IDs in CM PQ registers and context */ 388 #define CM_TX_PQ_BASE 0x200 389 390 /* number of global Vport/QCN rate limiters */ 391 #define MAX_QM_GLOBAL_RLS 256 392 393 /* QM registers data */ 394 #define QM_LINE_CRD_REG_WIDTH 16 395 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 396 #define QM_BYTE_CRD_REG_WIDTH 24 397 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 398 #define QM_WFQ_CRD_REG_WIDTH 32 399 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) 400 #define QM_RL_CRD_REG_WIDTH 32 401 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) 402 403 /*****************/ 404 /* CAU CONSTANTS */ 405 /*****************/ 406 407 #define CAU_FSM_ETH_RX 0 408 #define CAU_FSM_ETH_TX 1 409 410 /* Number of Protocol Indices per Status Block */ 411 #define PIS_PER_SB_E4 12 412 #define PIS_PER_SB_E5 8 413 #define MAX_PIS_PER_SB OSAL_MAX_T(PIS_PER_SB_E4,PIS_PER_SB_E5) 414 415 416 #define CAU_HC_STOPPED_STATE 3 /* fsm is stopped or not valid for this sb */ 417 #define CAU_HC_DISABLE_STATE 4 /* fsm is working without interrupt coalescing for this sb*/ 418 #define CAU_HC_ENABLE_STATE 0 /* fsm is working with interrupt coalescing for this sb*/ 419 420 421 /*****************/ 422 /* IGU CONSTANTS */ 423 /*****************/ 424 425 #define MAX_SB_PER_PATH_K2 (368) 426 #define MAX_SB_PER_PATH_BB (288) 427 #define MAX_SB_PER_PATH_E5 (512) 428 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_E5 429 430 #define MAX_SB_PER_PF_MIMD 129 431 #define MAX_SB_PER_PF_SIMD 64 432 #define MAX_SB_PER_VF 64 433 434 /* Memory addresses on the BAR for the IGU Sub Block */ 435 #define IGU_MEM_BASE 0x0000 436 437 #define IGU_MEM_MSIX_BASE 0x0000 438 #define IGU_MEM_MSIX_UPPER 0x0101 439 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 440 441 #define IGU_MEM_PBA_MSIX_BASE 0x0200 442 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 443 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 444 445 #define IGU_CMD_INT_ACK_BASE 0x0400 446 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + MAX_TOT_SB_PER_PATH - 1) 447 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 448 449 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 450 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 451 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 452 453 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 454 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 455 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 456 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 457 458 #define IGU_CMD_PROD_UPD_BASE 0x0600 459 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + MAX_TOT_SB_PER_PATH - 1) 460 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 461 462 /*****************/ 463 /* PXP CONSTANTS */ 464 /*****************/ 465 466 /* Bars for Blocks */ 467 #define PXP_BAR_GRC 0 468 #define PXP_BAR_TSDM 0 469 #define PXP_BAR_USDM 0 470 #define PXP_BAR_XSDM 0 471 #define PXP_BAR_MSDM 0 472 #define PXP_BAR_YSDM 0 473 #define PXP_BAR_PSDM 0 474 #define PXP_BAR_IGU 0 475 #define PXP_BAR_DQ 1 476 477 /* PTT and GTT */ 478 #define PXP_PER_PF_ENTRY_SIZE 8 479 #define PXP_NUM_GLOBAL_WINDOWS 243 480 #define PXP_GLOBAL_ENTRY_SIZE 4 481 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 482 #define PXP_PF_WINDOW_ADMIN_START 0 483 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 484 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_LENGTH - 1) 485 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 486 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * PXP_PER_PF_ENTRY_SIZE) 487 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 488 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 489 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * PXP_GLOBAL_ENTRY_SIZE) 490 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END (PXP_PF_WINDOW_ADMIN_GLOBAL_START + PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 491 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 492 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 493 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 494 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 495 496 #define PXP_NUM_PF_WINDOWS 12 497 498 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 499 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 500 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 501 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 502 #define PXP_EXTERNAL_BAR_PF_WINDOW_END (PXP_EXTERNAL_BAR_PF_WINDOW_START + PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 503 504 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 505 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 506 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 507 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 508 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 509 510 /* PF BAR */ 511 #define PXP_BAR0_START_GRC 0x0000 512 #define PXP_BAR0_GRC_LENGTH 0x1C00000 513 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1) 514 515 #define PXP_BAR0_START_IGU 0x1C00000 516 #define PXP_BAR0_IGU_LENGTH 0x10000 517 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1) 518 519 #define PXP_BAR0_START_TSDM 0x1C80000 520 #define PXP_BAR0_SDM_LENGTH 0x40000 521 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 522 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1) 523 524 #define PXP_BAR0_START_MSDM 0x1D00000 525 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1) 526 527 #define PXP_BAR0_START_USDM 0x1D80000 528 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1) 529 530 #define PXP_BAR0_START_XSDM 0x1E00000 531 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1) 532 533 #define PXP_BAR0_START_YSDM 0x1E80000 534 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1) 535 536 #define PXP_BAR0_START_PSDM 0x1F00000 537 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1) 538 539 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 540 541 /* VF BAR */ 542 #define PXP_VF_BAR0 0 543 544 #define PXP_VF_BAR0_START_IGU 0 545 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 546 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1) 547 548 #define PXP_VF_BAR0_START_DQ 0x3000 549 #define PXP_VF_BAR0_DQ_LENGTH 0x200 550 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 551 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 552 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4) 553 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1) 554 555 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 556 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 557 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 558 559 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 560 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 561 562 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 563 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 564 565 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 566 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 567 568 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 569 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 570 571 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 572 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 573 574 #define PXP_VF_BAR0_START_GRC 0x3E00 575 #define PXP_VF_BAR0_GRC_LENGTH 0x200 576 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1) 577 578 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 579 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 580 581 #define PXP_VF_BAR0_START_IGU2 0x10000 582 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000 583 #define PXP_VF_BAR0_END_IGU2 (PXP_VF_BAR0_START_IGU2 + PXP_VF_BAR0_IGU2_LENGTH - 1) 584 585 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 586 587 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 588 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 589 590 // ILT Records 591 #define PXP_NUM_ILT_RECORDS_BB 7600 592 #define PXP_NUM_ILT_RECORDS_K2 11000 593 #define MAX_NUM_ILT_RECORDS OSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2) 594 595 #define PXP_NUM_ILT_RECORDS_E5 13664 596 597 598 // Host Interface 599 #define PXP_QUEUES_ZONE_MAX_NUM_E4 320 600 #define PXP_QUEUES_ZONE_MAX_NUM_E5 512 601 602 603 /*****************/ 604 /* PRM CONSTANTS */ 605 /*****************/ 606 #define PRM_DMA_PAD_BYTES_NUM 2 607 /*****************/ 608 /* SDMs CONSTANTS */ 609 /*****************/ 610 611 612 #define SDM_OP_GEN_TRIG_NONE 0 613 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 614 #define SDM_OP_GEN_TRIG_AGG_INT 2 615 #define SDM_OP_GEN_TRIG_LOADER 4 616 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 617 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 618 619 ///////////////////////////////////////////////////////////// 620 // Completion types 621 ///////////////////////////////////////////////////////////// 622 623 #define SDM_COMP_TYPE_NONE 0 624 #define SDM_COMP_TYPE_WAKE_THREAD 1 625 #define SDM_COMP_TYPE_AGG_INT 2 626 #define SDM_COMP_TYPE_CM 3 // Send direct message to local CM and/or remote CMs. Destinations are defined by vector in CompParams. 627 #define SDM_COMP_TYPE_LOADER 4 628 #define SDM_COMP_TYPE_PXP 5 // Send direct message to PXP (like "internal write" command) to write to remote Storm RAM via remote SDM 629 #define SDM_COMP_TYPE_INDICATE_ERROR 6 // Indicate error per thread 630 #define SDM_COMP_TYPE_RELEASE_THREAD 7 // Obsolete in E5 631 #define SDM_COMP_TYPE_RAM 8 // Write to local RAM as a completion 632 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 // Applicable only for E4 633 634 /******************/ 635 /* PBF CONSTANTS */ 636 /******************/ 637 638 /* Number of PBF command queue lines. Each line is 32B. */ 639 #define PBF_MAX_CMD_LINES_E4 3328 640 #define PBF_MAX_CMD_LINES_E5 5280 641 642 /* Number of BTB blocks. Each block is 256B. */ 643 #define BTB_MAX_BLOCKS 1440 644 645 /*****************/ 646 /* PRS CONSTANTS */ 647 /*****************/ 648 649 #define PRS_GFT_CAM_LINES_NO_MATCH 31 650 651 /* 652 * Interrupt coalescing TimeSet 653 */ 654 struct coalescing_timeset 655 { 656 u8 value; 657 #define COALESCING_TIMESET_TIMESET_MASK 0x7F /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */ 658 #define COALESCING_TIMESET_TIMESET_SHIFT 0 659 #define COALESCING_TIMESET_VALID_MASK 0x1 /* Only if this flag is set, timeset will take effect */ 660 #define COALESCING_TIMESET_VALID_SHIFT 7 661 }; 662 663 664 struct common_queue_zone 665 { 666 __le16 ring_drv_data_consumer; 667 __le16 reserved; 668 }; 669 670 671 /* 672 * ETH Rx producers data 673 */ 674 struct eth_rx_prod_data 675 { 676 __le16 bd_prod /* BD producer. */; 677 __le16 cqe_prod /* CQE producer. */; 678 }; 679 680 681 struct tcp_ulp_connect_done_params 682 { 683 __le16 mss; 684 u8 snd_wnd_scale; 685 u8 flags; 686 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1 687 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0 688 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F 689 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1 690 }; 691 692 struct iscsi_connect_done_results 693 { 694 __le16 icid /* Context ID of the connection */; 695 __le16 conn_id /* Driver connection ID */; 696 struct tcp_ulp_connect_done_params params /* decided tcp params after connect done */; 697 }; 698 699 700 struct iscsi_eqe_data 701 { 702 __le16 icid /* Context ID of the connection */; 703 __le16 conn_id /* Driver connection ID */; 704 __le16 reserved; 705 u8 error_code /* error code - relevant only if the opcode indicates its an error */; 706 u8 error_pdu_opcode_reserved; 707 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F /* The processed PDUs opcode on which happened the error - updated for specific error codes, by defualt=0xFF */ 708 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 709 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 /* Indication for driver is the error_pdu_opcode field has valid value */ 710 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 711 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 712 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 713 }; 714 715 716 /* 717 * Multi function mode 718 */ 719 enum mf_mode 720 { 721 ERROR_MODE /* Unsupported mode */, 722 MF_OVLAN /* Multi function based on outer VLAN */, 723 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */, 724 MAX_MF_MODE 725 }; 726 727 728 /* 729 * Per-protocol connection types 730 */ 731 enum protocol_type 732 { 733 PROTOCOLID_ISCSI /* iSCSI */, 734 PROTOCOLID_FCOE /* FCoE */, 735 PROTOCOLID_ROCE /* RoCE */, 736 PROTOCOLID_CORE /* Core (light L2, slow path core) */, 737 PROTOCOLID_ETH /* Ethernet */, 738 PROTOCOLID_IWARP /* iWARP */, 739 PROTOCOLID_TOE /* TOE */, 740 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */, 741 PROTOCOLID_COMMON /* ProtocolCommon */, 742 PROTOCOLID_TCP /* TCP */, 743 MAX_PROTOCOL_TYPE 744 }; 745 746 747 struct regpair 748 { 749 __le32 lo /* low word for reg-pair */; 750 __le32 hi /* high word for reg-pair */; 751 }; 752 753 /* 754 * RoCE Destroy Event Data 755 */ 756 struct rdma_eqe_destroy_qp 757 { 758 __le32 cid /* Dedicated field RoCE destroy QP event */; 759 u8 reserved[4]; 760 }; 761 762 /* 763 * RDMA Event Data Union 764 */ 765 union rdma_eqe_data 766 { 767 struct regpair async_handle /* Host handle for the Async Completions */; 768 struct rdma_eqe_destroy_qp rdma_destroy_qp_data /* RoCE Destroy Event Data */; 769 }; 770 771 772 773 774 /* 775 * Ustorm Queue Zone 776 */ 777 struct ustorm_eth_queue_zone 778 { 779 struct coalescing_timeset int_coalescing_timeset /* Rx interrupt coalescing TimeSet */; 780 u8 reserved[3]; 781 }; 782 783 784 struct ustorm_queue_zone 785 { 786 struct ustorm_eth_queue_zone eth; 787 struct common_queue_zone common; 788 }; 789 790 791 /* 792 * status block structure 793 */ 794 struct cau_pi_entry 795 { 796 __le32 prod; 797 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF /* A per protocol indexPROD value. */ 798 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 799 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F /* This value determines the TimeSet that the PI is associated with */ 800 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 801 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 /* Select the FSM within the SB */ 802 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 803 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF /* Select the FSM within the SB */ 804 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 805 }; 806 807 808 /* 809 * status block structure 810 */ 811 struct cau_sb_entry 812 { 813 __le32 data; 814 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF /* The SB PROD index which is sent to the IGU. */ 815 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 816 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */ 817 #define CAU_SB_ENTRY_STATE0_SHIFT 24 818 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */ 819 #define CAU_SB_ENTRY_STATE1_SHIFT 28 820 __le32 params; 821 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F /* Indicates the RX TimeSet that this SB is associated with. */ 822 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 823 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F /* Indicates the TX TimeSet that this SB is associated with. */ 824 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 825 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 /* This value will determine the RX FSM timer resolution in ticks */ 826 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 827 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 /* This value will determine the TX FSM timer resolution in ticks */ 828 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 829 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 830 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 831 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 832 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 833 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 834 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 835 #define CAU_SB_ENTRY_TPH_MASK 0x1 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones. */ 836 #define CAU_SB_ENTRY_TPH_SHIFT 31 837 }; 838 839 840 /* 841 * Igu cleanup bit values to distinguish between clean or producer consumer update. 842 */ 843 enum command_type_bit 844 { 845 IGU_COMMAND_TYPE_NOP=0, 846 IGU_COMMAND_TYPE_SET=1, 847 MAX_COMMAND_TYPE_BIT 848 }; 849 850 851 /* 852 * core doorbell data 853 */ 854 struct core_db_data 855 { 856 u8 params; 857 #define CORE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 858 #define CORE_DB_DATA_DEST_SHIFT 0 859 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 860 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 861 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 862 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 863 #define CORE_DB_DATA_RESERVED_MASK 0x1 864 #define CORE_DB_DATA_RESERVED_SHIFT 5 865 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 866 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 867 u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 868 __le16 spq_prod; 869 }; 870 871 872 /* 873 * Enum of doorbell aggregative command selection 874 */ 875 enum db_agg_cmd_sel 876 { 877 DB_AGG_CMD_NOP /* No operation */, 878 DB_AGG_CMD_SET /* Set the value */, 879 DB_AGG_CMD_ADD /* Add the value */, 880 DB_AGG_CMD_MAX /* Set max of current and new value */, 881 MAX_DB_AGG_CMD_SEL 882 }; 883 884 885 /* 886 * Enum of doorbell destination 887 */ 888 enum db_dest 889 { 890 DB_DEST_XCM /* TX doorbell to XCM */, 891 DB_DEST_UCM /* RX doorbell to UCM */, 892 DB_DEST_TCM /* RX doorbell to TCM */, 893 DB_NUM_DESTINATIONS, 894 MAX_DB_DEST 895 }; 896 897 898 /* 899 * Enum of doorbell DPM types 900 */ 901 enum db_dpm_type 902 { 903 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */, 904 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */, 905 DPM_L2_INLINE /* L2 DPM inline- to PBF, with packet data on doorbell */, 906 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */, 907 MAX_DB_DPM_TYPE 908 }; 909 910 911 /* 912 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM burst 913 */ 914 struct db_l2_dpm_data 915 { 916 __le16 icid /* internal CID */; 917 __le16 bd_prod /* bd producer value to update */; 918 __le32 params; 919 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 920 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 921 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) */ 922 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 923 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ 924 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 925 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF /* size of the packet to be transmitted in bytes */ 926 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 927 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 928 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 929 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 /* In DPM_L2_BD mode: the number of SGE-s */ 930 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 931 #define DB_L2_DPM_DATA_GFS_SRC_EN_MASK 0x1 /* Flag indicating whether to enable GFS search */ 932 #define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT 31 933 }; 934 935 936 /* 937 * Structure for SGE in a DPM doorbell of type DPM_L2_BD 938 */ 939 struct db_l2_dpm_sge 940 { 941 struct regpair addr /* Single continuous buffer */; 942 __le16 nbytes /* Number of bytes in this BD. */; 943 __le16 bitfields; 944 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF /* The TPH STAG index value */ 945 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 946 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 947 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 948 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 /* Indicate if ST hint is requested or not */ 949 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 950 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 951 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 952 __le32 reserved2; 953 }; 954 955 956 /* 957 * Structure for doorbell address, in legacy mode 958 */ 959 struct db_legacy_addr 960 { 961 __le32 addr; 962 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 963 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 964 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 /* doorbell extraction mode specifier- 0 if not used */ 965 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 966 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */ 967 #define DB_LEGACY_ADDR_ICID_SHIFT 5 968 }; 969 970 971 /* 972 * Structure for doorbell address, in PWM mode 973 */ 974 struct db_pwm_addr 975 { 976 __le32 addr; 977 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 978 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 979 #define DB_PWM_ADDR_OFFSET_MASK 0x7F /* Offset in PWM address space */ 980 #define DB_PWM_ADDR_OFFSET_SHIFT 3 981 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 982 #define DB_PWM_ADDR_WID_SHIFT 10 983 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */ 984 #define DB_PWM_ADDR_DPI_SHIFT 12 985 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 986 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 987 }; 988 989 990 /* 991 * Parameters to RDMA firmware, passed in EDPM doorbell 992 */ 993 struct db_rdma_dpm_params 994 { 995 __le32 params; 996 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 997 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 998 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 999 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 1000 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF /* opcode for RDMA operation */ 1001 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 1002 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF /* the size of the WQE payload in bytes */ 1003 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 1004 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 1005 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 1006 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 /* RoCE completion flag */ 1007 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 1008 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ 1009 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 1010 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 1011 #define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 1012 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 /* Connection type is iWARP */ 1013 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 1014 }; 1015 1016 /* 1017 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a DPM burst 1018 */ 1019 struct db_rdma_dpm_data 1020 { 1021 __le16 icid /* internal CID */; 1022 __le16 prod_val /* aggregated value to update */; 1023 struct db_rdma_dpm_params params /* parametes passed to RDMA firmware */; 1024 }; 1025 1026 1027 1028 /* 1029 * Igu interrupt command 1030 */ 1031 enum igu_int_cmd 1032 { 1033 IGU_INT_ENABLE=0, 1034 IGU_INT_DISABLE=1, 1035 IGU_INT_NOP=2, 1036 IGU_INT_NOP2=3, 1037 MAX_IGU_INT_CMD 1038 }; 1039 1040 1041 /* 1042 * IGU producer or consumer update command 1043 */ 1044 struct igu_prod_cons_update 1045 { 1046 __le32 sb_id_and_flags; 1047 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 1048 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 1049 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 1050 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 1051 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 /* interrupt enable/disable/nop (use enum igu_int_cmd) */ 1052 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 1053 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 /* (use enum igu_seg_access) */ 1054 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 1055 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 1056 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 1057 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 1058 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 1059 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 /* must always be set cleared (use enum command_type_bit) */ 1060 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 1061 __le32 reserved1; 1062 }; 1063 1064 1065 /* 1066 * Igu segments access for default status block only 1067 */ 1068 enum igu_seg_access 1069 { 1070 IGU_SEG_ACCESS_REG=0, 1071 IGU_SEG_ACCESS_ATTN=1, 1072 MAX_IGU_SEG_ACCESS 1073 }; 1074 1075 1076 /* 1077 * Enumeration for L3 type field of parsing_and_err_flags. L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) 1078 */ 1079 enum l3_type 1080 { 1081 e_l3_type_unknown, 1082 e_l3_type_ipv4, 1083 e_l3_type_ipv6, 1084 MAX_L3_TYPE 1085 }; 1086 1087 1088 /* 1089 * Enumeration for l4Protocol field of parsing_and_err_flags. L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. 1090 */ 1091 enum l4_protocol 1092 { 1093 e_l4_protocol_none, 1094 e_l4_protocol_tcp, 1095 e_l4_protocol_udp, 1096 MAX_L4_PROTOCOL 1097 }; 1098 1099 1100 /* 1101 * Parsing and error flags field. 1102 */ 1103 struct parsing_and_err_flags 1104 { 1105 __le16 flags; 1106 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) (use enum l3_type) */ 1107 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1108 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. (use enum l4_protocol) */ 1109 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1110 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 /* Set if the packet is IPv4/IPv6 fragment. */ 1111 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1112 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 /* corresponds to the same 8021q tag that is selected for 8021q-tag fiel. This flag should be set if the tag appears in the packet, regardless of its value. */ 1113 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1114 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 /* Set if L4 checksum was calculated. taken from the EOP descriptor. */ 1115 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1116 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 /* Set for PTP packet. */ 1117 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1118 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 /* Set if PTP timestamp recorded. */ 1119 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1120 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6 ver mismatch */ 1121 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1122 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 /* Set if L4 checksum validation failed. Valid only if L4 checksum was calculated. */ 1123 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1124 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ 1125 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1126 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 /* This flag should be set if the tag appears in the packet tunnel header, regardless of its value.. */ 1127 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1128 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch */ 1129 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1130 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 /* taken from the EOP descriptor. */ 1131 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1132 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum was calculated. */ 1133 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1134 }; 1135 1136 1137 /* 1138 * Parsing error flags bitmap. 1139 */ 1140 struct parsing_err_flags 1141 { 1142 __le16 flags; 1143 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 /* MAC error indication */ 1144 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1145 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 /* truncation error indication */ 1146 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1147 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 /* packet too small indication */ 1148 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1149 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 /* Header Missing Tag */ 1150 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1151 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 /* from frame cracker output */ 1152 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1153 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 /* from frame cracker output */ 1154 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1155 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len indicates number that is bigger than real packet length 3. tunneling: total-ip-length of the outer header points to offset that is smaller than the one pointed to by the total-ip-len of the inner hdr. */ 1156 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1157 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1158 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1159 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 /* from frame cracker output. for either TCP or UDP */ 1160 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1161 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 /* from frame cracker output */ 1162 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1163 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 /* cksm calculated and value isnt 0xffff or L4-cksm-wasnt-calculated for any reason, like: udp/ipv4 checksum is 0 etc. */ 1164 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1165 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 /* from frame cracker output */ 1166 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1167 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 /* from frame cracker output */ 1168 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1169 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 /* set if geneve option size was over 32 byte */ 1170 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1171 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1172 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1173 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1174 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1175 }; 1176 1177 1178 /* 1179 * Pb context 1180 */ 1181 struct pb_context 1182 { 1183 __le32 crc[4]; 1184 }; 1185 1186 1187 /* 1188 * Concrete Function ID. 1189 */ 1190 struct pxp_concrete_fid 1191 { 1192 __le16 fid; 1193 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1194 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1195 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */ 1196 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1197 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */ 1198 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1199 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1200 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1201 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1202 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1203 }; 1204 1205 1206 /* 1207 * Concrete Function ID. 1208 */ 1209 struct pxp_pretend_concrete_fid 1210 { 1211 __le16 fid; 1212 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1213 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1214 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 /* port number. Only when part of ME register. */ 1215 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1216 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1217 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1218 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1219 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1220 }; 1221 1222 /* 1223 * Function ID. 1224 */ 1225 union pxp_pretend_fid 1226 { 1227 struct pxp_pretend_concrete_fid concrete_fid; 1228 __le16 opaque_fid; 1229 }; 1230 1231 /* 1232 * Pxp Pretend Command Register. 1233 */ 1234 struct pxp_pretend_cmd 1235 { 1236 union pxp_pretend_fid fid; 1237 __le16 control; 1238 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1239 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1240 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1241 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1242 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1243 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1244 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1245 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1246 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1247 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1248 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 /* is pretend mode? */ 1249 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1250 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 /* is pretend mode? */ 1251 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1252 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 /* is pretend mode? */ 1253 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1254 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 /* is fid concrete? */ 1255 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1256 }; 1257 1258 1259 1260 1261 /* 1262 * PTT Record in PXP Admin Window. 1263 */ 1264 struct pxp_ptt_entry 1265 { 1266 __le32 offset; 1267 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1268 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1269 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1270 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1271 struct pxp_pretend_cmd pretend; 1272 }; 1273 1274 1275 /* 1276 * VF Zone A Permission Register. 1277 */ 1278 struct pxp_vf_zone_a_permission 1279 { 1280 __le32 control; 1281 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1282 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1283 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1284 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1285 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1286 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1287 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1288 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1289 }; 1290 1291 1292 /* 1293 * Rdif context 1294 */ 1295 struct rdif_task_context 1296 { 1297 __le32 initial_ref_tag; 1298 __le16 app_tag_value; 1299 __le16 app_tag_mask; 1300 u8 flags0; 1301 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1302 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1303 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1304 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1305 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1306 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1307 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1308 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1309 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1310 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1311 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1312 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1313 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 /* Keep reference tag constant */ 1314 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7 1315 u8 partial_dif_data[7]; 1316 __le16 partial_crc_value; 1317 __le16 partial_checksum_value; 1318 __le32 offset_in_io; 1319 __le16 flags1; 1320 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1321 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1322 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1323 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1324 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1325 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1326 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1327 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1328 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1329 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1330 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1331 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1332 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1333 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1334 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1335 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1336 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1337 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1338 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1339 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1340 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1341 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1342 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 /* Forward application tag with mask */ 1343 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14 1344 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 /* Forward reference tag with mask */ 1345 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15 1346 __le16 state; 1347 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF 1348 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0 1349 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF 1350 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4 1351 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1 1352 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8 1353 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1 1354 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9 1355 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF /* mask for refernce tag handling */ 1356 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10 1357 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1358 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1359 __le32 reserved2; 1360 }; 1361 1362 1363 1364 /* 1365 * status block structure 1366 */ 1367 struct status_block_e4 1368 { 1369 __le16 pi_array[PIS_PER_SB_E4]; 1370 __le32 sb_num; 1371 #define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF 1372 #define STATUS_BLOCK_E4_SB_NUM_SHIFT 0 1373 #define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F 1374 #define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9 1375 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF 1376 #define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16 1377 __le32 prod_index; 1378 #define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF 1379 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0 1380 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF 1381 #define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24 1382 }; 1383 1384 1385 /* 1386 * status block structure 1387 */ 1388 struct status_block_e5 1389 { 1390 __le16 pi_array[PIS_PER_SB_E5]; 1391 __le32 sb_num; 1392 #define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF 1393 #define STATUS_BLOCK_E5_SB_NUM_SHIFT 0 1394 #define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F 1395 #define STATUS_BLOCK_E5_ZERO_PAD_SHIFT 9 1396 #define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF 1397 #define STATUS_BLOCK_E5_ZERO_PAD2_SHIFT 16 1398 __le32 prod_index; 1399 #define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF 1400 #define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0 1401 #define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF 1402 #define STATUS_BLOCK_E5_ZERO_PAD3_SHIFT 24 1403 }; 1404 1405 1406 /* 1407 * Tdif context 1408 */ 1409 struct tdif_task_context 1410 { 1411 __le32 initial_ref_tag; 1412 __le16 app_tag_value; 1413 __le16 app_tag_mask; 1414 __le16 partial_crc_value_b; 1415 __le16 partial_checksum_value_b; 1416 __le16 stateB; 1417 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF 1418 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0 1419 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF 1420 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4 1421 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1 1422 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8 1423 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1 1424 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9 1425 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1426 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1427 u8 reserved1; 1428 u8 flags0; 1429 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1430 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1431 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1432 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1433 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1434 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1435 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1436 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1437 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1438 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1439 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1440 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1441 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1442 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1443 __le32 flags1; 1444 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1445 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1446 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1447 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1448 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1449 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1450 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1451 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1452 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1453 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1454 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1455 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1456 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1457 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1458 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1459 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1460 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1461 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1462 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */ 1463 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1464 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1465 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1466 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF 1467 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14 1468 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF 1469 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18 1470 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1 1471 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22 1472 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1 1473 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23 1474 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF /* mask for refernce tag handling */ 1475 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24 1476 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 /* Forward application tag with mask */ 1477 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28 1478 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 /* Forward reference tag with mask */ 1479 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29 1480 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 /* Keep reference tag constant */ 1481 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30 1482 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1483 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1484 __le32 offset_in_io_b; 1485 __le16 partial_crc_value_a; 1486 __le16 partial_checksum_value_a; 1487 __le32 offset_in_io_a; 1488 u8 partial_dif_data_a[8]; 1489 u8 partial_dif_data_b[8]; 1490 }; 1491 1492 1493 /* 1494 * Timers context 1495 */ 1496 struct timers_context 1497 { 1498 __le32 logical_client_0; 1499 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF /* Expiration time of logical client 0 */ 1500 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1501 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1502 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1503 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 /* Valid bit of logical client 0 */ 1504 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1505 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 /* Active bit of logical client 0 */ 1506 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1507 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1508 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1509 __le32 logical_client_1; 1510 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF /* Expiration time of logical client 1 */ 1511 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1512 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1513 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1514 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 /* Valid bit of logical client 1 */ 1515 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1516 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 /* Active bit of logical client 1 */ 1517 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1518 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1519 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1520 __le32 logical_client_2; 1521 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF /* Expiration time of logical client 2 */ 1522 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1523 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1524 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1525 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 /* Valid bit of logical client 2 */ 1526 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1527 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 /* Active bit of logical client 2 */ 1528 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1529 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1530 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1531 __le32 host_expiration_fields; 1532 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF /* Expiration time on host (closest one) */ 1533 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1534 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1535 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1536 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 /* Valid bit of host expiration */ 1537 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1538 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1539 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1540 }; 1541 1542 1543 /* 1544 * Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc 1545 */ 1546 enum tunnel_next_protocol 1547 { 1548 e_unknown=0, 1549 e_l2=1, 1550 e_ipv4=2, 1551 e_ipv6=3, 1552 MAX_TUNNEL_NEXT_PROTOCOL 1553 }; 1554 1555 #endif /* __COMMON_HSI__ */ 1556