1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __COMMON_HSI__ 32 #define __COMMON_HSI__ 33 /********************************/ 34 /* PROTOCOL COMMON FW CONSTANTS */ 35 /********************************/ 36 37 /* Temporarily here should be added to HSI automatically by resource allocation tool.*/ 38 #define T_TEST_AGG_INT_TEMP 6 39 #define M_TEST_AGG_INT_TEMP 8 40 #define U_TEST_AGG_INT_TEMP 6 41 #define X_TEST_AGG_INT_TEMP 14 42 #define Y_TEST_AGG_INT_TEMP 4 43 #define P_TEST_AGG_INT_TEMP 4 44 45 #define X_FINAL_CLEANUP_AGG_INT 1 46 47 #define EVENT_RING_PAGE_SIZE_BYTES 4096 48 49 #define NUM_OF_GLOBAL_QUEUES 128 50 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 51 52 #define ISCSI_CDU_TASK_SEG_TYPE 0 53 #define FCOE_CDU_TASK_SEG_TYPE 0 54 #define RDMA_CDU_TASK_SEG_TYPE 1 55 56 #define FW_ASSERT_GENERAL_ATTN_IDX 32 57 58 #define MAX_PINNED_CCFC 32 59 60 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 61 62 /* Queue Zone sizes in bytes */ 63 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/ 64 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX producer of VFs in backward compatibility mode.*/ 65 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/ 66 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ 67 #define YSTORM_QZONE_SIZE 0 68 #define PSTORM_QZONE_SIZE 0 69 70 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 /*Log of mstorm default VF zone size.*/ 71 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 /*Maximum number of RX queues that can be allocated to VF by default*/ 72 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone size. Up to 96 VF supported in this mode*/ 73 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. Up to 48 VF supported in this mode*/ 74 75 /********************************/ 76 /* CORE (LIGHT L2) FW CONSTANTS */ 77 /********************************/ 78 79 #define CORE_LL2_MAX_RAMROD_PER_CON 8 80 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 81 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 82 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 83 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 84 85 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 86 87 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 88 89 /* 90 * Usually LL2 queues are opened in pairs � TX-RX. 91 * There is a hard restriction on number of RX queues (limited by Tstorm RAM) and TX counters (Pstorm RAM). 92 * Number of TX queues is almost unlimited. 93 * The constants are different so as to allow asymmetric LL2 connections 94 */ 95 96 #define MAX_NUM_LL2_RX_QUEUES 48 97 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 98 99 /////////////////////////////////////////////////////////////////////////////////////////////////// 100 // Include firmware verison number only- do not add constants here to avoid redundunt compilations 101 /////////////////////////////////////////////////////////////////////////////////////////////////// 102 103 #define FW_MAJOR_VERSION 8 104 #define FW_MINOR_VERSION 33 105 #define FW_REVISION_VERSION 7 106 #define FW_ENGINEERING_VERSION 0 107 108 /***********************/ 109 /* COMMON HW CONSTANTS */ 110 /***********************/ 111 112 /* PCI functions */ 113 #define MAX_NUM_PORTS_BB (2) 114 #define MAX_NUM_PORTS_K2 (4) 115 #define MAX_NUM_PORTS_E5 (4) 116 #define MAX_NUM_PORTS (MAX_NUM_PORTS_E5) 117 118 #define MAX_NUM_PFS_BB (8) 119 #define MAX_NUM_PFS_K2 (16) 120 #define MAX_NUM_PFS_E5 (16) 121 #define MAX_NUM_PFS (MAX_NUM_PFS_E5) 122 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 123 124 #define MAX_NUM_VFS_BB (120) 125 #define MAX_NUM_VFS_K2 (192) 126 #define MAX_NUM_VFS_E4 (MAX_NUM_VFS_K2) 127 #define MAX_NUM_VFS_E5 (240) 128 #define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_E5) 129 130 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 131 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) 132 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS_E4) 133 134 /* in both BB and K2, the VF number starts from 16. so for arrays containing all */ 135 /* possible PFs and VFs - we need a constant for this size */ 136 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 137 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 138 #define MAX_FUNCTION_NUMBER_E4 (MAX_NUM_PFS + MAX_NUM_VFS_E4) 139 #define MAX_FUNCTION_NUMBER_E5 (MAX_NUM_PFS + MAX_NUM_VFS_E5) 140 #define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_E5) 141 142 #define MAX_NUM_VPORTS_K2 (208) 143 #define MAX_NUM_VPORTS_BB (160) 144 #define MAX_NUM_VPORTS_E4 (MAX_NUM_VPORTS_K2) 145 #define MAX_NUM_VPORTS_E5 (256) 146 #define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_E5) 147 148 #define MAX_NUM_L2_QUEUES_BB (256) 149 #define MAX_NUM_L2_QUEUES_K2 (320) 150 #define MAX_NUM_L2_QUEUES_E5 (320) /* TODO_E5_VITALY - fix to 512 */ 151 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_E5) 152 153 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 154 #define NUM_PHYS_TCS_4PORT_K2 4 155 #define NUM_PHYS_TCS_4PORT_TX_E5 6 156 #define NUM_PHYS_TCS_4PORT_RX_E5 4 157 #define NUM_OF_PHYS_TCS 8 158 #define PURE_LB_TC NUM_OF_PHYS_TCS 159 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 160 #define NUM_TCS_4PORT_TX_E5 (NUM_PHYS_TCS_4PORT_TX_E5 + 1) 161 #define NUM_TCS_4PORT_RX_E5 (NUM_PHYS_TCS_4PORT_RX_E5 + 1) 162 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 163 164 /* CIDs */ 165 #define NUM_OF_CONNECTION_TYPES_E4 (8) 166 #define NUM_OF_CONNECTION_TYPES_E5 (16) 167 #define NUM_OF_TASK_TYPES (8) 168 #define NUM_OF_LCIDS (320) 169 #define NUM_OF_LTIDS (320) 170 171 /* Global PXP windows (GTT) */ 172 #define NUM_OF_GTT 19 173 #define GTT_DWORD_SIZE_BITS 10 174 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 175 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) 176 177 /* Tools Version */ 178 #define TOOLS_VERSION 10 179 /*****************/ 180 /* CDU CONSTANTS */ 181 /*****************/ 182 183 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 184 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 185 186 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 187 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 188 189 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 190 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 191 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 192 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 193 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 194 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 195 196 /*****************/ 197 /* DQ CONSTANTS */ 198 /*****************/ 199 200 /* DEMS */ 201 #define DQ_DEMS_LEGACY 0 202 #define DQ_DEMS_TOE_MORE_TO_SEND 3 203 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 204 #define DQ_DEMS_ROCE_CQ_CONS 7 205 206 /* XCM agg val selection (HW) */ 207 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 208 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 209 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 210 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 211 #define DQ_XCM_AGG_VAL_SEL_REG3 4 212 #define DQ_XCM_AGG_VAL_SEL_REG4 5 213 #define DQ_XCM_AGG_VAL_SEL_REG5 6 214 #define DQ_XCM_AGG_VAL_SEL_REG6 7 215 216 /* XCM agg val selection (FW) */ 217 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 218 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 219 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 220 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 221 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 222 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 223 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 224 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 225 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 226 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 227 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 228 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 229 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 230 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 231 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 232 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 233 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 234 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 235 236 /* UCM agg val selection (HW) */ 237 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 238 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 239 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 240 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 241 #define DQ_UCM_AGG_VAL_SEL_REG0 4 242 #define DQ_UCM_AGG_VAL_SEL_REG1 5 243 #define DQ_UCM_AGG_VAL_SEL_REG2 6 244 #define DQ_UCM_AGG_VAL_SEL_REG3 7 245 246 /* UCM agg val selection (FW) */ 247 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 248 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 249 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 250 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 251 252 /* TCM agg val selection (HW) */ 253 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 254 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 255 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 256 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 257 #define DQ_TCM_AGG_VAL_SEL_REG1 4 258 #define DQ_TCM_AGG_VAL_SEL_REG2 5 259 #define DQ_TCM_AGG_VAL_SEL_REG6 6 260 #define DQ_TCM_AGG_VAL_SEL_REG9 7 261 262 /* TCM agg val selection (FW) */ 263 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 264 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 265 266 /* XCM agg counter flag selection (HW) */ 267 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 268 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 269 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 270 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 271 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 272 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 273 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 274 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 275 276 /* XCM agg counter flag selection (FW) */ 277 #define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 278 #define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 279 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 280 #define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 281 #define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 282 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 283 #define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 284 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 285 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 286 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 287 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 288 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 289 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 290 291 /* UCM agg counter flag selection (HW) */ 292 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 293 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 294 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 295 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 296 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 297 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 298 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 299 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 300 301 /* UCM agg counter flag selection (FW) */ 302 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 303 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 304 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 305 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 306 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) 307 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 308 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 309 310 /* TCM agg counter flag selection (HW) */ 311 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 312 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 313 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 314 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 315 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 316 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 317 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 318 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 319 320 /* TCM agg counter flag selection (FW) */ 321 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 322 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2) 323 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 324 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 325 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 326 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 327 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 328 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 329 330 /* PWM address mapping */ 331 #define DQ_PWM_OFFSET_DPM_BASE 0x0 332 #define DQ_PWM_OFFSET_DPM_END 0x27 333 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 334 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 335 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 336 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 337 #define DQ_PWM_OFFSET_UCM16_4 0x50 338 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 339 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 340 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 341 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 342 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 343 344 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 345 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 346 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 347 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 348 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 349 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 350 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 351 352 #define DQ_REGION_SHIFT (12) 353 354 /* DPM */ 355 #define DQ_DPM_WQE_BUFF_SIZE (320) 356 357 // Conn type ranges 358 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 359 360 /*****************/ 361 /* QM CONSTANTS */ 362 /*****************/ 363 364 /* number of TX queues in the QM */ 365 #define MAX_QM_TX_QUEUES_K2 512 366 #define MAX_QM_TX_QUEUES_BB 448 367 #define MAX_QM_TX_QUEUES_E5 MAX_QM_TX_QUEUES_K2 368 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 369 370 /* number of Other queues in the QM */ 371 #define MAX_QM_OTHER_QUEUES_BB 64 372 #define MAX_QM_OTHER_QUEUES_K2 128 373 #define MAX_QM_OTHER_QUEUES_E5 MAX_QM_OTHER_QUEUES_K2 374 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 375 376 /* number of queues in a PF queue group */ 377 #define QM_PF_QUEUE_GROUP_SIZE 8 378 379 /* the size of a single queue element in bytes */ 380 #define QM_PQ_ELEMENT_SIZE 4 381 382 /* base number of Tx PQs in the CM PQ representation. 383 should be used when storing PQ IDs in CM PQ registers and context */ 384 #define CM_TX_PQ_BASE 0x200 385 386 /* number of global Vport/QCN rate limiters */ 387 #define MAX_QM_GLOBAL_RLS 256 388 389 /* QM registers data */ 390 #define QM_LINE_CRD_REG_WIDTH 16 391 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 392 #define QM_BYTE_CRD_REG_WIDTH 24 393 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 394 #define QM_WFQ_CRD_REG_WIDTH 32 395 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) 396 #define QM_RL_CRD_REG_WIDTH 32 397 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) 398 399 /*****************/ 400 /* CAU CONSTANTS */ 401 /*****************/ 402 403 #define CAU_FSM_ETH_RX 0 404 #define CAU_FSM_ETH_TX 1 405 406 /* Number of Protocol Indices per Status Block */ 407 #define PIS_PER_SB_E4 12 408 #define PIS_PER_SB_E5 8 409 #define MAX_PIS_PER_SB OSAL_MAX_T(PIS_PER_SB_E4,PIS_PER_SB_E5) 410 411 #define CAU_HC_STOPPED_STATE 3 /* fsm is stopped or not valid for this sb */ 412 #define CAU_HC_DISABLE_STATE 4 /* fsm is working without interrupt coalescing for this sb*/ 413 #define CAU_HC_ENABLE_STATE 0 /* fsm is working with interrupt coalescing for this sb*/ 414 415 /*****************/ 416 /* IGU CONSTANTS */ 417 /*****************/ 418 419 #define MAX_SB_PER_PATH_K2 (368) 420 #define MAX_SB_PER_PATH_BB (288) 421 #define MAX_SB_PER_PATH_E5 (512) 422 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_E5 423 424 #define MAX_SB_PER_PF_MIMD 129 425 #define MAX_SB_PER_PF_SIMD 64 426 #define MAX_SB_PER_VF 64 427 428 /* Memory addresses on the BAR for the IGU Sub Block */ 429 #define IGU_MEM_BASE 0x0000 430 431 #define IGU_MEM_MSIX_BASE 0x0000 432 #define IGU_MEM_MSIX_UPPER 0x0101 433 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 434 435 #define IGU_MEM_PBA_MSIX_BASE 0x0200 436 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 437 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 438 439 #define IGU_CMD_INT_ACK_BASE 0x0400 440 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + MAX_TOT_SB_PER_PATH - 1) 441 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 442 443 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 444 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 445 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 446 447 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 448 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 449 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 450 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 451 452 #define IGU_CMD_PROD_UPD_BASE 0x0600 453 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + MAX_TOT_SB_PER_PATH - 1) 454 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 455 456 /*****************/ 457 /* PXP CONSTANTS */ 458 /*****************/ 459 460 /* Bars for Blocks */ 461 #define PXP_BAR_GRC 0 462 #define PXP_BAR_TSDM 0 463 #define PXP_BAR_USDM 0 464 #define PXP_BAR_XSDM 0 465 #define PXP_BAR_MSDM 0 466 #define PXP_BAR_YSDM 0 467 #define PXP_BAR_PSDM 0 468 #define PXP_BAR_IGU 0 469 #define PXP_BAR_DQ 1 470 471 /* PTT and GTT */ 472 #define PXP_PER_PF_ENTRY_SIZE 8 473 #define PXP_NUM_GLOBAL_WINDOWS 243 474 #define PXP_GLOBAL_ENTRY_SIZE 4 475 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 476 #define PXP_PF_WINDOW_ADMIN_START 0 477 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 478 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_LENGTH - 1) 479 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 480 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * PXP_PER_PF_ENTRY_SIZE) 481 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 482 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 483 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * PXP_GLOBAL_ENTRY_SIZE) 484 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END (PXP_PF_WINDOW_ADMIN_GLOBAL_START + PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 485 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 486 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 487 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 488 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 489 490 #define PXP_NUM_PF_WINDOWS 12 491 492 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 493 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 494 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 495 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 496 #define PXP_EXTERNAL_BAR_PF_WINDOW_END (PXP_EXTERNAL_BAR_PF_WINDOW_START + PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 497 498 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 499 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 500 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 501 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 502 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 503 504 /* PF BAR */ 505 #define PXP_BAR0_START_GRC 0x0000 506 #define PXP_BAR0_GRC_LENGTH 0x1C00000 507 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1) 508 509 #define PXP_BAR0_START_IGU 0x1C00000 510 #define PXP_BAR0_IGU_LENGTH 0x10000 511 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1) 512 513 #define PXP_BAR0_START_TSDM 0x1C80000 514 #define PXP_BAR0_SDM_LENGTH 0x40000 515 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 516 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1) 517 518 #define PXP_BAR0_START_MSDM 0x1D00000 519 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1) 520 521 #define PXP_BAR0_START_USDM 0x1D80000 522 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1) 523 524 #define PXP_BAR0_START_XSDM 0x1E00000 525 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1) 526 527 #define PXP_BAR0_START_YSDM 0x1E80000 528 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1) 529 530 #define PXP_BAR0_START_PSDM 0x1F00000 531 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1) 532 533 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 534 535 /* VF BAR */ 536 #define PXP_VF_BAR0 0 537 538 #define PXP_VF_BAR0_START_IGU 0 539 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 540 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1) 541 542 #define PXP_VF_BAR0_START_DQ 0x3000 543 #define PXP_VF_BAR0_DQ_LENGTH 0x200 544 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 545 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 546 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4) 547 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1) 548 549 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 550 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 551 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 552 553 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 554 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 555 556 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 557 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 558 559 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 560 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 561 562 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 563 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 564 565 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 566 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 567 568 #define PXP_VF_BAR0_START_GRC 0x3E00 569 #define PXP_VF_BAR0_GRC_LENGTH 0x200 570 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1) 571 572 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 573 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 574 575 #define PXP_VF_BAR0_START_IGU2 0x10000 576 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000 577 #define PXP_VF_BAR0_END_IGU2 (PXP_VF_BAR0_START_IGU2 + PXP_VF_BAR0_IGU2_LENGTH - 1) 578 579 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 580 581 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 582 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 583 584 // ILT Records 585 #define PXP_NUM_ILT_RECORDS_BB 7600 586 #define PXP_NUM_ILT_RECORDS_K2 11000 587 #define MAX_NUM_ILT_RECORDS OSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2) 588 589 #define PXP_NUM_ILT_RECORDS_E5 13664 590 591 // Host Interface 592 #define PXP_QUEUES_ZONE_MAX_NUM_E4 320 593 #define PXP_QUEUES_ZONE_MAX_NUM_E5 512 594 595 /*****************/ 596 /* PRM CONSTANTS */ 597 /*****************/ 598 #define PRM_DMA_PAD_BYTES_NUM 2 599 /*****************/ 600 /* SDMs CONSTANTS */ 601 /*****************/ 602 603 #define SDM_OP_GEN_TRIG_NONE 0 604 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 605 #define SDM_OP_GEN_TRIG_AGG_INT 2 606 #define SDM_OP_GEN_TRIG_LOADER 4 607 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 608 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 609 610 ///////////////////////////////////////////////////////////// 611 // Completion types 612 ///////////////////////////////////////////////////////////// 613 614 #define SDM_COMP_TYPE_NONE 0 615 #define SDM_COMP_TYPE_WAKE_THREAD 1 616 #define SDM_COMP_TYPE_AGG_INT 2 617 #define SDM_COMP_TYPE_CM 3 // Send direct message to local CM and/or remote CMs. Destinations are defined by vector in CompParams. 618 #define SDM_COMP_TYPE_LOADER 4 619 #define SDM_COMP_TYPE_PXP 5 // Send direct message to PXP (like "internal write" command) to write to remote Storm RAM via remote SDM 620 #define SDM_COMP_TYPE_INDICATE_ERROR 6 // Indicate error per thread 621 #define SDM_COMP_TYPE_RELEASE_THREAD 7 // Obsolete in E5 622 #define SDM_COMP_TYPE_RAM 8 // Write to local RAM as a completion 623 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 // Applicable only for E4 624 625 /******************/ 626 /* PBF CONSTANTS */ 627 /******************/ 628 629 /* Number of PBF command queue lines. Each line is 32B. */ 630 #define PBF_MAX_CMD_LINES_E4 3328 631 #define PBF_MAX_CMD_LINES_E5 5280 632 633 /* Number of BTB blocks. Each block is 256B. */ 634 #define BTB_MAX_BLOCKS 1440 635 636 /*****************/ 637 /* PRS CONSTANTS */ 638 /*****************/ 639 640 #define PRS_GFT_CAM_LINES_NO_MATCH 31 641 642 /* 643 * Interrupt coalescing TimeSet 644 */ 645 struct coalescing_timeset 646 { 647 u8 value; 648 #define COALESCING_TIMESET_TIMESET_MASK 0x7F /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */ 649 #define COALESCING_TIMESET_TIMESET_SHIFT 0 650 #define COALESCING_TIMESET_VALID_MASK 0x1 /* Only if this flag is set, timeset will take effect */ 651 #define COALESCING_TIMESET_VALID_SHIFT 7 652 }; 653 654 struct common_queue_zone 655 { 656 __le16 ring_drv_data_consumer; 657 __le16 reserved; 658 }; 659 660 /* 661 * ETH Rx producers data 662 */ 663 struct eth_rx_prod_data 664 { 665 __le16 bd_prod /* BD producer. */; 666 __le16 cqe_prod /* CQE producer. */; 667 }; 668 669 struct tcp_ulp_connect_done_params 670 { 671 __le16 mss; 672 u8 snd_wnd_scale; 673 u8 flags; 674 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1 675 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0 676 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F 677 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1 678 }; 679 680 struct iscsi_connect_done_results 681 { 682 __le16 icid /* Context ID of the connection */; 683 __le16 conn_id /* Driver connection ID */; 684 struct tcp_ulp_connect_done_params params /* decided tcp params after connect done */; 685 }; 686 687 struct iscsi_eqe_data 688 { 689 __le16 icid /* Context ID of the connection */; 690 __le16 conn_id /* Driver connection ID */; 691 __le16 reserved; 692 u8 error_code /* error code - relevant only if the opcode indicates its an error */; 693 u8 error_pdu_opcode_reserved; 694 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F /* The processed PDUs opcode on which happened the error - updated for specific error codes, by defualt=0xFF */ 695 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 696 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 /* Indication for driver is the error_pdu_opcode field has valid value */ 697 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 698 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 699 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 700 }; 701 702 /* 703 * Multi function mode 704 */ 705 enum mf_mode 706 { 707 ERROR_MODE /* Unsupported mode */, 708 MF_OVLAN /* Multi function based on outer VLAN */, 709 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */, 710 MAX_MF_MODE 711 }; 712 713 /* 714 * Per-protocol connection types 715 */ 716 enum protocol_type 717 { 718 PROTOCOLID_ISCSI /* iSCSI */, 719 PROTOCOLID_FCOE /* FCoE */, 720 PROTOCOLID_ROCE /* RoCE */, 721 PROTOCOLID_CORE /* Core (light L2, slow path core) */, 722 PROTOCOLID_ETH /* Ethernet */, 723 PROTOCOLID_IWARP /* iWARP */, 724 PROTOCOLID_TOE /* TOE */, 725 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */, 726 PROTOCOLID_COMMON /* ProtocolCommon */, 727 PROTOCOLID_TCP /* TCP */, 728 MAX_PROTOCOL_TYPE 729 }; 730 731 struct regpair 732 { 733 __le32 lo /* low word for reg-pair */; 734 __le32 hi /* high word for reg-pair */; 735 }; 736 737 /* 738 * RoCE Destroy Event Data 739 */ 740 struct rdma_eqe_destroy_qp 741 { 742 __le32 cid /* Dedicated field RoCE destroy QP event */; 743 u8 reserved[4]; 744 }; 745 746 /* 747 * RDMA Event Data Union 748 */ 749 union rdma_eqe_data 750 { 751 struct regpair async_handle /* Host handle for the Async Completions */; 752 struct rdma_eqe_destroy_qp rdma_destroy_qp_data /* RoCE Destroy Event Data */; 753 }; 754 755 /* 756 * Ustorm Queue Zone 757 */ 758 struct ustorm_eth_queue_zone 759 { 760 struct coalescing_timeset int_coalescing_timeset /* Rx interrupt coalescing TimeSet */; 761 u8 reserved[3]; 762 }; 763 764 struct ustorm_queue_zone 765 { 766 struct ustorm_eth_queue_zone eth; 767 struct common_queue_zone common; 768 }; 769 770 /* 771 * status block structure 772 */ 773 struct cau_pi_entry 774 { 775 __le32 prod; 776 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF /* A per protocol indexPROD value. */ 777 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 778 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F /* This value determines the TimeSet that the PI is associated with */ 779 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 780 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 /* Select the FSM within the SB */ 781 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 782 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF /* Select the FSM within the SB */ 783 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 784 }; 785 786 /* 787 * status block structure 788 */ 789 struct cau_sb_entry 790 { 791 __le32 data; 792 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF /* The SB PROD index which is sent to the IGU. */ 793 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 794 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */ 795 #define CAU_SB_ENTRY_STATE0_SHIFT 24 796 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */ 797 #define CAU_SB_ENTRY_STATE1_SHIFT 28 798 __le32 params; 799 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F /* Indicates the RX TimeSet that this SB is associated with. */ 800 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 801 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F /* Indicates the TX TimeSet that this SB is associated with. */ 802 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 803 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 /* This value will determine the RX FSM timer resolution in ticks */ 804 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 805 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 /* This value will determine the TX FSM timer resolution in ticks */ 806 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 807 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 808 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 809 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 810 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 811 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 812 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 813 #define CAU_SB_ENTRY_TPH_MASK 0x1 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones. */ 814 #define CAU_SB_ENTRY_TPH_SHIFT 31 815 }; 816 817 /* 818 * Igu cleanup bit values to distinguish between clean or producer consumer update. 819 */ 820 enum command_type_bit 821 { 822 IGU_COMMAND_TYPE_NOP=0, 823 IGU_COMMAND_TYPE_SET=1, 824 MAX_COMMAND_TYPE_BIT 825 }; 826 827 /* 828 * core doorbell data 829 */ 830 struct core_db_data 831 { 832 u8 params; 833 #define CORE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 834 #define CORE_DB_DATA_DEST_SHIFT 0 835 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 836 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 837 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 838 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 839 #define CORE_DB_DATA_RESERVED_MASK 0x1 840 #define CORE_DB_DATA_RESERVED_SHIFT 5 841 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 842 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 843 u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 844 __le16 spq_prod; 845 }; 846 847 /* 848 * Enum of doorbell aggregative command selection 849 */ 850 enum db_agg_cmd_sel 851 { 852 DB_AGG_CMD_NOP /* No operation */, 853 DB_AGG_CMD_SET /* Set the value */, 854 DB_AGG_CMD_ADD /* Add the value */, 855 DB_AGG_CMD_MAX /* Set max of current and new value */, 856 MAX_DB_AGG_CMD_SEL 857 }; 858 859 /* 860 * Enum of doorbell destination 861 */ 862 enum db_dest 863 { 864 DB_DEST_XCM /* TX doorbell to XCM */, 865 DB_DEST_UCM /* RX doorbell to UCM */, 866 DB_DEST_TCM /* RX doorbell to TCM */, 867 DB_NUM_DESTINATIONS, 868 MAX_DB_DEST 869 }; 870 871 /* 872 * Enum of doorbell DPM types 873 */ 874 enum db_dpm_type 875 { 876 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */, 877 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */, 878 DPM_L2_INLINE /* L2 DPM inline- to PBF, with packet data on doorbell */, 879 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */, 880 MAX_DB_DPM_TYPE 881 }; 882 883 /* 884 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM burst 885 */ 886 struct db_l2_dpm_data 887 { 888 __le16 icid /* internal CID */; 889 __le16 bd_prod /* bd producer value to update */; 890 __le32 params; 891 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 892 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 893 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) */ 894 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 895 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ 896 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 897 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF /* size of the packet to be transmitted in bytes */ 898 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 899 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 900 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 901 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 /* In DPM_L2_BD mode: the number of SGE-s */ 902 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 903 #define DB_L2_DPM_DATA_GFS_SRC_EN_MASK 0x1 /* Flag indicating whether to enable GFS search */ 904 #define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT 31 905 }; 906 907 /* 908 * Structure for SGE in a DPM doorbell of type DPM_L2_BD 909 */ 910 struct db_l2_dpm_sge 911 { 912 struct regpair addr /* Single continuous buffer */; 913 __le16 nbytes /* Number of bytes in this BD. */; 914 __le16 bitfields; 915 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF /* The TPH STAG index value */ 916 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 917 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 918 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 919 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 /* Indicate if ST hint is requested or not */ 920 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 921 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 922 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 923 __le32 reserved2; 924 }; 925 926 /* 927 * Structure for doorbell address, in legacy mode 928 */ 929 struct db_legacy_addr 930 { 931 __le32 addr; 932 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 933 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 934 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 /* doorbell extraction mode specifier- 0 if not used */ 935 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 936 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */ 937 #define DB_LEGACY_ADDR_ICID_SHIFT 5 938 }; 939 940 /* 941 * Structure for doorbell address, in PWM mode 942 */ 943 struct db_pwm_addr 944 { 945 __le32 addr; 946 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 947 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 948 #define DB_PWM_ADDR_OFFSET_MASK 0x7F /* Offset in PWM address space */ 949 #define DB_PWM_ADDR_OFFSET_SHIFT 3 950 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 951 #define DB_PWM_ADDR_WID_SHIFT 10 952 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */ 953 #define DB_PWM_ADDR_DPI_SHIFT 12 954 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 955 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 956 }; 957 958 /* 959 * Parameters to RDMA firmware, passed in EDPM doorbell 960 */ 961 struct db_rdma_dpm_params 962 { 963 __le32 params; 964 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 965 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 966 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 967 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 968 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF /* opcode for RDMA operation */ 969 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 970 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF /* the size of the WQE payload in bytes */ 971 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 972 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 973 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 974 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 /* RoCE completion flag */ 975 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 976 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ 977 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 978 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 979 #define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 980 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 /* Connection type is iWARP */ 981 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 982 }; 983 984 /* 985 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a DPM burst 986 */ 987 struct db_rdma_dpm_data 988 { 989 __le16 icid /* internal CID */; 990 __le16 prod_val /* aggregated value to update */; 991 struct db_rdma_dpm_params params /* parametes passed to RDMA firmware */; 992 }; 993 994 /* 995 * Igu interrupt command 996 */ 997 enum igu_int_cmd 998 { 999 IGU_INT_ENABLE=0, 1000 IGU_INT_DISABLE=1, 1001 IGU_INT_NOP=2, 1002 IGU_INT_NOP2=3, 1003 MAX_IGU_INT_CMD 1004 }; 1005 1006 /* 1007 * IGU producer or consumer update command 1008 */ 1009 struct igu_prod_cons_update 1010 { 1011 __le32 sb_id_and_flags; 1012 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 1013 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 1014 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 1015 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 1016 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 /* interrupt enable/disable/nop (use enum igu_int_cmd) */ 1017 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 1018 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 /* (use enum igu_seg_access) */ 1019 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 1020 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 1021 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 1022 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 1023 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 1024 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 /* must always be set cleared (use enum command_type_bit) */ 1025 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 1026 __le32 reserved1; 1027 }; 1028 1029 /* 1030 * Igu segments access for default status block only 1031 */ 1032 enum igu_seg_access 1033 { 1034 IGU_SEG_ACCESS_REG=0, 1035 IGU_SEG_ACCESS_ATTN=1, 1036 MAX_IGU_SEG_ACCESS 1037 }; 1038 1039 /* 1040 * Enumeration for L3 type field of parsing_and_err_flags. L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) 1041 */ 1042 enum l3_type 1043 { 1044 e_l3_type_unknown, 1045 e_l3_type_ipv4, 1046 e_l3_type_ipv6, 1047 MAX_L3_TYPE 1048 }; 1049 1050 /* 1051 * Enumeration for l4Protocol field of parsing_and_err_flags. L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. 1052 */ 1053 enum l4_protocol 1054 { 1055 e_l4_protocol_none, 1056 e_l4_protocol_tcp, 1057 e_l4_protocol_udp, 1058 MAX_L4_PROTOCOL 1059 }; 1060 1061 /* 1062 * Parsing and error flags field. 1063 */ 1064 struct parsing_and_err_flags 1065 { 1066 __le16 flags; 1067 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) (use enum l3_type) */ 1068 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1069 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. (use enum l4_protocol) */ 1070 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1071 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 /* Set if the packet is IPv4/IPv6 fragment. */ 1072 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1073 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 /* corresponds to the same 8021q tag that is selected for 8021q-tag fiel. This flag should be set if the tag appears in the packet, regardless of its value. */ 1074 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1075 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 /* Set if L4 checksum was calculated. taken from the EOP descriptor. */ 1076 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1077 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 /* Set for PTP packet. */ 1078 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1079 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 /* Set if PTP timestamp recorded. */ 1080 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1081 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6 ver mismatch */ 1082 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1083 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 /* Set if L4 checksum validation failed. Valid only if L4 checksum was calculated. */ 1084 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1085 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ 1086 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1087 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 /* This flag should be set if the tag appears in the packet tunnel header, regardless of its value.. */ 1088 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1089 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch */ 1090 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1091 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 /* taken from the EOP descriptor. */ 1092 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1093 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum was calculated. */ 1094 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1095 }; 1096 1097 /* 1098 * Parsing error flags bitmap. 1099 */ 1100 struct parsing_err_flags 1101 { 1102 __le16 flags; 1103 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 /* MAC error indication */ 1104 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1105 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 /* truncation error indication */ 1106 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1107 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 /* packet too small indication */ 1108 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1109 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 /* Header Missing Tag */ 1110 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1111 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 /* from frame cracker output */ 1112 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1113 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 /* from frame cracker output */ 1114 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1115 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len indicates number that is bigger than real packet length 3. tunneling: total-ip-length of the outer header points to offset that is smaller than the one pointed to by the total-ip-len of the inner hdr. */ 1116 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1117 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1118 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1119 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 /* from frame cracker output. for either TCP or UDP */ 1120 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1121 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 /* from frame cracker output */ 1122 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1123 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 /* cksm calculated and value isnt 0xffff or L4-cksm-wasnt-calculated for any reason, like: udp/ipv4 checksum is 0 etc. */ 1124 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1125 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 /* from frame cracker output */ 1126 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1127 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 /* from frame cracker output */ 1128 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1129 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 /* set if geneve option size was over 32 byte */ 1130 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1131 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1132 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1133 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1134 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1135 }; 1136 1137 /* 1138 * Pb context 1139 */ 1140 struct pb_context 1141 { 1142 __le32 crc[4]; 1143 }; 1144 1145 /* 1146 * Concrete Function ID. 1147 */ 1148 struct pxp_concrete_fid 1149 { 1150 __le16 fid; 1151 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1152 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1153 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */ 1154 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1155 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */ 1156 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1157 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1158 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1159 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1160 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1161 }; 1162 1163 /* 1164 * Concrete Function ID. 1165 */ 1166 struct pxp_pretend_concrete_fid 1167 { 1168 __le16 fid; 1169 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1170 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1171 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 /* port number. Only when part of ME register. */ 1172 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1173 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1174 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1175 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1176 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1177 }; 1178 1179 /* 1180 * Function ID. 1181 */ 1182 union pxp_pretend_fid 1183 { 1184 struct pxp_pretend_concrete_fid concrete_fid; 1185 __le16 opaque_fid; 1186 }; 1187 1188 /* 1189 * Pxp Pretend Command Register. 1190 */ 1191 struct pxp_pretend_cmd 1192 { 1193 union pxp_pretend_fid fid; 1194 __le16 control; 1195 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1196 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1197 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1198 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1199 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1200 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1201 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1202 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1203 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1204 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1205 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 /* is pretend mode? */ 1206 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1207 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 /* is pretend mode? */ 1208 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1209 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 /* is pretend mode? */ 1210 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1211 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 /* is fid concrete? */ 1212 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1213 }; 1214 1215 /* 1216 * PTT Record in PXP Admin Window. 1217 */ 1218 struct pxp_ptt_entry 1219 { 1220 __le32 offset; 1221 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1222 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1223 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1224 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1225 struct pxp_pretend_cmd pretend; 1226 }; 1227 1228 /* 1229 * VF Zone A Permission Register. 1230 */ 1231 struct pxp_vf_zone_a_permission 1232 { 1233 __le32 control; 1234 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1235 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1236 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1237 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1238 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1239 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1240 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1241 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1242 }; 1243 1244 /* 1245 * Rdif context 1246 */ 1247 struct rdif_task_context 1248 { 1249 __le32 initial_ref_tag; 1250 __le16 app_tag_value; 1251 __le16 app_tag_mask; 1252 u8 flags0; 1253 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1254 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1255 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1256 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1257 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1258 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1259 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1260 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1261 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1262 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1263 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1264 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1265 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 /* Keep reference tag constant */ 1266 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7 1267 u8 partial_dif_data[7]; 1268 __le16 partial_crc_value; 1269 __le16 partial_checksum_value; 1270 __le32 offset_in_io; 1271 __le16 flags1; 1272 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1273 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1274 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1275 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1276 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1277 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1278 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1279 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1280 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1281 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1282 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1283 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1284 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1285 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1286 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1287 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1288 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1289 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1290 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1291 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1292 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1293 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1294 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 /* Forward application tag with mask */ 1295 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14 1296 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 /* Forward reference tag with mask */ 1297 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15 1298 __le16 state; 1299 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF 1300 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0 1301 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF 1302 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4 1303 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1 1304 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8 1305 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1 1306 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9 1307 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF /* mask for refernce tag handling */ 1308 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10 1309 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1310 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1311 __le32 reserved2; 1312 }; 1313 1314 /* 1315 * status block structure 1316 */ 1317 struct status_block_e4 1318 { 1319 __le16 pi_array[PIS_PER_SB_E4]; 1320 __le32 sb_num; 1321 #define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF 1322 #define STATUS_BLOCK_E4_SB_NUM_SHIFT 0 1323 #define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F 1324 #define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9 1325 #define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF 1326 #define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16 1327 __le32 prod_index; 1328 #define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF 1329 #define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0 1330 #define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF 1331 #define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24 1332 }; 1333 1334 /* 1335 * status block structure 1336 */ 1337 struct status_block_e5 1338 { 1339 __le16 pi_array[PIS_PER_SB_E5]; 1340 __le32 sb_num; 1341 #define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF 1342 #define STATUS_BLOCK_E5_SB_NUM_SHIFT 0 1343 #define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F 1344 #define STATUS_BLOCK_E5_ZERO_PAD_SHIFT 9 1345 #define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF 1346 #define STATUS_BLOCK_E5_ZERO_PAD2_SHIFT 16 1347 __le32 prod_index; 1348 #define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF 1349 #define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0 1350 #define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF 1351 #define STATUS_BLOCK_E5_ZERO_PAD3_SHIFT 24 1352 }; 1353 1354 /* 1355 * Tdif context 1356 */ 1357 struct tdif_task_context 1358 { 1359 __le32 initial_ref_tag; 1360 __le16 app_tag_value; 1361 __le16 app_tag_mask; 1362 __le16 partial_crc_value_b; 1363 __le16 partial_checksum_value_b; 1364 __le16 stateB; 1365 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF 1366 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0 1367 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF 1368 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4 1369 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1 1370 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8 1371 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1 1372 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9 1373 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1374 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1375 u8 reserved1; 1376 u8 flags0; 1377 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1 1378 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0 1379 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1 1380 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1 1381 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1382 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2 1383 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1 1384 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3 1385 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1386 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4 1387 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1388 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1389 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1390 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1391 __le32 flags1; 1392 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1 1393 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0 1394 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1 1395 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1 1396 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1 1397 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2 1398 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1 1399 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3 1400 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1 1401 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4 1402 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1 1403 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5 1404 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1405 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6 1406 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1407 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9 1408 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1409 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11 1410 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */ 1411 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1412 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1413 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13 1414 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF 1415 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14 1416 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF 1417 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18 1418 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1 1419 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22 1420 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1 1421 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23 1422 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF /* mask for refernce tag handling */ 1423 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24 1424 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1 /* Forward application tag with mask */ 1425 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28 1426 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1 /* Forward reference tag with mask */ 1427 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29 1428 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1 /* Keep reference tag constant */ 1429 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30 1430 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1431 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1432 __le32 offset_in_io_b; 1433 __le16 partial_crc_value_a; 1434 __le16 partial_checksum_value_a; 1435 __le32 offset_in_io_a; 1436 u8 partial_dif_data_a[8]; 1437 u8 partial_dif_data_b[8]; 1438 }; 1439 1440 /* 1441 * Timers context 1442 */ 1443 struct timers_context 1444 { 1445 __le32 logical_client_0; 1446 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF /* Expiration time of logical client 0 */ 1447 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1448 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1449 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1450 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 /* Valid bit of logical client 0 */ 1451 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1452 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 /* Active bit of logical client 0 */ 1453 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1454 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1455 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1456 __le32 logical_client_1; 1457 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF /* Expiration time of logical client 1 */ 1458 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1459 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1460 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1461 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 /* Valid bit of logical client 1 */ 1462 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1463 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 /* Active bit of logical client 1 */ 1464 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1465 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1466 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1467 __le32 logical_client_2; 1468 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF /* Expiration time of logical client 2 */ 1469 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1470 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1471 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1472 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 /* Valid bit of logical client 2 */ 1473 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1474 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 /* Active bit of logical client 2 */ 1475 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1476 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1477 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1478 __le32 host_expiration_fields; 1479 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF /* Expiration time on host (closest one) */ 1480 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1481 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1482 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1483 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 /* Valid bit of host expiration */ 1484 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1485 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1486 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1487 }; 1488 1489 /* 1490 * Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc 1491 */ 1492 enum tunnel_next_protocol 1493 { 1494 e_unknown=0, 1495 e_l2=1, 1496 e_ipv4=2, 1497 e_ipv6=3, 1498 MAX_TUNNEL_NEXT_PROTOCOL 1499 }; 1500 1501 #endif /* __COMMON_HSI__ */ 1502