1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __COMMON_HSI__ 32 #define __COMMON_HSI__ 33 /********************************/ 34 /* PROTOCOL COMMON FW CONSTANTS */ 35 /********************************/ 36 37 /* Temporarily here should be added to HSI automatically by resource allocation tool.*/ 38 #define T_TEST_AGG_INT_TEMP 6 39 #define M_TEST_AGG_INT_TEMP 8 40 #define U_TEST_AGG_INT_TEMP 6 41 #define X_TEST_AGG_INT_TEMP 14 42 #define Y_TEST_AGG_INT_TEMP 4 43 #define P_TEST_AGG_INT_TEMP 4 44 45 #define X_FINAL_CLEANUP_AGG_INT 1 46 47 #define EVENT_RING_PAGE_SIZE_BYTES 4096 48 49 #define NUM_OF_GLOBAL_QUEUES 128 50 #define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64 51 52 #define ISCSI_CDU_TASK_SEG_TYPE 0 53 #define FCOE_CDU_TASK_SEG_TYPE 0 54 #define RDMA_CDU_TASK_SEG_TYPE 1 55 56 #define FW_ASSERT_GENERAL_ATTN_IDX 32 57 58 #define MAX_PINNED_CCFC 32 59 60 #define EAGLE_ENG1_WORKAROUND_NIG_FLOWCTRL_MODE 3 61 62 /* Queue Zone sizes in bytes */ 63 #define TSTORM_QZONE_SIZE 8 /*tstorm_scsi_queue_zone*/ 64 #define MSTORM_QZONE_SIZE 16 /*mstorm_eth_queue_zone. Used only for RX producer of VFs in backward compatibility mode.*/ 65 #define USTORM_QZONE_SIZE 8 /*ustorm_eth_queue_zone*/ 66 #define XSTORM_QZONE_SIZE 8 /*xstorm_eth_queue_zone*/ 67 #define YSTORM_QZONE_SIZE 0 68 #define PSTORM_QZONE_SIZE 0 69 70 #define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7 /*Log of mstorm default VF zone size.*/ 71 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16 /*Maximum number of RX queues that can be allocated to VF by default*/ 72 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48 /*Maximum number of RX queues that can be allocated to VF with doubled VF zone size. Up to 96 VF supported in this mode*/ 73 #define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112 /*Maximum number of RX queues that can be allocated to VF with 4 VF zone size. Up to 48 VF supported in this mode*/ 74 75 76 /********************************/ 77 /* CORE (LIGHT L2) FW CONSTANTS */ 78 /********************************/ 79 80 #define CORE_LL2_MAX_RAMROD_PER_CON 8 81 #define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096 82 #define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096 83 #define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096 84 #define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1 85 86 #define CORE_LL2_TX_MAX_BDS_PER_PACKET 12 87 88 #define CORE_SPQE_PAGE_SIZE_BYTES 4096 89 90 /* 91 * Usually LL2 queues are opened in pairs TX-RX. 92 * There is a hard restriction on number of RX queues (limited by Tstorm RAM) and TX counters (Pstorm RAM). 93 * Number of TX queues is almost unlimited. 94 * The constants are different so as to allow asymmetric LL2 connections 95 */ 96 97 #define MAX_NUM_LL2_RX_QUEUES 48 98 #define MAX_NUM_LL2_TX_STATS_COUNTERS 48 99 100 101 /////////////////////////////////////////////////////////////////////////////////////////////////// 102 // Include firmware version number only- do not add constants here to avoid redundunt compilations 103 /////////////////////////////////////////////////////////////////////////////////////////////////// 104 105 106 #define FW_MAJOR_VERSION 8 107 #define FW_MINOR_VERSION 18 108 #define FW_REVISION_VERSION 14 109 #define FW_ENGINEERING_VERSION 0 110 111 /***********************/ 112 /* COMMON HW CONSTANTS */ 113 /***********************/ 114 115 /* PCI functions */ 116 #define MAX_NUM_PORTS_K2 (4) 117 #define MAX_NUM_PORTS_BB (2) 118 #define MAX_NUM_PORTS (MAX_NUM_PORTS_K2) 119 120 #define MAX_NUM_PFS_K2 (16) 121 #define MAX_NUM_PFS_BB (8) 122 #define MAX_NUM_PFS (MAX_NUM_PFS_K2) 123 #define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */ 124 125 #define MAX_NUM_VFS_BB (120) 126 #define MAX_NUM_VFS_K2 (192) 127 #define E4_MAX_NUM_VFS (MAX_NUM_VFS_K2) 128 #define E5_MAX_NUM_VFS (240) 129 #define COMMON_MAX_NUM_VFS (E5_MAX_NUM_VFS) 130 131 #define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB) 132 #define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2) 133 #define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + E4_MAX_NUM_VFS) 134 135 /* in both BB and K2, the VF number starts from 16. so for arrays containing all */ 136 /* possible PFs and VFs - we need a constant for this size */ 137 #define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB) 138 #define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2) 139 #define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + E4_MAX_NUM_VFS) 140 141 #define MAX_NUM_VPORTS_K2 (208) 142 #define MAX_NUM_VPORTS_BB (160) 143 #define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2) 144 145 #define MAX_NUM_L2_QUEUES_K2 (320) 146 #define MAX_NUM_L2_QUEUES_BB (256) 147 #define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2) 148 149 /* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */ 150 // 4-Port K2. 151 #define NUM_PHYS_TCS_4PORT_K2 (4) 152 #define NUM_OF_PHYS_TCS (8) 153 154 #define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1) 155 #define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1) 156 157 #define LB_TC (NUM_OF_PHYS_TCS) 158 159 /* Num of possible traffic priority values */ 160 #define NUM_OF_PRIO (8) 161 162 #define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2) 163 #define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB) 164 #define MAX_NUM_VOQS (MAX_NUM_VOQS_K2) 165 #define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB) 166 167 /* CIDs */ 168 #define E4_NUM_OF_CONNECTION_TYPES (8) 169 #define E5_NUM_OF_CONNECTION_TYPES (16) 170 #define NUM_OF_TASK_TYPES (8) 171 #define NUM_OF_LCIDS (320) 172 #define NUM_OF_LTIDS (320) 173 174 /* Clock values */ 175 #define MASTER_CLK_FREQ_E4 (375e6) 176 #define STORM_CLK_FREQ_E4 (1000e6) 177 #define CLK25M_CLK_FREQ_E4 (25e6) 178 179 #define STORM_CLK_DUAL_CORE_FREQ_E5 (3000e6) 180 181 /* Global PXP windows (GTT) */ 182 #define NUM_OF_GTT 19 183 #define GTT_DWORD_SIZE_BITS 10 184 #define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2) 185 #define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS) 186 187 /* Tools Version */ 188 #define TOOLS_VERSION 10 189 /*****************/ 190 /* CDU CONSTANTS */ 191 /*****************/ 192 193 #define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17) 194 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff) 195 196 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12) 197 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff) 198 199 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0) 200 #define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1) 201 #define CDU_CONTEXT_VALIDATION_CFG_USE_TYPE (2) 202 #define CDU_CONTEXT_VALIDATION_CFG_USE_REGION (3) 203 #define CDU_CONTEXT_VALIDATION_CFG_USE_CID (4) 204 #define CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE (5) 205 206 207 /*****************/ 208 /* DQ CONSTANTS */ 209 /*****************/ 210 211 /* DEMS */ 212 #define DQ_DEMS_LEGACY 0 213 #define DQ_DEMS_TOE_MORE_TO_SEND 3 214 #define DQ_DEMS_TOE_LOCAL_ADV_WND 4 215 #define DQ_DEMS_ROCE_CQ_CONS 7 216 217 /* XCM agg val selection (HW) */ 218 #define DQ_XCM_AGG_VAL_SEL_WORD2 0 219 #define DQ_XCM_AGG_VAL_SEL_WORD3 1 220 #define DQ_XCM_AGG_VAL_SEL_WORD4 2 221 #define DQ_XCM_AGG_VAL_SEL_WORD5 3 222 #define DQ_XCM_AGG_VAL_SEL_REG3 4 223 #define DQ_XCM_AGG_VAL_SEL_REG4 5 224 #define DQ_XCM_AGG_VAL_SEL_REG5 6 225 #define DQ_XCM_AGG_VAL_SEL_REG6 7 226 227 /* XCM agg val selection (FW) */ 228 #define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 229 #define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 230 #define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 231 #define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2 232 #define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 233 #define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 234 #define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5 235 #define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 236 #define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 237 #define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5 238 #define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3 239 #define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 240 #define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 241 #define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6 242 #define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 243 #define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4 244 #define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3 245 #define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4 246 247 /* UCM agg val selection (HW) */ 248 #define DQ_UCM_AGG_VAL_SEL_WORD0 0 249 #define DQ_UCM_AGG_VAL_SEL_WORD1 1 250 #define DQ_UCM_AGG_VAL_SEL_WORD2 2 251 #define DQ_UCM_AGG_VAL_SEL_WORD3 3 252 #define DQ_UCM_AGG_VAL_SEL_REG0 4 253 #define DQ_UCM_AGG_VAL_SEL_REG1 5 254 #define DQ_UCM_AGG_VAL_SEL_REG2 6 255 #define DQ_UCM_AGG_VAL_SEL_REG3 7 256 257 /* UCM agg val selection (FW) */ 258 #define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2 259 #define DQ_UCM_ETH_PMD_RX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD3 260 #define DQ_UCM_ROCE_CQ_CONS_CMD DQ_UCM_AGG_VAL_SEL_REG0 261 #define DQ_UCM_ROCE_CQ_PROD_CMD DQ_UCM_AGG_VAL_SEL_REG2 262 263 /* TCM agg val selection (HW) */ 264 #define DQ_TCM_AGG_VAL_SEL_WORD0 0 265 #define DQ_TCM_AGG_VAL_SEL_WORD1 1 266 #define DQ_TCM_AGG_VAL_SEL_WORD2 2 267 #define DQ_TCM_AGG_VAL_SEL_WORD3 3 268 #define DQ_TCM_AGG_VAL_SEL_REG1 4 269 #define DQ_TCM_AGG_VAL_SEL_REG2 5 270 #define DQ_TCM_AGG_VAL_SEL_REG6 6 271 #define DQ_TCM_AGG_VAL_SEL_REG9 7 272 273 /* TCM agg val selection (FW) */ 274 #define DQ_TCM_L2B_BD_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD1 275 #define DQ_TCM_ROCE_RQ_PROD_CMD DQ_TCM_AGG_VAL_SEL_WORD0 276 277 /* XCM agg counter flag selection (HW) */ 278 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0 279 #define DQ_XCM_AGG_FLG_SHIFT_BIT15 1 280 #define DQ_XCM_AGG_FLG_SHIFT_CF12 2 281 #define DQ_XCM_AGG_FLG_SHIFT_CF13 3 282 #define DQ_XCM_AGG_FLG_SHIFT_CF18 4 283 #define DQ_XCM_AGG_FLG_SHIFT_CF19 5 284 #define DQ_XCM_AGG_FLG_SHIFT_CF22 6 285 #define DQ_XCM_AGG_FLG_SHIFT_CF23 7 286 287 /* XCM agg counter flag selection (FW) */ 288 #define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 289 #define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 290 #define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 291 #define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18) 292 #define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 293 #define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 294 #define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 295 #define DQ_XCM_FCOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 296 #define DQ_XCM_ISCSI_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 297 #define DQ_XCM_ISCSI_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 298 #define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23) 299 #define DQ_XCM_TOE_DQ_FLUSH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19) 300 #define DQ_XCM_TOE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22) 301 302 /* UCM agg counter flag selection (HW) */ 303 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0 304 #define DQ_UCM_AGG_FLG_SHIFT_CF1 1 305 #define DQ_UCM_AGG_FLG_SHIFT_CF3 2 306 #define DQ_UCM_AGG_FLG_SHIFT_CF4 3 307 #define DQ_UCM_AGG_FLG_SHIFT_CF5 4 308 #define DQ_UCM_AGG_FLG_SHIFT_CF6 5 309 #define DQ_UCM_AGG_FLG_SHIFT_RULE0EN 6 310 #define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7 311 312 /* UCM agg counter flag selection (FW) */ 313 #define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 314 #define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 315 #define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 316 #define DQ_UCM_ROCE_CQ_ARM_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 317 #define DQ_UCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF3) 318 #define DQ_UCM_TOE_SLOW_PATH_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4) 319 #define DQ_UCM_TOE_DQ_CF_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5) 320 321 /* TCM agg counter flag selection (HW) */ 322 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0 323 #define DQ_TCM_AGG_FLG_SHIFT_CF1 1 324 #define DQ_TCM_AGG_FLG_SHIFT_CF2 2 325 #define DQ_TCM_AGG_FLG_SHIFT_CF3 3 326 #define DQ_TCM_AGG_FLG_SHIFT_CF4 4 327 #define DQ_TCM_AGG_FLG_SHIFT_CF5 5 328 #define DQ_TCM_AGG_FLG_SHIFT_CF6 6 329 #define DQ_TCM_AGG_FLG_SHIFT_CF7 7 330 331 /* TCM agg counter flag selection (FW) */ 332 #define DQ_TCM_FCOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 333 #define DQ_TCM_FCOE_DUMMY_TIMER_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF2) 334 #define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 335 #define DQ_TCM_ISCSI_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 336 #define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 337 #define DQ_TCM_TOE_FLUSH_Q0_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 338 #define DQ_TCM_TOE_TIMER_STOP_ALL_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF3) 339 #define DQ_TCM_IWARP_POST_RQ_CF_CMD (1 << DQ_TCM_AGG_FLG_SHIFT_CF1) 340 341 /* PWM address mapping */ 342 #define DQ_PWM_OFFSET_DPM_BASE 0x0 343 #define DQ_PWM_OFFSET_DPM_END 0x27 344 #define DQ_PWM_OFFSET_XCM16_BASE 0x40 345 #define DQ_PWM_OFFSET_XCM32_BASE 0x44 346 #define DQ_PWM_OFFSET_UCM16_BASE 0x48 347 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C 348 #define DQ_PWM_OFFSET_UCM16_4 0x50 349 #define DQ_PWM_OFFSET_TCM16_BASE 0x58 350 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C 351 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68 352 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69 353 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B 354 355 #define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2) 356 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE) 357 #define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4) 358 #define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2) 359 #define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS) 360 #define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1) 361 #define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3) 362 363 #define DQ_REGION_SHIFT (12) 364 365 /* DPM */ 366 #define DQ_DPM_WQE_BUFF_SIZE (320) 367 368 // Conn type ranges 369 #define DQ_CONN_TYPE_RANGE_SHIFT (4) 370 371 /*****************/ 372 /* QM CONSTANTS */ 373 /*****************/ 374 375 /* number of TX queues in the QM */ 376 #define MAX_QM_TX_QUEUES_K2 512 377 #define MAX_QM_TX_QUEUES_BB 448 378 #define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2 379 380 /* number of Other queues in the QM */ 381 #define MAX_QM_OTHER_QUEUES_BB 64 382 #define MAX_QM_OTHER_QUEUES_K2 128 383 #define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2 384 385 /* number of queues in a PF queue group */ 386 #define QM_PF_QUEUE_GROUP_SIZE 8 387 388 /* the size of a single queue element in bytes */ 389 #define QM_PQ_ELEMENT_SIZE 4 390 391 /* base number of Tx PQs in the CM PQ representation. 392 should be used when storing PQ IDs in CM PQ registers and context */ 393 #define CM_TX_PQ_BASE 0x200 394 395 /* number of global Vport/QCN rate limiters */ 396 #define MAX_QM_GLOBAL_RLS 256 397 398 /* QM registers data */ 399 #define QM_LINE_CRD_REG_WIDTH 16 400 #define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1)) 401 #define QM_BYTE_CRD_REG_WIDTH 24 402 #define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1)) 403 #define QM_WFQ_CRD_REG_WIDTH 32 404 #define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1)) 405 #define QM_RL_CRD_REG_WIDTH 32 406 #define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1)) 407 408 /*****************/ 409 /* CAU CONSTANTS */ 410 /*****************/ 411 412 #define CAU_FSM_ETH_RX 0 413 #define CAU_FSM_ETH_TX 1 414 415 /* Number of Protocol Indices per Status Block */ 416 #define PIS_PER_SB 12 417 418 419 #define CAU_HC_STOPPED_STATE 3 /* fsm is stopped or not valid for this sb */ 420 #define CAU_HC_DISABLE_STATE 4 /* fsm is working without interrupt coalescing for this sb*/ 421 #define CAU_HC_ENABLE_STATE 0 /* fsm is working with interrupt coalescing for this sb*/ 422 423 424 /*****************/ 425 /* IGU CONSTANTS */ 426 /*****************/ 427 428 #define MAX_SB_PER_PATH_K2 (368) 429 #define MAX_SB_PER_PATH_BB (288) 430 #define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_K2 431 432 #define MAX_SB_PER_PF_MIMD 129 433 #define MAX_SB_PER_PF_SIMD 64 434 #define MAX_SB_PER_VF 64 435 436 /* Memory addresses on the BAR for the IGU Sub Block */ 437 #define IGU_MEM_BASE 0x0000 438 439 #define IGU_MEM_MSIX_BASE 0x0000 440 #define IGU_MEM_MSIX_UPPER 0x0101 441 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 442 443 #define IGU_MEM_PBA_MSIX_BASE 0x0200 444 #define IGU_MEM_PBA_MSIX_UPPER 0x0202 445 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 446 447 #define IGU_CMD_INT_ACK_BASE 0x0400 448 #define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + MAX_TOT_SB_PER_PATH - 1) 449 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff 450 451 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0 452 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1 453 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2 454 455 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3 456 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4 457 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5 458 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6 459 460 #define IGU_CMD_PROD_UPD_BASE 0x0600 461 #define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + MAX_TOT_SB_PER_PATH - 1) 462 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff 463 464 /*****************/ 465 /* PXP CONSTANTS */ 466 /*****************/ 467 468 /* Bars for Blocks */ 469 #define PXP_BAR_GRC 0 470 #define PXP_BAR_TSDM 0 471 #define PXP_BAR_USDM 0 472 #define PXP_BAR_XSDM 0 473 #define PXP_BAR_MSDM 0 474 #define PXP_BAR_YSDM 0 475 #define PXP_BAR_PSDM 0 476 #define PXP_BAR_IGU 0 477 #define PXP_BAR_DQ 1 478 479 /* PTT and GTT */ 480 #define PXP_PER_PF_ENTRY_SIZE 8 481 #define PXP_NUM_GLOBAL_WINDOWS 243 482 #define PXP_GLOBAL_ENTRY_SIZE 4 483 #define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4 484 #define PXP_PF_WINDOW_ADMIN_START 0 485 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000 486 #define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_LENGTH - 1) 487 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0 488 #define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * PXP_PER_PF_ENTRY_SIZE) 489 #define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1) 490 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200 491 #define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * PXP_GLOBAL_ENTRY_SIZE) 492 #define PXP_PF_WINDOW_ADMIN_GLOBAL_END (PXP_PF_WINDOW_ADMIN_GLOBAL_START + PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH - 1) 493 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0 494 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4 495 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8 496 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc 497 498 #define PXP_NUM_PF_WINDOWS 12 499 500 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000 501 #define PXP_EXTERNAL_BAR_PF_WINDOW_NUM PXP_NUM_PF_WINDOWS 502 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000 503 #define PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH (PXP_EXTERNAL_BAR_PF_WINDOW_NUM * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) 504 #define PXP_EXTERNAL_BAR_PF_WINDOW_END (PXP_EXTERNAL_BAR_PF_WINDOW_START + PXP_EXTERNAL_BAR_PF_WINDOW_LENGTH - 1) 505 506 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START (PXP_EXTERNAL_BAR_PF_WINDOW_END + 1) 507 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM PXP_NUM_GLOBAL_WINDOWS 508 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000 509 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_NUM * PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE) 510 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_END (PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1) 511 512 /* PF BAR */ 513 #define PXP_BAR0_START_GRC 0x0000 514 #define PXP_BAR0_GRC_LENGTH 0x1C00000 515 #define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + PXP_BAR0_GRC_LENGTH - 1) 516 517 #define PXP_BAR0_START_IGU 0x1C00000 518 #define PXP_BAR0_IGU_LENGTH 0x10000 519 #define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + PXP_BAR0_IGU_LENGTH - 1) 520 521 #define PXP_BAR0_START_TSDM 0x1C80000 522 #define PXP_BAR0_SDM_LENGTH 0x40000 523 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000 524 #define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + PXP_BAR0_SDM_LENGTH - 1) 525 526 #define PXP_BAR0_START_MSDM 0x1D00000 527 #define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + PXP_BAR0_SDM_LENGTH - 1) 528 529 #define PXP_BAR0_START_USDM 0x1D80000 530 #define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + PXP_BAR0_SDM_LENGTH - 1) 531 532 #define PXP_BAR0_START_XSDM 0x1E00000 533 #define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + PXP_BAR0_SDM_LENGTH - 1) 534 535 #define PXP_BAR0_START_YSDM 0x1E80000 536 #define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + PXP_BAR0_SDM_LENGTH - 1) 537 538 #define PXP_BAR0_START_PSDM 0x1F00000 539 #define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + PXP_BAR0_SDM_LENGTH - 1) 540 541 #define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1) 542 543 /* VF BAR */ 544 #define PXP_VF_BAR0 0 545 546 #define PXP_VF_BAR0_START_GRC 0x3E00 547 #define PXP_VF_BAR0_GRC_LENGTH 0x200 548 #define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1) 549 550 #define PXP_VF_BAR0_START_IGU 0 551 #define PXP_VF_BAR0_IGU_LENGTH 0x3000 552 #define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1) 553 554 #define PXP_VF_BAR0_START_DQ 0x3000 555 #define PXP_VF_BAR0_DQ_LENGTH 0x200 556 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0 557 #define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET) 558 #define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4) 559 #define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1) 560 561 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200 562 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200 563 #define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 564 565 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400 566 #define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 567 568 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600 569 #define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 570 571 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800 572 #define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 573 574 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00 575 #define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 576 577 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00 578 #define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1) 579 580 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000 581 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000 582 583 #define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32 584 585 #define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12 586 #define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024 587 588 // ILT Records 589 #define PXP_NUM_ILT_RECORDS_BB 7600 590 #define PXP_NUM_ILT_RECORDS_K2 11000 591 #define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB,PXP_NUM_ILT_RECORDS_K2) 592 593 594 // Host Interface 595 #define PXP_QUEUES_ZONE_MAX_NUM 320 596 597 598 599 600 /*****************/ 601 /* PRM CONSTANTS */ 602 /*****************/ 603 #define PRM_DMA_PAD_BYTES_NUM 2 604 /*****************/ 605 /* SDMs CONSTANTS */ 606 /*****************/ 607 608 609 #define SDM_OP_GEN_TRIG_NONE 0 610 #define SDM_OP_GEN_TRIG_WAKE_THREAD 1 611 #define SDM_OP_GEN_TRIG_AGG_INT 2 612 #define SDM_OP_GEN_TRIG_LOADER 4 613 #define SDM_OP_GEN_TRIG_INDICATE_ERROR 6 614 #define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9 615 616 ///////////////////////////////////////////////////////////// 617 // Completion types 618 ///////////////////////////////////////////////////////////// 619 620 #define SDM_COMP_TYPE_NONE 0 621 #define SDM_COMP_TYPE_WAKE_THREAD 1 622 #define SDM_COMP_TYPE_AGG_INT 2 623 #define SDM_COMP_TYPE_CM 3 // Send direct message to local CM and/or remote CMs. Destinations are defined by vector in CompParams. 624 #define SDM_COMP_TYPE_LOADER 4 625 #define SDM_COMP_TYPE_PXP 5 // Send direct message to PXP (like "internal write" command) to write to remote Storm RAM via remote SDM 626 #define SDM_COMP_TYPE_INDICATE_ERROR 6 // Indicate error per thread 627 #define SDM_COMP_TYPE_RELEASE_THREAD 7 // Obsolete in E5 628 #define SDM_COMP_TYPE_RAM 8 // Write to local RAM as a completion 629 #define SDM_COMP_TYPE_INC_ORDER_CNT 9 // Applicable only for E4 630 631 /******************/ 632 /* PBF CONSTANTS */ 633 /******************/ 634 635 /* Number of PBF command queue lines. Each line is 32B. */ 636 #define PBF_MAX_CMD_LINES 3328 637 638 /* Number of BTB blocks. Each block is 256B. */ 639 #define BTB_MAX_BLOCKS 1440 640 641 /*****************/ 642 /* PRS CONSTANTS */ 643 /*****************/ 644 645 #define PRS_GFT_CAM_LINES_NO_MATCH 31 646 647 /* 648 * Async data KCQ CQE 649 */ 650 struct async_data 651 { 652 __le32 cid /* Context ID of the connection */; 653 __le16 itid /* Task Id of the task (for error that happened on a a task) */; 654 u8 error_code /* error code - relevant only if the opcode indicates its an error */; 655 u8 fw_debug_param /* internal fw debug parameter */; 656 }; 657 658 659 /* 660 * Interrupt coalescing TimeSet 661 */ 662 struct coalescing_timeset 663 { 664 u8 value; 665 #define COALESCING_TIMESET_TIMESET_MASK 0x7F /* Interrupt coalescing TimeSet (timeout_ticks = TimeSet shl (TimerRes+1)) */ 666 #define COALESCING_TIMESET_TIMESET_SHIFT 0 667 #define COALESCING_TIMESET_VALID_MASK 0x1 /* Only if this flag is set, timeset will take effect */ 668 #define COALESCING_TIMESET_VALID_SHIFT 7 669 }; 670 671 672 struct common_queue_zone 673 { 674 __le16 ring_drv_data_consumer; 675 __le16 reserved; 676 }; 677 678 679 /* 680 * ETH Rx producers data 681 */ 682 struct eth_rx_prod_data 683 { 684 __le16 bd_prod /* BD producer. */; 685 __le16 cqe_prod /* CQE producer. */; 686 }; 687 688 689 struct regpair 690 { 691 __le32 lo /* low word for reg-pair */; 692 __le32 hi /* high word for reg-pair */; 693 }; 694 695 /* 696 * Event Ring VF-PF Channel data 697 */ 698 struct vf_pf_channel_eqe_data 699 { 700 struct regpair msg_addr /* VF-PF message address */; 701 }; 702 703 struct iscsi_eqe_data 704 { 705 __le32 cid /* Context ID of the connection */; 706 __le16 conn_id /* Task Id of the task (for error that happened on a a task) */; 707 u8 error_code /* error code - relevant only if the opcode indicates its an error */; 708 u8 error_pdu_opcode_reserved; 709 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F /* The processed PDUs opcode on which happened the error - updated for specific error codes, by defualt=0xFF */ 710 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0 711 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1 /* Indication for driver is the error_pdu_opcode field has valid value */ 712 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6 713 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1 714 #define ISCSI_EQE_DATA_RESERVED0_SHIFT 7 715 }; 716 717 /* 718 * RoCE Destroy Event Data 719 */ 720 struct rdma_eqe_destroy_qp 721 { 722 __le32 cid /* Dedicated field RoCE destroy QP event */; 723 u8 reserved[4]; 724 }; 725 726 /* 727 * RDMA Event Data Union 728 */ 729 union rdma_eqe_data 730 { 731 struct regpair async_handle /* Host handle for the Async Completions */; 732 struct rdma_eqe_destroy_qp rdma_destroy_qp_data /* RoCE Destroy Event Data */; 733 }; 734 735 /* 736 * Event Ring malicious VF data 737 */ 738 struct malicious_vf_eqe_data 739 { 740 u8 vfId /* Malicious VF ID */; 741 u8 errId /* Malicious VF error */; 742 __le16 reserved[3]; 743 }; 744 745 /* 746 * Event Ring initial cleanup data 747 */ 748 struct initial_cleanup_eqe_data 749 { 750 u8 vfId /* VF ID */; 751 u8 reserved[7]; 752 }; 753 754 /* 755 * Event Data Union 756 */ 757 union event_ring_data 758 { 759 u8 bytes[8] /* Byte Array */; 760 struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */; 761 struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */; 762 union rdma_eqe_data rdma_data /* Dedicated field for RDMA data */; 763 struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */; 764 struct initial_cleanup_eqe_data vf_init_cleanup /* VF Initial Cleanup data */; 765 }; 766 767 768 /* 769 * Event Ring Entry 770 */ 771 struct event_ring_entry 772 { 773 u8 protocol_id /* Event Protocol ID */; 774 u8 opcode /* Event Opcode */; 775 __le16 reserved0 /* Reserved */; 776 __le16 echo /* Echo value from ramrod data on the host */; 777 u8 fw_return_code /* FW return code for SP ramrods */; 778 u8 flags; 779 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */ 780 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 781 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 782 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 783 union event_ring_data data; 784 }; 785 786 787 788 789 790 /* 791 * Multi function mode 792 */ 793 enum mf_mode 794 { 795 ERROR_MODE /* Unsupported mode */, 796 MF_OVLAN /* Multi function based on outer VLAN */, 797 MF_NPAR /* Multi function based on MAC address (NIC partitioning) */, 798 MAX_MF_MODE 799 }; 800 801 802 /* 803 * Per-protocol connection types 804 */ 805 enum protocol_type 806 { 807 PROTOCOLID_ISCSI /* iSCSI */, 808 PROTOCOLID_FCOE /* FCoE */, 809 PROTOCOLID_ROCE /* RoCE */, 810 PROTOCOLID_CORE /* Core (light L2, slow path core) */, 811 PROTOCOLID_ETH /* Ethernet */, 812 PROTOCOLID_IWARP /* iWARP */, 813 PROTOCOLID_TOE /* TOE */, 814 PROTOCOLID_PREROCE /* Pre (tapeout) RoCE */, 815 PROTOCOLID_COMMON /* ProtocolCommon */, 816 PROTOCOLID_TCP /* TCP */, 817 MAX_PROTOCOL_TYPE 818 }; 819 820 821 822 823 /* 824 * Ustorm Queue Zone 825 */ 826 struct ustorm_eth_queue_zone 827 { 828 struct coalescing_timeset int_coalescing_timeset /* Rx interrupt coalescing TimeSet */; 829 u8 reserved[3]; 830 }; 831 832 833 struct ustorm_queue_zone 834 { 835 struct ustorm_eth_queue_zone eth; 836 struct common_queue_zone common; 837 }; 838 839 840 841 /* 842 * status block structure 843 */ 844 struct cau_pi_entry 845 { 846 __le32 prod; 847 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF /* A per protocol indexPROD value. */ 848 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0 849 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F /* This value determines the TimeSet that the PI is associated with */ 850 #define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16 851 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1 /* Select the FSM within the SB */ 852 #define CAU_PI_ENTRY_FSM_SEL_SHIFT 23 853 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF /* Select the FSM within the SB */ 854 #define CAU_PI_ENTRY_RESERVED_SHIFT 24 855 }; 856 857 858 /* 859 * status block structure 860 */ 861 struct cau_sb_entry 862 { 863 __le32 data; 864 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF /* The SB PROD index which is sent to the IGU. */ 865 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0 866 #define CAU_SB_ENTRY_STATE0_MASK 0xF /* RX state */ 867 #define CAU_SB_ENTRY_STATE0_SHIFT 24 868 #define CAU_SB_ENTRY_STATE1_MASK 0xF /* TX state */ 869 #define CAU_SB_ENTRY_STATE1_SHIFT 28 870 __le32 params; 871 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F /* Indicates the RX TimeSet that this SB is associated with. */ 872 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0 873 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F /* Indicates the TX TimeSet that this SB is associated with. */ 874 #define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7 875 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3 /* This value will determine the RX FSM timer resolution in ticks */ 876 #define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14 877 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3 /* This value will determine the TX FSM timer resolution in ticks */ 878 #define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16 879 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF 880 #define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18 881 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1 882 #define CAU_SB_ENTRY_VF_VALID_SHIFT 26 883 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF 884 #define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27 885 #define CAU_SB_ENTRY_TPH_MASK 0x1 /* If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones. */ 886 #define CAU_SB_ENTRY_TPH_SHIFT 31 887 }; 888 889 890 /* 891 * core doorbell data 892 */ 893 struct core_db_data 894 { 895 u8 params; 896 #define CORE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 897 #define CORE_DB_DATA_DEST_SHIFT 0 898 #define CORE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 899 #define CORE_DB_DATA_AGG_CMD_SHIFT 2 900 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 901 #define CORE_DB_DATA_BYPASS_EN_SHIFT 4 902 #define CORE_DB_DATA_RESERVED_MASK 0x1 903 #define CORE_DB_DATA_RESERVED_SHIFT 5 904 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 905 #define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6 906 u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 907 __le16 spq_prod; 908 }; 909 910 911 /* 912 * Enum of doorbell aggregative command selection 913 */ 914 enum db_agg_cmd_sel 915 { 916 DB_AGG_CMD_NOP /* No operation */, 917 DB_AGG_CMD_SET /* Set the value */, 918 DB_AGG_CMD_ADD /* Add the value */, 919 DB_AGG_CMD_MAX /* Set max of current and new value */, 920 MAX_DB_AGG_CMD_SEL 921 }; 922 923 924 /* 925 * Enum of doorbell destination 926 */ 927 enum db_dest 928 { 929 DB_DEST_XCM /* TX doorbell to XCM */, 930 DB_DEST_UCM /* RX doorbell to UCM */, 931 DB_DEST_TCM /* RX doorbell to TCM */, 932 DB_NUM_DESTINATIONS, 933 MAX_DB_DEST 934 }; 935 936 937 /* 938 * Enum of doorbell DPM types 939 */ 940 enum db_dpm_type 941 { 942 DPM_LEGACY /* Legacy DPM- to Xstorm RAM */, 943 DPM_RDMA /* RDMA DPM (only RoCE in E4) - to NIG */, 944 DPM_L2_INLINE /* L2 DPM inline- to PBF, with packet data on doorbell */, 945 DPM_L2_BD /* L2 DPM with BD- to PBF, with TX BD data on doorbell */, 946 MAX_DB_DPM_TYPE 947 }; 948 949 950 /* 951 * Structure for doorbell data, in L2 DPM mode, for the first doorbell in a DPM burst 952 */ 953 struct db_l2_dpm_data 954 { 955 __le16 icid /* internal CID */; 956 __le16 bd_prod /* bd producer value to update */; 957 __le32 params; 958 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 959 #define DB_L2_DPM_DATA_SIZE_SHIFT 0 960 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3 /* Type of DPM transaction (DPM_L2_INLINE or DPM_L2_BD) (use enum db_dpm_type) */ 961 #define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6 962 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF /* number of BD-s */ 963 #define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8 964 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF /* size of the packet to be transmitted in bytes */ 965 #define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16 966 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1 967 #define DB_L2_DPM_DATA_RESERVED0_SHIFT 27 968 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7 /* In DPM_L2_BD mode: the number of SGE-s */ 969 #define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28 970 #define DB_L2_DPM_DATA_GFS_SRC_EN_MASK 0x1 /* Flag indicating whether to enable GFS search */ 971 #define DB_L2_DPM_DATA_GFS_SRC_EN_SHIFT 31 972 }; 973 974 975 /* 976 * Structure for SGE in a DPM doorbell of type DPM_L2_BD 977 */ 978 struct db_l2_dpm_sge 979 { 980 struct regpair addr /* Single continuous buffer */; 981 __le16 nbytes /* Number of bytes in this BD. */; 982 __le16 bitfields; 983 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF /* The TPH STAG index value */ 984 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0 985 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3 986 #define DB_L2_DPM_SGE_RESERVED0_SHIFT 9 987 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1 /* Indicate if ST hint is requested or not */ 988 #define DB_L2_DPM_SGE_ST_VALID_SHIFT 11 989 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF 990 #define DB_L2_DPM_SGE_RESERVED1_SHIFT 12 991 __le32 reserved2; 992 }; 993 994 995 /* 996 * Structure for doorbell address, in legacy mode 997 */ 998 struct db_legacy_addr 999 { 1000 __le32 addr; 1001 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3 1002 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0 1003 #define DB_LEGACY_ADDR_DEMS_MASK 0x7 /* doorbell extraction mode specifier- 0 if not used */ 1004 #define DB_LEGACY_ADDR_DEMS_SHIFT 2 1005 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF /* internal CID */ 1006 #define DB_LEGACY_ADDR_ICID_SHIFT 5 1007 }; 1008 1009 1010 /* 1011 * Structure for doorbell address, in PWM mode 1012 */ 1013 struct db_pwm_addr 1014 { 1015 __le32 addr; 1016 #define DB_PWM_ADDR_RESERVED0_MASK 0x7 1017 #define DB_PWM_ADDR_RESERVED0_SHIFT 0 1018 #define DB_PWM_ADDR_OFFSET_MASK 0x7F /* Offset in PWM address space */ 1019 #define DB_PWM_ADDR_OFFSET_SHIFT 3 1020 #define DB_PWM_ADDR_WID_MASK 0x3 /* Window ID */ 1021 #define DB_PWM_ADDR_WID_SHIFT 10 1022 #define DB_PWM_ADDR_DPI_MASK 0xFFFF /* Doorbell page ID */ 1023 #define DB_PWM_ADDR_DPI_SHIFT 12 1024 #define DB_PWM_ADDR_RESERVED1_MASK 0xF 1025 #define DB_PWM_ADDR_RESERVED1_SHIFT 28 1026 }; 1027 1028 1029 /* 1030 * Parameters to RDMA firmware, passed in EDPM doorbell 1031 */ 1032 struct db_rdma_dpm_params 1033 { 1034 __le32 params; 1035 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F /* Size in QWORD-s of the DPM burst */ 1036 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0 1037 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3 /* Type of DPM transacation (DPM_RDMA) (use enum db_dpm_type) */ 1038 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6 1039 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF /* opcode for RDMA operation */ 1040 #define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8 1041 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF /* the size of the WQE payload in bytes */ 1042 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16 1043 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1 1044 #define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27 1045 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1 /* RoCE completion flag */ 1046 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28 1047 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */ 1048 #define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29 1049 #define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1 1050 #define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30 1051 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1 /* Connection type is iWARP */ 1052 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31 1053 }; 1054 1055 /* 1056 * Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a DPM burst 1057 */ 1058 struct db_rdma_dpm_data 1059 { 1060 __le16 icid /* internal CID */; 1061 __le16 prod_val /* aggregated value to update */; 1062 struct db_rdma_dpm_params params /* parameters passed to RDMA firmware */; 1063 }; 1064 1065 1066 1067 /* 1068 * Igu interrupt command 1069 */ 1070 enum igu_int_cmd 1071 { 1072 IGU_INT_ENABLE=0, 1073 IGU_INT_DISABLE=1, 1074 IGU_INT_NOP=2, 1075 IGU_INT_NOP2=3, 1076 MAX_IGU_INT_CMD 1077 }; 1078 1079 1080 /* 1081 * IGU producer or consumer update command 1082 */ 1083 struct igu_prod_cons_update 1084 { 1085 __le32 sb_id_and_flags; 1086 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF 1087 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0 1088 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1 1089 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24 1090 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3 /* interrupt enable/disable/nop (use enum igu_int_cmd) */ 1091 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25 1092 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1 /* (use enum igu_seg_access) */ 1093 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27 1094 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1 1095 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28 1096 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3 1097 #define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29 1098 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1 /* must always be set cleared (use enum command_type_bit) */ 1099 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31 1100 __le32 reserved1; 1101 }; 1102 1103 1104 /* 1105 * Igu segments access for default status block only 1106 */ 1107 enum igu_seg_access 1108 { 1109 IGU_SEG_ACCESS_REG=0, 1110 IGU_SEG_ACCESS_ATTN=1, 1111 MAX_IGU_SEG_ACCESS 1112 }; 1113 1114 1115 /* 1116 * Enumeration for L3 type field of parsing_and_err_flags_union. L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) 1117 */ 1118 enum l3_type 1119 { 1120 e_l3Type_unknown, 1121 e_l3Type_ipv4, 1122 e_l3Type_ipv6, 1123 MAX_L3_TYPE 1124 }; 1125 1126 1127 /* 1128 * Enumeration for l4Protocol field of parsing_and_err_flags_union. L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. 1129 */ 1130 enum l4_protocol 1131 { 1132 e_l4Protocol_none, 1133 e_l4Protocol_tcp, 1134 e_l4Protocol_udp, 1135 MAX_L4_PROTOCOL 1136 }; 1137 1138 1139 /* 1140 * Parsing and error flags field. 1141 */ 1142 struct parsing_and_err_flags 1143 { 1144 __le16 flags; 1145 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3 /* L3Type: 0 - unknown (not ip) ,1 - Ipv4, 2 - Ipv6 (this field can be filled according to the last-ethertype) (use enum l3_type) */ 1146 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0 1147 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3 /* L4-protocol 0 - none, 1 - TCP, 2- UDP. if the packet is IPv4 fragment, and its not the first fragment, the protocol-type should be set to none. (use enum l4_protocol) */ 1148 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2 1149 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1 /* Set if the packet is IPv4 fragment. */ 1150 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4 1151 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1 /* Set if VLAN tag exists. Invalid if tunnel type are IP GRE or IP GENEVE. */ 1152 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5 1153 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1 /* Set if L4 checksum was calculated. */ 1154 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6 1155 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1 /* Set for PTP packet. */ 1156 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7 1157 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1 /* Set if PTP timestamp recorded. */ 1158 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8 1159 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1 /* Set if either version-mismatch or hdr-len-error or ipv4-cksm is set or ipv6 ver mismatch */ 1160 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9 1161 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1 /* Set if L4 checksum validation failed. Valid only if L4 checksum was calculated. */ 1162 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10 1163 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1 /* Set if GRE/VXLAN/GENEVE tunnel detected. */ 1164 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11 1165 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1 /* Set if VLAN tag exists in tunnel header. */ 1166 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12 1167 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1 /* Set if either tunnel-ipv4-version-mismatch or tunnel-ipv4-hdr-len-error or tunnel-ipv4-cksm is set or tunneling ipv6 ver mismatch */ 1168 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13 1169 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1 /* Set if GRE or VXLAN/GENEVE UDP checksum was calculated. */ 1170 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14 1171 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1 /* Set if tunnel L4 checksum validation failed. Valid only if tunnel L4 checksum was calculated. */ 1172 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15 1173 }; 1174 1175 1176 /* 1177 * Parsing error flags bitmap. 1178 */ 1179 struct parsing_err_flags 1180 { 1181 __le16 flags; 1182 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1 /* MAC error indication */ 1183 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0 1184 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1 /* truncation error indication */ 1185 #define PARSING_ERR_FLAGS_TRUNC_ERROR_SHIFT 1 1186 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1 /* packet too small indication */ 1187 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_SHIFT 2 1188 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1 /* Header Missing Tag */ 1189 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_SHIFT 3 1190 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1 /* from frame cracker output */ 1191 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_SHIFT 4 1192 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1 /* from frame cracker output */ 1193 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_SHIFT 5 1194 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1 /* set this error if: 1. total-len is smaller than hdr-len 2. total-ip-len indicates number that is bigger than real packet length 3. tunneling: total-ip-length of the outer header points to offset that is smaller than the one pointed to by the total-ip-len of the inner hdr. */ 1195 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_SHIFT 6 1196 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1197 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_SHIFT 7 1198 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1 /* from frame cracker output. for either TCP or UDP */ 1199 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_SHIFT 8 1200 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1 /* from frame cracker output */ 1201 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_SHIFT 9 1202 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1 /* cksm calculated and value isnt 0xffff or L4-cksm-wasnt-calculated for any reason, like: udp/ipv4 checksum is 0 etc. */ 1203 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_SHIFT 10 1204 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1 /* from frame cracker output */ 1205 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_SHIFT 11 1206 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1 /* from frame cracker output */ 1207 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_SHIFT 12 1208 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1 /* set if geneve option size was over 32 byte */ 1209 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_SHIFT 13 1210 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1211 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_SHIFT 14 1212 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1 /* from frame cracker output */ 1213 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15 1214 }; 1215 1216 1217 /* 1218 * Pb context 1219 */ 1220 struct pb_context 1221 { 1222 __le32 crc[4]; 1223 }; 1224 1225 1226 /* 1227 * Concrete Function ID. 1228 */ 1229 struct pxp_concrete_fid 1230 { 1231 __le16 fid; 1232 #define PXP_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1233 #define PXP_CONCRETE_FID_PFID_SHIFT 0 1234 #define PXP_CONCRETE_FID_PORT_MASK 0x3 /* port number */ 1235 #define PXP_CONCRETE_FID_PORT_SHIFT 4 1236 #define PXP_CONCRETE_FID_PATH_MASK 0x1 /* path number */ 1237 #define PXP_CONCRETE_FID_PATH_SHIFT 6 1238 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1 1239 #define PXP_CONCRETE_FID_VFVALID_SHIFT 7 1240 #define PXP_CONCRETE_FID_VFID_MASK 0xFF 1241 #define PXP_CONCRETE_FID_VFID_SHIFT 8 1242 }; 1243 1244 1245 /* 1246 * Concrete Function ID. 1247 */ 1248 struct pxp_pretend_concrete_fid 1249 { 1250 __le16 fid; 1251 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF /* Parent PFID */ 1252 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0 1253 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7 /* port number. Only when part of ME register. */ 1254 #define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4 1255 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1 1256 #define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7 1257 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF 1258 #define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8 1259 }; 1260 1261 /* 1262 * Function ID. 1263 */ 1264 union pxp_pretend_fid 1265 { 1266 struct pxp_pretend_concrete_fid concrete_fid; 1267 __le16 opaque_fid; 1268 }; 1269 1270 /* 1271 * Pxp Pretend Command Register. 1272 */ 1273 struct pxp_pretend_cmd 1274 { 1275 union pxp_pretend_fid fid; 1276 __le16 control; 1277 #define PXP_PRETEND_CMD_PATH_MASK 0x1 1278 #define PXP_PRETEND_CMD_PATH_SHIFT 0 1279 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1 1280 #define PXP_PRETEND_CMD_USE_PORT_SHIFT 1 1281 #define PXP_PRETEND_CMD_PORT_MASK 0x3 1282 #define PXP_PRETEND_CMD_PORT_SHIFT 2 1283 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF 1284 #define PXP_PRETEND_CMD_RESERVED0_SHIFT 4 1285 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF 1286 #define PXP_PRETEND_CMD_RESERVED1_SHIFT 8 1287 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1 /* is pretend mode? */ 1288 #define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12 1289 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1 /* is pretend mode? */ 1290 #define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13 1291 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1 /* is pretend mode? */ 1292 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14 1293 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1 /* is fid concrete? */ 1294 #define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15 1295 }; 1296 1297 1298 1299 1300 /* 1301 * PTT Record in PXP Admin Window. 1302 */ 1303 struct pxp_ptt_entry 1304 { 1305 __le32 offset; 1306 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF 1307 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0 1308 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF 1309 #define PXP_PTT_ENTRY_RESERVED0_SHIFT 23 1310 struct pxp_pretend_cmd pretend; 1311 }; 1312 1313 1314 /* 1315 * VF Zone A Permission Register. 1316 */ 1317 struct pxp_vf_zone_a_permission 1318 { 1319 __le32 control; 1320 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF 1321 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0 1322 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1 1323 #define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8 1324 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F 1325 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9 1326 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF 1327 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16 1328 }; 1329 1330 1331 /* 1332 * Rdif context 1333 */ 1334 struct rdif_task_context 1335 { 1336 __le32 initialRefTag; 1337 __le16 appTagValue; 1338 __le16 appTagMask; 1339 u8 flags0; 1340 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1341 #define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1342 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1343 #define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1344 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1345 #define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1346 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1347 #define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1348 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1349 #define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1350 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1351 #define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1352 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 /* Keep reference tag constant */ 1353 #define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7 1354 u8 partialDifData[7]; 1355 __le16 partialCrcValue; 1356 __le16 partialChecksumValue; 1357 __le32 offsetInIO; 1358 __le16 flags1; 1359 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1360 #define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1361 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1362 #define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1363 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1364 #define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1365 #define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1366 #define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1367 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1368 #define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1369 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1370 #define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1371 #define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1372 #define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1373 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1374 #define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1375 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1376 #define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1377 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1 1378 #define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12 1379 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1380 #define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1381 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 /* Forward application tag with mask */ 1382 #define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14 1383 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 /* Forward reference tag with mask */ 1384 #define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15 1385 __le16 state; 1386 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF 1387 #define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0 1388 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF 1389 #define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4 1390 #define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1 1391 #define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8 1392 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1393 #define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1394 #define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF /* mask for refernce tag handling */ 1395 #define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10 1396 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3 1397 #define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14 1398 __le32 reserved2; 1399 }; 1400 1401 1402 1403 /* 1404 * RSS hash type 1405 */ 1406 enum rss_hash_type 1407 { 1408 RSS_HASH_TYPE_DEFAULT=0, 1409 RSS_HASH_TYPE_IPV4=1, 1410 RSS_HASH_TYPE_TCP_IPV4=2, 1411 RSS_HASH_TYPE_IPV6=3, 1412 RSS_HASH_TYPE_TCP_IPV6=4, 1413 RSS_HASH_TYPE_UDP_IPV4=5, 1414 RSS_HASH_TYPE_UDP_IPV6=6, 1415 MAX_RSS_HASH_TYPE 1416 }; 1417 1418 1419 /* 1420 * status block structure 1421 */ 1422 struct status_block 1423 { 1424 __le16 pi_array[PIS_PER_SB]; 1425 __le32 sb_num; 1426 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF 1427 #define STATUS_BLOCK_SB_NUM_SHIFT 0 1428 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F 1429 #define STATUS_BLOCK_ZERO_PAD_SHIFT 9 1430 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF 1431 #define STATUS_BLOCK_ZERO_PAD2_SHIFT 16 1432 __le32 prod_index; 1433 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF 1434 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0 1435 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF 1436 #define STATUS_BLOCK_ZERO_PAD3_SHIFT 24 1437 }; 1438 1439 1440 /* 1441 * Tdif context 1442 */ 1443 struct tdif_task_context 1444 { 1445 __le32 initialRefTag; 1446 __le16 appTagValue; 1447 __le16 appTagMask; 1448 __le16 partialCrcValueB; 1449 __le16 partialChecksumValueB; 1450 __le16 stateB; 1451 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF 1452 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0 1453 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF 1454 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4 1455 #define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1 1456 #define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8 1457 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1 1458 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9 1459 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F 1460 #define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10 1461 u8 reserved1; 1462 u8 flags0; 1463 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1 1464 #define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0 1465 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1 1466 #define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1 1467 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1 /* 0 = IP checksum, 1 = CRC */ 1468 #define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2 1469 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1 1470 #define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3 1471 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3 /* 1/2/3 - Protection Type */ 1472 #define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4 1473 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1 /* 0=0x0000, 1=0xffff */ 1474 #define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6 1475 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1 1476 #define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7 1477 __le32 flags1; 1478 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1 1479 #define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0 1480 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1 1481 #define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1 1482 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1 1483 #define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2 1484 #define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1 1485 #define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3 1486 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1 1487 #define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4 1488 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1 1489 #define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5 1490 #define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7 /* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */ 1491 #define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6 1492 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3 /* 0=None, 1=DIF, 2=DIX */ 1493 #define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9 1494 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1 /* DIF tag right at the beginning of DIF interval */ 1495 #define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11 1496 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */ 1497 #define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12 1498 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1 /* 0=None, 1=DIF */ 1499 #define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13 1500 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF 1501 #define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14 1502 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF 1503 #define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18 1504 #define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1 1505 #define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22 1506 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1 1507 #define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23 1508 #define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF /* mask for refernce tag handling */ 1509 #define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24 1510 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1 /* Forward application tag with mask */ 1511 #define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28 1512 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1 /* Forward reference tag with mask */ 1513 #define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29 1514 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1 /* Keep reference tag constant */ 1515 #define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30 1516 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1 1517 #define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31 1518 __le32 offsetInIOB; 1519 __le16 partialCrcValueA; 1520 __le16 partialChecksumValueA; 1521 __le32 offsetInIOA; 1522 u8 partialDifDataA[8]; 1523 u8 partialDifDataB[8]; 1524 }; 1525 1526 1527 /* 1528 * Timers context 1529 */ 1530 struct timers_context 1531 { 1532 __le32 logical_client_0; 1533 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF /* Expiration time of logical client 0 */ 1534 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0 1535 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1 1536 #define TIMERS_CONTEXT_RESERVED0_SHIFT 27 1537 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1 /* Valid bit of logical client 0 */ 1538 #define TIMERS_CONTEXT_VALIDLC0_SHIFT 28 1539 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1 /* Active bit of logical client 0 */ 1540 #define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29 1541 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3 1542 #define TIMERS_CONTEXT_RESERVED1_SHIFT 30 1543 __le32 logical_client_1; 1544 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF /* Expiration time of logical client 1 */ 1545 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0 1546 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1 1547 #define TIMERS_CONTEXT_RESERVED2_SHIFT 27 1548 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1 /* Valid bit of logical client 1 */ 1549 #define TIMERS_CONTEXT_VALIDLC1_SHIFT 28 1550 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1 /* Active bit of logical client 1 */ 1551 #define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29 1552 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3 1553 #define TIMERS_CONTEXT_RESERVED3_SHIFT 30 1554 __le32 logical_client_2; 1555 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF /* Expiration time of logical client 2 */ 1556 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0 1557 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1 1558 #define TIMERS_CONTEXT_RESERVED4_SHIFT 27 1559 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1 /* Valid bit of logical client 2 */ 1560 #define TIMERS_CONTEXT_VALIDLC2_SHIFT 28 1561 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1 /* Active bit of logical client 2 */ 1562 #define TIMERS_CONTEXT_ACTIVELC2_SHIFT 29 1563 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3 1564 #define TIMERS_CONTEXT_RESERVED5_SHIFT 30 1565 __le32 host_expiration_fields; 1566 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF /* Expiration time on host (closest one) */ 1567 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0 1568 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1 1569 #define TIMERS_CONTEXT_RESERVED6_SHIFT 27 1570 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1 /* Valid bit of host expiration */ 1571 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT 28 1572 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7 1573 #define TIMERS_CONTEXT_RESERVED7_SHIFT 29 1574 }; 1575 1576 1577 /* 1578 * Enum for next_protocol field of tunnel_parsing_flags 1579 */ 1580 enum tunnel_next_protocol 1581 { 1582 e_unknown=0, 1583 e_l2=1, 1584 e_ipv4=2, 1585 e_ipv6=3, 1586 MAX_TUNNEL_NEXT_PROTOCOL 1587 }; 1588 1589 #endif /* __COMMON_HSI__ */ 1590