1 /* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef __BCM_OSAL_ECORE_PACKAGE 29 #define __BCM_OSAL_ECORE_PACKAGE 30 31 #include "qlnx_os.h" 32 #include "ecore_status.h" 33 #include <sys/bitstring.h> 34 35 #include <linux/types.h> 36 #include <linux/bitmap.h> 37 38 #define OSAL_NUM_CPUS() mp_ncpus 39 /* 40 * prototypes of freebsd specific functions required by ecore 41 */ 42 extern uint32_t qlnx_pci_bus_get_bar_size(void *ecore_dev, uint8_t bar_id); 43 extern uint32_t qlnx_pci_read_config_byte(void *ecore_dev, uint32_t pci_reg, 44 uint8_t *reg_value); 45 extern uint32_t qlnx_pci_read_config_word(void *ecore_dev, uint32_t pci_reg, 46 uint16_t *reg_value); 47 extern uint32_t qlnx_pci_read_config_dword(void *ecore_dev, uint32_t pci_reg, 48 uint32_t *reg_value); 49 extern void qlnx_pci_write_config_byte(void *ecore_dev, uint32_t pci_reg, 50 uint8_t reg_value); 51 extern void qlnx_pci_write_config_word(void *ecore_dev, uint32_t pci_reg, 52 uint16_t reg_value); 53 extern void qlnx_pci_write_config_dword(void *ecore_dev, uint32_t pci_reg, 54 uint32_t reg_value); 55 extern int qlnx_pci_find_capability(void *ecore_dev, int cap); 56 extern int qlnx_pci_find_ext_capability(void *ecore_dev, int ext_cap); 57 58 extern uint32_t qlnx_direct_reg_rd32(void *p_hwfn, uint32_t *reg_addr); 59 extern void qlnx_direct_reg_wr32(void *p_hwfn, void *reg_addr, uint32_t value); 60 extern void qlnx_direct_reg_wr64(void *p_hwfn, void *reg_addr, uint64_t value); 61 62 extern uint32_t qlnx_reg_rd32(void *p_hwfn, uint32_t reg_addr); 63 extern void qlnx_reg_wr32(void *p_hwfn, uint32_t reg_addr, uint32_t value); 64 extern void qlnx_reg_wr16(void *p_hwfn, uint32_t reg_addr, uint16_t value); 65 66 extern void qlnx_dbell_wr32(void *p_hwfn, uint32_t reg_addr, uint32_t value); 67 extern void qlnx_dbell_wr32_db(void *p_hwfn, void *reg_addr, uint32_t value); 68 69 extern void *qlnx_dma_alloc_coherent(void *ecore_dev, bus_addr_t *phys, 70 uint32_t size); 71 extern void qlnx_dma_free_coherent(void *ecore_dev, void *v_addr, 72 bus_addr_t phys, uint32_t size); 73 74 extern void qlnx_link_update(void *p_hwfn); 75 extern void qlnx_barrier(void *p_dev); 76 77 extern void *qlnx_zalloc(uint32_t size); 78 79 extern void qlnx_get_protocol_stats(void *cdev, int proto_type, 80 void *proto_stats); 81 82 extern void qlnx_sp_isr(void *arg); 83 84 extern void qlnx_osal_vf_fill_acquire_resc_req(void *p_hwfn, void *p_resc_req, 85 void *p_sw_info); 86 extern void qlnx_osal_iov_vf_cleanup(void *p_hwfn, uint8_t relative_vf_id); 87 extern int qlnx_iov_chk_ucast(void *p_hwfn, int vfid, void *params); 88 extern int qlnx_iov_update_vport(void *p_hwfn, uint8_t vfid, void *params, 89 uint16_t *tlvs); 90 extern int qlnx_pf_vf_msg(void *p_hwfn, uint16_t relative_vf_id); 91 extern void qlnx_vf_flr_update(void *p_hwfn); 92 93 #define nothing do {} while(0) 94 95 /* Memory Types */ 96 #define u8 uint8_t 97 #define u16 uint16_t 98 #define u32 uint32_t 99 #define u64 uint64_t 100 #define s16 uint16_t 101 #define s32 uint32_t 102 103 #ifndef QLNX_RDMA 104 105 #define max_t(type, val1, val2) \ 106 ((type)(val1) > (type)(val2) ? (type)(val1) : (val2)) 107 #define min_t(type, val1, val2) \ 108 ((type)(val1) < (type)(val2) ? (type)(val1) : (val2)) 109 110 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) 111 #define BUILD_BUG_ON(cond) nothing 112 113 #endif /* #ifndef QLNX_RDMA */ 114 115 #define OSAL_UNUSED 116 117 #define OSAL_CPU_TO_BE64(val) htobe64(val) 118 #define OSAL_BE64_TO_CPU(val) be64toh(val) 119 120 #define OSAL_CPU_TO_BE32(val) htobe32(val) 121 #define OSAL_BE32_TO_CPU(val) be32toh(val) 122 123 #define OSAL_CPU_TO_LE32(val) htole32(val) 124 #define OSAL_LE32_TO_CPU(val) le32toh(val) 125 126 #define OSAL_CPU_TO_BE16(val) htobe16(val) 127 #define OSAL_BE16_TO_CPU(val) be16toh(val) 128 129 #define OSAL_CPU_TO_LE16(val) htole16(val) 130 #define OSAL_LE16_TO_CPU(val) le16toh(val) 131 132 static __inline uint32_t 133 qlnx_get_cache_line_size(void) 134 { 135 return (CACHE_LINE_SIZE); 136 } 137 138 #define OSAL_CACHE_LINE_SIZE qlnx_get_cache_line_size() 139 140 #define OSAL_BE32 uint32_t 141 #define dma_addr_t bus_addr_t 142 #define osal_size_t size_t 143 144 typedef struct mtx osal_spinlock_t; 145 typedef struct mtx osal_mutex_t; 146 147 typedef void * osal_dpc_t; 148 149 typedef struct _osal_list_entry_t 150 { 151 struct _osal_list_entry_t *next, *prev; 152 } osal_list_entry_t; 153 154 typedef struct osal_list_t 155 { 156 osal_list_entry_t *head, *tail; 157 unsigned long cnt; 158 } osal_list_t; 159 160 /* OSAL functions */ 161 162 #define OSAL_UDELAY(time) DELAY(time) 163 #define OSAL_MSLEEP(time) qlnx_mdelay(__func__, time) 164 165 #define OSAL_ALLOC(dev, GFP, size) qlnx_zalloc(size) 166 #define OSAL_ZALLOC(dev, GFP, size) qlnx_zalloc(size) 167 #define OSAL_VALLOC(dev, size) qlnx_zalloc(size) 168 #define OSAL_VZALLOC(dev, size) qlnx_zalloc(size) 169 170 #define OSAL_FREE(dev, memory) free(memory, M_QLNXBUF) 171 #define OSAL_VFREE(dev, memory) free(memory, M_QLNXBUF) 172 173 #define OSAL_MEM_ZERO(mem, size) bzero(mem, size) 174 175 #define OSAL_MEMCPY(dst, src, size) memcpy(dst, src, size) 176 177 #define OSAL_DMA_ALLOC_COHERENT(dev, phys, size) \ 178 qlnx_dma_alloc_coherent(dev, phys, size) 179 180 #define OSAL_DMA_FREE_COHERENT(dev, virt, phys, size) \ 181 qlnx_dma_free_coherent(dev, virt, phys, size) 182 #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol) (0) 183 184 #define REG_WR(hwfn, addr, val) qlnx_reg_wr32(hwfn, addr, val) 185 #define REG_WR16(hwfn, addr, val) qlnx_reg_wr16(hwfn, addr, val) 186 #define DIRECT_REG_WR(p_hwfn, addr, value) qlnx_direct_reg_wr32(p_hwfn, addr, value) 187 #define DIRECT_REG_WR64(p_hwfn, addr, value) \ 188 qlnx_direct_reg_wr64(p_hwfn, addr, value) 189 #define DIRECT_REG_WR_DB(p_hwfn, addr, value) qlnx_dbell_wr32_db(p_hwfn, addr, value) 190 #define DIRECT_REG_RD(p_hwfn, addr) qlnx_direct_reg_rd32(p_hwfn, addr) 191 #define REG_RD(hwfn, addr) qlnx_reg_rd32(hwfn, addr) 192 #define DOORBELL(hwfn, addr, value) \ 193 qlnx_dbell_wr32(hwfn, addr, value) 194 195 #define OSAL_SPIN_LOCK_ALLOC(p_hwfn, mutex) 196 #define OSAL_SPIN_LOCK_DEALLOC(mutex) mtx_destroy(mutex) 197 #define OSAL_SPIN_LOCK_INIT(lock) {\ 198 mtx_init(lock, __func__, "OSAL spin lock", MTX_SPIN); \ 199 } 200 201 #define OSAL_SPIN_UNLOCK(lock) {\ 202 mtx_unlock_spin(lock); \ 203 } 204 #define OSAL_SPIN_LOCK(lock) {\ 205 mtx_lock_spin(lock); \ 206 } 207 208 #define OSAL_MUTEX_ALLOC(p_hwfn, mutex) 209 #define OSAL_MUTEX_DEALLOC(mutex) mtx_destroy(mutex) 210 #define OSAL_MUTEX_INIT(lock) {\ 211 mtx_init(lock, __func__, MTX_NETWORK_LOCK, MTX_DEF);\ 212 } 213 214 #define OSAL_MUTEX_ACQUIRE(lock) mtx_lock(lock) 215 #define OSAL_MUTEX_RELEASE(lock) mtx_unlock(lock) 216 217 #define OSAL_DPC_ALLOC(hwfn) malloc(PAGE_SIZE, M_QLNXBUF, M_NOWAIT) 218 #define OSAL_DPC_INIT(dpc, hwfn) nothing 219 extern void qlnx_schedule_recovery(void *p_hwfn); 220 #define OSAL_SCHEDULE_RECOVERY_HANDLER(x) do {qlnx_schedule_recovery(x);} while(0) 221 #define OSAL_HW_ERROR_OCCURRED(hwfn, err_type) nothing 222 #define OSAL_DPC_SYNC(hwfn) nothing 223 224 static inline void OSAL_DCBX_AEN(void *p_hwfn, u32 mib_type) 225 { 226 return; 227 } 228 229 static inline bool OSAL_NVM_IS_ACCESS_ENABLED(void *p_hwfn) 230 { 231 return 1; 232 } 233 234 #define OSAL_LIST_INIT(list) \ 235 do { \ 236 (list)->head = NULL; \ 237 (list)->tail = NULL; \ 238 (list)->cnt = 0; \ 239 } while (0) 240 241 #define OSAL_LIST_INSERT_ENTRY_AFTER(entry, entry_prev, list) \ 242 do { \ 243 (entry)->prev = (entry_prev); \ 244 (entry)->next = (entry_prev)->next; \ 245 (entry)->next->prev = (entry); \ 246 (entry_prev)->next = (entry); \ 247 (list)->cnt++; \ 248 } while (0); 249 250 #define OSAL_LIST_SPLICE_TAIL_INIT(new_list, list) \ 251 do { \ 252 ((new_list)->tail)->next = ((list)->head); \ 253 ((list)->head)->prev = ((new_list)->tail); \ 254 (list)->head = (new_list)->head; \ 255 (list)->cnt = (list)->cnt + (new_list)->cnt; \ 256 OSAL_LIST_INIT(new_list); \ 257 } while (0); 258 259 #define OSAL_LIST_PUSH_HEAD(entry, list) \ 260 do { \ 261 (entry)->prev = (osal_list_entry_t *)0; \ 262 (entry)->next = (list)->head; \ 263 if ((list)->tail == (osal_list_entry_t *)0) { \ 264 (list)->tail = (entry); \ 265 } else { \ 266 (list)->head->prev = (entry); \ 267 } \ 268 (list)->head = (entry); \ 269 (list)->cnt++; \ 270 } while (0) 271 272 #define OSAL_LIST_PUSH_TAIL(entry, list) \ 273 do { \ 274 (entry)->next = (osal_list_entry_t *)0; \ 275 (entry)->prev = (list)->tail; \ 276 if ((list)->tail) { \ 277 (list)->tail->next = (entry); \ 278 } else { \ 279 (list)->head = (entry); \ 280 } \ 281 (list)->tail = (entry); \ 282 (list)->cnt++; \ 283 } while (0) 284 285 #define OSAL_LIST_FIRST_ENTRY(list, type, field) \ 286 (type *)((list)->head) 287 288 #define OSAL_LIST_REMOVE_ENTRY(entry, list) \ 289 do { \ 290 if ((list)->head == (entry)) { \ 291 if ((list)->head) { \ 292 (list)->head = (list)->head->next; \ 293 if ((list)->head) { \ 294 (list)->head->prev = (osal_list_entry_t *)0; \ 295 } else { \ 296 (list)->tail = (osal_list_entry_t *)0; \ 297 } \ 298 (list)->cnt--; \ 299 } \ 300 } else if ((list)->tail == (entry)) { \ 301 if ((list)->tail) { \ 302 (list)->tail = (list)->tail->prev; \ 303 if ((list)->tail) { \ 304 (list)->tail->next = (osal_list_entry_t *)0; \ 305 } else { \ 306 (list)->head = (osal_list_entry_t *)0; \ 307 } \ 308 (list)->cnt--; \ 309 } \ 310 } else { \ 311 (entry)->prev->next = (entry)->next; \ 312 (entry)->next->prev = (entry)->prev; \ 313 (list)->cnt--; \ 314 } \ 315 } while (0) 316 317 #define OSAL_LIST_IS_EMPTY(list) \ 318 ((list)->cnt == 0) 319 320 #define OSAL_LIST_NEXT(entry, field, type) \ 321 (type *)((&((entry)->field))->next) 322 323 #define OSAL_LIST_FOR_EACH_ENTRY(entry, list, field, type) \ 324 for (entry = OSAL_LIST_FIRST_ENTRY(list, type, field); \ 325 entry; \ 326 entry = OSAL_LIST_NEXT(entry, field, type)) 327 328 #define OSAL_LIST_FOR_EACH_ENTRY_SAFE(entry, tmp_entry, list, field, type) \ 329 for (entry = OSAL_LIST_FIRST_ENTRY(list, type, field), \ 330 tmp_entry = (entry) ? OSAL_LIST_NEXT(entry, field, type) : NULL; \ 331 entry != NULL; \ 332 entry = (type *)tmp_entry, \ 333 tmp_entry = (entry) ? OSAL_LIST_NEXT(entry, field, type) : NULL) 334 335 #define OSAL_BAR_SIZE(dev, bar_id) qlnx_pci_bus_get_bar_size(dev, bar_id) 336 337 #define OSAL_PCI_READ_CONFIG_BYTE(dev, reg, value) \ 338 qlnx_pci_read_config_byte(dev, reg, value); 339 #define OSAL_PCI_READ_CONFIG_WORD(dev, reg, value) \ 340 qlnx_pci_read_config_word(dev, reg, value); 341 #define OSAL_PCI_READ_CONFIG_DWORD(dev, reg, value) \ 342 qlnx_pci_read_config_dword(dev, reg, value); 343 344 #define OSAL_PCI_WRITE_CONFIG_BYTE(dev, reg, value) \ 345 qlnx_pci_write_config_byte(dev, reg, value); 346 #define OSAL_PCI_WRITE_CONFIG_WORD(dev, reg, value) \ 347 qlnx_pci_write_config_word(dev, reg, value); 348 #define OSAL_PCI_WRITE_CONFIG_DWORD(dev, reg, value) \ 349 qlnx_pci_write_config_dword(dev, reg, value); 350 351 #define OSAL_PCI_FIND_CAPABILITY(dev, cap) qlnx_pci_find_capability(dev, cap) 352 #define OSAL_PCI_FIND_EXT_CAPABILITY(dev, ext_cap) \ 353 qlnx_pci_find_ext_capability(dev, ext_cap) 354 355 #define OSAL_MMIOWB(dev) qlnx_barrier(dev) 356 #define OSAL_BARRIER(dev) qlnx_barrier(dev) 357 358 #define OSAL_SMP_MB(dev) mb() 359 #define OSAL_SMP_RMB(dev) rmb() 360 #define OSAL_SMP_WMB(dev) wmb() 361 #define OSAL_RMB(dev) rmb() 362 #define OSAL_WMB(dev) wmb() 363 #define OSAL_DMA_SYNC(dev, addr, length, is_post) 364 365 #define OSAL_FIND_FIRST_BIT find_first_bit 366 #define OSAL_SET_BIT(bit, bitmap) bit_set((bitstr_t *)bitmap, bit) 367 #define OSAL_CLEAR_BIT(bit, bitmap) bit_clear((bitstr_t *)bitmap, bit) 368 #define OSAL_TEST_BIT(bit, bitmap) bit_test((bitstr_t *)bitmap, bit) 369 #define OSAL_FIND_FIRST_ZERO_BIT(bitmap, length) \ 370 find_first_zero_bit(bitmap, length) 371 372 #define OSAL_LINK_UPDATE(hwfn, ptt) qlnx_link_update(hwfn) 373 374 #define QLNX_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 375 #define QLNX_ROUNDUP(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 376 377 #define OSAL_NUM_ACTIVE_CPU() mp_ncpus 378 379 #ifndef DIV_ROUND_UP 380 #define DIV_ROUND_UP(size, to_what) QLNX_DIV_ROUND_UP((size), (to_what)) 381 #endif 382 383 #define ROUNDUP(value, to_what) QLNX_ROUNDUP((value), (to_what)) 384 385 #define OSAL_ROUNDUP_POW_OF_TWO(val) roundup_pow_of_two((val)) 386 387 static __inline uint32_t 388 qlnx_log2(uint32_t x) 389 { 390 uint32_t log = 0; 391 392 while (x >>= 1) log++; 393 394 return (log); 395 } 396 397 #define OSAL_LOG2(val) qlnx_log2(val) 398 #define OFFSETOF(str, field) offsetof(str, field) 399 #define PRINT device_printf 400 #define PRINT_ERR device_printf 401 #define OSAL_ASSERT(is_assert) nothing 402 #define OSAL_BEFORE_PF_START(cdev, my_id) {}; 403 #define OSAL_AFTER_PF_STOP(cdev, my_id) {}; 404 405 #define INLINE __inline 406 #define OSAL_INLINE __inline 407 #define OSAL_UNLIKELY 408 #define OSAL_NULL NULL 409 410 #define OSAL_MAX_T(type, __max1, __max2) max_t(type, __max1, __max2) 411 #define OSAL_MIN_T(type, __max1, __max2) min_t(type, __max1, __max2) 412 413 #define __iomem 414 #define OSAL_IOMEM 415 416 #define int_ptr_t void * 417 #define osal_int_ptr_t void * 418 #define OSAL_BUILD_BUG_ON(cond) nothing 419 #define REG_ADDR(hwfn, offset) (void *)((u8 *)(hwfn->regview) + (offset)) 420 #define OSAL_REG_ADDR(hwfn, offset) (void *)((u8 *)(hwfn->regview) + (offset)) 421 422 #define OSAL_PAGE_SIZE PAGE_SIZE 423 424 #define OSAL_STRCPY(dst, src) strcpy(dst, src) 425 #define OSAL_STRNCPY(dst, src, bytes) strncpy(dst, src, bytes) 426 #define OSAL_STRLEN(src) strlen(src) 427 #define OSAL_SPRINTF sprintf 428 #define OSAL_SNPRINTF snprintf 429 #define OSAL_MEMSET memset 430 #define OSAL_ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) 431 #define osal_uintptr_t u64 432 433 #define OSAL_SLOWPATH_IRQ_REQ(p_hwfn) (0) 434 #define OSAL_GET_PROTOCOL_STATS(p_hwfn, type, stats) \ 435 qlnx_get_protocol_stats(p_hwfn, type, stats); 436 #define OSAL_POLL_MODE_DPC(hwfn) {if (cold) qlnx_sp_isr(hwfn);} 437 #define OSAL_WARN(cond, fmt, args...) \ 438 if (cond) printf("%s: WARNING: " fmt, __func__, ## args); 439 440 #define OSAL_BITMAP_WEIGHT(bitmap, nbits) bitmap_weight(bitmap, nbits) 441 #define OSAL_GET_RDMA_SB_ID(p_hwfn, cnq_id) ecore_rdma_get_sb_id(p_hwfn, cnq_id) 442 443 static inline int 444 qlnx_test_and_change_bit(long bit, volatile unsigned long *var) 445 { 446 long val; 447 448 var += BIT_WORD(bit); 449 bit %= BITS_PER_LONG; 450 bit = (1UL << bit); 451 452 val = *var; 453 454 if (val & bit) 455 return (test_and_clear_bit(bit, var)); 456 457 return (test_and_set_bit(bit, var)); 458 } 459 460 #define OSAL_TEST_AND_FLIP_BIT qlnx_test_and_change_bit 461 #define OSAL_TEST_AND_CLEAR_BIT test_and_clear_bit 462 #define OSAL_MEMCMP memcmp 463 #define OSAL_SPIN_LOCK_IRQSAVE(x, y) { (void)y; mtx_lock(x); } 464 #define OSAL_SPIN_UNLOCK_IRQSAVE(x, y) { (void)y; mtx_unlock(x); } 465 466 static inline u32 467 OSAL_CRC32(u32 crc, u8 *ptr, u32 length) 468 { 469 int i; 470 471 while (length--) { 472 crc ^= *ptr++; 473 for (i = 0; i < 8; i++) 474 crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0); 475 } 476 return crc; 477 } 478 479 static inline void 480 OSAL_CRC8_POPULATE(u8 * cdu_crc8_table, u8 polynomial) 481 { 482 return; 483 } 484 485 static inline u8 486 OSAL_CRC8(u8 * cdu_crc8_table, u8 * data_to_crc, int data_to_crc_len, u8 init_value) 487 { 488 return ECORE_NOTIMPL; 489 } 490 491 #define OSAL_HW_INFO_CHANGE(p_hwfn, offset) 492 #define OSAL_MFW_TLV_REQ(p_hwfn) 493 #define OSAL_LLDP_RX_TLVS(p_hwfn, buffer, len) 494 #define OSAL_MFW_CMD_PREEMPT(p_hwfn) 495 #define OSAL_TRANSCEIVER_UPDATE(p_hwfn) 496 #define OSAL_MFW_FILL_TLV_DATA(p_hwfn, group, data) (0) 497 498 #define OSAL_VF_UPDATE_ACQUIRE_RESC_RESP(p_hwfn, res) (0) 499 500 #define OSAL_VF_FILL_ACQUIRE_RESC_REQ(p_hwfn, req, vf_sw_info) \ 501 qlnx_osal_vf_fill_acquire_resc_req(p_hwfn, req, vf_sw_info) 502 503 #define OSAL_IOV_PF_RESP_TYPE(p_hwfn, relative_vf_id, status) 504 #define OSAL_IOV_VF_CLEANUP(p_hwfn, relative_vf_id) \ 505 qlnx_osal_iov_vf_cleanup(p_hwfn, relative_vf_id) 506 507 #define OSAL_IOV_VF_ACQUIRE(p_hwfn, relative_vf_id) ECORE_SUCCESS 508 #define OSAL_IOV_GET_OS_TYPE() VFPF_ACQUIRE_OS_FREEBSD 509 #define OSAL_IOV_PRE_START_VPORT(p_hwfn, relative_vf_id, params) ECORE_SUCCESS 510 #define OSAL_IOV_POST_START_VPORT(p_hwfn, relative_vf_id, vport_id, opaque_fid) 511 #define OSAL_PF_VALIDATE_MODIFY_TUNN_CONFIG(p_hwfn, x, y, z) ECORE_SUCCESS 512 #define OSAL_IOV_CHK_UCAST(p_hwfn, vfid, params) \ 513 qlnx_iov_chk_ucast(p_hwfn, vfid, params); 514 #define OSAL_PF_VF_MALICIOUS(p_hwfn, relative_vf_id) 515 #define OSAL_IOV_VF_MSG_TYPE(p_hwfn, relative_vf_id, type) 516 #define OSAL_IOV_VF_VPORT_UPDATE(p_hwfn, vfid, params, tlvs) \ 517 qlnx_iov_update_vport(p_hwfn, vfid, params, tlvs) 518 #define OSAL_PF_VF_MSG(p_hwfn, relative_vf_id) \ 519 qlnx_pf_vf_msg(p_hwfn, relative_vf_id) 520 521 #define OSAL_VF_FLR_UPDATE(p_hwfn) qlnx_vf_flr_update(p_hwfn) 522 #define OSAL_IOV_VF_VPORT_STOP(p_hwfn, vf) 523 524 #endif /* #ifdef __BCM_OSAL_ECORE_PACKAGE */ 525